drivers/net/wireless/iwlwifi/iwl-eeprom-read.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *****************************************************************************/
  62 #include <linux/types.h>
  63 #include <linux/slab.h>
  64 #include <linux/export.h>
  65
  66 #include "iwl-debug.h"
  67 #include "iwl-eeprom-read.h"
  68 #include "iwl-io.h"
  69 #include "iwl-prph.h"
  70 #include "iwl-csr.h"
  71
  72 /*
  73  * EEPROM access time values:
  74  *
  75  * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
  76  * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
  77  * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
  78  * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
  79  */
  80 #define IWL_EEPROM_ACCESS_TIMEOUT       5000 /* uSec */
  81
  82 #define IWL_EEPROM_SEM_TIMEOUT          10   /* microseconds */
  83 #define IWL_EEPROM_SEM_RETRY_LIMIT      1000 /* number of attempts (not time) */
  84
  85
  86 /*
  87  * The device's EEPROM semaphore prevents conflicts between driver and uCode
  88  * when accessing the EEPROM; each access is a series of pulses to/from the
  89  * EEPROM chip, not a single event, so even reads could conflict if they
  90  * weren't arbitrated by the semaphore.
  91  */
  92
  93 #define EEPROM_SEM_TIMEOUT 10           /* milliseconds */
  94 #define EEPROM_SEM_RETRY_LIMIT 1000     /* number of attempts (not time) */
  95
  96 static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
  97 {
  98         u16 count;
  99         int ret;
 100
 101         for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
 102                 /* Request semaphore */
 103                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 104                             CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
 105
 106                 /* See if we got it */
 107                 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 108                                 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
 109                                 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
 110                                 EEPROM_SEM_TIMEOUT);
 111                 if (ret >= 0) {
 112                         IWL_DEBUG_EEPROM(trans->dev,
 113                                          "Acquired semaphore after %d tries.\n",
 114                                          count+1);
 115                         return ret;
 116                 }
 117         }
 118
 119         return ret;
 120 }
 121
 122 static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)
 123 {
 124         iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
 125                       CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
 126 }
 127
 128 static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)
 129 {
 130         u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
 131
 132         IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp);
 133
 134         switch (gp) {
 135         case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
 136                 if (!nvm_is_otp) {
 137                         IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n",
 138                                 gp);
 139                         return -ENOENT;
 140                 }
 141                 return 0;
 142         case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
 143         case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
 144                 if (nvm_is_otp) {
 145                         IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp);
 146                         return -ENOENT;
 147                 }
 148                 return 0;
 149         case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
 150         default:
 151                 IWL_ERR(trans,
 152                         "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n",
 153                         nvm_is_otp ? "OTP" : "EEPROM", gp);
 154                 return -ENOENT;
 155         }
 156 }
 157
 158 /******************************************************************************
 159  *
 160  * OTP related functions
 161  *
 162 ******************************************************************************/
 163
 164 static void iwl_set_otp_access_absolute(struct iwl_trans *trans)
 165 {
 166         iwl_read32(trans, CSR_OTP_GP_REG);
 167
 168         iwl_clear_bit(trans, CSR_OTP_GP_REG,
 169                       CSR_OTP_GP_REG_OTP_ACCESS_MODE);
 170 }
 171
 172 static int iwl_nvm_is_otp(struct iwl_trans *trans)
 173 {
 174         u32 otpgp;
 175
 176         /* OTP only valid for CP/PP and after */
 177         switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) {
 178         case CSR_HW_REV_TYPE_NONE:
 179                 IWL_ERR(trans, "Unknown hardware type\n");
 180                 return -EIO;
 181         case CSR_HW_REV_TYPE_5300:
 182         case CSR_HW_REV_TYPE_5350:
 183         case CSR_HW_REV_TYPE_5100:
 184         case CSR_HW_REV_TYPE_5150:
 185                 return 0;
 186         default:
 187                 otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
 188                 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
 189                         return 1;
 190                 return 0;
 191         }
 192 }
 193
 194 static int iwl_init_otp_access(struct iwl_trans *trans)
 195 {
 196         int ret;
 197
 198         /* Enable 40MHz radio clock */
 199         iwl_write32(trans, CSR_GP_CNTRL,
 200                     iwl_read32(trans, CSR_GP_CNTRL) |
 201                     CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 202
 203         /* wait for clock to be ready */
 204         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 205                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 206                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 207                            25000);
 208         if (ret < 0) {
 209                 IWL_ERR(trans, "Time out access OTP\n");
 210         } else {
 211                 iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
 212                                   APMG_PS_CTRL_VAL_RESET_REQ);
 213                 udelay(5);
 214                 iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
 215                                     APMG_PS_CTRL_VAL_RESET_REQ);
 216
 217                 /*
 218                  * CSR auto clock gate disable bit -
 219                  * this is only applicable for HW with OTP shadow RAM
 220                  */
 221                 if (trans->cfg->base_params->shadow_ram_support)
 222                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 223                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 224         }
 225         return ret;
 226 }
 227
 228 static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
 229                              __le16 *eeprom_data)
 230 {
 231         int ret = 0;
 232         u32 r;
 233         u32 otpgp;
 234
 235         iwl_write32(trans, CSR_EEPROM_REG,
 236                     CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 237         ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
 238                                  CSR_EEPROM_REG_READ_VALID_MSK,
 239                                  CSR_EEPROM_REG_READ_VALID_MSK,
 240                                  IWL_EEPROM_ACCESS_TIMEOUT);
 241         if (ret < 0) {
 242                 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
 243                 return ret;
 244         }
 245         r = iwl_read32(trans, CSR_EEPROM_REG);
 246         /* check for ECC errors: */
 247         otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
 248         if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
 249                 /* stop in this case */
 250                 /* set the uncorrectable OTP ECC bit for acknowledgement */
 251                 iwl_set_bit(trans, CSR_OTP_GP_REG,
 252                             CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
 253                 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n");
 254                 return -EINVAL;
 255         }
 256         if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
 257                 /* continue in this case */
 258                 /* set the correctable OTP ECC bit for acknowledgement */
 259                 iwl_set_bit(trans, CSR_OTP_GP_REG,
 260                             CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
 261                 IWL_ERR(trans, "Correctable OTP ECC error, continue read\n");
 262         }
 263         *eeprom_data = cpu_to_le16(r >> 16);
 264         return 0;
 265 }
 266
 267 /*
 268  * iwl_is_otp_empty: check for empty OTP
 269  */
 270 static bool iwl_is_otp_empty(struct iwl_trans *trans)
 271 {
 272         u16 next_link_addr = 0;
 273         __le16 link_value;
 274         bool is_empty = false;
 275
 276         /* locate the beginning of OTP link list */
 277         if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) {
 278                 if (!link_value) {
 279                         IWL_ERR(trans, "OTP is empty\n");
 280                         is_empty = true;
 281                 }
 282         } else {
 283                 IWL_ERR(trans, "Unable to read first block of OTP list.\n");
 284                 is_empty = true;
 285         }
 286
 287         return is_empty;
 288 }
 289
 290
 291 /*
 292  * iwl_find_otp_image: find EEPROM image in OTP
 293  *   finding the OTP block that contains the EEPROM image.
 294  *   the last valid block on the link list (the block _before_ the last block)
 295  *   is the block we should read and used to configure the device.
 296  *   If all the available OTP blocks are full, the last block will be the block
 297  *   we should read and used to configure the device.
 298  *   only perform this operation if shadow RAM is disabled
 299  */
 300 static int iwl_find_otp_image(struct iwl_trans *trans,
 301                                         u16 *validblockaddr)
 302 {
 303         u16 next_link_addr = 0, valid_addr;
 304         __le16 link_value = 0;
 305         int usedblocks = 0;
 306
 307         /* set addressing mode to absolute to traverse the link list */
 308         iwl_set_otp_access_absolute(trans);
 309
 310         /* checking for empty OTP or error */
 311         if (iwl_is_otp_empty(trans))
 312                 return -EINVAL;
 313
 314         /*
 315          * start traverse link list
 316          * until reach the max number of OTP blocks
 317          * different devices have different number of OTP blocks
 318          */
 319         do {
 320                 /* save current valid block address
 321                  * check for more block on the link list
 322                  */
 323                 valid_addr = next_link_addr;
 324                 next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
 325                 IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n",
 326                                  usedblocks, next_link_addr);
 327                 if (iwl_read_otp_word(trans, next_link_addr, &link_value))
 328                         return -EINVAL;
 329                 if (!link_value) {
 330                         /*
 331                          * reach the end of link list, return success and
 332                          * set address point to the starting address
 333                          * of the image
 334                          */
 335                         *validblockaddr = valid_addr;
 336                         /* skip first 2 bytes (link list pointer) */
 337                         *validblockaddr += 2;
 338                         return 0;
 339                 }
 340                 /* more in the link list, continue */
 341                 usedblocks++;
 342         } while (usedblocks <= trans->cfg->base_params->max_ll_items);
 343
 344         /* OTP has no valid blocks */
 345         IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n");
 346         return -EINVAL;
 347 }
 348
 349 /**
 350  * iwl_read_eeprom - read EEPROM contents
 351  *
 352  * Load the EEPROM contents from adapter and return it
 353  * and its size.
 354  *
 355  * NOTE:  This routine uses the non-debug IO access functions.
 356  */
 357 int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)
 358 {
 359         __le16 *e;
 360         u32 gp = iwl_read32(trans, CSR_EEPROM_GP);
 361         int sz;
 362         int ret;
 363         u16 addr;
 364         u16 validblockaddr = 0;
 365         u16 cache_addr = 0;
 366         int nvm_is_otp;
 367
 368         if (!eeprom || !eeprom_size)
 369                 return -EINVAL;
 370
 371         nvm_is_otp = iwl_nvm_is_otp(trans);
 372         if (nvm_is_otp < 0)
 373                 return nvm_is_otp;
 374
 375         sz = trans->cfg->base_params->eeprom_size;
 376         IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz);
 377
 378         e = kmalloc(sz, GFP_KERNEL);
 379         if (!e)
 380                 return -ENOMEM;
 381
 382         ret = iwl_eeprom_verify_signature(trans, nvm_is_otp);
 383         if (ret < 0) {
 384                 IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
 385                 goto err_free;
 386         }
 387
 388         /* Make sure driver (instead of uCode) is allowed to read EEPROM */
 389         ret = iwl_eeprom_acquire_semaphore(trans);
 390         if (ret < 0) {
 391                 IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n");
 392                 goto err_free;
 393         }
 394
 395         if (nvm_is_otp) {
 396                 ret = iwl_init_otp_access(trans);
 397                 if (ret) {
 398                         IWL_ERR(trans, "Failed to initialize OTP access.\n");
 399                         goto err_unlock;
 400                 }
 401
 402                 iwl_write32(trans, CSR_EEPROM_GP,
 403                             iwl_read32(trans, CSR_EEPROM_GP) &
 404                             ~CSR_EEPROM_GP_IF_OWNER_MSK);
 405
 406                 iwl_set_bit(trans, CSR_OTP_GP_REG,
 407                             CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
 408                             CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
 409                 /* traversing the linked list if no shadow ram supported */
 410                 if (!trans->cfg->base_params->shadow_ram_support) {
 411                         ret = iwl_find_otp_image(trans, &validblockaddr);
 412                         if (ret)
 413                                 goto err_unlock;
 414                 }
 415                 for (addr = validblockaddr; addr < validblockaddr + sz;
 416                      addr += sizeof(u16)) {
 417                         __le16 eeprom_data;
 418
 419                         ret = iwl_read_otp_word(trans, addr, &eeprom_data);
 420                         if (ret)
 421                                 goto err_unlock;
 422                         e[cache_addr / 2] = eeprom_data;
 423                         cache_addr += sizeof(u16);
 424                 }
 425         } else {
 426                 /* eeprom is an array of 16bit values */
 427                 for (addr = 0; addr < sz; addr += sizeof(u16)) {
 428                         u32 r;
 429
 430                         iwl_write32(trans, CSR_EEPROM_REG,
 431                                     CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 432
 433                         ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
 434                                            CSR_EEPROM_REG_READ_VALID_MSK,
 435                                            CSR_EEPROM_REG_READ_VALID_MSK,
 436                                            IWL_EEPROM_ACCESS_TIMEOUT);
 437                         if (ret < 0) {
 438                                 IWL_ERR(trans,
 439                                         "Time out reading EEPROM[%d]\n", addr);
 440                                 goto err_unlock;
 441                         }
 442                         r = iwl_read32(trans, CSR_EEPROM_REG);
 443                         e[addr / 2] = cpu_to_le16(r >> 16);
 444                 }
 445         }
 446
 447         IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n",
 448                          nvm_is_otp ? "OTP" : "EEPROM");
 449
 450         iwl_eeprom_release_semaphore(trans);
 451
 452         *eeprom_size = sz;
 453         *eeprom = (u8 *)e;
 454         return 0;
 455
 456  err_unlock:
 457         iwl_eeprom_release_semaphore(trans);
 458  err_free:
 459         kfree(e);
 460
 461         return ret;
 462 }
 463 EXPORT_SYMBOL_GPL(iwl_read_eeprom);