Merge branches 'dma-omap', 'dma-pl08x' and 'dma-sa11x0' into dmaengine
[linux-3.10.git] / drivers / mmc / host / omap_hsmmc.c
1 /*
2  * drivers/mmc/host/omap_hsmmc.c
3  *
4  * Driver for OMAP2430/3430 MMC controller.
5  *
6  * Copyright (C) 2007 Texas Instruments.
7  *
8  * Authors:
9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
10  *      Madhusudhan             <madhu.cr@ti.com>
11  *      Mohit Jalori            <mjalori@ti.com>
12  *
13  * This file is licensed under the terms of the GNU General Public License
14  * version 2. This program is licensed "as is" without any warranty of any
15  * kind, whether express or implied.
16  */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/timer.h>
29 #include <linux/clk.h>
30 #include <linux/of.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_device.h>
33 #include <linux/omap-dma.h>
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/core.h>
36 #include <linux/mmc/mmc.h>
37 #include <linux/io.h>
38 #include <linux/semaphore.h>
39 #include <linux/gpio.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/pm_runtime.h>
42 #include <mach/hardware.h>
43 #include <plat/board.h>
44 #include <plat/mmc.h>
45 #include <plat/cpu.h>
46
47 /* OMAP HSMMC Host Controller Registers */
48 #define OMAP_HSMMC_SYSCONFIG    0x0010
49 #define OMAP_HSMMC_SYSSTATUS    0x0014
50 #define OMAP_HSMMC_CON          0x002C
51 #define OMAP_HSMMC_BLK          0x0104
52 #define OMAP_HSMMC_ARG          0x0108
53 #define OMAP_HSMMC_CMD          0x010C
54 #define OMAP_HSMMC_RSP10        0x0110
55 #define OMAP_HSMMC_RSP32        0x0114
56 #define OMAP_HSMMC_RSP54        0x0118
57 #define OMAP_HSMMC_RSP76        0x011C
58 #define OMAP_HSMMC_DATA         0x0120
59 #define OMAP_HSMMC_HCTL         0x0128
60 #define OMAP_HSMMC_SYSCTL       0x012C
61 #define OMAP_HSMMC_STAT         0x0130
62 #define OMAP_HSMMC_IE           0x0134
63 #define OMAP_HSMMC_ISE          0x0138
64 #define OMAP_HSMMC_CAPA         0x0140
65
66 #define VS18                    (1 << 26)
67 #define VS30                    (1 << 25)
68 #define SDVS18                  (0x5 << 9)
69 #define SDVS30                  (0x6 << 9)
70 #define SDVS33                  (0x7 << 9)
71 #define SDVS_MASK               0x00000E00
72 #define SDVSCLR                 0xFFFFF1FF
73 #define SDVSDET                 0x00000400
74 #define AUTOIDLE                0x1
75 #define SDBP                    (1 << 8)
76 #define DTO                     0xe
77 #define ICE                     0x1
78 #define ICS                     0x2
79 #define CEN                     (1 << 2)
80 #define CLKD_MASK               0x0000FFC0
81 #define CLKD_SHIFT              6
82 #define DTO_MASK                0x000F0000
83 #define DTO_SHIFT               16
84 #define INT_EN_MASK             0x307F0033
85 #define BWR_ENABLE              (1 << 4)
86 #define BRR_ENABLE              (1 << 5)
87 #define DTO_ENABLE              (1 << 20)
88 #define INIT_STREAM             (1 << 1)
89 #define DP_SELECT               (1 << 21)
90 #define DDIR                    (1 << 4)
91 #define DMA_EN                  0x1
92 #define MSBS                    (1 << 5)
93 #define BCE                     (1 << 1)
94 #define FOUR_BIT                (1 << 1)
95 #define DDR                     (1 << 19)
96 #define DW8                     (1 << 5)
97 #define CC                      0x1
98 #define TC                      0x02
99 #define OD                      0x1
100 #define ERR                     (1 << 15)
101 #define CMD_TIMEOUT             (1 << 16)
102 #define DATA_TIMEOUT            (1 << 20)
103 #define CMD_CRC                 (1 << 17)
104 #define DATA_CRC                (1 << 21)
105 #define CARD_ERR                (1 << 28)
106 #define STAT_CLEAR              0xFFFFFFFF
107 #define INIT_STREAM_CMD         0x00000000
108 #define DUAL_VOLT_OCR_BIT       7
109 #define SRC                     (1 << 25)
110 #define SRD                     (1 << 26)
111 #define SOFTRESET               (1 << 1)
112 #define RESETDONE               (1 << 0)
113
114 #define MMC_AUTOSUSPEND_DELAY   100
115 #define MMC_TIMEOUT_MS          20
116 #define OMAP_MMC_MIN_CLOCK      400000
117 #define OMAP_MMC_MAX_CLOCK      52000000
118 #define DRIVER_NAME             "omap_hsmmc"
119
120 /*
121  * One controller can have multiple slots, like on some omap boards using
122  * omap.c controller driver. Luckily this is not currently done on any known
123  * omap_hsmmc.c device.
124  */
125 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
126
127 /*
128  * MMC Host controller read/write API's
129  */
130 #define OMAP_HSMMC_READ(base, reg)      \
131         __raw_readl((base) + OMAP_HSMMC_##reg)
132
133 #define OMAP_HSMMC_WRITE(base, reg, val) \
134         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
135
136 struct omap_hsmmc_next {
137         unsigned int    dma_len;
138         s32             cookie;
139 };
140
141 struct omap_hsmmc_host {
142         struct  device          *dev;
143         struct  mmc_host        *mmc;
144         struct  mmc_request     *mrq;
145         struct  mmc_command     *cmd;
146         struct  mmc_data        *data;
147         struct  clk             *fclk;
148         struct  clk             *dbclk;
149         /*
150          * vcc == configured supply
151          * vcc_aux == optional
152          *   -  MMC1, supply for DAT4..DAT7
153          *   -  MMC2/MMC2, external level shifter voltage supply, for
154          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
155          */
156         struct  regulator       *vcc;
157         struct  regulator       *vcc_aux;
158         void    __iomem         *base;
159         resource_size_t         mapbase;
160         spinlock_t              irq_lock; /* Prevent races with irq handler */
161         unsigned int            dma_len;
162         unsigned int            dma_sg_idx;
163         unsigned char           bus_mode;
164         unsigned char           power_mode;
165         u32                     *buffer;
166         u32                     bytesleft;
167         int                     suspended;
168         int                     irq;
169         int                     use_dma, dma_ch;
170         struct dma_chan         *tx_chan;
171         struct dma_chan         *rx_chan;
172         int                     slot_id;
173         int                     response_busy;
174         int                     context_loss;
175         int                     vdd;
176         int                     protect_card;
177         int                     reqs_blocked;
178         int                     use_reg;
179         int                     req_in_progress;
180         struct omap_hsmmc_next  next_data;
181
182         struct  omap_mmc_platform_data  *pdata;
183 };
184
185 static int omap_hsmmc_card_detect(struct device *dev, int slot)
186 {
187         struct omap_mmc_platform_data *mmc = dev->platform_data;
188
189         /* NOTE: assumes card detect signal is active-low */
190         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
191 }
192
193 static int omap_hsmmc_get_wp(struct device *dev, int slot)
194 {
195         struct omap_mmc_platform_data *mmc = dev->platform_data;
196
197         /* NOTE: assumes write protect signal is active-high */
198         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
199 }
200
201 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
202 {
203         struct omap_mmc_platform_data *mmc = dev->platform_data;
204
205         /* NOTE: assumes card detect signal is active-low */
206         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
207 }
208
209 #ifdef CONFIG_PM
210
211 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
212 {
213         struct omap_mmc_platform_data *mmc = dev->platform_data;
214
215         disable_irq(mmc->slots[0].card_detect_irq);
216         return 0;
217 }
218
219 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
220 {
221         struct omap_mmc_platform_data *mmc = dev->platform_data;
222
223         enable_irq(mmc->slots[0].card_detect_irq);
224         return 0;
225 }
226
227 #else
228
229 #define omap_hsmmc_suspend_cdirq        NULL
230 #define omap_hsmmc_resume_cdirq         NULL
231
232 #endif
233
234 #ifdef CONFIG_REGULATOR
235
236 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
237                                    int vdd)
238 {
239         struct omap_hsmmc_host *host =
240                 platform_get_drvdata(to_platform_device(dev));
241         int ret = 0;
242
243         /*
244          * If we don't see a Vcc regulator, assume it's a fixed
245          * voltage always-on regulator.
246          */
247         if (!host->vcc)
248                 return 0;
249         /*
250          * With DT, never turn OFF the regulator. This is because
251          * the pbias cell programming support is still missing when
252          * booting with Device tree
253          */
254         if (dev->of_node && !vdd)
255                 return 0;
256
257         if (mmc_slot(host).before_set_reg)
258                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
259
260         /*
261          * Assume Vcc regulator is used only to power the card ... OMAP
262          * VDDS is used to power the pins, optionally with a transceiver to
263          * support cards using voltages other than VDDS (1.8V nominal).  When a
264          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
265          *
266          * In some cases this regulator won't support enable/disable;
267          * e.g. it's a fixed rail for a WLAN chip.
268          *
269          * In other cases vcc_aux switches interface power.  Example, for
270          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
271          * chips/cards need an interface voltage rail too.
272          */
273         if (power_on) {
274                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
275                 /* Enable interface voltage rail, if needed */
276                 if (ret == 0 && host->vcc_aux) {
277                         ret = regulator_enable(host->vcc_aux);
278                         if (ret < 0)
279                                 ret = mmc_regulator_set_ocr(host->mmc,
280                                                         host->vcc, 0);
281                 }
282         } else {
283                 /* Shut down the rail */
284                 if (host->vcc_aux)
285                         ret = regulator_disable(host->vcc_aux);
286                 if (!ret) {
287                         /* Then proceed to shut down the local regulator */
288                         ret = mmc_regulator_set_ocr(host->mmc,
289                                                 host->vcc, 0);
290                 }
291         }
292
293         if (mmc_slot(host).after_set_reg)
294                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
295
296         return ret;
297 }
298
299 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
300 {
301         struct regulator *reg;
302         int ocr_value = 0;
303
304         mmc_slot(host).set_power = omap_hsmmc_set_power;
305
306         reg = regulator_get(host->dev, "vmmc");
307         if (IS_ERR(reg)) {
308                 dev_dbg(host->dev, "vmmc regulator missing\n");
309         } else {
310                 host->vcc = reg;
311                 ocr_value = mmc_regulator_get_ocrmask(reg);
312                 if (!mmc_slot(host).ocr_mask) {
313                         mmc_slot(host).ocr_mask = ocr_value;
314                 } else {
315                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
316                                 dev_err(host->dev, "ocrmask %x is not supported\n",
317                                         mmc_slot(host).ocr_mask);
318                                 mmc_slot(host).ocr_mask = 0;
319                                 return -EINVAL;
320                         }
321                 }
322
323                 /* Allow an aux regulator */
324                 reg = regulator_get(host->dev, "vmmc_aux");
325                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
326
327                 /* For eMMC do not power off when not in sleep state */
328                 if (mmc_slot(host).no_regulator_off_init)
329                         return 0;
330                 /*
331                 * UGLY HACK:  workaround regulator framework bugs.
332                 * When the bootloader leaves a supply active, it's
333                 * initialized with zero usecount ... and we can't
334                 * disable it without first enabling it.  Until the
335                 * framework is fixed, we need a workaround like this
336                 * (which is safe for MMC, but not in general).
337                 */
338                 if (regulator_is_enabled(host->vcc) > 0 ||
339                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
340                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
341
342                         mmc_slot(host).set_power(host->dev, host->slot_id,
343                                                  1, vdd);
344                         mmc_slot(host).set_power(host->dev, host->slot_id,
345                                                  0, 0);
346                 }
347         }
348
349         return 0;
350 }
351
352 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
353 {
354         regulator_put(host->vcc);
355         regulator_put(host->vcc_aux);
356         mmc_slot(host).set_power = NULL;
357 }
358
359 static inline int omap_hsmmc_have_reg(void)
360 {
361         return 1;
362 }
363
364 #else
365
366 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
367 {
368         return -EINVAL;
369 }
370
371 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
372 {
373 }
374
375 static inline int omap_hsmmc_have_reg(void)
376 {
377         return 0;
378 }
379
380 #endif
381
382 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
383 {
384         int ret;
385
386         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
387                 if (pdata->slots[0].cover)
388                         pdata->slots[0].get_cover_state =
389                                         omap_hsmmc_get_cover_state;
390                 else
391                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
392                 pdata->slots[0].card_detect_irq =
393                                 gpio_to_irq(pdata->slots[0].switch_pin);
394                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
395                 if (ret)
396                         return ret;
397                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
398                 if (ret)
399                         goto err_free_sp;
400         } else
401                 pdata->slots[0].switch_pin = -EINVAL;
402
403         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
404                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
405                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
406                 if (ret)
407                         goto err_free_cd;
408                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
409                 if (ret)
410                         goto err_free_wp;
411         } else
412                 pdata->slots[0].gpio_wp = -EINVAL;
413
414         return 0;
415
416 err_free_wp:
417         gpio_free(pdata->slots[0].gpio_wp);
418 err_free_cd:
419         if (gpio_is_valid(pdata->slots[0].switch_pin))
420 err_free_sp:
421                 gpio_free(pdata->slots[0].switch_pin);
422         return ret;
423 }
424
425 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
426 {
427         if (gpio_is_valid(pdata->slots[0].gpio_wp))
428                 gpio_free(pdata->slots[0].gpio_wp);
429         if (gpio_is_valid(pdata->slots[0].switch_pin))
430                 gpio_free(pdata->slots[0].switch_pin);
431 }
432
433 /*
434  * Start clock to the card
435  */
436 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
437 {
438         OMAP_HSMMC_WRITE(host->base, SYSCTL,
439                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
440 }
441
442 /*
443  * Stop clock to the card
444  */
445 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
446 {
447         OMAP_HSMMC_WRITE(host->base, SYSCTL,
448                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
449         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
450                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
451 }
452
453 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
454                                   struct mmc_command *cmd)
455 {
456         unsigned int irq_mask;
457
458         if (host->use_dma)
459                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
460         else
461                 irq_mask = INT_EN_MASK;
462
463         /* Disable timeout for erases */
464         if (cmd->opcode == MMC_ERASE)
465                 irq_mask &= ~DTO_ENABLE;
466
467         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
468         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
469         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
470 }
471
472 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
473 {
474         OMAP_HSMMC_WRITE(host->base, ISE, 0);
475         OMAP_HSMMC_WRITE(host->base, IE, 0);
476         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
477 }
478
479 /* Calculate divisor for the given clock frequency */
480 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
481 {
482         u16 dsor = 0;
483
484         if (ios->clock) {
485                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
486                 if (dsor > 250)
487                         dsor = 250;
488         }
489
490         return dsor;
491 }
492
493 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
494 {
495         struct mmc_ios *ios = &host->mmc->ios;
496         unsigned long regval;
497         unsigned long timeout;
498
499         dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
500
501         omap_hsmmc_stop_clock(host);
502
503         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
504         regval = regval & ~(CLKD_MASK | DTO_MASK);
505         regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
506         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
507         OMAP_HSMMC_WRITE(host->base, SYSCTL,
508                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
509
510         /* Wait till the ICS bit is set */
511         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
512         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
513                 && time_before(jiffies, timeout))
514                 cpu_relax();
515
516         omap_hsmmc_start_clock(host);
517 }
518
519 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
520 {
521         struct mmc_ios *ios = &host->mmc->ios;
522         u32 con;
523
524         con = OMAP_HSMMC_READ(host->base, CON);
525         if (ios->timing == MMC_TIMING_UHS_DDR50)
526                 con |= DDR;     /* configure in DDR mode */
527         else
528                 con &= ~DDR;
529         switch (ios->bus_width) {
530         case MMC_BUS_WIDTH_8:
531                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
532                 break;
533         case MMC_BUS_WIDTH_4:
534                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
535                 OMAP_HSMMC_WRITE(host->base, HCTL,
536                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
537                 break;
538         case MMC_BUS_WIDTH_1:
539                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
540                 OMAP_HSMMC_WRITE(host->base, HCTL,
541                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
542                 break;
543         }
544 }
545
546 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
547 {
548         struct mmc_ios *ios = &host->mmc->ios;
549         u32 con;
550
551         con = OMAP_HSMMC_READ(host->base, CON);
552         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
553                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
554         else
555                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
556 }
557
558 #ifdef CONFIG_PM
559
560 /*
561  * Restore the MMC host context, if it was lost as result of a
562  * power state change.
563  */
564 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
565 {
566         struct mmc_ios *ios = &host->mmc->ios;
567         struct omap_mmc_platform_data *pdata = host->pdata;
568         int context_loss = 0;
569         u32 hctl, capa;
570         unsigned long timeout;
571
572         if (pdata->get_context_loss_count) {
573                 context_loss = pdata->get_context_loss_count(host->dev);
574                 if (context_loss < 0)
575                         return 1;
576         }
577
578         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
579                 context_loss == host->context_loss ? "not " : "");
580         if (host->context_loss == context_loss)
581                 return 1;
582
583         /* Wait for hardware reset */
584         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
585         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
586                 && time_before(jiffies, timeout))
587                 ;
588
589         /* Do software reset */
590         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
591         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
592         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
593                 && time_before(jiffies, timeout))
594                 ;
595
596         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
597                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
598
599         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
600                 if (host->power_mode != MMC_POWER_OFF &&
601                     (1 << ios->vdd) <= MMC_VDD_23_24)
602                         hctl = SDVS18;
603                 else
604                         hctl = SDVS30;
605                 capa = VS30 | VS18;
606         } else {
607                 hctl = SDVS18;
608                 capa = VS18;
609         }
610
611         OMAP_HSMMC_WRITE(host->base, HCTL,
612                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
613
614         OMAP_HSMMC_WRITE(host->base, CAPA,
615                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
616
617         OMAP_HSMMC_WRITE(host->base, HCTL,
618                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
619
620         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
621         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
622                 && time_before(jiffies, timeout))
623                 ;
624
625         omap_hsmmc_disable_irq(host);
626
627         /* Do not initialize card-specific things if the power is off */
628         if (host->power_mode == MMC_POWER_OFF)
629                 goto out;
630
631         omap_hsmmc_set_bus_width(host);
632
633         omap_hsmmc_set_clock(host);
634
635         omap_hsmmc_set_bus_mode(host);
636
637 out:
638         host->context_loss = context_loss;
639
640         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
641         return 0;
642 }
643
644 /*
645  * Save the MMC host context (store the number of power state changes so far).
646  */
647 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
648 {
649         struct omap_mmc_platform_data *pdata = host->pdata;
650         int context_loss;
651
652         if (pdata->get_context_loss_count) {
653                 context_loss = pdata->get_context_loss_count(host->dev);
654                 if (context_loss < 0)
655                         return;
656                 host->context_loss = context_loss;
657         }
658 }
659
660 #else
661
662 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
663 {
664         return 0;
665 }
666
667 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
668 {
669 }
670
671 #endif
672
673 /*
674  * Send init stream sequence to card
675  * before sending IDLE command
676  */
677 static void send_init_stream(struct omap_hsmmc_host *host)
678 {
679         int reg = 0;
680         unsigned long timeout;
681
682         if (host->protect_card)
683                 return;
684
685         disable_irq(host->irq);
686
687         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
688         OMAP_HSMMC_WRITE(host->base, CON,
689                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
690         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
691
692         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
693         while ((reg != CC) && time_before(jiffies, timeout))
694                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
695
696         OMAP_HSMMC_WRITE(host->base, CON,
697                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
698
699         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
700         OMAP_HSMMC_READ(host->base, STAT);
701
702         enable_irq(host->irq);
703 }
704
705 static inline
706 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
707 {
708         int r = 1;
709
710         if (mmc_slot(host).get_cover_state)
711                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
712         return r;
713 }
714
715 static ssize_t
716 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
717                            char *buf)
718 {
719         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
720         struct omap_hsmmc_host *host = mmc_priv(mmc);
721
722         return sprintf(buf, "%s\n",
723                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
724 }
725
726 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
727
728 static ssize_t
729 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
730                         char *buf)
731 {
732         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
733         struct omap_hsmmc_host *host = mmc_priv(mmc);
734
735         return sprintf(buf, "%s\n", mmc_slot(host).name);
736 }
737
738 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
739
740 /*
741  * Configure the response type and send the cmd.
742  */
743 static void
744 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
745         struct mmc_data *data)
746 {
747         int cmdreg = 0, resptype = 0, cmdtype = 0;
748
749         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
750                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
751         host->cmd = cmd;
752
753         omap_hsmmc_enable_irq(host, cmd);
754
755         host->response_busy = 0;
756         if (cmd->flags & MMC_RSP_PRESENT) {
757                 if (cmd->flags & MMC_RSP_136)
758                         resptype = 1;
759                 else if (cmd->flags & MMC_RSP_BUSY) {
760                         resptype = 3;
761                         host->response_busy = 1;
762                 } else
763                         resptype = 2;
764         }
765
766         /*
767          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
768          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
769          * a val of 0x3, rest 0x0.
770          */
771         if (cmd == host->mrq->stop)
772                 cmdtype = 0x3;
773
774         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
775
776         if (data) {
777                 cmdreg |= DP_SELECT | MSBS | BCE;
778                 if (data->flags & MMC_DATA_READ)
779                         cmdreg |= DDIR;
780                 else
781                         cmdreg &= ~(DDIR);
782         }
783
784         if (host->use_dma)
785                 cmdreg |= DMA_EN;
786
787         host->req_in_progress = 1;
788
789         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
790         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
791 }
792
793 static int
794 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
795 {
796         if (data->flags & MMC_DATA_WRITE)
797                 return DMA_TO_DEVICE;
798         else
799                 return DMA_FROM_DEVICE;
800 }
801
802 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
803         struct mmc_data *data)
804 {
805         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
806 }
807
808 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
809 {
810         int dma_ch;
811         unsigned long flags;
812
813         spin_lock_irqsave(&host->irq_lock, flags);
814         host->req_in_progress = 0;
815         dma_ch = host->dma_ch;
816         spin_unlock_irqrestore(&host->irq_lock, flags);
817
818         omap_hsmmc_disable_irq(host);
819         /* Do not complete the request if DMA is still in progress */
820         if (mrq->data && host->use_dma && dma_ch != -1)
821                 return;
822         host->mrq = NULL;
823         mmc_request_done(host->mmc, mrq);
824 }
825
826 /*
827  * Notify the transfer complete to MMC core
828  */
829 static void
830 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
831 {
832         if (!data) {
833                 struct mmc_request *mrq = host->mrq;
834
835                 /* TC before CC from CMD6 - don't know why, but it happens */
836                 if (host->cmd && host->cmd->opcode == 6 &&
837                     host->response_busy) {
838                         host->response_busy = 0;
839                         return;
840                 }
841
842                 omap_hsmmc_request_done(host, mrq);
843                 return;
844         }
845
846         host->data = NULL;
847
848         if (!data->error)
849                 data->bytes_xfered += data->blocks * (data->blksz);
850         else
851                 data->bytes_xfered = 0;
852
853         if (!data->stop) {
854                 omap_hsmmc_request_done(host, data->mrq);
855                 return;
856         }
857         omap_hsmmc_start_command(host, data->stop, NULL);
858 }
859
860 /*
861  * Notify the core about command completion
862  */
863 static void
864 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
865 {
866         host->cmd = NULL;
867
868         if (cmd->flags & MMC_RSP_PRESENT) {
869                 if (cmd->flags & MMC_RSP_136) {
870                         /* response type 2 */
871                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
872                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
873                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
874                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
875                 } else {
876                         /* response types 1, 1b, 3, 4, 5, 6 */
877                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
878                 }
879         }
880         if ((host->data == NULL && !host->response_busy) || cmd->error)
881                 omap_hsmmc_request_done(host, cmd->mrq);
882 }
883
884 /*
885  * DMA clean up for command errors
886  */
887 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
888 {
889         int dma_ch;
890         unsigned long flags;
891
892         host->data->error = errno;
893
894         spin_lock_irqsave(&host->irq_lock, flags);
895         dma_ch = host->dma_ch;
896         host->dma_ch = -1;
897         spin_unlock_irqrestore(&host->irq_lock, flags);
898
899         if (host->use_dma && dma_ch != -1) {
900                 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
901
902                 dmaengine_terminate_all(chan);
903                 dma_unmap_sg(chan->device->dev,
904                         host->data->sg, host->data->sg_len,
905                         omap_hsmmc_get_dma_dir(host, host->data));
906
907                 host->data->host_cookie = 0;
908         }
909         host->data = NULL;
910 }
911
912 /*
913  * Readable error output
914  */
915 #ifdef CONFIG_MMC_DEBUG
916 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
917 {
918         /* --- means reserved bit without definition at documentation */
919         static const char *omap_hsmmc_status_bits[] = {
920                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
921                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
922                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
923                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
924         };
925         char res[256];
926         char *buf = res;
927         int len, i;
928
929         len = sprintf(buf, "MMC IRQ 0x%x :", status);
930         buf += len;
931
932         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
933                 if (status & (1 << i)) {
934                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
935                         buf += len;
936                 }
937
938         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
939 }
940 #else
941 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
942                                              u32 status)
943 {
944 }
945 #endif  /* CONFIG_MMC_DEBUG */
946
947 /*
948  * MMC controller internal state machines reset
949  *
950  * Used to reset command or data internal state machines, using respectively
951  *  SRC or SRD bit of SYSCTL register
952  * Can be called from interrupt context
953  */
954 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
955                                                    unsigned long bit)
956 {
957         unsigned long i = 0;
958         unsigned long limit = (loops_per_jiffy *
959                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
960
961         OMAP_HSMMC_WRITE(host->base, SYSCTL,
962                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
963
964         /*
965          * OMAP4 ES2 and greater has an updated reset logic.
966          * Monitor a 0->1 transition first
967          */
968         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
969                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
970                                         && (i++ < limit))
971                         cpu_relax();
972         }
973         i = 0;
974
975         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
976                 (i++ < limit))
977                 cpu_relax();
978
979         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
980                 dev_err(mmc_dev(host->mmc),
981                         "Timeout waiting on controller reset in %s\n",
982                         __func__);
983 }
984
985 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
986 {
987         struct mmc_data *data;
988         int end_cmd = 0, end_trans = 0;
989
990         if (!host->req_in_progress) {
991                 do {
992                         OMAP_HSMMC_WRITE(host->base, STAT, status);
993                         /* Flush posted write */
994                         status = OMAP_HSMMC_READ(host->base, STAT);
995                 } while (status & INT_EN_MASK);
996                 return;
997         }
998
999         data = host->data;
1000         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1001
1002         if (status & ERR) {
1003                 omap_hsmmc_dbg_report_irq(host, status);
1004                 if ((status & CMD_TIMEOUT) ||
1005                         (status & CMD_CRC)) {
1006                         if (host->cmd) {
1007                                 if (status & CMD_TIMEOUT) {
1008                                         omap_hsmmc_reset_controller_fsm(host,
1009                                                                         SRC);
1010                                         host->cmd->error = -ETIMEDOUT;
1011                                 } else {
1012                                         host->cmd->error = -EILSEQ;
1013                                 }
1014                                 end_cmd = 1;
1015                         }
1016                         if (host->data || host->response_busy) {
1017                                 if (host->data)
1018                                         omap_hsmmc_dma_cleanup(host,
1019                                                                 -ETIMEDOUT);
1020                                 host->response_busy = 0;
1021                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1022                         }
1023                 }
1024                 if ((status & DATA_TIMEOUT) ||
1025                         (status & DATA_CRC)) {
1026                         if (host->data || host->response_busy) {
1027                                 int err = (status & DATA_TIMEOUT) ?
1028                                                 -ETIMEDOUT : -EILSEQ;
1029
1030                                 if (host->data)
1031                                         omap_hsmmc_dma_cleanup(host, err);
1032                                 else
1033                                         host->mrq->cmd->error = err;
1034                                 host->response_busy = 0;
1035                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1036                                 end_trans = 1;
1037                         }
1038                 }
1039                 if (status & CARD_ERR) {
1040                         dev_dbg(mmc_dev(host->mmc),
1041                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1042                         if (host->cmd)
1043                                 end_cmd = 1;
1044                         if (host->data)
1045                                 end_trans = 1;
1046                 }
1047         }
1048
1049         OMAP_HSMMC_WRITE(host->base, STAT, status);
1050
1051         if (end_cmd || ((status & CC) && host->cmd))
1052                 omap_hsmmc_cmd_done(host, host->cmd);
1053         if ((end_trans || (status & TC)) && host->mrq)
1054                 omap_hsmmc_xfer_done(host, data);
1055 }
1056
1057 /*
1058  * MMC controller IRQ handler
1059  */
1060 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1061 {
1062         struct omap_hsmmc_host *host = dev_id;
1063         int status;
1064
1065         status = OMAP_HSMMC_READ(host->base, STAT);
1066         do {
1067                 omap_hsmmc_do_irq(host, status);
1068                 /* Flush posted write */
1069                 status = OMAP_HSMMC_READ(host->base, STAT);
1070         } while (status & INT_EN_MASK);
1071
1072         return IRQ_HANDLED;
1073 }
1074
1075 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1076 {
1077         unsigned long i;
1078
1079         OMAP_HSMMC_WRITE(host->base, HCTL,
1080                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1081         for (i = 0; i < loops_per_jiffy; i++) {
1082                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1083                         break;
1084                 cpu_relax();
1085         }
1086 }
1087
1088 /*
1089  * Switch MMC interface voltage ... only relevant for MMC1.
1090  *
1091  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1092  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1093  * Some chips, like eMMC ones, use internal transceivers.
1094  */
1095 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1096 {
1097         u32 reg_val = 0;
1098         int ret;
1099
1100         /* Disable the clocks */
1101         pm_runtime_put_sync(host->dev);
1102         if (host->dbclk)
1103                 clk_disable(host->dbclk);
1104
1105         /* Turn the power off */
1106         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1107
1108         /* Turn the power ON with given VDD 1.8 or 3.0v */
1109         if (!ret)
1110                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1111                                                vdd);
1112         pm_runtime_get_sync(host->dev);
1113         if (host->dbclk)
1114                 clk_enable(host->dbclk);
1115
1116         if (ret != 0)
1117                 goto err;
1118
1119         OMAP_HSMMC_WRITE(host->base, HCTL,
1120                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1121         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1122
1123         /*
1124          * If a MMC dual voltage card is detected, the set_ios fn calls
1125          * this fn with VDD bit set for 1.8V. Upon card removal from the
1126          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1127          *
1128          * Cope with a bit of slop in the range ... per data sheets:
1129          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1130          *    but recommended values are 1.71V to 1.89V
1131          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1132          *    but recommended values are 2.7V to 3.3V
1133          *
1134          * Board setup code shouldn't permit anything very out-of-range.
1135          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1136          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1137          */
1138         if ((1 << vdd) <= MMC_VDD_23_24)
1139                 reg_val |= SDVS18;
1140         else
1141                 reg_val |= SDVS30;
1142
1143         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1144         set_sd_bus_power(host);
1145
1146         return 0;
1147 err:
1148         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1149         return ret;
1150 }
1151
1152 /* Protect the card while the cover is open */
1153 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1154 {
1155         if (!mmc_slot(host).get_cover_state)
1156                 return;
1157
1158         host->reqs_blocked = 0;
1159         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1160                 if (host->protect_card) {
1161                         dev_info(host->dev, "%s: cover is closed, "
1162                                          "card is now accessible\n",
1163                                          mmc_hostname(host->mmc));
1164                         host->protect_card = 0;
1165                 }
1166         } else {
1167                 if (!host->protect_card) {
1168                         dev_info(host->dev, "%s: cover is open, "
1169                                          "card is now inaccessible\n",
1170                                          mmc_hostname(host->mmc));
1171                         host->protect_card = 1;
1172                 }
1173         }
1174 }
1175
1176 /*
1177  * irq handler to notify the core about card insertion/removal
1178  */
1179 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1180 {
1181         struct omap_hsmmc_host *host = dev_id;
1182         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1183         int carddetect;
1184
1185         if (host->suspended)
1186                 return IRQ_HANDLED;
1187
1188         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1189
1190         if (slot->card_detect)
1191                 carddetect = slot->card_detect(host->dev, host->slot_id);
1192         else {
1193                 omap_hsmmc_protect_card(host);
1194                 carddetect = -ENOSYS;
1195         }
1196
1197         if (carddetect)
1198                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1199         else
1200                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1201         return IRQ_HANDLED;
1202 }
1203
1204 static void omap_hsmmc_dma_callback(void *param)
1205 {
1206         struct omap_hsmmc_host *host = param;
1207         struct dma_chan *chan;
1208         struct mmc_data *data;
1209         int req_in_progress;
1210
1211         spin_lock_irq(&host->irq_lock);
1212         if (host->dma_ch < 0) {
1213                 spin_unlock_irq(&host->irq_lock);
1214                 return;
1215         }
1216
1217         data = host->mrq->data;
1218         chan = omap_hsmmc_get_dma_chan(host, data);
1219         if (!data->host_cookie)
1220                 dma_unmap_sg(chan->device->dev,
1221                              data->sg, data->sg_len,
1222                              omap_hsmmc_get_dma_dir(host, data));
1223
1224         req_in_progress = host->req_in_progress;
1225         host->dma_ch = -1;
1226         spin_unlock_irq(&host->irq_lock);
1227
1228         /* If DMA has finished after TC, complete the request */
1229         if (!req_in_progress) {
1230                 struct mmc_request *mrq = host->mrq;
1231
1232                 host->mrq = NULL;
1233                 mmc_request_done(host->mmc, mrq);
1234         }
1235 }
1236
1237 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1238                                        struct mmc_data *data,
1239                                        struct omap_hsmmc_next *next,
1240                                        struct dma_chan *chan)
1241 {
1242         int dma_len;
1243
1244         if (!next && data->host_cookie &&
1245             data->host_cookie != host->next_data.cookie) {
1246                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1247                        " host->next_data.cookie %d\n",
1248                        __func__, data->host_cookie, host->next_data.cookie);
1249                 data->host_cookie = 0;
1250         }
1251
1252         /* Check if next job is already prepared */
1253         if (next ||
1254             (!next && data->host_cookie != host->next_data.cookie)) {
1255                 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1256                                      omap_hsmmc_get_dma_dir(host, data));
1257
1258         } else {
1259                 dma_len = host->next_data.dma_len;
1260                 host->next_data.dma_len = 0;
1261         }
1262
1263
1264         if (dma_len == 0)
1265                 return -EINVAL;
1266
1267         if (next) {
1268                 next->dma_len = dma_len;
1269                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1270         } else
1271                 host->dma_len = dma_len;
1272
1273         return 0;
1274 }
1275
1276 /*
1277  * Routine to configure and start DMA for the MMC card
1278  */
1279 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1280                                         struct mmc_request *req)
1281 {
1282         struct dma_slave_config cfg;
1283         struct dma_async_tx_descriptor *tx;
1284         int ret = 0, i;
1285         struct mmc_data *data = req->data;
1286         struct dma_chan *chan;
1287
1288         /* Sanity check: all the SG entries must be aligned by block size. */
1289         for (i = 0; i < data->sg_len; i++) {
1290                 struct scatterlist *sgl;
1291
1292                 sgl = data->sg + i;
1293                 if (sgl->length % data->blksz)
1294                         return -EINVAL;
1295         }
1296         if ((data->blksz % 4) != 0)
1297                 /* REVISIT: The MMC buffer increments only when MSB is written.
1298                  * Return error for blksz which is non multiple of four.
1299                  */
1300                 return -EINVAL;
1301
1302         BUG_ON(host->dma_ch != -1);
1303
1304         chan = omap_hsmmc_get_dma_chan(host, data);
1305
1306         cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1307         cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1308         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1309         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1310         cfg.src_maxburst = data->blksz / 4;
1311         cfg.dst_maxburst = data->blksz / 4;
1312
1313         ret = dmaengine_slave_config(chan, &cfg);
1314         if (ret)
1315                 return ret;
1316
1317         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1318         if (ret)
1319                 return ret;
1320
1321         tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1322                 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1323                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1324         if (!tx) {
1325                 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1326                 /* FIXME: cleanup */
1327                 return -1;
1328         }
1329
1330         tx->callback = omap_hsmmc_dma_callback;
1331         tx->callback_param = host;
1332
1333         /* Does not fail */
1334         dmaengine_submit(tx);
1335
1336         host->dma_ch = 1;
1337
1338         dma_async_issue_pending(chan);
1339
1340         return 0;
1341 }
1342
1343 static void set_data_timeout(struct omap_hsmmc_host *host,
1344                              unsigned int timeout_ns,
1345                              unsigned int timeout_clks)
1346 {
1347         unsigned int timeout, cycle_ns;
1348         uint32_t reg, clkd, dto = 0;
1349
1350         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1351         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1352         if (clkd == 0)
1353                 clkd = 1;
1354
1355         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1356         timeout = timeout_ns / cycle_ns;
1357         timeout += timeout_clks;
1358         if (timeout) {
1359                 while ((timeout & 0x80000000) == 0) {
1360                         dto += 1;
1361                         timeout <<= 1;
1362                 }
1363                 dto = 31 - dto;
1364                 timeout <<= 1;
1365                 if (timeout && dto)
1366                         dto += 1;
1367                 if (dto >= 13)
1368                         dto -= 13;
1369                 else
1370                         dto = 0;
1371                 if (dto > 14)
1372                         dto = 14;
1373         }
1374
1375         reg &= ~DTO_MASK;
1376         reg |= dto << DTO_SHIFT;
1377         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1378 }
1379
1380 /*
1381  * Configure block length for MMC/SD cards and initiate the transfer.
1382  */
1383 static int
1384 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1385 {
1386         int ret;
1387         host->data = req->data;
1388
1389         if (req->data == NULL) {
1390                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1391                 /*
1392                  * Set an arbitrary 100ms data timeout for commands with
1393                  * busy signal.
1394                  */
1395                 if (req->cmd->flags & MMC_RSP_BUSY)
1396                         set_data_timeout(host, 100000000U, 0);
1397                 return 0;
1398         }
1399
1400         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1401                                         | (req->data->blocks << 16));
1402         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1403
1404         if (host->use_dma) {
1405                 ret = omap_hsmmc_start_dma_transfer(host, req);
1406                 if (ret != 0) {
1407                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1408                         return ret;
1409                 }
1410         }
1411         return 0;
1412 }
1413
1414 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1415                                 int err)
1416 {
1417         struct omap_hsmmc_host *host = mmc_priv(mmc);
1418         struct mmc_data *data = mrq->data;
1419
1420         if (host->use_dma && data->host_cookie) {
1421                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1422
1423                 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1424                              omap_hsmmc_get_dma_dir(host, data));
1425                 data->host_cookie = 0;
1426         }
1427 }
1428
1429 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1430                                bool is_first_req)
1431 {
1432         struct omap_hsmmc_host *host = mmc_priv(mmc);
1433
1434         if (mrq->data->host_cookie) {
1435                 mrq->data->host_cookie = 0;
1436                 return ;
1437         }
1438
1439         if (host->use_dma) {
1440                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1441
1442                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1443                                                 &host->next_data, c))
1444                         mrq->data->host_cookie = 0;
1445         }
1446 }
1447
1448 /*
1449  * Request function. for read/write operation
1450  */
1451 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1452 {
1453         struct omap_hsmmc_host *host = mmc_priv(mmc);
1454         int err;
1455
1456         BUG_ON(host->req_in_progress);
1457         BUG_ON(host->dma_ch != -1);
1458         if (host->protect_card) {
1459                 if (host->reqs_blocked < 3) {
1460                         /*
1461                          * Ensure the controller is left in a consistent
1462                          * state by resetting the command and data state
1463                          * machines.
1464                          */
1465                         omap_hsmmc_reset_controller_fsm(host, SRD);
1466                         omap_hsmmc_reset_controller_fsm(host, SRC);
1467                         host->reqs_blocked += 1;
1468                 }
1469                 req->cmd->error = -EBADF;
1470                 if (req->data)
1471                         req->data->error = -EBADF;
1472                 req->cmd->retries = 0;
1473                 mmc_request_done(mmc, req);
1474                 return;
1475         } else if (host->reqs_blocked)
1476                 host->reqs_blocked = 0;
1477         WARN_ON(host->mrq != NULL);
1478         host->mrq = req;
1479         err = omap_hsmmc_prepare_data(host, req);
1480         if (err) {
1481                 req->cmd->error = err;
1482                 if (req->data)
1483                         req->data->error = err;
1484                 host->mrq = NULL;
1485                 mmc_request_done(mmc, req);
1486                 return;
1487         }
1488
1489         omap_hsmmc_start_command(host, req->cmd, req->data);
1490 }
1491
1492 /* Routine to configure clock values. Exposed API to core */
1493 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1494 {
1495         struct omap_hsmmc_host *host = mmc_priv(mmc);
1496         int do_send_init_stream = 0;
1497
1498         pm_runtime_get_sync(host->dev);
1499
1500         if (ios->power_mode != host->power_mode) {
1501                 switch (ios->power_mode) {
1502                 case MMC_POWER_OFF:
1503                         mmc_slot(host).set_power(host->dev, host->slot_id,
1504                                                  0, 0);
1505                         host->vdd = 0;
1506                         break;
1507                 case MMC_POWER_UP:
1508                         mmc_slot(host).set_power(host->dev, host->slot_id,
1509                                                  1, ios->vdd);
1510                         host->vdd = ios->vdd;
1511                         break;
1512                 case MMC_POWER_ON:
1513                         do_send_init_stream = 1;
1514                         break;
1515                 }
1516                 host->power_mode = ios->power_mode;
1517         }
1518
1519         /* FIXME: set registers based only on changes to ios */
1520
1521         omap_hsmmc_set_bus_width(host);
1522
1523         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1524                 /* Only MMC1 can interface at 3V without some flavor
1525                  * of external transceiver; but they all handle 1.8V.
1526                  */
1527                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1528                         (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1529                         /*
1530                          * With pbias cell programming missing, this
1531                          * can't be allowed when booting with device
1532                          * tree.
1533                          */
1534                         !host->dev->of_node) {
1535                                 /*
1536                                  * The mmc_select_voltage fn of the core does
1537                                  * not seem to set the power_mode to
1538                                  * MMC_POWER_UP upon recalculating the voltage.
1539                                  * vdd 1.8v.
1540                                  */
1541                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1542                                 dev_dbg(mmc_dev(host->mmc),
1543                                                 "Switch operation failed\n");
1544                 }
1545         }
1546
1547         omap_hsmmc_set_clock(host);
1548
1549         if (do_send_init_stream)
1550                 send_init_stream(host);
1551
1552         omap_hsmmc_set_bus_mode(host);
1553
1554         pm_runtime_put_autosuspend(host->dev);
1555 }
1556
1557 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1558 {
1559         struct omap_hsmmc_host *host = mmc_priv(mmc);
1560
1561         if (!mmc_slot(host).card_detect)
1562                 return -ENOSYS;
1563         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1564 }
1565
1566 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1567 {
1568         struct omap_hsmmc_host *host = mmc_priv(mmc);
1569
1570         if (!mmc_slot(host).get_ro)
1571                 return -ENOSYS;
1572         return mmc_slot(host).get_ro(host->dev, 0);
1573 }
1574
1575 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1576 {
1577         struct omap_hsmmc_host *host = mmc_priv(mmc);
1578
1579         if (mmc_slot(host).init_card)
1580                 mmc_slot(host).init_card(card);
1581 }
1582
1583 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1584 {
1585         u32 hctl, capa, value;
1586
1587         /* Only MMC1 supports 3.0V */
1588         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1589                 hctl = SDVS30;
1590                 capa = VS30 | VS18;
1591         } else {
1592                 hctl = SDVS18;
1593                 capa = VS18;
1594         }
1595
1596         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1597         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1598
1599         value = OMAP_HSMMC_READ(host->base, CAPA);
1600         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1601
1602         /* Set the controller to AUTO IDLE mode */
1603         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1604         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1605
1606         /* Set SD bus power bit */
1607         set_sd_bus_power(host);
1608 }
1609
1610 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1611 {
1612         struct omap_hsmmc_host *host = mmc_priv(mmc);
1613
1614         pm_runtime_get_sync(host->dev);
1615
1616         return 0;
1617 }
1618
1619 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1620 {
1621         struct omap_hsmmc_host *host = mmc_priv(mmc);
1622
1623         pm_runtime_mark_last_busy(host->dev);
1624         pm_runtime_put_autosuspend(host->dev);
1625
1626         return 0;
1627 }
1628
1629 static const struct mmc_host_ops omap_hsmmc_ops = {
1630         .enable = omap_hsmmc_enable_fclk,
1631         .disable = omap_hsmmc_disable_fclk,
1632         .post_req = omap_hsmmc_post_req,
1633         .pre_req = omap_hsmmc_pre_req,
1634         .request = omap_hsmmc_request,
1635         .set_ios = omap_hsmmc_set_ios,
1636         .get_cd = omap_hsmmc_get_cd,
1637         .get_ro = omap_hsmmc_get_ro,
1638         .init_card = omap_hsmmc_init_card,
1639         /* NYET -- enable_sdio_irq */
1640 };
1641
1642 #ifdef CONFIG_DEBUG_FS
1643
1644 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1645 {
1646         struct mmc_host *mmc = s->private;
1647         struct omap_hsmmc_host *host = mmc_priv(mmc);
1648         int context_loss = 0;
1649
1650         if (host->pdata->get_context_loss_count)
1651                 context_loss = host->pdata->get_context_loss_count(host->dev);
1652
1653         seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1654                         mmc->index, host->context_loss, context_loss);
1655
1656         if (host->suspended) {
1657                 seq_printf(s, "host suspended, can't read registers\n");
1658                 return 0;
1659         }
1660
1661         pm_runtime_get_sync(host->dev);
1662
1663         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1664                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1665         seq_printf(s, "CON:\t\t0x%08x\n",
1666                         OMAP_HSMMC_READ(host->base, CON));
1667         seq_printf(s, "HCTL:\t\t0x%08x\n",
1668                         OMAP_HSMMC_READ(host->base, HCTL));
1669         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1670                         OMAP_HSMMC_READ(host->base, SYSCTL));
1671         seq_printf(s, "IE:\t\t0x%08x\n",
1672                         OMAP_HSMMC_READ(host->base, IE));
1673         seq_printf(s, "ISE:\t\t0x%08x\n",
1674                         OMAP_HSMMC_READ(host->base, ISE));
1675         seq_printf(s, "CAPA:\t\t0x%08x\n",
1676                         OMAP_HSMMC_READ(host->base, CAPA));
1677
1678         pm_runtime_mark_last_busy(host->dev);
1679         pm_runtime_put_autosuspend(host->dev);
1680
1681         return 0;
1682 }
1683
1684 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1685 {
1686         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1687 }
1688
1689 static const struct file_operations mmc_regs_fops = {
1690         .open           = omap_hsmmc_regs_open,
1691         .read           = seq_read,
1692         .llseek         = seq_lseek,
1693         .release        = single_release,
1694 };
1695
1696 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1697 {
1698         if (mmc->debugfs_root)
1699                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1700                         mmc, &mmc_regs_fops);
1701 }
1702
1703 #else
1704
1705 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1706 {
1707 }
1708
1709 #endif
1710
1711 #ifdef CONFIG_OF
1712 static u16 omap4_reg_offset = 0x100;
1713
1714 static const struct of_device_id omap_mmc_of_match[] = {
1715         {
1716                 .compatible = "ti,omap2-hsmmc",
1717         },
1718         {
1719                 .compatible = "ti,omap3-hsmmc",
1720         },
1721         {
1722                 .compatible = "ti,omap4-hsmmc",
1723                 .data = &omap4_reg_offset,
1724         },
1725         {},
1726 };
1727 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1728
1729 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1730 {
1731         struct omap_mmc_platform_data *pdata;
1732         struct device_node *np = dev->of_node;
1733         u32 bus_width;
1734
1735         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1736         if (!pdata)
1737                 return NULL; /* out of memory */
1738
1739         if (of_find_property(np, "ti,dual-volt", NULL))
1740                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1741
1742         /* This driver only supports 1 slot */
1743         pdata->nr_slots = 1;
1744         pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1745         pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1746
1747         if (of_find_property(np, "ti,non-removable", NULL)) {
1748                 pdata->slots[0].nonremovable = true;
1749                 pdata->slots[0].no_regulator_off_init = true;
1750         }
1751         of_property_read_u32(np, "bus-width", &bus_width);
1752         if (bus_width == 4)
1753                 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1754         else if (bus_width == 8)
1755                 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1756
1757         if (of_find_property(np, "ti,needs-special-reset", NULL))
1758                 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1759
1760         return pdata;
1761 }
1762 #else
1763 static inline struct omap_mmc_platform_data
1764                         *of_get_hsmmc_pdata(struct device *dev)
1765 {
1766         return NULL;
1767 }
1768 #endif
1769
1770 static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
1771 {
1772         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1773         struct mmc_host *mmc;
1774         struct omap_hsmmc_host *host = NULL;
1775         struct resource *res;
1776         int ret, irq;
1777         const struct of_device_id *match;
1778         dma_cap_mask_t mask;
1779         unsigned tx_req, rx_req;
1780
1781         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1782         if (match) {
1783                 pdata = of_get_hsmmc_pdata(&pdev->dev);
1784                 if (match->data) {
1785                         u16 *offsetp = match->data;
1786                         pdata->reg_offset = *offsetp;
1787                 }
1788         }
1789
1790         if (pdata == NULL) {
1791                 dev_err(&pdev->dev, "Platform Data is missing\n");
1792                 return -ENXIO;
1793         }
1794
1795         if (pdata->nr_slots == 0) {
1796                 dev_err(&pdev->dev, "No Slots\n");
1797                 return -ENXIO;
1798         }
1799
1800         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1801         irq = platform_get_irq(pdev, 0);
1802         if (res == NULL || irq < 0)
1803                 return -ENXIO;
1804
1805         res = request_mem_region(res->start, resource_size(res), pdev->name);
1806         if (res == NULL)
1807                 return -EBUSY;
1808
1809         ret = omap_hsmmc_gpio_init(pdata);
1810         if (ret)
1811                 goto err;
1812
1813         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1814         if (!mmc) {
1815                 ret = -ENOMEM;
1816                 goto err_alloc;
1817         }
1818
1819         host            = mmc_priv(mmc);
1820         host->mmc       = mmc;
1821         host->pdata     = pdata;
1822         host->dev       = &pdev->dev;
1823         host->use_dma   = 1;
1824         host->dma_ch    = -1;
1825         host->irq       = irq;
1826         host->slot_id   = 0;
1827         host->mapbase   = res->start + pdata->reg_offset;
1828         host->base      = ioremap(host->mapbase, SZ_4K);
1829         host->power_mode = MMC_POWER_OFF;
1830         host->next_data.cookie = 1;
1831
1832         platform_set_drvdata(pdev, host);
1833
1834         mmc->ops        = &omap_hsmmc_ops;
1835
1836         /*
1837          * If regulator_disable can only put vcc_aux to sleep then there is
1838          * no off state.
1839          */
1840         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1841                 mmc_slot(host).no_off = 1;
1842
1843         mmc->f_min = OMAP_MMC_MIN_CLOCK;
1844
1845         if (pdata->max_freq > 0)
1846                 mmc->f_max = pdata->max_freq;
1847         else
1848                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1849
1850         spin_lock_init(&host->irq_lock);
1851
1852         host->fclk = clk_get(&pdev->dev, "fck");
1853         if (IS_ERR(host->fclk)) {
1854                 ret = PTR_ERR(host->fclk);
1855                 host->fclk = NULL;
1856                 goto err1;
1857         }
1858
1859         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1860                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1861                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1862         }
1863
1864         pm_runtime_enable(host->dev);
1865         pm_runtime_get_sync(host->dev);
1866         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1867         pm_runtime_use_autosuspend(host->dev);
1868
1869         omap_hsmmc_context_save(host);
1870
1871         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1872         /*
1873          * MMC can still work without debounce clock.
1874          */
1875         if (IS_ERR(host->dbclk)) {
1876                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n");
1877                 host->dbclk = NULL;
1878         } else if (clk_enable(host->dbclk) != 0) {
1879                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1880                 clk_put(host->dbclk);
1881                 host->dbclk = NULL;
1882         }
1883
1884         /* Since we do only SG emulation, we can have as many segs
1885          * as we want. */
1886         mmc->max_segs = 1024;
1887
1888         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1889         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1890         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1891         mmc->max_seg_size = mmc->max_req_size;
1892
1893         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1894                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1895
1896         mmc->caps |= mmc_slot(host).caps;
1897         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1898                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1899
1900         if (mmc_slot(host).nonremovable)
1901                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1902
1903         mmc->pm_caps = mmc_slot(host).pm_caps;
1904
1905         omap_hsmmc_conf_bus_power(host);
1906
1907         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1908         if (!res) {
1909                 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1910                 goto err_irq;
1911         }
1912         tx_req = res->start;
1913
1914         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1915         if (!res) {
1916                 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1917                 goto err_irq;
1918         }
1919         rx_req = res->start;
1920
1921         dma_cap_zero(mask);
1922         dma_cap_set(DMA_SLAVE, mask);
1923
1924         host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
1925         if (!host->rx_chan) {
1926                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
1927                 ret = -ENXIO;
1928                 goto err_irq;
1929         }
1930
1931         host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
1932         if (!host->tx_chan) {
1933                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
1934                 ret = -ENXIO;
1935                 goto err_irq;
1936         }
1937
1938         /* Request IRQ for MMC operations */
1939         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1940                         mmc_hostname(mmc), host);
1941         if (ret) {
1942                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1943                 goto err_irq;
1944         }
1945
1946         if (pdata->init != NULL) {
1947                 if (pdata->init(&pdev->dev) != 0) {
1948                         dev_dbg(mmc_dev(host->mmc),
1949                                 "Unable to configure MMC IRQs\n");
1950                         goto err_irq_cd_init;
1951                 }
1952         }
1953
1954         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1955                 ret = omap_hsmmc_reg_get(host);
1956                 if (ret)
1957                         goto err_reg;
1958                 host->use_reg = 1;
1959         }
1960
1961         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1962
1963         /* Request IRQ for card detect */
1964         if ((mmc_slot(host).card_detect_irq)) {
1965                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1966                                            NULL,
1967                                            omap_hsmmc_detect,
1968                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1969                                            mmc_hostname(mmc), host);
1970                 if (ret) {
1971                         dev_dbg(mmc_dev(host->mmc),
1972                                 "Unable to grab MMC CD IRQ\n");
1973                         goto err_irq_cd;
1974                 }
1975                 pdata->suspend = omap_hsmmc_suspend_cdirq;
1976                 pdata->resume = omap_hsmmc_resume_cdirq;
1977         }
1978
1979         omap_hsmmc_disable_irq(host);
1980
1981         omap_hsmmc_protect_card(host);
1982
1983         mmc_add_host(mmc);
1984
1985         if (mmc_slot(host).name != NULL) {
1986                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1987                 if (ret < 0)
1988                         goto err_slot_name;
1989         }
1990         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1991                 ret = device_create_file(&mmc->class_dev,
1992                                         &dev_attr_cover_switch);
1993                 if (ret < 0)
1994                         goto err_slot_name;
1995         }
1996
1997         omap_hsmmc_debugfs(mmc);
1998         pm_runtime_mark_last_busy(host->dev);
1999         pm_runtime_put_autosuspend(host->dev);
2000
2001         return 0;
2002
2003 err_slot_name:
2004         mmc_remove_host(mmc);
2005         free_irq(mmc_slot(host).card_detect_irq, host);
2006 err_irq_cd:
2007         if (host->use_reg)
2008                 omap_hsmmc_reg_put(host);
2009 err_reg:
2010         if (host->pdata->cleanup)
2011                 host->pdata->cleanup(&pdev->dev);
2012 err_irq_cd_init:
2013         free_irq(host->irq, host);
2014 err_irq:
2015         if (host->tx_chan)
2016                 dma_release_channel(host->tx_chan);
2017         if (host->rx_chan)
2018                 dma_release_channel(host->rx_chan);
2019         pm_runtime_put_sync(host->dev);
2020         pm_runtime_disable(host->dev);
2021         clk_put(host->fclk);
2022         if (host->dbclk) {
2023                 clk_disable(host->dbclk);
2024                 clk_put(host->dbclk);
2025         }
2026 err1:
2027         iounmap(host->base);
2028         platform_set_drvdata(pdev, NULL);
2029         mmc_free_host(mmc);
2030 err_alloc:
2031         omap_hsmmc_gpio_free(pdata);
2032 err:
2033         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2034         if (res)
2035                 release_mem_region(res->start, resource_size(res));
2036         return ret;
2037 }
2038
2039 static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
2040 {
2041         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2042         struct resource *res;
2043
2044         pm_runtime_get_sync(host->dev);
2045         mmc_remove_host(host->mmc);
2046         if (host->use_reg)
2047                 omap_hsmmc_reg_put(host);
2048         if (host->pdata->cleanup)
2049                 host->pdata->cleanup(&pdev->dev);
2050         free_irq(host->irq, host);
2051         if (mmc_slot(host).card_detect_irq)
2052                 free_irq(mmc_slot(host).card_detect_irq, host);
2053
2054         if (host->tx_chan)
2055                 dma_release_channel(host->tx_chan);
2056         if (host->rx_chan)
2057                 dma_release_channel(host->rx_chan);
2058
2059         pm_runtime_put_sync(host->dev);
2060         pm_runtime_disable(host->dev);
2061         clk_put(host->fclk);
2062         if (host->dbclk) {
2063                 clk_disable(host->dbclk);
2064                 clk_put(host->dbclk);
2065         }
2066
2067         mmc_free_host(host->mmc);
2068         iounmap(host->base);
2069         omap_hsmmc_gpio_free(pdev->dev.platform_data);
2070
2071         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2072         if (res)
2073                 release_mem_region(res->start, resource_size(res));
2074         platform_set_drvdata(pdev, NULL);
2075
2076         return 0;
2077 }
2078
2079 #ifdef CONFIG_PM
2080 static int omap_hsmmc_suspend(struct device *dev)
2081 {
2082         int ret = 0;
2083         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2084
2085         if (!host)
2086                 return 0;
2087
2088         if (host && host->suspended)
2089                 return 0;
2090
2091         pm_runtime_get_sync(host->dev);
2092         host->suspended = 1;
2093         if (host->pdata->suspend) {
2094                 ret = host->pdata->suspend(dev, host->slot_id);
2095                 if (ret) {
2096                         dev_dbg(dev, "Unable to handle MMC board"
2097                                         " level suspend\n");
2098                         host->suspended = 0;
2099                         return ret;
2100                 }
2101         }
2102         ret = mmc_suspend_host(host->mmc);
2103
2104         if (ret) {
2105                 host->suspended = 0;
2106                 if (host->pdata->resume) {
2107                         ret = host->pdata->resume(dev, host->slot_id);
2108                         if (ret)
2109                                 dev_dbg(dev, "Unmask interrupt failed\n");
2110                 }
2111                 goto err;
2112         }
2113
2114         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2115                 omap_hsmmc_disable_irq(host);
2116                 OMAP_HSMMC_WRITE(host->base, HCTL,
2117                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2118         }
2119
2120         if (host->dbclk)
2121                 clk_disable(host->dbclk);
2122 err:
2123         pm_runtime_put_sync(host->dev);
2124         return ret;
2125 }
2126
2127 /* Routine to resume the MMC device */
2128 static int omap_hsmmc_resume(struct device *dev)
2129 {
2130         int ret = 0;
2131         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2132
2133         if (!host)
2134                 return 0;
2135
2136         if (host && !host->suspended)
2137                 return 0;
2138
2139         pm_runtime_get_sync(host->dev);
2140
2141         if (host->dbclk)
2142                 clk_enable(host->dbclk);
2143
2144         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2145                 omap_hsmmc_conf_bus_power(host);
2146
2147         if (host->pdata->resume) {
2148                 ret = host->pdata->resume(dev, host->slot_id);
2149                 if (ret)
2150                         dev_dbg(dev, "Unmask interrupt failed\n");
2151         }
2152
2153         omap_hsmmc_protect_card(host);
2154
2155         /* Notify the core to resume the host */
2156         ret = mmc_resume_host(host->mmc);
2157         if (ret == 0)
2158                 host->suspended = 0;
2159
2160         pm_runtime_mark_last_busy(host->dev);
2161         pm_runtime_put_autosuspend(host->dev);
2162
2163         return ret;
2164
2165 }
2166
2167 #else
2168 #define omap_hsmmc_suspend      NULL
2169 #define omap_hsmmc_resume               NULL
2170 #endif
2171
2172 static int omap_hsmmc_runtime_suspend(struct device *dev)
2173 {
2174         struct omap_hsmmc_host *host;
2175
2176         host = platform_get_drvdata(to_platform_device(dev));
2177         omap_hsmmc_context_save(host);
2178         dev_dbg(dev, "disabled\n");
2179
2180         return 0;
2181 }
2182
2183 static int omap_hsmmc_runtime_resume(struct device *dev)
2184 {
2185         struct omap_hsmmc_host *host;
2186
2187         host = platform_get_drvdata(to_platform_device(dev));
2188         omap_hsmmc_context_restore(host);
2189         dev_dbg(dev, "enabled\n");
2190
2191         return 0;
2192 }
2193
2194 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2195         .suspend        = omap_hsmmc_suspend,
2196         .resume         = omap_hsmmc_resume,
2197         .runtime_suspend = omap_hsmmc_runtime_suspend,
2198         .runtime_resume = omap_hsmmc_runtime_resume,
2199 };
2200
2201 static struct platform_driver omap_hsmmc_driver = {
2202         .probe          = omap_hsmmc_probe,
2203         .remove         = __devexit_p(omap_hsmmc_remove),
2204         .driver         = {
2205                 .name = DRIVER_NAME,
2206                 .owner = THIS_MODULE,
2207                 .pm = &omap_hsmmc_dev_pm_ops,
2208                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2209         },
2210 };
2211
2212 module_platform_driver(omap_hsmmc_driver);
2213 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2214 MODULE_LICENSE("GPL");
2215 MODULE_ALIAS("platform:" DRIVER_NAME);
2216 MODULE_AUTHOR("Texas Instruments Inc");