c75fd3564040bbef6540b92e03cf574696a31333
[linux-3.10.git] / drivers / gpu / drm / r128 / r128_cce.c
1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2  * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
3  */
4 /*
5  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
6  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7  * All Rights Reserved.
8  *
9  * Permission is hereby granted, free of charge, to any person obtaining a
10  * copy of this software and associated documentation files (the "Software"),
11  * to deal in the Software without restriction, including without limitation
12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13  * and/or sell copies of the Software, and to permit persons to whom the
14  * Software is furnished to do so, subject to the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the next
17  * paragraph) shall be included in all copies or substantial portions of the
18  * Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26  * DEALINGS IN THE SOFTWARE.
27  *
28  * Authors:
29  *    Gareth Hughes <gareth@valinux.com>
30  */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "r128_drm.h"
35 #include "r128_drv.h"
36
37 #define R128_FIFO_DEBUG         0
38
39 /* CCE microcode (from ATI) */
40 static u32 r128_cce_microcode[] = {
41         0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
42         1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
43         599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
44         11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
45         262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
46         1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
47         30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
48         1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
49         15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
50         12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
51         46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
52         459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
53         18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
54         15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
55         268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
56         15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
57         1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
58         3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
59         1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
60         15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
61         180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
62         114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
63         33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
64         1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
65         14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
66         1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
67         198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
68         114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
69         1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
70         1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
71         16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
72         174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
73         33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
74         33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
75         409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
76         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
77         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
78         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
82 };
83
84 static int R128_READ_PLL(struct drm_device * dev, int addr)
85 {
86         drm_r128_private_t *dev_priv = dev->dev_private;
87
88         R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
89         return R128_READ(R128_CLOCK_CNTL_DATA);
90 }
91
92 #if R128_FIFO_DEBUG
93 static void r128_status(drm_r128_private_t * dev_priv)
94 {
95         printk("GUI_STAT           = 0x%08x\n",
96                (unsigned int)R128_READ(R128_GUI_STAT));
97         printk("PM4_STAT           = 0x%08x\n",
98                (unsigned int)R128_READ(R128_PM4_STAT));
99         printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
100                (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
101         printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
102                (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
103         printk("PM4_MICRO_CNTL     = 0x%08x\n",
104                (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
105         printk("PM4_BUFFER_CNTL    = 0x%08x\n",
106                (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
107 }
108 #endif
109
110 /* ================================================================
111  * Engine, FIFO control
112  */
113
114 static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
115 {
116         u32 tmp;
117         int i;
118
119         tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
120         R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
121
122         for (i = 0; i < dev_priv->usec_timeout; i++) {
123                 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {
124                         return 0;
125                 }
126                 DRM_UDELAY(1);
127         }
128
129 #if R128_FIFO_DEBUG
130         DRM_ERROR("failed!\n");
131 #endif
132         return -EBUSY;
133 }
134
135 static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
136 {
137         int i;
138
139         for (i = 0; i < dev_priv->usec_timeout; i++) {
140                 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
141                 if (slots >= entries)
142                         return 0;
143                 DRM_UDELAY(1);
144         }
145
146 #if R128_FIFO_DEBUG
147         DRM_ERROR("failed!\n");
148 #endif
149         return -EBUSY;
150 }
151
152 static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
153 {
154         int i, ret;
155
156         ret = r128_do_wait_for_fifo(dev_priv, 64);
157         if (ret)
158                 return ret;
159
160         for (i = 0; i < dev_priv->usec_timeout; i++) {
161                 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
162                         r128_do_pixcache_flush(dev_priv);
163                         return 0;
164                 }
165                 DRM_UDELAY(1);
166         }
167
168 #if R128_FIFO_DEBUG
169         DRM_ERROR("failed!\n");
170 #endif
171         return -EBUSY;
172 }
173
174 /* ================================================================
175  * CCE control, initialization
176  */
177
178 /* Load the microcode for the CCE */
179 static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
180 {
181         int i;
182
183         DRM_DEBUG("\n");
184
185         r128_do_wait_for_idle(dev_priv);
186
187         R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
188         for (i = 0; i < 256; i++) {
189                 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
190                 R128_WRITE(R128_PM4_MICROCODE_DATAL,
191                            r128_cce_microcode[i * 2 + 1]);
192         }
193 }
194
195 /* Flush any pending commands to the CCE.  This should only be used just
196  * prior to a wait for idle, as it informs the engine that the command
197  * stream is ending.
198  */
199 static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
200 {
201         u32 tmp;
202
203         tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
204         R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
205 }
206
207 /* Wait for the CCE to go idle.
208  */
209 int r128_do_cce_idle(drm_r128_private_t * dev_priv)
210 {
211         int i;
212
213         for (i = 0; i < dev_priv->usec_timeout; i++) {
214                 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
215                         int pm4stat = R128_READ(R128_PM4_STAT);
216                         if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
217                              dev_priv->cce_fifo_size) &&
218                             !(pm4stat & (R128_PM4_BUSY |
219                                          R128_PM4_GUI_ACTIVE))) {
220                                 return r128_do_pixcache_flush(dev_priv);
221                         }
222                 }
223                 DRM_UDELAY(1);
224         }
225
226 #if R128_FIFO_DEBUG
227         DRM_ERROR("failed!\n");
228         r128_status(dev_priv);
229 #endif
230         return -EBUSY;
231 }
232
233 /* Start the Concurrent Command Engine.
234  */
235 static void r128_do_cce_start(drm_r128_private_t * dev_priv)
236 {
237         r128_do_wait_for_idle(dev_priv);
238
239         R128_WRITE(R128_PM4_BUFFER_CNTL,
240                    dev_priv->cce_mode | dev_priv->ring.size_l2qw
241                    | R128_PM4_BUFFER_CNTL_NOUPDATE);
242         R128_READ(R128_PM4_BUFFER_ADDR);        /* as per the sample code */
243         R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
244
245         dev_priv->cce_running = 1;
246 }
247
248 /* Reset the Concurrent Command Engine.  This will not flush any pending
249  * commands, so you must wait for the CCE command stream to complete
250  * before calling this routine.
251  */
252 static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
253 {
254         R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
255         R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
256         dev_priv->ring.tail = 0;
257 }
258
259 /* Stop the Concurrent Command Engine.  This will not flush any pending
260  * commands, so you must flush the command stream and wait for the CCE
261  * to go idle before calling this routine.
262  */
263 static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
264 {
265         R128_WRITE(R128_PM4_MICRO_CNTL, 0);
266         R128_WRITE(R128_PM4_BUFFER_CNTL,
267                    R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
268
269         dev_priv->cce_running = 0;
270 }
271
272 /* Reset the engine.  This will stop the CCE if it is running.
273  */
274 static int r128_do_engine_reset(struct drm_device * dev)
275 {
276         drm_r128_private_t *dev_priv = dev->dev_private;
277         u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
278
279         r128_do_pixcache_flush(dev_priv);
280
281         clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
282         mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
283
284         R128_WRITE_PLL(R128_MCLK_CNTL,
285                        mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
286
287         gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
288
289         /* Taken from the sample code - do not change */
290         R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
291         R128_READ(R128_GEN_RESET_CNTL);
292         R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
293         R128_READ(R128_GEN_RESET_CNTL);
294
295         R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
296         R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
297         R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
298
299         /* Reset the CCE ring */
300         r128_do_cce_reset(dev_priv);
301
302         /* The CCE is no longer running after an engine reset */
303         dev_priv->cce_running = 0;
304
305         /* Reset any pending vertex, indirect buffers */
306         r128_freelist_reset(dev);
307
308         return 0;
309 }
310
311 static void r128_cce_init_ring_buffer(struct drm_device * dev,
312                                       drm_r128_private_t * dev_priv)
313 {
314         u32 ring_start;
315         u32 tmp;
316
317         DRM_DEBUG("\n");
318
319         /* The manual (p. 2) says this address is in "VM space".  This
320          * means it's an offset from the start of AGP space.
321          */
322 #if __OS_HAS_AGP
323         if (!dev_priv->is_pci)
324                 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
325         else
326 #endif
327                 ring_start = dev_priv->cce_ring->offset -
328                     (unsigned long)dev->sg->virtual;
329
330         R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
331
332         R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
333         R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
334
335         /* Set watermark control */
336         R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
337                    ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
338                    | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
339                    | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
340                    | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
341
342         /* Force read.  Why?  Because it's in the examples... */
343         R128_READ(R128_PM4_BUFFER_ADDR);
344
345         /* Turn on bus mastering */
346         tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
347         R128_WRITE(R128_BUS_CNTL, tmp);
348 }
349
350 static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
351 {
352         drm_r128_private_t *dev_priv;
353
354         DRM_DEBUG("\n");
355
356         dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL);
357         if (dev_priv == NULL)
358                 return -ENOMEM;
359
360         dev_priv->is_pci = init->is_pci;
361
362         if (dev_priv->is_pci && !dev->sg) {
363                 DRM_ERROR("PCI GART memory not allocated!\n");
364                 dev->dev_private = (void *)dev_priv;
365                 r128_do_cleanup_cce(dev);
366                 return -EINVAL;
367         }
368
369         dev_priv->usec_timeout = init->usec_timeout;
370         if (dev_priv->usec_timeout < 1 ||
371             dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
372                 DRM_DEBUG("TIMEOUT problem!\n");
373                 dev->dev_private = (void *)dev_priv;
374                 r128_do_cleanup_cce(dev);
375                 return -EINVAL;
376         }
377
378         dev_priv->cce_mode = init->cce_mode;
379
380         /* GH: Simple idle check.
381          */
382         atomic_set(&dev_priv->idle_count, 0);
383
384         /* We don't support anything other than bus-mastering ring mode,
385          * but the ring can be in either AGP or PCI space for the ring
386          * read pointer.
387          */
388         if ((init->cce_mode != R128_PM4_192BM) &&
389             (init->cce_mode != R128_PM4_128BM_64INDBM) &&
390             (init->cce_mode != R128_PM4_64BM_128INDBM) &&
391             (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
392                 DRM_DEBUG("Bad cce_mode!\n");
393                 dev->dev_private = (void *)dev_priv;
394                 r128_do_cleanup_cce(dev);
395                 return -EINVAL;
396         }
397
398         switch (init->cce_mode) {
399         case R128_PM4_NONPM4:
400                 dev_priv->cce_fifo_size = 0;
401                 break;
402         case R128_PM4_192PIO:
403         case R128_PM4_192BM:
404                 dev_priv->cce_fifo_size = 192;
405                 break;
406         case R128_PM4_128PIO_64INDBM:
407         case R128_PM4_128BM_64INDBM:
408                 dev_priv->cce_fifo_size = 128;
409                 break;
410         case R128_PM4_64PIO_128INDBM:
411         case R128_PM4_64BM_128INDBM:
412         case R128_PM4_64PIO_64VCBM_64INDBM:
413         case R128_PM4_64BM_64VCBM_64INDBM:
414         case R128_PM4_64PIO_64VCPIO_64INDPIO:
415                 dev_priv->cce_fifo_size = 64;
416                 break;
417         }
418
419         switch (init->fb_bpp) {
420         case 16:
421                 dev_priv->color_fmt = R128_DATATYPE_RGB565;
422                 break;
423         case 32:
424         default:
425                 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
426                 break;
427         }
428         dev_priv->front_offset = init->front_offset;
429         dev_priv->front_pitch = init->front_pitch;
430         dev_priv->back_offset = init->back_offset;
431         dev_priv->back_pitch = init->back_pitch;
432
433         switch (init->depth_bpp) {
434         case 16:
435                 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
436                 break;
437         case 24:
438         case 32:
439         default:
440                 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
441                 break;
442         }
443         dev_priv->depth_offset = init->depth_offset;
444         dev_priv->depth_pitch = init->depth_pitch;
445         dev_priv->span_offset = init->span_offset;
446
447         dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
448                                           (dev_priv->front_offset >> 5));
449         dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
450                                          (dev_priv->back_offset >> 5));
451         dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
452                                           (dev_priv->depth_offset >> 5) |
453                                           R128_DST_TILE);
454         dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
455                                          (dev_priv->span_offset >> 5));
456
457         dev_priv->sarea = drm_getsarea(dev);
458         if (!dev_priv->sarea) {
459                 DRM_ERROR("could not find sarea!\n");
460                 dev->dev_private = (void *)dev_priv;
461                 r128_do_cleanup_cce(dev);
462                 return -EINVAL;
463         }
464
465         dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
466         if (!dev_priv->mmio) {
467                 DRM_ERROR("could not find mmio region!\n");
468                 dev->dev_private = (void *)dev_priv;
469                 r128_do_cleanup_cce(dev);
470                 return -EINVAL;
471         }
472         dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
473         if (!dev_priv->cce_ring) {
474                 DRM_ERROR("could not find cce ring region!\n");
475                 dev->dev_private = (void *)dev_priv;
476                 r128_do_cleanup_cce(dev);
477                 return -EINVAL;
478         }
479         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
480         if (!dev_priv->ring_rptr) {
481                 DRM_ERROR("could not find ring read pointer!\n");
482                 dev->dev_private = (void *)dev_priv;
483                 r128_do_cleanup_cce(dev);
484                 return -EINVAL;
485         }
486         dev->agp_buffer_token = init->buffers_offset;
487         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
488         if (!dev->agp_buffer_map) {
489                 DRM_ERROR("could not find dma buffer region!\n");
490                 dev->dev_private = (void *)dev_priv;
491                 r128_do_cleanup_cce(dev);
492                 return -EINVAL;
493         }
494
495         if (!dev_priv->is_pci) {
496                 dev_priv->agp_textures =
497                     drm_core_findmap(dev, init->agp_textures_offset);
498                 if (!dev_priv->agp_textures) {
499                         DRM_ERROR("could not find agp texture region!\n");
500                         dev->dev_private = (void *)dev_priv;
501                         r128_do_cleanup_cce(dev);
502                         return -EINVAL;
503                 }
504         }
505
506         dev_priv->sarea_priv =
507             (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
508                                   init->sarea_priv_offset);
509
510 #if __OS_HAS_AGP
511         if (!dev_priv->is_pci) {
512                 drm_core_ioremap_wc(dev_priv->cce_ring, dev);
513                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
514                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
515                 if (!dev_priv->cce_ring->handle ||
516                     !dev_priv->ring_rptr->handle ||
517                     !dev->agp_buffer_map->handle) {
518                         DRM_ERROR("Could not ioremap agp regions!\n");
519                         dev->dev_private = (void *)dev_priv;
520                         r128_do_cleanup_cce(dev);
521                         return -ENOMEM;
522                 }
523         } else
524 #endif
525         {
526                 dev_priv->cce_ring->handle =
527                         (void *)(unsigned long)dev_priv->cce_ring->offset;
528                 dev_priv->ring_rptr->handle =
529                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
530                 dev->agp_buffer_map->handle =
531                         (void *)(unsigned long)dev->agp_buffer_map->offset;
532         }
533
534 #if __OS_HAS_AGP
535         if (!dev_priv->is_pci)
536                 dev_priv->cce_buffers_offset = dev->agp->base;
537         else
538 #endif
539                 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
540
541         dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
542         dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
543                               + init->ring_size / sizeof(u32));
544         dev_priv->ring.size = init->ring_size;
545         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
546
547         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
548
549         dev_priv->ring.high_mark = 128;
550
551         dev_priv->sarea_priv->last_frame = 0;
552         R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
553
554         dev_priv->sarea_priv->last_dispatch = 0;
555         R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
556
557 #if __OS_HAS_AGP
558         if (dev_priv->is_pci) {
559 #endif
560                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
561                 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
562                 dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
563                 dev_priv->gart_info.addr = NULL;
564                 dev_priv->gart_info.bus_addr = 0;
565                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
566                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
567                         DRM_ERROR("failed to init PCI GART!\n");
568                         dev->dev_private = (void *)dev_priv;
569                         r128_do_cleanup_cce(dev);
570                         return -ENOMEM;
571                 }
572                 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
573 #if __OS_HAS_AGP
574         }
575 #endif
576
577         r128_cce_init_ring_buffer(dev, dev_priv);
578         r128_cce_load_microcode(dev_priv);
579
580         dev->dev_private = (void *)dev_priv;
581
582         r128_do_engine_reset(dev);
583
584         return 0;
585 }
586
587 int r128_do_cleanup_cce(struct drm_device * dev)
588 {
589
590         /* Make sure interrupts are disabled here because the uninstall ioctl
591          * may not have been called from userspace and after dev_private
592          * is freed, it's too late.
593          */
594         if (dev->irq_enabled)
595                 drm_irq_uninstall(dev);
596
597         if (dev->dev_private) {
598                 drm_r128_private_t *dev_priv = dev->dev_private;
599
600 #if __OS_HAS_AGP
601                 if (!dev_priv->is_pci) {
602                         if (dev_priv->cce_ring != NULL)
603                                 drm_core_ioremapfree(dev_priv->cce_ring, dev);
604                         if (dev_priv->ring_rptr != NULL)
605                                 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
606                         if (dev->agp_buffer_map != NULL) {
607                                 drm_core_ioremapfree(dev->agp_buffer_map, dev);
608                                 dev->agp_buffer_map = NULL;
609                         }
610                 } else
611 #endif
612                 {
613                         if (dev_priv->gart_info.bus_addr)
614                                 if (!drm_ati_pcigart_cleanup(dev,
615                                                         &dev_priv->gart_info))
616                                         DRM_ERROR
617                                             ("failed to cleanup PCI GART!\n");
618                 }
619
620                 kfree(dev->dev_private);
621                 dev->dev_private = NULL;
622         }
623
624         return 0;
625 }
626
627 int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
628 {
629         drm_r128_init_t *init = data;
630
631         DRM_DEBUG("\n");
632
633         LOCK_TEST_WITH_RETURN(dev, file_priv);
634
635         switch (init->func) {
636         case R128_INIT_CCE:
637                 return r128_do_init_cce(dev, init);
638         case R128_CLEANUP_CCE:
639                 return r128_do_cleanup_cce(dev);
640         }
641
642         return -EINVAL;
643 }
644
645 int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
646 {
647         drm_r128_private_t *dev_priv = dev->dev_private;
648         DRM_DEBUG("\n");
649
650         LOCK_TEST_WITH_RETURN(dev, file_priv);
651
652         if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
653                 DRM_DEBUG("while CCE running\n");
654                 return 0;
655         }
656
657         r128_do_cce_start(dev_priv);
658
659         return 0;
660 }
661
662 /* Stop the CCE.  The engine must have been idled before calling this
663  * routine.
664  */
665 int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
666 {
667         drm_r128_private_t *dev_priv = dev->dev_private;
668         drm_r128_cce_stop_t *stop = data;
669         int ret;
670         DRM_DEBUG("\n");
671
672         LOCK_TEST_WITH_RETURN(dev, file_priv);
673
674         /* Flush any pending CCE commands.  This ensures any outstanding
675          * commands are exectuted by the engine before we turn it off.
676          */
677         if (stop->flush) {
678                 r128_do_cce_flush(dev_priv);
679         }
680
681         /* If we fail to make the engine go idle, we return an error
682          * code so that the DRM ioctl wrapper can try again.
683          */
684         if (stop->idle) {
685                 ret = r128_do_cce_idle(dev_priv);
686                 if (ret)
687                         return ret;
688         }
689
690         /* Finally, we can turn off the CCE.  If the engine isn't idle,
691          * we will get some dropped triangles as they won't be fully
692          * rendered before the CCE is shut down.
693          */
694         r128_do_cce_stop(dev_priv);
695
696         /* Reset the engine */
697         r128_do_engine_reset(dev);
698
699         return 0;
700 }
701
702 /* Just reset the CCE ring.  Called as part of an X Server engine reset.
703  */
704 int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
705 {
706         drm_r128_private_t *dev_priv = dev->dev_private;
707         DRM_DEBUG("\n");
708
709         LOCK_TEST_WITH_RETURN(dev, file_priv);
710
711         if (!dev_priv) {
712                 DRM_DEBUG("called before init done\n");
713                 return -EINVAL;
714         }
715
716         r128_do_cce_reset(dev_priv);
717
718         /* The CCE is no longer running after an engine reset */
719         dev_priv->cce_running = 0;
720
721         return 0;
722 }
723
724 int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
725 {
726         drm_r128_private_t *dev_priv = dev->dev_private;
727         DRM_DEBUG("\n");
728
729         LOCK_TEST_WITH_RETURN(dev, file_priv);
730
731         if (dev_priv->cce_running) {
732                 r128_do_cce_flush(dev_priv);
733         }
734
735         return r128_do_cce_idle(dev_priv);
736 }
737
738 int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
739 {
740         DRM_DEBUG("\n");
741
742         LOCK_TEST_WITH_RETURN(dev, file_priv);
743
744         return r128_do_engine_reset(dev);
745 }
746
747 int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
748 {
749         return -EINVAL;
750 }
751
752 /* ================================================================
753  * Freelist management
754  */
755 #define R128_BUFFER_USED        0xffffffff
756 #define R128_BUFFER_FREE        0
757
758 #if 0
759 static int r128_freelist_init(struct drm_device * dev)
760 {
761         struct drm_device_dma *dma = dev->dma;
762         drm_r128_private_t *dev_priv = dev->dev_private;
763         struct drm_buf *buf;
764         drm_r128_buf_priv_t *buf_priv;
765         drm_r128_freelist_t *entry;
766         int i;
767
768         dev_priv->head = kzalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
769         if (dev_priv->head == NULL)
770                 return -ENOMEM;
771
772         dev_priv->head->age = R128_BUFFER_USED;
773
774         for (i = 0; i < dma->buf_count; i++) {
775                 buf = dma->buflist[i];
776                 buf_priv = buf->dev_private;
777
778                 entry = kmalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
779                 if (!entry)
780                         return -ENOMEM;
781
782                 entry->age = R128_BUFFER_FREE;
783                 entry->buf = buf;
784                 entry->prev = dev_priv->head;
785                 entry->next = dev_priv->head->next;
786                 if (!entry->next)
787                         dev_priv->tail = entry;
788
789                 buf_priv->discard = 0;
790                 buf_priv->dispatched = 0;
791                 buf_priv->list_entry = entry;
792
793                 dev_priv->head->next = entry;
794
795                 if (dev_priv->head->next)
796                         dev_priv->head->next->prev = entry;
797         }
798
799         return 0;
800
801 }
802 #endif
803
804 static struct drm_buf *r128_freelist_get(struct drm_device * dev)
805 {
806         struct drm_device_dma *dma = dev->dma;
807         drm_r128_private_t *dev_priv = dev->dev_private;
808         drm_r128_buf_priv_t *buf_priv;
809         struct drm_buf *buf;
810         int i, t;
811
812         /* FIXME: Optimize -- use freelist code */
813
814         for (i = 0; i < dma->buf_count; i++) {
815                 buf = dma->buflist[i];
816                 buf_priv = buf->dev_private;
817                 if (!buf->file_priv)
818                         return buf;
819         }
820
821         for (t = 0; t < dev_priv->usec_timeout; t++) {
822                 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
823
824                 for (i = 0; i < dma->buf_count; i++) {
825                         buf = dma->buflist[i];
826                         buf_priv = buf->dev_private;
827                         if (buf->pending && buf_priv->age <= done_age) {
828                                 /* The buffer has been processed, so it
829                                  * can now be used.
830                                  */
831                                 buf->pending = 0;
832                                 return buf;
833                         }
834                 }
835                 DRM_UDELAY(1);
836         }
837
838         DRM_DEBUG("returning NULL!\n");
839         return NULL;
840 }
841
842 void r128_freelist_reset(struct drm_device * dev)
843 {
844         struct drm_device_dma *dma = dev->dma;
845         int i;
846
847         for (i = 0; i < dma->buf_count; i++) {
848                 struct drm_buf *buf = dma->buflist[i];
849                 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
850                 buf_priv->age = 0;
851         }
852 }
853
854 /* ================================================================
855  * CCE command submission
856  */
857
858 int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
859 {
860         drm_r128_ring_buffer_t *ring = &dev_priv->ring;
861         int i;
862
863         for (i = 0; i < dev_priv->usec_timeout; i++) {
864                 r128_update_ring_snapshot(dev_priv);
865                 if (ring->space >= n)
866                         return 0;
867                 DRM_UDELAY(1);
868         }
869
870         /* FIXME: This is being ignored... */
871         DRM_ERROR("failed!\n");
872         return -EBUSY;
873 }
874
875 static int r128_cce_get_buffers(struct drm_device * dev,
876                                 struct drm_file *file_priv,
877                                 struct drm_dma * d)
878 {
879         int i;
880         struct drm_buf *buf;
881
882         for (i = d->granted_count; i < d->request_count; i++) {
883                 buf = r128_freelist_get(dev);
884                 if (!buf)
885                         return -EAGAIN;
886
887                 buf->file_priv = file_priv;
888
889                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
890                                      sizeof(buf->idx)))
891                         return -EFAULT;
892                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
893                                      sizeof(buf->total)))
894                         return -EFAULT;
895
896                 d->granted_count++;
897         }
898         return 0;
899 }
900
901 int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
902 {
903         struct drm_device_dma *dma = dev->dma;
904         int ret = 0;
905         struct drm_dma *d = data;
906
907         LOCK_TEST_WITH_RETURN(dev, file_priv);
908
909         /* Please don't send us buffers.
910          */
911         if (d->send_count != 0) {
912                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
913                           DRM_CURRENTPID, d->send_count);
914                 return -EINVAL;
915         }
916
917         /* We'll send you buffers.
918          */
919         if (d->request_count < 0 || d->request_count > dma->buf_count) {
920                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
921                           DRM_CURRENTPID, d->request_count, dma->buf_count);
922                 return -EINVAL;
923         }
924
925         d->granted_count = 0;
926
927         if (d->request_count) {
928                 ret = r128_cce_get_buffers(dev, file_priv, d);
929         }
930
931         return ret;
932 }