KVM: Add resampling irqfds for level triggered interrupts
[linux-3.10.git] / arch / x86 / kvm / x86.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * derived from drivers/kvm/kvm_main.c
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright (C) 2008 Qumranet, Inc.
8  * Copyright IBM Corporation, 2008
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Amit Shah    <amit.shah@qumranet.com>
15  *   Ben-Ami Yassour <benami@il.ibm.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <trace/events/kvm.h>
50
51 #define CREATE_TRACE_POINTS
52 #include "trace.h"
53
54 #include <asm/debugreg.h>
55 #include <asm/msr.h>
56 #include <asm/desc.h>
57 #include <asm/mtrr.h>
58 #include <asm/mce.h>
59 #include <asm/i387.h>
60 #include <asm/fpu-internal.h> /* Ugh! */
61 #include <asm/xcr.h>
62 #include <asm/pvclock.h>
63 #include <asm/div64.h>
64
65 #define MAX_IO_MSRS 256
66 #define KVM_MAX_MCE_BANKS 32
67 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
68
69 #define emul_to_vcpu(ctxt) \
70         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
72 /* EFER defaults:
73  * - enable syscall per default because its emulated by KVM
74  * - enable LME and LMA per default on 64 bit KVM
75  */
76 #ifdef CONFIG_X86_64
77 static
78 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
79 #else
80 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
81 #endif
82
83 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
85
86 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
87 static void process_nmi(struct kvm_vcpu *vcpu);
88
89 struct kvm_x86_ops *kvm_x86_ops;
90 EXPORT_SYMBOL_GPL(kvm_x86_ops);
91
92 static bool ignore_msrs = 0;
93 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
95 bool kvm_has_tsc_control;
96 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97 u32  kvm_max_guest_tsc_khz;
98 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
100 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101 static u32 tsc_tolerance_ppm = 250;
102 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
104 #define KVM_NR_SHARED_MSRS 16
105
106 struct kvm_shared_msrs_global {
107         int nr;
108         u32 msrs[KVM_NR_SHARED_MSRS];
109 };
110
111 struct kvm_shared_msrs {
112         struct user_return_notifier urn;
113         bool registered;
114         struct kvm_shared_msr_values {
115                 u64 host;
116                 u64 curr;
117         } values[KVM_NR_SHARED_MSRS];
118 };
119
120 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
123 struct kvm_stats_debugfs_item debugfs_entries[] = {
124         { "pf_fixed", VCPU_STAT(pf_fixed) },
125         { "pf_guest", VCPU_STAT(pf_guest) },
126         { "tlb_flush", VCPU_STAT(tlb_flush) },
127         { "invlpg", VCPU_STAT(invlpg) },
128         { "exits", VCPU_STAT(exits) },
129         { "io_exits", VCPU_STAT(io_exits) },
130         { "mmio_exits", VCPU_STAT(mmio_exits) },
131         { "signal_exits", VCPU_STAT(signal_exits) },
132         { "irq_window", VCPU_STAT(irq_window_exits) },
133         { "nmi_window", VCPU_STAT(nmi_window_exits) },
134         { "halt_exits", VCPU_STAT(halt_exits) },
135         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
136         { "hypercalls", VCPU_STAT(hypercalls) },
137         { "request_irq", VCPU_STAT(request_irq_exits) },
138         { "irq_exits", VCPU_STAT(irq_exits) },
139         { "host_state_reload", VCPU_STAT(host_state_reload) },
140         { "efer_reload", VCPU_STAT(efer_reload) },
141         { "fpu_reload", VCPU_STAT(fpu_reload) },
142         { "insn_emulation", VCPU_STAT(insn_emulation) },
143         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
144         { "irq_injections", VCPU_STAT(irq_injections) },
145         { "nmi_injections", VCPU_STAT(nmi_injections) },
146         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150         { "mmu_flooded", VM_STAT(mmu_flooded) },
151         { "mmu_recycled", VM_STAT(mmu_recycled) },
152         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
153         { "mmu_unsync", VM_STAT(mmu_unsync) },
154         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
155         { "largepages", VM_STAT(lpages) },
156         { NULL }
157 };
158
159 u64 __read_mostly host_xcr0;
160
161 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162
163 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
164 {
165         int i;
166         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167                 vcpu->arch.apf.gfns[i] = ~0;
168 }
169
170 static void kvm_on_user_return(struct user_return_notifier *urn)
171 {
172         unsigned slot;
173         struct kvm_shared_msrs *locals
174                 = container_of(urn, struct kvm_shared_msrs, urn);
175         struct kvm_shared_msr_values *values;
176
177         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
178                 values = &locals->values[slot];
179                 if (values->host != values->curr) {
180                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
181                         values->curr = values->host;
182                 }
183         }
184         locals->registered = false;
185         user_return_notifier_unregister(urn);
186 }
187
188 static void shared_msr_update(unsigned slot, u32 msr)
189 {
190         struct kvm_shared_msrs *smsr;
191         u64 value;
192
193         smsr = &__get_cpu_var(shared_msrs);
194         /* only read, and nobody should modify it at this time,
195          * so don't need lock */
196         if (slot >= shared_msrs_global.nr) {
197                 printk(KERN_ERR "kvm: invalid MSR slot!");
198                 return;
199         }
200         rdmsrl_safe(msr, &value);
201         smsr->values[slot].host = value;
202         smsr->values[slot].curr = value;
203 }
204
205 void kvm_define_shared_msr(unsigned slot, u32 msr)
206 {
207         if (slot >= shared_msrs_global.nr)
208                 shared_msrs_global.nr = slot + 1;
209         shared_msrs_global.msrs[slot] = msr;
210         /* we need ensured the shared_msr_global have been updated */
211         smp_wmb();
212 }
213 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214
215 static void kvm_shared_msr_cpu_online(void)
216 {
217         unsigned i;
218
219         for (i = 0; i < shared_msrs_global.nr; ++i)
220                 shared_msr_update(i, shared_msrs_global.msrs[i]);
221 }
222
223 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
224 {
225         struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
227         if (((value ^ smsr->values[slot].curr) & mask) == 0)
228                 return;
229         smsr->values[slot].curr = value;
230         wrmsrl(shared_msrs_global.msrs[slot], value);
231         if (!smsr->registered) {
232                 smsr->urn.on_user_return = kvm_on_user_return;
233                 user_return_notifier_register(&smsr->urn);
234                 smsr->registered = true;
235         }
236 }
237 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238
239 static void drop_user_return_notifiers(void *ignore)
240 {
241         struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242
243         if (smsr->registered)
244                 kvm_on_user_return(&smsr->urn);
245 }
246
247 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248 {
249         return vcpu->arch.apic_base;
250 }
251 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
252
253 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
254 {
255         /* TODO: reserve bits check */
256         kvm_lapic_set_base(vcpu, data);
257 }
258 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
260 #define EXCPT_BENIGN            0
261 #define EXCPT_CONTRIBUTORY      1
262 #define EXCPT_PF                2
263
264 static int exception_class(int vector)
265 {
266         switch (vector) {
267         case PF_VECTOR:
268                 return EXCPT_PF;
269         case DE_VECTOR:
270         case TS_VECTOR:
271         case NP_VECTOR:
272         case SS_VECTOR:
273         case GP_VECTOR:
274                 return EXCPT_CONTRIBUTORY;
275         default:
276                 break;
277         }
278         return EXCPT_BENIGN;
279 }
280
281 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
282                 unsigned nr, bool has_error, u32 error_code,
283                 bool reinject)
284 {
285         u32 prev_nr;
286         int class1, class2;
287
288         kvm_make_request(KVM_REQ_EVENT, vcpu);
289
290         if (!vcpu->arch.exception.pending) {
291         queue:
292                 vcpu->arch.exception.pending = true;
293                 vcpu->arch.exception.has_error_code = has_error;
294                 vcpu->arch.exception.nr = nr;
295                 vcpu->arch.exception.error_code = error_code;
296                 vcpu->arch.exception.reinject = reinject;
297                 return;
298         }
299
300         /* to check exception */
301         prev_nr = vcpu->arch.exception.nr;
302         if (prev_nr == DF_VECTOR) {
303                 /* triple fault -> shutdown */
304                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
305                 return;
306         }
307         class1 = exception_class(prev_nr);
308         class2 = exception_class(nr);
309         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
310                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
311                 /* generate double fault per SDM Table 5-5 */
312                 vcpu->arch.exception.pending = true;
313                 vcpu->arch.exception.has_error_code = true;
314                 vcpu->arch.exception.nr = DF_VECTOR;
315                 vcpu->arch.exception.error_code = 0;
316         } else
317                 /* replace previous exception with a new one in a hope
318                    that instruction re-execution will regenerate lost
319                    exception */
320                 goto queue;
321 }
322
323 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324 {
325         kvm_multiple_exception(vcpu, nr, false, 0, false);
326 }
327 EXPORT_SYMBOL_GPL(kvm_queue_exception);
328
329 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330 {
331         kvm_multiple_exception(vcpu, nr, false, 0, true);
332 }
333 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334
335 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
336 {
337         if (err)
338                 kvm_inject_gp(vcpu, 0);
339         else
340                 kvm_x86_ops->skip_emulated_instruction(vcpu);
341 }
342 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
343
344 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
345 {
346         ++vcpu->stat.pf_guest;
347         vcpu->arch.cr2 = fault->address;
348         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
349 }
350 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
351
352 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
353 {
354         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
355                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
356         else
357                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
358 }
359
360 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
361 {
362         atomic_inc(&vcpu->arch.nmi_queued);
363         kvm_make_request(KVM_REQ_NMI, vcpu);
364 }
365 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
366
367 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
368 {
369         kvm_multiple_exception(vcpu, nr, true, error_code, false);
370 }
371 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
372
373 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374 {
375         kvm_multiple_exception(vcpu, nr, true, error_code, true);
376 }
377 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
378
379 /*
380  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
381  * a #GP and return false.
382  */
383 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
384 {
385         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
386                 return true;
387         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
388         return false;
389 }
390 EXPORT_SYMBOL_GPL(kvm_require_cpl);
391
392 /*
393  * This function will be used to read from the physical memory of the currently
394  * running guest. The difference to kvm_read_guest_page is that this function
395  * can read from guest physical or from the guest's guest physical memory.
396  */
397 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
398                             gfn_t ngfn, void *data, int offset, int len,
399                             u32 access)
400 {
401         gfn_t real_gfn;
402         gpa_t ngpa;
403
404         ngpa     = gfn_to_gpa(ngfn);
405         real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
406         if (real_gfn == UNMAPPED_GVA)
407                 return -EFAULT;
408
409         real_gfn = gpa_to_gfn(real_gfn);
410
411         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
412 }
413 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
414
415 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
416                                void *data, int offset, int len, u32 access)
417 {
418         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
419                                        data, offset, len, access);
420 }
421
422 /*
423  * Load the pae pdptrs.  Return true is they are all valid.
424  */
425 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
426 {
427         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
428         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
429         int i;
430         int ret;
431         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
432
433         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
434                                       offset * sizeof(u64), sizeof(pdpte),
435                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
436         if (ret < 0) {
437                 ret = 0;
438                 goto out;
439         }
440         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
441                 if (is_present_gpte(pdpte[i]) &&
442                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
443                         ret = 0;
444                         goto out;
445                 }
446         }
447         ret = 1;
448
449         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
450         __set_bit(VCPU_EXREG_PDPTR,
451                   (unsigned long *)&vcpu->arch.regs_avail);
452         __set_bit(VCPU_EXREG_PDPTR,
453                   (unsigned long *)&vcpu->arch.regs_dirty);
454 out:
455
456         return ret;
457 }
458 EXPORT_SYMBOL_GPL(load_pdptrs);
459
460 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
461 {
462         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
463         bool changed = true;
464         int offset;
465         gfn_t gfn;
466         int r;
467
468         if (is_long_mode(vcpu) || !is_pae(vcpu))
469                 return false;
470
471         if (!test_bit(VCPU_EXREG_PDPTR,
472                       (unsigned long *)&vcpu->arch.regs_avail))
473                 return true;
474
475         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
476         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
477         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
478                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
479         if (r < 0)
480                 goto out;
481         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
482 out:
483
484         return changed;
485 }
486
487 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
488 {
489         unsigned long old_cr0 = kvm_read_cr0(vcpu);
490         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
491                                     X86_CR0_CD | X86_CR0_NW;
492
493         cr0 |= X86_CR0_ET;
494
495 #ifdef CONFIG_X86_64
496         if (cr0 & 0xffffffff00000000UL)
497                 return 1;
498 #endif
499
500         cr0 &= ~CR0_RESERVED_BITS;
501
502         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
503                 return 1;
504
505         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
506                 return 1;
507
508         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
509 #ifdef CONFIG_X86_64
510                 if ((vcpu->arch.efer & EFER_LME)) {
511                         int cs_db, cs_l;
512
513                         if (!is_pae(vcpu))
514                                 return 1;
515                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
516                         if (cs_l)
517                                 return 1;
518                 } else
519 #endif
520                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
521                                                  kvm_read_cr3(vcpu)))
522                         return 1;
523         }
524
525         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
526                 return 1;
527
528         kvm_x86_ops->set_cr0(vcpu, cr0);
529
530         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
531                 kvm_clear_async_pf_completion_queue(vcpu);
532                 kvm_async_pf_hash_reset(vcpu);
533         }
534
535         if ((cr0 ^ old_cr0) & update_bits)
536                 kvm_mmu_reset_context(vcpu);
537         return 0;
538 }
539 EXPORT_SYMBOL_GPL(kvm_set_cr0);
540
541 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
542 {
543         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
544 }
545 EXPORT_SYMBOL_GPL(kvm_lmsw);
546
547 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
548 {
549         u64 xcr0;
550
551         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
552         if (index != XCR_XFEATURE_ENABLED_MASK)
553                 return 1;
554         xcr0 = xcr;
555         if (kvm_x86_ops->get_cpl(vcpu) != 0)
556                 return 1;
557         if (!(xcr0 & XSTATE_FP))
558                 return 1;
559         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
560                 return 1;
561         if (xcr0 & ~host_xcr0)
562                 return 1;
563         vcpu->arch.xcr0 = xcr0;
564         vcpu->guest_xcr0_loaded = 0;
565         return 0;
566 }
567
568 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
569 {
570         if (__kvm_set_xcr(vcpu, index, xcr)) {
571                 kvm_inject_gp(vcpu, 0);
572                 return 1;
573         }
574         return 0;
575 }
576 EXPORT_SYMBOL_GPL(kvm_set_xcr);
577
578 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
579 {
580         unsigned long old_cr4 = kvm_read_cr4(vcpu);
581         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
582                                    X86_CR4_PAE | X86_CR4_SMEP;
583         if (cr4 & CR4_RESERVED_BITS)
584                 return 1;
585
586         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
587                 return 1;
588
589         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
590                 return 1;
591
592         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
593                 return 1;
594
595         if (is_long_mode(vcpu)) {
596                 if (!(cr4 & X86_CR4_PAE))
597                         return 1;
598         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
599                    && ((cr4 ^ old_cr4) & pdptr_bits)
600                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
601                                    kvm_read_cr3(vcpu)))
602                 return 1;
603
604         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
605                 if (!guest_cpuid_has_pcid(vcpu))
606                         return 1;
607
608                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
609                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
610                         return 1;
611         }
612
613         if (kvm_x86_ops->set_cr4(vcpu, cr4))
614                 return 1;
615
616         if (((cr4 ^ old_cr4) & pdptr_bits) ||
617             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
618                 kvm_mmu_reset_context(vcpu);
619
620         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
621                 kvm_update_cpuid(vcpu);
622
623         return 0;
624 }
625 EXPORT_SYMBOL_GPL(kvm_set_cr4);
626
627 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
628 {
629         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
630                 kvm_mmu_sync_roots(vcpu);
631                 kvm_mmu_flush_tlb(vcpu);
632                 return 0;
633         }
634
635         if (is_long_mode(vcpu)) {
636                 if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) {
637                         if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
638                                 return 1;
639                 } else
640                         if (cr3 & CR3_L_MODE_RESERVED_BITS)
641                                 return 1;
642         } else {
643                 if (is_pae(vcpu)) {
644                         if (cr3 & CR3_PAE_RESERVED_BITS)
645                                 return 1;
646                         if (is_paging(vcpu) &&
647                             !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
648                                 return 1;
649                 }
650                 /*
651                  * We don't check reserved bits in nonpae mode, because
652                  * this isn't enforced, and VMware depends on this.
653                  */
654         }
655
656         /*
657          * Does the new cr3 value map to physical memory? (Note, we
658          * catch an invalid cr3 even in real-mode, because it would
659          * cause trouble later on when we turn on paging anyway.)
660          *
661          * A real CPU would silently accept an invalid cr3 and would
662          * attempt to use it - with largely undefined (and often hard
663          * to debug) behavior on the guest side.
664          */
665         if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
666                 return 1;
667         vcpu->arch.cr3 = cr3;
668         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
669         vcpu->arch.mmu.new_cr3(vcpu);
670         return 0;
671 }
672 EXPORT_SYMBOL_GPL(kvm_set_cr3);
673
674 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
675 {
676         if (cr8 & CR8_RESERVED_BITS)
677                 return 1;
678         if (irqchip_in_kernel(vcpu->kvm))
679                 kvm_lapic_set_tpr(vcpu, cr8);
680         else
681                 vcpu->arch.cr8 = cr8;
682         return 0;
683 }
684 EXPORT_SYMBOL_GPL(kvm_set_cr8);
685
686 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
687 {
688         if (irqchip_in_kernel(vcpu->kvm))
689                 return kvm_lapic_get_cr8(vcpu);
690         else
691                 return vcpu->arch.cr8;
692 }
693 EXPORT_SYMBOL_GPL(kvm_get_cr8);
694
695 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
696 {
697         switch (dr) {
698         case 0 ... 3:
699                 vcpu->arch.db[dr] = val;
700                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
701                         vcpu->arch.eff_db[dr] = val;
702                 break;
703         case 4:
704                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705                         return 1; /* #UD */
706                 /* fall through */
707         case 6:
708                 if (val & 0xffffffff00000000ULL)
709                         return -1; /* #GP */
710                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
711                 break;
712         case 5:
713                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
714                         return 1; /* #UD */
715                 /* fall through */
716         default: /* 7 */
717                 if (val & 0xffffffff00000000ULL)
718                         return -1; /* #GP */
719                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
720                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
721                         kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
722                         vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
723                 }
724                 break;
725         }
726
727         return 0;
728 }
729
730 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
731 {
732         int res;
733
734         res = __kvm_set_dr(vcpu, dr, val);
735         if (res > 0)
736                 kvm_queue_exception(vcpu, UD_VECTOR);
737         else if (res < 0)
738                 kvm_inject_gp(vcpu, 0);
739
740         return res;
741 }
742 EXPORT_SYMBOL_GPL(kvm_set_dr);
743
744 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
745 {
746         switch (dr) {
747         case 0 ... 3:
748                 *val = vcpu->arch.db[dr];
749                 break;
750         case 4:
751                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
752                         return 1;
753                 /* fall through */
754         case 6:
755                 *val = vcpu->arch.dr6;
756                 break;
757         case 5:
758                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
759                         return 1;
760                 /* fall through */
761         default: /* 7 */
762                 *val = vcpu->arch.dr7;
763                 break;
764         }
765
766         return 0;
767 }
768
769 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
770 {
771         if (_kvm_get_dr(vcpu, dr, val)) {
772                 kvm_queue_exception(vcpu, UD_VECTOR);
773                 return 1;
774         }
775         return 0;
776 }
777 EXPORT_SYMBOL_GPL(kvm_get_dr);
778
779 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
780 {
781         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
782         u64 data;
783         int err;
784
785         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
786         if (err)
787                 return err;
788         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
789         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
790         return err;
791 }
792 EXPORT_SYMBOL_GPL(kvm_rdpmc);
793
794 /*
795  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
796  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
797  *
798  * This list is modified at module load time to reflect the
799  * capabilities of the host cpu. This capabilities test skips MSRs that are
800  * kvm-specific. Those are put in the beginning of the list.
801  */
802
803 #define KVM_SAVE_MSRS_BEGIN     10
804 static u32 msrs_to_save[] = {
805         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
806         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
807         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
808         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
809         MSR_KVM_PV_EOI_EN,
810         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
811         MSR_STAR,
812 #ifdef CONFIG_X86_64
813         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
814 #endif
815         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
816 };
817
818 static unsigned num_msrs_to_save;
819
820 static const u32 emulated_msrs[] = {
821         MSR_IA32_TSCDEADLINE,
822         MSR_IA32_MISC_ENABLE,
823         MSR_IA32_MCG_STATUS,
824         MSR_IA32_MCG_CTL,
825 };
826
827 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
828 {
829         u64 old_efer = vcpu->arch.efer;
830
831         if (efer & efer_reserved_bits)
832                 return 1;
833
834         if (is_paging(vcpu)
835             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
836                 return 1;
837
838         if (efer & EFER_FFXSR) {
839                 struct kvm_cpuid_entry2 *feat;
840
841                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
842                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
843                         return 1;
844         }
845
846         if (efer & EFER_SVME) {
847                 struct kvm_cpuid_entry2 *feat;
848
849                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
850                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
851                         return 1;
852         }
853
854         efer &= ~EFER_LMA;
855         efer |= vcpu->arch.efer & EFER_LMA;
856
857         kvm_x86_ops->set_efer(vcpu, efer);
858
859         vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
860
861         /* Update reserved bits */
862         if ((efer ^ old_efer) & EFER_NX)
863                 kvm_mmu_reset_context(vcpu);
864
865         return 0;
866 }
867
868 void kvm_enable_efer_bits(u64 mask)
869 {
870        efer_reserved_bits &= ~mask;
871 }
872 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
873
874
875 /*
876  * Writes msr value into into the appropriate "register".
877  * Returns 0 on success, non-0 otherwise.
878  * Assumes vcpu_load() was already called.
879  */
880 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
881 {
882         return kvm_x86_ops->set_msr(vcpu, msr_index, data);
883 }
884
885 /*
886  * Adapt set_msr() to msr_io()'s calling convention
887  */
888 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
889 {
890         return kvm_set_msr(vcpu, index, *data);
891 }
892
893 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
894 {
895         int version;
896         int r;
897         struct pvclock_wall_clock wc;
898         struct timespec boot;
899
900         if (!wall_clock)
901                 return;
902
903         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
904         if (r)
905                 return;
906
907         if (version & 1)
908                 ++version;  /* first time write, random junk */
909
910         ++version;
911
912         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
913
914         /*
915          * The guest calculates current wall clock time by adding
916          * system time (updated by kvm_guest_time_update below) to the
917          * wall clock specified here.  guest system time equals host
918          * system time for us, thus we must fill in host boot time here.
919          */
920         getboottime(&boot);
921
922         if (kvm->arch.kvmclock_offset) {
923                 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
924                 boot = timespec_sub(boot, ts);
925         }
926         wc.sec = boot.tv_sec;
927         wc.nsec = boot.tv_nsec;
928         wc.version = version;
929
930         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
931
932         version++;
933         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
934 }
935
936 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
937 {
938         uint32_t quotient, remainder;
939
940         /* Don't try to replace with do_div(), this one calculates
941          * "(dividend << 32) / divisor" */
942         __asm__ ( "divl %4"
943                   : "=a" (quotient), "=d" (remainder)
944                   : "0" (0), "1" (dividend), "r" (divisor) );
945         return quotient;
946 }
947
948 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
949                                s8 *pshift, u32 *pmultiplier)
950 {
951         uint64_t scaled64;
952         int32_t  shift = 0;
953         uint64_t tps64;
954         uint32_t tps32;
955
956         tps64 = base_khz * 1000LL;
957         scaled64 = scaled_khz * 1000LL;
958         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
959                 tps64 >>= 1;
960                 shift--;
961         }
962
963         tps32 = (uint32_t)tps64;
964         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
965                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
966                         scaled64 >>= 1;
967                 else
968                         tps32 <<= 1;
969                 shift++;
970         }
971
972         *pshift = shift;
973         *pmultiplier = div_frac(scaled64, tps32);
974
975         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
976                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
977 }
978
979 static inline u64 get_kernel_ns(void)
980 {
981         struct timespec ts;
982
983         WARN_ON(preemptible());
984         ktime_get_ts(&ts);
985         monotonic_to_bootbased(&ts);
986         return timespec_to_ns(&ts);
987 }
988
989 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
990 unsigned long max_tsc_khz;
991
992 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
993 {
994         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
995                                    vcpu->arch.virtual_tsc_shift);
996 }
997
998 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
999 {
1000         u64 v = (u64)khz * (1000000 + ppm);
1001         do_div(v, 1000000);
1002         return v;
1003 }
1004
1005 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1006 {
1007         u32 thresh_lo, thresh_hi;
1008         int use_scaling = 0;
1009
1010         /* Compute a scale to convert nanoseconds in TSC cycles */
1011         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1012                            &vcpu->arch.virtual_tsc_shift,
1013                            &vcpu->arch.virtual_tsc_mult);
1014         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1015
1016         /*
1017          * Compute the variation in TSC rate which is acceptable
1018          * within the range of tolerance and decide if the
1019          * rate being applied is within that bounds of the hardware
1020          * rate.  If so, no scaling or compensation need be done.
1021          */
1022         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1023         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1024         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1025                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1026                 use_scaling = 1;
1027         }
1028         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1029 }
1030
1031 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1032 {
1033         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1034                                       vcpu->arch.virtual_tsc_mult,
1035                                       vcpu->arch.virtual_tsc_shift);
1036         tsc += vcpu->arch.this_tsc_write;
1037         return tsc;
1038 }
1039
1040 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1041 {
1042         struct kvm *kvm = vcpu->kvm;
1043         u64 offset, ns, elapsed;
1044         unsigned long flags;
1045         s64 usdiff;
1046
1047         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1048         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1049         ns = get_kernel_ns();
1050         elapsed = ns - kvm->arch.last_tsc_nsec;
1051
1052         /* n.b - signed multiplication and division required */
1053         usdiff = data - kvm->arch.last_tsc_write;
1054 #ifdef CONFIG_X86_64
1055         usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1056 #else
1057         /* do_div() only does unsigned */
1058         asm("idivl %2; xor %%edx, %%edx"
1059             : "=A"(usdiff)
1060             : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1061 #endif
1062         do_div(elapsed, 1000);
1063         usdiff -= elapsed;
1064         if (usdiff < 0)
1065                 usdiff = -usdiff;
1066
1067         /*
1068          * Special case: TSC write with a small delta (1 second) of virtual
1069          * cycle time against real time is interpreted as an attempt to
1070          * synchronize the CPU.
1071          *
1072          * For a reliable TSC, we can match TSC offsets, and for an unstable
1073          * TSC, we add elapsed time in this computation.  We could let the
1074          * compensation code attempt to catch up if we fall behind, but
1075          * it's better to try to match offsets from the beginning.
1076          */
1077         if (usdiff < USEC_PER_SEC &&
1078             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1079                 if (!check_tsc_unstable()) {
1080                         offset = kvm->arch.cur_tsc_offset;
1081                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1082                 } else {
1083                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1084                         data += delta;
1085                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1086                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1087                 }
1088         } else {
1089                 /*
1090                  * We split periods of matched TSC writes into generations.
1091                  * For each generation, we track the original measured
1092                  * nanosecond time, offset, and write, so if TSCs are in
1093                  * sync, we can match exact offset, and if not, we can match
1094                  * exact software computation in compute_guest_tsc()
1095                  *
1096                  * These values are tracked in kvm->arch.cur_xxx variables.
1097                  */
1098                 kvm->arch.cur_tsc_generation++;
1099                 kvm->arch.cur_tsc_nsec = ns;
1100                 kvm->arch.cur_tsc_write = data;
1101                 kvm->arch.cur_tsc_offset = offset;
1102                 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1103                          kvm->arch.cur_tsc_generation, data);
1104         }
1105
1106         /*
1107          * We also track th most recent recorded KHZ, write and time to
1108          * allow the matching interval to be extended at each write.
1109          */
1110         kvm->arch.last_tsc_nsec = ns;
1111         kvm->arch.last_tsc_write = data;
1112         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1113
1114         /* Reset of TSC must disable overshoot protection below */
1115         vcpu->arch.hv_clock.tsc_timestamp = 0;
1116         vcpu->arch.last_guest_tsc = data;
1117
1118         /* Keep track of which generation this VCPU has synchronized to */
1119         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1120         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1121         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1122
1123         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1124         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1125 }
1126
1127 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1128
1129 static int kvm_guest_time_update(struct kvm_vcpu *v)
1130 {
1131         unsigned long flags;
1132         struct kvm_vcpu_arch *vcpu = &v->arch;
1133         void *shared_kaddr;
1134         unsigned long this_tsc_khz;
1135         s64 kernel_ns, max_kernel_ns;
1136         u64 tsc_timestamp;
1137         u8 pvclock_flags;
1138
1139         /* Keep irq disabled to prevent changes to the clock */
1140         local_irq_save(flags);
1141         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1142         kernel_ns = get_kernel_ns();
1143         this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1144         if (unlikely(this_tsc_khz == 0)) {
1145                 local_irq_restore(flags);
1146                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1147                 return 1;
1148         }
1149
1150         /*
1151          * We may have to catch up the TSC to match elapsed wall clock
1152          * time for two reasons, even if kvmclock is used.
1153          *   1) CPU could have been running below the maximum TSC rate
1154          *   2) Broken TSC compensation resets the base at each VCPU
1155          *      entry to avoid unknown leaps of TSC even when running
1156          *      again on the same CPU.  This may cause apparent elapsed
1157          *      time to disappear, and the guest to stand still or run
1158          *      very slowly.
1159          */
1160         if (vcpu->tsc_catchup) {
1161                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1162                 if (tsc > tsc_timestamp) {
1163                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1164                         tsc_timestamp = tsc;
1165                 }
1166         }
1167
1168         local_irq_restore(flags);
1169
1170         if (!vcpu->time_page)
1171                 return 0;
1172
1173         /*
1174          * Time as measured by the TSC may go backwards when resetting the base
1175          * tsc_timestamp.  The reason for this is that the TSC resolution is
1176          * higher than the resolution of the other clock scales.  Thus, many
1177          * possible measurments of the TSC correspond to one measurement of any
1178          * other clock, and so a spread of values is possible.  This is not a
1179          * problem for the computation of the nanosecond clock; with TSC rates
1180          * around 1GHZ, there can only be a few cycles which correspond to one
1181          * nanosecond value, and any path through this code will inevitably
1182          * take longer than that.  However, with the kernel_ns value itself,
1183          * the precision may be much lower, down to HZ granularity.  If the
1184          * first sampling of TSC against kernel_ns ends in the low part of the
1185          * range, and the second in the high end of the range, we can get:
1186          *
1187          * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1188          *
1189          * As the sampling errors potentially range in the thousands of cycles,
1190          * it is possible such a time value has already been observed by the
1191          * guest.  To protect against this, we must compute the system time as
1192          * observed by the guest and ensure the new system time is greater.
1193          */
1194         max_kernel_ns = 0;
1195         if (vcpu->hv_clock.tsc_timestamp) {
1196                 max_kernel_ns = vcpu->last_guest_tsc -
1197                                 vcpu->hv_clock.tsc_timestamp;
1198                 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1199                                     vcpu->hv_clock.tsc_to_system_mul,
1200                                     vcpu->hv_clock.tsc_shift);
1201                 max_kernel_ns += vcpu->last_kernel_ns;
1202         }
1203
1204         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1205                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1206                                    &vcpu->hv_clock.tsc_shift,
1207                                    &vcpu->hv_clock.tsc_to_system_mul);
1208                 vcpu->hw_tsc_khz = this_tsc_khz;
1209         }
1210
1211         if (max_kernel_ns > kernel_ns)
1212                 kernel_ns = max_kernel_ns;
1213
1214         /* With all the info we got, fill in the values */
1215         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1216         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1217         vcpu->last_kernel_ns = kernel_ns;
1218         vcpu->last_guest_tsc = tsc_timestamp;
1219
1220         pvclock_flags = 0;
1221         if (vcpu->pvclock_set_guest_stopped_request) {
1222                 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1223                 vcpu->pvclock_set_guest_stopped_request = false;
1224         }
1225
1226         vcpu->hv_clock.flags = pvclock_flags;
1227
1228         /*
1229          * The interface expects us to write an even number signaling that the
1230          * update is finished. Since the guest won't see the intermediate
1231          * state, we just increase by 2 at the end.
1232          */
1233         vcpu->hv_clock.version += 2;
1234
1235         shared_kaddr = kmap_atomic(vcpu->time_page);
1236
1237         memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1238                sizeof(vcpu->hv_clock));
1239
1240         kunmap_atomic(shared_kaddr);
1241
1242         mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1243         return 0;
1244 }
1245
1246 static bool msr_mtrr_valid(unsigned msr)
1247 {
1248         switch (msr) {
1249         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1250         case MSR_MTRRfix64K_00000:
1251         case MSR_MTRRfix16K_80000:
1252         case MSR_MTRRfix16K_A0000:
1253         case MSR_MTRRfix4K_C0000:
1254         case MSR_MTRRfix4K_C8000:
1255         case MSR_MTRRfix4K_D0000:
1256         case MSR_MTRRfix4K_D8000:
1257         case MSR_MTRRfix4K_E0000:
1258         case MSR_MTRRfix4K_E8000:
1259         case MSR_MTRRfix4K_F0000:
1260         case MSR_MTRRfix4K_F8000:
1261         case MSR_MTRRdefType:
1262         case MSR_IA32_CR_PAT:
1263                 return true;
1264         case 0x2f8:
1265                 return true;
1266         }
1267         return false;
1268 }
1269
1270 static bool valid_pat_type(unsigned t)
1271 {
1272         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1273 }
1274
1275 static bool valid_mtrr_type(unsigned t)
1276 {
1277         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1278 }
1279
1280 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1281 {
1282         int i;
1283
1284         if (!msr_mtrr_valid(msr))
1285                 return false;
1286
1287         if (msr == MSR_IA32_CR_PAT) {
1288                 for (i = 0; i < 8; i++)
1289                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1290                                 return false;
1291                 return true;
1292         } else if (msr == MSR_MTRRdefType) {
1293                 if (data & ~0xcff)
1294                         return false;
1295                 return valid_mtrr_type(data & 0xff);
1296         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1297                 for (i = 0; i < 8 ; i++)
1298                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1299                                 return false;
1300                 return true;
1301         }
1302
1303         /* variable MTRRs */
1304         return valid_mtrr_type(data & 0xff);
1305 }
1306
1307 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1308 {
1309         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1310
1311         if (!mtrr_valid(vcpu, msr, data))
1312                 return 1;
1313
1314         if (msr == MSR_MTRRdefType) {
1315                 vcpu->arch.mtrr_state.def_type = data;
1316                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1317         } else if (msr == MSR_MTRRfix64K_00000)
1318                 p[0] = data;
1319         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1320                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1321         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1322                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1323         else if (msr == MSR_IA32_CR_PAT)
1324                 vcpu->arch.pat = data;
1325         else {  /* Variable MTRRs */
1326                 int idx, is_mtrr_mask;
1327                 u64 *pt;
1328
1329                 idx = (msr - 0x200) / 2;
1330                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1331                 if (!is_mtrr_mask)
1332                         pt =
1333                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1334                 else
1335                         pt =
1336                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1337                 *pt = data;
1338         }
1339
1340         kvm_mmu_reset_context(vcpu);
1341         return 0;
1342 }
1343
1344 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1345 {
1346         u64 mcg_cap = vcpu->arch.mcg_cap;
1347         unsigned bank_num = mcg_cap & 0xff;
1348
1349         switch (msr) {
1350         case MSR_IA32_MCG_STATUS:
1351                 vcpu->arch.mcg_status = data;
1352                 break;
1353         case MSR_IA32_MCG_CTL:
1354                 if (!(mcg_cap & MCG_CTL_P))
1355                         return 1;
1356                 if (data != 0 && data != ~(u64)0)
1357                         return -1;
1358                 vcpu->arch.mcg_ctl = data;
1359                 break;
1360         default:
1361                 if (msr >= MSR_IA32_MC0_CTL &&
1362                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1363                         u32 offset = msr - MSR_IA32_MC0_CTL;
1364                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1365                          * some Linux kernels though clear bit 10 in bank 4 to
1366                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1367                          * this to avoid an uncatched #GP in the guest
1368                          */
1369                         if ((offset & 0x3) == 0 &&
1370                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1371                                 return -1;
1372                         vcpu->arch.mce_banks[offset] = data;
1373                         break;
1374                 }
1375                 return 1;
1376         }
1377         return 0;
1378 }
1379
1380 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1381 {
1382         struct kvm *kvm = vcpu->kvm;
1383         int lm = is_long_mode(vcpu);
1384         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1385                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1386         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1387                 : kvm->arch.xen_hvm_config.blob_size_32;
1388         u32 page_num = data & ~PAGE_MASK;
1389         u64 page_addr = data & PAGE_MASK;
1390         u8 *page;
1391         int r;
1392
1393         r = -E2BIG;
1394         if (page_num >= blob_size)
1395                 goto out;
1396         r = -ENOMEM;
1397         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1398         if (IS_ERR(page)) {
1399                 r = PTR_ERR(page);
1400                 goto out;
1401         }
1402         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1403                 goto out_free;
1404         r = 0;
1405 out_free:
1406         kfree(page);
1407 out:
1408         return r;
1409 }
1410
1411 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1412 {
1413         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1414 }
1415
1416 static bool kvm_hv_msr_partition_wide(u32 msr)
1417 {
1418         bool r = false;
1419         switch (msr) {
1420         case HV_X64_MSR_GUEST_OS_ID:
1421         case HV_X64_MSR_HYPERCALL:
1422                 r = true;
1423                 break;
1424         }
1425
1426         return r;
1427 }
1428
1429 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1430 {
1431         struct kvm *kvm = vcpu->kvm;
1432
1433         switch (msr) {
1434         case HV_X64_MSR_GUEST_OS_ID:
1435                 kvm->arch.hv_guest_os_id = data;
1436                 /* setting guest os id to zero disables hypercall page */
1437                 if (!kvm->arch.hv_guest_os_id)
1438                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1439                 break;
1440         case HV_X64_MSR_HYPERCALL: {
1441                 u64 gfn;
1442                 unsigned long addr;
1443                 u8 instructions[4];
1444
1445                 /* if guest os id is not set hypercall should remain disabled */
1446                 if (!kvm->arch.hv_guest_os_id)
1447                         break;
1448                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1449                         kvm->arch.hv_hypercall = data;
1450                         break;
1451                 }
1452                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1453                 addr = gfn_to_hva(kvm, gfn);
1454                 if (kvm_is_error_hva(addr))
1455                         return 1;
1456                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1457                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1458                 if (__copy_to_user((void __user *)addr, instructions, 4))
1459                         return 1;
1460                 kvm->arch.hv_hypercall = data;
1461                 break;
1462         }
1463         default:
1464                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1465                             "data 0x%llx\n", msr, data);
1466                 return 1;
1467         }
1468         return 0;
1469 }
1470
1471 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1472 {
1473         switch (msr) {
1474         case HV_X64_MSR_APIC_ASSIST_PAGE: {
1475                 unsigned long addr;
1476
1477                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1478                         vcpu->arch.hv_vapic = data;
1479                         break;
1480                 }
1481                 addr = gfn_to_hva(vcpu->kvm, data >>
1482                                   HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1483                 if (kvm_is_error_hva(addr))
1484                         return 1;
1485                 if (__clear_user((void __user *)addr, PAGE_SIZE))
1486                         return 1;
1487                 vcpu->arch.hv_vapic = data;
1488                 break;
1489         }
1490         case HV_X64_MSR_EOI:
1491                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1492         case HV_X64_MSR_ICR:
1493                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1494         case HV_X64_MSR_TPR:
1495                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1496         default:
1497                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1498                             "data 0x%llx\n", msr, data);
1499                 return 1;
1500         }
1501
1502         return 0;
1503 }
1504
1505 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1506 {
1507         gpa_t gpa = data & ~0x3f;
1508
1509         /* Bits 2:5 are reserved, Should be zero */
1510         if (data & 0x3c)
1511                 return 1;
1512
1513         vcpu->arch.apf.msr_val = data;
1514
1515         if (!(data & KVM_ASYNC_PF_ENABLED)) {
1516                 kvm_clear_async_pf_completion_queue(vcpu);
1517                 kvm_async_pf_hash_reset(vcpu);
1518                 return 0;
1519         }
1520
1521         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1522                 return 1;
1523
1524         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1525         kvm_async_pf_wakeup_all(vcpu);
1526         return 0;
1527 }
1528
1529 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1530 {
1531         if (vcpu->arch.time_page) {
1532                 kvm_release_page_dirty(vcpu->arch.time_page);
1533                 vcpu->arch.time_page = NULL;
1534         }
1535 }
1536
1537 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1538 {
1539         u64 delta;
1540
1541         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1542                 return;
1543
1544         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1545         vcpu->arch.st.last_steal = current->sched_info.run_delay;
1546         vcpu->arch.st.accum_steal = delta;
1547 }
1548
1549 static void record_steal_time(struct kvm_vcpu *vcpu)
1550 {
1551         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1552                 return;
1553
1554         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1555                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1556                 return;
1557
1558         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1559         vcpu->arch.st.steal.version += 2;
1560         vcpu->arch.st.accum_steal = 0;
1561
1562         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1563                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1564 }
1565
1566 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1567 {
1568         bool pr = false;
1569
1570         switch (msr) {
1571         case MSR_EFER:
1572                 return set_efer(vcpu, data);
1573         case MSR_K7_HWCR:
1574                 data &= ~(u64)0x40;     /* ignore flush filter disable */
1575                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
1576                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
1577                 if (data != 0) {
1578                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1579                                     data);
1580                         return 1;
1581                 }
1582                 break;
1583         case MSR_FAM10H_MMIO_CONF_BASE:
1584                 if (data != 0) {
1585                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1586                                     "0x%llx\n", data);
1587                         return 1;
1588                 }
1589                 break;
1590         case MSR_AMD64_NB_CFG:
1591                 break;
1592         case MSR_IA32_DEBUGCTLMSR:
1593                 if (!data) {
1594                         /* We support the non-activated case already */
1595                         break;
1596                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1597                         /* Values other than LBR and BTF are vendor-specific,
1598                            thus reserved and should throw a #GP */
1599                         return 1;
1600                 }
1601                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1602                             __func__, data);
1603                 break;
1604         case MSR_IA32_UCODE_REV:
1605         case MSR_IA32_UCODE_WRITE:
1606         case MSR_VM_HSAVE_PA:
1607         case MSR_AMD64_PATCH_LOADER:
1608                 break;
1609         case 0x200 ... 0x2ff:
1610                 return set_msr_mtrr(vcpu, msr, data);
1611         case MSR_IA32_APICBASE:
1612                 kvm_set_apic_base(vcpu, data);
1613                 break;
1614         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1615                 return kvm_x2apic_msr_write(vcpu, msr, data);
1616         case MSR_IA32_TSCDEADLINE:
1617                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1618                 break;
1619         case MSR_IA32_MISC_ENABLE:
1620                 vcpu->arch.ia32_misc_enable_msr = data;
1621                 break;
1622         case MSR_KVM_WALL_CLOCK_NEW:
1623         case MSR_KVM_WALL_CLOCK:
1624                 vcpu->kvm->arch.wall_clock = data;
1625                 kvm_write_wall_clock(vcpu->kvm, data);
1626                 break;
1627         case MSR_KVM_SYSTEM_TIME_NEW:
1628         case MSR_KVM_SYSTEM_TIME: {
1629                 kvmclock_reset(vcpu);
1630
1631                 vcpu->arch.time = data;
1632                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1633
1634                 /* we verify if the enable bit is set... */
1635                 if (!(data & 1))
1636                         break;
1637
1638                 /* ...but clean it before doing the actual write */
1639                 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1640
1641                 vcpu->arch.time_page =
1642                                 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1643
1644                 if (is_error_page(vcpu->arch.time_page))
1645                         vcpu->arch.time_page = NULL;
1646
1647                 break;
1648         }
1649         case MSR_KVM_ASYNC_PF_EN:
1650                 if (kvm_pv_enable_async_pf(vcpu, data))
1651                         return 1;
1652                 break;
1653         case MSR_KVM_STEAL_TIME:
1654
1655                 if (unlikely(!sched_info_on()))
1656                         return 1;
1657
1658                 if (data & KVM_STEAL_RESERVED_MASK)
1659                         return 1;
1660
1661                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1662                                                         data & KVM_STEAL_VALID_BITS))
1663                         return 1;
1664
1665                 vcpu->arch.st.msr_val = data;
1666
1667                 if (!(data & KVM_MSR_ENABLED))
1668                         break;
1669
1670                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1671
1672                 preempt_disable();
1673                 accumulate_steal_time(vcpu);
1674                 preempt_enable();
1675
1676                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1677
1678                 break;
1679         case MSR_KVM_PV_EOI_EN:
1680                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1681                         return 1;
1682                 break;
1683
1684         case MSR_IA32_MCG_CTL:
1685         case MSR_IA32_MCG_STATUS:
1686         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1687                 return set_msr_mce(vcpu, msr, data);
1688
1689         /* Performance counters are not protected by a CPUID bit,
1690          * so we should check all of them in the generic path for the sake of
1691          * cross vendor migration.
1692          * Writing a zero into the event select MSRs disables them,
1693          * which we perfectly emulate ;-). Any other value should be at least
1694          * reported, some guests depend on them.
1695          */
1696         case MSR_K7_EVNTSEL0:
1697         case MSR_K7_EVNTSEL1:
1698         case MSR_K7_EVNTSEL2:
1699         case MSR_K7_EVNTSEL3:
1700                 if (data != 0)
1701                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1702                                     "0x%x data 0x%llx\n", msr, data);
1703                 break;
1704         /* at least RHEL 4 unconditionally writes to the perfctr registers,
1705          * so we ignore writes to make it happy.
1706          */
1707         case MSR_K7_PERFCTR0:
1708         case MSR_K7_PERFCTR1:
1709         case MSR_K7_PERFCTR2:
1710         case MSR_K7_PERFCTR3:
1711                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1712                             "0x%x data 0x%llx\n", msr, data);
1713                 break;
1714         case MSR_P6_PERFCTR0:
1715         case MSR_P6_PERFCTR1:
1716                 pr = true;
1717         case MSR_P6_EVNTSEL0:
1718         case MSR_P6_EVNTSEL1:
1719                 if (kvm_pmu_msr(vcpu, msr))
1720                         return kvm_pmu_set_msr(vcpu, msr, data);
1721
1722                 if (pr || data != 0)
1723                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1724                                     "0x%x data 0x%llx\n", msr, data);
1725                 break;
1726         case MSR_K7_CLK_CTL:
1727                 /*
1728                  * Ignore all writes to this no longer documented MSR.
1729                  * Writes are only relevant for old K7 processors,
1730                  * all pre-dating SVM, but a recommended workaround from
1731                  * AMD for these chips. It is possible to specify the
1732                  * affected processor models on the command line, hence
1733                  * the need to ignore the workaround.
1734                  */
1735                 break;
1736         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1737                 if (kvm_hv_msr_partition_wide(msr)) {
1738                         int r;
1739                         mutex_lock(&vcpu->kvm->lock);
1740                         r = set_msr_hyperv_pw(vcpu, msr, data);
1741                         mutex_unlock(&vcpu->kvm->lock);
1742                         return r;
1743                 } else
1744                         return set_msr_hyperv(vcpu, msr, data);
1745                 break;
1746         case MSR_IA32_BBL_CR_CTL3:
1747                 /* Drop writes to this legacy MSR -- see rdmsr
1748                  * counterpart for further detail.
1749                  */
1750                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1751                 break;
1752         case MSR_AMD64_OSVW_ID_LENGTH:
1753                 if (!guest_cpuid_has_osvw(vcpu))
1754                         return 1;
1755                 vcpu->arch.osvw.length = data;
1756                 break;
1757         case MSR_AMD64_OSVW_STATUS:
1758                 if (!guest_cpuid_has_osvw(vcpu))
1759                         return 1;
1760                 vcpu->arch.osvw.status = data;
1761                 break;
1762         default:
1763                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1764                         return xen_hvm_config(vcpu, data);
1765                 if (kvm_pmu_msr(vcpu, msr))
1766                         return kvm_pmu_set_msr(vcpu, msr, data);
1767                 if (!ignore_msrs) {
1768                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1769                                     msr, data);
1770                         return 1;
1771                 } else {
1772                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1773                                     msr, data);
1774                         break;
1775                 }
1776         }
1777         return 0;
1778 }
1779 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1780
1781
1782 /*
1783  * Reads an msr value (of 'msr_index') into 'pdata'.
1784  * Returns 0 on success, non-0 otherwise.
1785  * Assumes vcpu_load() was already called.
1786  */
1787 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1788 {
1789         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1790 }
1791
1792 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1793 {
1794         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1795
1796         if (!msr_mtrr_valid(msr))
1797                 return 1;
1798
1799         if (msr == MSR_MTRRdefType)
1800                 *pdata = vcpu->arch.mtrr_state.def_type +
1801                          (vcpu->arch.mtrr_state.enabled << 10);
1802         else if (msr == MSR_MTRRfix64K_00000)
1803                 *pdata = p[0];
1804         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1805                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1806         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1807                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1808         else if (msr == MSR_IA32_CR_PAT)
1809                 *pdata = vcpu->arch.pat;
1810         else {  /* Variable MTRRs */
1811                 int idx, is_mtrr_mask;
1812                 u64 *pt;
1813
1814                 idx = (msr - 0x200) / 2;
1815                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1816                 if (!is_mtrr_mask)
1817                         pt =
1818                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1819                 else
1820                         pt =
1821                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1822                 *pdata = *pt;
1823         }
1824
1825         return 0;
1826 }
1827
1828 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1829 {
1830         u64 data;
1831         u64 mcg_cap = vcpu->arch.mcg_cap;
1832         unsigned bank_num = mcg_cap & 0xff;
1833
1834         switch (msr) {
1835         case MSR_IA32_P5_MC_ADDR:
1836         case MSR_IA32_P5_MC_TYPE:
1837                 data = 0;
1838                 break;
1839         case MSR_IA32_MCG_CAP:
1840                 data = vcpu->arch.mcg_cap;
1841                 break;
1842         case MSR_IA32_MCG_CTL:
1843                 if (!(mcg_cap & MCG_CTL_P))
1844                         return 1;
1845                 data = vcpu->arch.mcg_ctl;
1846                 break;
1847         case MSR_IA32_MCG_STATUS:
1848                 data = vcpu->arch.mcg_status;
1849                 break;
1850         default:
1851                 if (msr >= MSR_IA32_MC0_CTL &&
1852                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1853                         u32 offset = msr - MSR_IA32_MC0_CTL;
1854                         data = vcpu->arch.mce_banks[offset];
1855                         break;
1856                 }
1857                 return 1;
1858         }
1859         *pdata = data;
1860         return 0;
1861 }
1862
1863 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1864 {
1865         u64 data = 0;
1866         struct kvm *kvm = vcpu->kvm;
1867
1868         switch (msr) {
1869         case HV_X64_MSR_GUEST_OS_ID:
1870                 data = kvm->arch.hv_guest_os_id;
1871                 break;
1872         case HV_X64_MSR_HYPERCALL:
1873                 data = kvm->arch.hv_hypercall;
1874                 break;
1875         default:
1876                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1877                 return 1;
1878         }
1879
1880         *pdata = data;
1881         return 0;
1882 }
1883
1884 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1885 {
1886         u64 data = 0;
1887
1888         switch (msr) {
1889         case HV_X64_MSR_VP_INDEX: {
1890                 int r;
1891                 struct kvm_vcpu *v;
1892                 kvm_for_each_vcpu(r, v, vcpu->kvm)
1893                         if (v == vcpu)
1894                                 data = r;
1895                 break;
1896         }
1897         case HV_X64_MSR_EOI:
1898                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1899         case HV_X64_MSR_ICR:
1900                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1901         case HV_X64_MSR_TPR:
1902                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1903         case HV_X64_MSR_APIC_ASSIST_PAGE:
1904                 data = vcpu->arch.hv_vapic;
1905                 break;
1906         default:
1907                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1908                 return 1;
1909         }
1910         *pdata = data;
1911         return 0;
1912 }
1913
1914 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1915 {
1916         u64 data;
1917
1918         switch (msr) {
1919         case MSR_IA32_PLATFORM_ID:
1920         case MSR_IA32_EBL_CR_POWERON:
1921         case MSR_IA32_DEBUGCTLMSR:
1922         case MSR_IA32_LASTBRANCHFROMIP:
1923         case MSR_IA32_LASTBRANCHTOIP:
1924         case MSR_IA32_LASTINTFROMIP:
1925         case MSR_IA32_LASTINTTOIP:
1926         case MSR_K8_SYSCFG:
1927         case MSR_K7_HWCR:
1928         case MSR_VM_HSAVE_PA:
1929         case MSR_K7_EVNTSEL0:
1930         case MSR_K7_PERFCTR0:
1931         case MSR_K8_INT_PENDING_MSG:
1932         case MSR_AMD64_NB_CFG:
1933         case MSR_FAM10H_MMIO_CONF_BASE:
1934                 data = 0;
1935                 break;
1936         case MSR_P6_PERFCTR0:
1937         case MSR_P6_PERFCTR1:
1938         case MSR_P6_EVNTSEL0:
1939         case MSR_P6_EVNTSEL1:
1940                 if (kvm_pmu_msr(vcpu, msr))
1941                         return kvm_pmu_get_msr(vcpu, msr, pdata);
1942                 data = 0;
1943                 break;
1944         case MSR_IA32_UCODE_REV:
1945                 data = 0x100000000ULL;
1946                 break;
1947         case MSR_MTRRcap:
1948                 data = 0x500 | KVM_NR_VAR_MTRR;
1949                 break;
1950         case 0x200 ... 0x2ff:
1951                 return get_msr_mtrr(vcpu, msr, pdata);
1952         case 0xcd: /* fsb frequency */
1953                 data = 3;
1954                 break;
1955                 /*
1956                  * MSR_EBC_FREQUENCY_ID
1957                  * Conservative value valid for even the basic CPU models.
1958                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1959                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1960                  * and 266MHz for model 3, or 4. Set Core Clock
1961                  * Frequency to System Bus Frequency Ratio to 1 (bits
1962                  * 31:24) even though these are only valid for CPU
1963                  * models > 2, however guests may end up dividing or
1964                  * multiplying by zero otherwise.
1965                  */
1966         case MSR_EBC_FREQUENCY_ID:
1967                 data = 1 << 24;
1968                 break;
1969         case MSR_IA32_APICBASE:
1970                 data = kvm_get_apic_base(vcpu);
1971                 break;
1972         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1973                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1974                 break;
1975         case MSR_IA32_TSCDEADLINE:
1976                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1977                 break;
1978         case MSR_IA32_MISC_ENABLE:
1979                 data = vcpu->arch.ia32_misc_enable_msr;
1980                 break;
1981         case MSR_IA32_PERF_STATUS:
1982                 /* TSC increment by tick */
1983                 data = 1000ULL;
1984                 /* CPU multiplier */
1985                 data |= (((uint64_t)4ULL) << 40);
1986                 break;
1987         case MSR_EFER:
1988                 data = vcpu->arch.efer;
1989                 break;
1990         case MSR_KVM_WALL_CLOCK:
1991         case MSR_KVM_WALL_CLOCK_NEW:
1992                 data = vcpu->kvm->arch.wall_clock;
1993                 break;
1994         case MSR_KVM_SYSTEM_TIME:
1995         case MSR_KVM_SYSTEM_TIME_NEW:
1996                 data = vcpu->arch.time;
1997                 break;
1998         case MSR_KVM_ASYNC_PF_EN:
1999                 data = vcpu->arch.apf.msr_val;
2000                 break;
2001         case MSR_KVM_STEAL_TIME:
2002                 data = vcpu->arch.st.msr_val;
2003                 break;
2004         case MSR_IA32_P5_MC_ADDR:
2005         case MSR_IA32_P5_MC_TYPE:
2006         case MSR_IA32_MCG_CAP:
2007         case MSR_IA32_MCG_CTL:
2008         case MSR_IA32_MCG_STATUS:
2009         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2010                 return get_msr_mce(vcpu, msr, pdata);
2011         case MSR_K7_CLK_CTL:
2012                 /*
2013                  * Provide expected ramp-up count for K7. All other
2014                  * are set to zero, indicating minimum divisors for
2015                  * every field.
2016                  *
2017                  * This prevents guest kernels on AMD host with CPU
2018                  * type 6, model 8 and higher from exploding due to
2019                  * the rdmsr failing.
2020                  */
2021                 data = 0x20000000;
2022                 break;
2023         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2024                 if (kvm_hv_msr_partition_wide(msr)) {
2025                         int r;
2026                         mutex_lock(&vcpu->kvm->lock);
2027                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2028                         mutex_unlock(&vcpu->kvm->lock);
2029                         return r;
2030                 } else
2031                         return get_msr_hyperv(vcpu, msr, pdata);
2032                 break;
2033         case MSR_IA32_BBL_CR_CTL3:
2034                 /* This legacy MSR exists but isn't fully documented in current
2035                  * silicon.  It is however accessed by winxp in very narrow
2036                  * scenarios where it sets bit #19, itself documented as
2037                  * a "reserved" bit.  Best effort attempt to source coherent
2038                  * read data here should the balance of the register be
2039                  * interpreted by the guest:
2040                  *
2041                  * L2 cache control register 3: 64GB range, 256KB size,
2042                  * enabled, latency 0x1, configured
2043                  */
2044                 data = 0xbe702111;
2045                 break;
2046         case MSR_AMD64_OSVW_ID_LENGTH:
2047                 if (!guest_cpuid_has_osvw(vcpu))
2048                         return 1;
2049                 data = vcpu->arch.osvw.length;
2050                 break;
2051         case MSR_AMD64_OSVW_STATUS:
2052                 if (!guest_cpuid_has_osvw(vcpu))
2053                         return 1;
2054                 data = vcpu->arch.osvw.status;
2055                 break;
2056         default:
2057                 if (kvm_pmu_msr(vcpu, msr))
2058                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2059                 if (!ignore_msrs) {
2060                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2061                         return 1;
2062                 } else {
2063                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2064                         data = 0;
2065                 }
2066                 break;
2067         }
2068         *pdata = data;
2069         return 0;
2070 }
2071 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2072
2073 /*
2074  * Read or write a bunch of msrs. All parameters are kernel addresses.
2075  *
2076  * @return number of msrs set successfully.
2077  */
2078 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2079                     struct kvm_msr_entry *entries,
2080                     int (*do_msr)(struct kvm_vcpu *vcpu,
2081                                   unsigned index, u64 *data))
2082 {
2083         int i, idx;
2084
2085         idx = srcu_read_lock(&vcpu->kvm->srcu);
2086         for (i = 0; i < msrs->nmsrs; ++i)
2087                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2088                         break;
2089         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2090
2091         return i;
2092 }
2093
2094 /*
2095  * Read or write a bunch of msrs. Parameters are user addresses.
2096  *
2097  * @return number of msrs set successfully.
2098  */
2099 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2100                   int (*do_msr)(struct kvm_vcpu *vcpu,
2101                                 unsigned index, u64 *data),
2102                   int writeback)
2103 {
2104         struct kvm_msrs msrs;
2105         struct kvm_msr_entry *entries;
2106         int r, n;
2107         unsigned size;
2108
2109         r = -EFAULT;
2110         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2111                 goto out;
2112
2113         r = -E2BIG;
2114         if (msrs.nmsrs >= MAX_IO_MSRS)
2115                 goto out;
2116
2117         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2118         entries = memdup_user(user_msrs->entries, size);
2119         if (IS_ERR(entries)) {
2120                 r = PTR_ERR(entries);
2121                 goto out;
2122         }
2123
2124         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2125         if (r < 0)
2126                 goto out_free;
2127
2128         r = -EFAULT;
2129         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2130                 goto out_free;
2131
2132         r = n;
2133
2134 out_free:
2135         kfree(entries);
2136 out:
2137         return r;
2138 }
2139
2140 int kvm_dev_ioctl_check_extension(long ext)
2141 {
2142         int r;
2143
2144         switch (ext) {
2145         case KVM_CAP_IRQCHIP:
2146         case KVM_CAP_HLT:
2147         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2148         case KVM_CAP_SET_TSS_ADDR:
2149         case KVM_CAP_EXT_CPUID:
2150         case KVM_CAP_CLOCKSOURCE:
2151         case KVM_CAP_PIT:
2152         case KVM_CAP_NOP_IO_DELAY:
2153         case KVM_CAP_MP_STATE:
2154         case KVM_CAP_SYNC_MMU:
2155         case KVM_CAP_USER_NMI:
2156         case KVM_CAP_REINJECT_CONTROL:
2157         case KVM_CAP_IRQ_INJECT_STATUS:
2158         case KVM_CAP_ASSIGN_DEV_IRQ:
2159         case KVM_CAP_IRQFD:
2160         case KVM_CAP_IOEVENTFD:
2161         case KVM_CAP_PIT2:
2162         case KVM_CAP_PIT_STATE2:
2163         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2164         case KVM_CAP_XEN_HVM:
2165         case KVM_CAP_ADJUST_CLOCK:
2166         case KVM_CAP_VCPU_EVENTS:
2167         case KVM_CAP_HYPERV:
2168         case KVM_CAP_HYPERV_VAPIC:
2169         case KVM_CAP_HYPERV_SPIN:
2170         case KVM_CAP_PCI_SEGMENT:
2171         case KVM_CAP_DEBUGREGS:
2172         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2173         case KVM_CAP_XSAVE:
2174         case KVM_CAP_ASYNC_PF:
2175         case KVM_CAP_GET_TSC_KHZ:
2176         case KVM_CAP_PCI_2_3:
2177         case KVM_CAP_KVMCLOCK_CTRL:
2178         case KVM_CAP_READONLY_MEM:
2179         case KVM_CAP_IRQFD_RESAMPLE:
2180                 r = 1;
2181                 break;
2182         case KVM_CAP_COALESCED_MMIO:
2183                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2184                 break;
2185         case KVM_CAP_VAPIC:
2186                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2187                 break;
2188         case KVM_CAP_NR_VCPUS:
2189                 r = KVM_SOFT_MAX_VCPUS;
2190                 break;
2191         case KVM_CAP_MAX_VCPUS:
2192                 r = KVM_MAX_VCPUS;
2193                 break;
2194         case KVM_CAP_NR_MEMSLOTS:
2195                 r = KVM_MEMORY_SLOTS;
2196                 break;
2197         case KVM_CAP_PV_MMU:    /* obsolete */
2198                 r = 0;
2199                 break;
2200         case KVM_CAP_IOMMU:
2201                 r = iommu_present(&pci_bus_type);
2202                 break;
2203         case KVM_CAP_MCE:
2204                 r = KVM_MAX_MCE_BANKS;
2205                 break;
2206         case KVM_CAP_XCRS:
2207                 r = cpu_has_xsave;
2208                 break;
2209         case KVM_CAP_TSC_CONTROL:
2210                 r = kvm_has_tsc_control;
2211                 break;
2212         case KVM_CAP_TSC_DEADLINE_TIMER:
2213                 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2214                 break;
2215         default:
2216                 r = 0;
2217                 break;
2218         }
2219         return r;
2220
2221 }
2222
2223 long kvm_arch_dev_ioctl(struct file *filp,
2224                         unsigned int ioctl, unsigned long arg)
2225 {
2226         void __user *argp = (void __user *)arg;
2227         long r;
2228
2229         switch (ioctl) {
2230         case KVM_GET_MSR_INDEX_LIST: {
2231                 struct kvm_msr_list __user *user_msr_list = argp;
2232                 struct kvm_msr_list msr_list;
2233                 unsigned n;
2234
2235                 r = -EFAULT;
2236                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2237                         goto out;
2238                 n = msr_list.nmsrs;
2239                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2240                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2241                         goto out;
2242                 r = -E2BIG;
2243                 if (n < msr_list.nmsrs)
2244                         goto out;
2245                 r = -EFAULT;
2246                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2247                                  num_msrs_to_save * sizeof(u32)))
2248                         goto out;
2249                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2250                                  &emulated_msrs,
2251                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2252                         goto out;
2253                 r = 0;
2254                 break;
2255         }
2256         case KVM_GET_SUPPORTED_CPUID: {
2257                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2258                 struct kvm_cpuid2 cpuid;
2259
2260                 r = -EFAULT;
2261                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2262                         goto out;
2263                 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2264                                                       cpuid_arg->entries);
2265                 if (r)
2266                         goto out;
2267
2268                 r = -EFAULT;
2269                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2270                         goto out;
2271                 r = 0;
2272                 break;
2273         }
2274         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2275                 u64 mce_cap;
2276
2277                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2278                 r = -EFAULT;
2279                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2280                         goto out;
2281                 r = 0;
2282                 break;
2283         }
2284         default:
2285                 r = -EINVAL;
2286         }
2287 out:
2288         return r;
2289 }
2290
2291 static void wbinvd_ipi(void *garbage)
2292 {
2293         wbinvd();
2294 }
2295
2296 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2297 {
2298         return vcpu->kvm->arch.iommu_domain &&
2299                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2300 }
2301
2302 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2303 {
2304         /* Address WBINVD may be executed by guest */
2305         if (need_emulate_wbinvd(vcpu)) {
2306                 if (kvm_x86_ops->has_wbinvd_exit())
2307                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2308                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2309                         smp_call_function_single(vcpu->cpu,
2310                                         wbinvd_ipi, NULL, 1);
2311         }
2312
2313         kvm_x86_ops->vcpu_load(vcpu, cpu);
2314
2315         /* Apply any externally detected TSC adjustments (due to suspend) */
2316         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2317                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2318                 vcpu->arch.tsc_offset_adjustment = 0;
2319                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2320         }
2321
2322         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2323                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2324                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2325                 if (tsc_delta < 0)
2326                         mark_tsc_unstable("KVM discovered backwards TSC");
2327                 if (check_tsc_unstable()) {
2328                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2329                                                 vcpu->arch.last_guest_tsc);
2330                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2331                         vcpu->arch.tsc_catchup = 1;
2332                 }
2333                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2334                 if (vcpu->cpu != cpu)
2335                         kvm_migrate_timers(vcpu);
2336                 vcpu->cpu = cpu;
2337         }
2338
2339         accumulate_steal_time(vcpu);
2340         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2341 }
2342
2343 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2344 {
2345         kvm_x86_ops->vcpu_put(vcpu);
2346         kvm_put_guest_fpu(vcpu);
2347         vcpu->arch.last_host_tsc = native_read_tsc();
2348 }
2349
2350 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2351                                     struct kvm_lapic_state *s)
2352 {
2353         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2354
2355         return 0;
2356 }
2357
2358 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2359                                     struct kvm_lapic_state *s)
2360 {
2361         kvm_apic_post_state_restore(vcpu, s);
2362         update_cr8_intercept(vcpu);
2363
2364         return 0;
2365 }
2366
2367 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2368                                     struct kvm_interrupt *irq)
2369 {
2370         if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS)
2371                 return -EINVAL;
2372         if (irqchip_in_kernel(vcpu->kvm))
2373                 return -ENXIO;
2374
2375         kvm_queue_interrupt(vcpu, irq->irq, false);
2376         kvm_make_request(KVM_REQ_EVENT, vcpu);
2377
2378         return 0;
2379 }
2380
2381 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2382 {
2383         kvm_inject_nmi(vcpu);
2384
2385         return 0;
2386 }
2387
2388 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2389                                            struct kvm_tpr_access_ctl *tac)
2390 {
2391         if (tac->flags)
2392                 return -EINVAL;
2393         vcpu->arch.tpr_access_reporting = !!tac->enabled;
2394         return 0;
2395 }
2396
2397 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2398                                         u64 mcg_cap)
2399 {
2400         int r;
2401         unsigned bank_num = mcg_cap & 0xff, bank;
2402
2403         r = -EINVAL;
2404         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2405                 goto out;
2406         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2407                 goto out;
2408         r = 0;
2409         vcpu->arch.mcg_cap = mcg_cap;
2410         /* Init IA32_MCG_CTL to all 1s */
2411         if (mcg_cap & MCG_CTL_P)
2412                 vcpu->arch.mcg_ctl = ~(u64)0;
2413         /* Init IA32_MCi_CTL to all 1s */
2414         for (bank = 0; bank < bank_num; bank++)
2415                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2416 out:
2417         return r;
2418 }
2419
2420 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2421                                       struct kvm_x86_mce *mce)
2422 {
2423         u64 mcg_cap = vcpu->arch.mcg_cap;
2424         unsigned bank_num = mcg_cap & 0xff;
2425         u64 *banks = vcpu->arch.mce_banks;
2426
2427         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2428                 return -EINVAL;
2429         /*
2430          * if IA32_MCG_CTL is not all 1s, the uncorrected error
2431          * reporting is disabled
2432          */
2433         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2434             vcpu->arch.mcg_ctl != ~(u64)0)
2435                 return 0;
2436         banks += 4 * mce->bank;
2437         /*
2438          * if IA32_MCi_CTL is not all 1s, the uncorrected error
2439          * reporting is disabled for the bank
2440          */
2441         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2442                 return 0;
2443         if (mce->status & MCI_STATUS_UC) {
2444                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2445                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2446                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2447                         return 0;
2448                 }
2449                 if (banks[1] & MCI_STATUS_VAL)
2450                         mce->status |= MCI_STATUS_OVER;
2451                 banks[2] = mce->addr;
2452                 banks[3] = mce->misc;
2453                 vcpu->arch.mcg_status = mce->mcg_status;
2454                 banks[1] = mce->status;
2455                 kvm_queue_exception(vcpu, MC_VECTOR);
2456         } else if (!(banks[1] & MCI_STATUS_VAL)
2457                    || !(banks[1] & MCI_STATUS_UC)) {
2458                 if (banks[1] & MCI_STATUS_VAL)
2459                         mce->status |= MCI_STATUS_OVER;
2460                 banks[2] = mce->addr;
2461                 banks[3] = mce->misc;
2462                 banks[1] = mce->status;
2463         } else
2464                 banks[1] |= MCI_STATUS_OVER;
2465         return 0;
2466 }
2467
2468 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2469                                                struct kvm_vcpu_events *events)
2470 {
2471         process_nmi(vcpu);
2472         events->exception.injected =
2473                 vcpu->arch.exception.pending &&
2474                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2475         events->exception.nr = vcpu->arch.exception.nr;
2476         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2477         events->exception.pad = 0;
2478         events->exception.error_code = vcpu->arch.exception.error_code;
2479
2480         events->interrupt.injected =
2481                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2482         events->interrupt.nr = vcpu->arch.interrupt.nr;
2483         events->interrupt.soft = 0;
2484         events->interrupt.shadow =
2485                 kvm_x86_ops->get_interrupt_shadow(vcpu,
2486                         KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2487
2488         events->nmi.injected = vcpu->arch.nmi_injected;
2489         events->nmi.pending = vcpu->arch.nmi_pending != 0;
2490         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2491         events->nmi.pad = 0;
2492
2493         events->sipi_vector = vcpu->arch.sipi_vector;
2494
2495         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2496                          | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2497                          | KVM_VCPUEVENT_VALID_SHADOW);
2498         memset(&events->reserved, 0, sizeof(events->reserved));
2499 }
2500
2501 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2502                                               struct kvm_vcpu_events *events)
2503 {
2504         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2505                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2506                               | KVM_VCPUEVENT_VALID_SHADOW))
2507                 return -EINVAL;
2508
2509         process_nmi(vcpu);
2510         vcpu->arch.exception.pending = events->exception.injected;
2511         vcpu->arch.exception.nr = events->exception.nr;
2512         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2513         vcpu->arch.exception.error_code = events->exception.error_code;
2514
2515         vcpu->arch.interrupt.pending = events->interrupt.injected;
2516         vcpu->arch.interrupt.nr = events->interrupt.nr;
2517         vcpu->arch.interrupt.soft = events->interrupt.soft;
2518         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2519                 kvm_x86_ops->set_interrupt_shadow(vcpu,
2520                                                   events->interrupt.shadow);
2521
2522         vcpu->arch.nmi_injected = events->nmi.injected;
2523         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2524                 vcpu->arch.nmi_pending = events->nmi.pending;
2525         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2526
2527         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2528                 vcpu->arch.sipi_vector = events->sipi_vector;
2529
2530         kvm_make_request(KVM_REQ_EVENT, vcpu);
2531
2532         return 0;
2533 }
2534
2535 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2536                                              struct kvm_debugregs *dbgregs)
2537 {
2538         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2539         dbgregs->dr6 = vcpu->arch.dr6;
2540         dbgregs->dr7 = vcpu->arch.dr7;
2541         dbgregs->flags = 0;
2542         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2543 }
2544
2545 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2546                                             struct kvm_debugregs *dbgregs)
2547 {
2548         if (dbgregs->flags)
2549                 return -EINVAL;
2550
2551         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2552         vcpu->arch.dr6 = dbgregs->dr6;
2553         vcpu->arch.dr7 = dbgregs->dr7;
2554
2555         return 0;
2556 }
2557
2558 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2559                                          struct kvm_xsave *guest_xsave)
2560 {
2561         if (cpu_has_xsave)
2562                 memcpy(guest_xsave->region,
2563                         &vcpu->arch.guest_fpu.state->xsave,
2564                         xstate_size);
2565         else {
2566                 memcpy(guest_xsave->region,
2567                         &vcpu->arch.guest_fpu.state->fxsave,
2568                         sizeof(struct i387_fxsave_struct));
2569                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2570                         XSTATE_FPSSE;
2571         }
2572 }
2573
2574 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2575                                         struct kvm_xsave *guest_xsave)
2576 {
2577         u64 xstate_bv =
2578                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2579
2580         if (cpu_has_xsave)
2581                 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2582                         guest_xsave->region, xstate_size);
2583         else {
2584                 if (xstate_bv & ~XSTATE_FPSSE)
2585                         return -EINVAL;
2586                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2587                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
2588         }
2589         return 0;
2590 }
2591
2592 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2593                                         struct kvm_xcrs *guest_xcrs)
2594 {
2595         if (!cpu_has_xsave) {
2596                 guest_xcrs->nr_xcrs = 0;
2597                 return;
2598         }
2599
2600         guest_xcrs->nr_xcrs = 1;
2601         guest_xcrs->flags = 0;
2602         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2603         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2604 }
2605
2606 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2607                                        struct kvm_xcrs *guest_xcrs)
2608 {
2609         int i, r = 0;
2610
2611         if (!cpu_has_xsave)
2612                 return -EINVAL;
2613
2614         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2615                 return -EINVAL;
2616
2617         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2618                 /* Only support XCR0 currently */
2619                 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2620                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2621                                 guest_xcrs->xcrs[0].value);
2622                         break;
2623                 }
2624         if (r)
2625                 r = -EINVAL;
2626         return r;
2627 }
2628
2629 /*
2630  * kvm_set_guest_paused() indicates to the guest kernel that it has been
2631  * stopped by the hypervisor.  This function will be called from the host only.
2632  * EINVAL is returned when the host attempts to set the flag for a guest that
2633  * does not support pv clocks.
2634  */
2635 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2636 {
2637         if (!vcpu->arch.time_page)
2638                 return -EINVAL;
2639         vcpu->arch.pvclock_set_guest_stopped_request = true;
2640         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2641         return 0;
2642 }
2643
2644 long kvm_arch_vcpu_ioctl(struct file *filp,
2645                          unsigned int ioctl, unsigned long arg)
2646 {
2647         struct kvm_vcpu *vcpu = filp->private_data;
2648         void __user *argp = (void __user *)arg;
2649         int r;
2650         union {
2651                 struct kvm_lapic_state *lapic;
2652                 struct kvm_xsave *xsave;
2653                 struct kvm_xcrs *xcrs;
2654                 void *buffer;
2655         } u;
2656
2657         u.buffer = NULL;
2658         switch (ioctl) {
2659         case KVM_GET_LAPIC: {
2660                 r = -EINVAL;
2661                 if (!vcpu->arch.apic)
2662                         goto out;
2663                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2664
2665                 r = -ENOMEM;
2666                 if (!u.lapic)
2667                         goto out;
2668                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2669                 if (r)
2670                         goto out;
2671                 r = -EFAULT;
2672                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2673                         goto out;
2674                 r = 0;
2675                 break;
2676         }
2677         case KVM_SET_LAPIC: {
2678                 r = -EINVAL;
2679                 if (!vcpu->arch.apic)
2680                         goto out;
2681                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2682                 if (IS_ERR(u.lapic)) {
2683                         r = PTR_ERR(u.lapic);
2684                         goto out;
2685                 }
2686
2687                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2688                 if (r)
2689                         goto out;
2690                 r = 0;
2691                 break;
2692         }
2693         case KVM_INTERRUPT: {
2694                 struct kvm_interrupt irq;
2695
2696                 r = -EFAULT;
2697                 if (copy_from_user(&irq, argp, sizeof irq))
2698                         goto out;
2699                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2700                 if (r)
2701                         goto out;
2702                 r = 0;
2703                 break;
2704         }
2705         case KVM_NMI: {
2706                 r = kvm_vcpu_ioctl_nmi(vcpu);
2707                 if (r)
2708                         goto out;
2709                 r = 0;
2710                 break;
2711         }
2712         case KVM_SET_CPUID: {
2713                 struct kvm_cpuid __user *cpuid_arg = argp;
2714                 struct kvm_cpuid cpuid;
2715
2716                 r = -EFAULT;
2717                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2718                         goto out;
2719                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2720                 if (r)
2721                         goto out;
2722                 break;
2723         }
2724         case KVM_SET_CPUID2: {
2725                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2726                 struct kvm_cpuid2 cpuid;
2727
2728                 r = -EFAULT;
2729                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2730                         goto out;
2731                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2732                                               cpuid_arg->entries);
2733                 if (r)
2734                         goto out;
2735                 break;
2736         }
2737         case KVM_GET_CPUID2: {
2738                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2739                 struct kvm_cpuid2 cpuid;
2740
2741                 r = -EFAULT;
2742                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2743                         goto out;
2744                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2745                                               cpuid_arg->entries);
2746                 if (r)
2747                         goto out;
2748                 r = -EFAULT;
2749                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2750                         goto out;
2751                 r = 0;
2752                 break;
2753         }
2754         case KVM_GET_MSRS:
2755                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2756                 break;
2757         case KVM_SET_MSRS:
2758                 r = msr_io(vcpu, argp, do_set_msr, 0);
2759                 break;
2760         case KVM_TPR_ACCESS_REPORTING: {
2761                 struct kvm_tpr_access_ctl tac;
2762
2763                 r = -EFAULT;
2764                 if (copy_from_user(&tac, argp, sizeof tac))
2765                         goto out;
2766                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2767                 if (r)
2768                         goto out;
2769                 r = -EFAULT;
2770                 if (copy_to_user(argp, &tac, sizeof tac))
2771                         goto out;
2772                 r = 0;
2773                 break;
2774         };
2775         case KVM_SET_VAPIC_ADDR: {
2776                 struct kvm_vapic_addr va;
2777
2778                 r = -EINVAL;
2779                 if (!irqchip_in_kernel(vcpu->kvm))
2780                         goto out;
2781                 r = -EFAULT;
2782                 if (copy_from_user(&va, argp, sizeof va))
2783                         goto out;
2784                 r = 0;
2785                 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2786                 break;
2787         }
2788         case KVM_X86_SETUP_MCE: {
2789                 u64 mcg_cap;
2790
2791                 r = -EFAULT;
2792                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2793                         goto out;
2794                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2795                 break;
2796         }
2797         case KVM_X86_SET_MCE: {
2798                 struct kvm_x86_mce mce;
2799
2800                 r = -EFAULT;
2801                 if (copy_from_user(&mce, argp, sizeof mce))
2802                         goto out;
2803                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2804                 break;
2805         }
2806         case KVM_GET_VCPU_EVENTS: {
2807                 struct kvm_vcpu_events events;
2808
2809                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2810
2811                 r = -EFAULT;
2812                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2813                         break;
2814                 r = 0;
2815                 break;
2816         }
2817         case KVM_SET_VCPU_EVENTS: {
2818                 struct kvm_vcpu_events events;
2819
2820                 r = -EFAULT;
2821                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2822                         break;
2823
2824                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2825                 break;
2826         }
2827         case KVM_GET_DEBUGREGS: {
2828                 struct kvm_debugregs dbgregs;
2829
2830                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2831
2832                 r = -EFAULT;
2833                 if (copy_to_user(argp, &dbgregs,
2834                                  sizeof(struct kvm_debugregs)))
2835                         break;
2836                 r = 0;
2837                 break;
2838         }
2839         case KVM_SET_DEBUGREGS: {
2840                 struct kvm_debugregs dbgregs;
2841
2842                 r = -EFAULT;
2843                 if (copy_from_user(&dbgregs, argp,
2844                                    sizeof(struct kvm_debugregs)))
2845                         break;
2846
2847                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2848                 break;
2849         }
2850         case KVM_GET_XSAVE: {
2851                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2852                 r = -ENOMEM;
2853                 if (!u.xsave)
2854                         break;
2855
2856                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2857
2858                 r = -EFAULT;
2859                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2860                         break;
2861                 r = 0;
2862                 break;
2863         }
2864         case KVM_SET_XSAVE: {
2865                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2866                 if (IS_ERR(u.xsave)) {
2867                         r = PTR_ERR(u.xsave);
2868                         goto out;
2869                 }
2870
2871                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2872                 break;
2873         }
2874         case KVM_GET_XCRS: {
2875                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2876                 r = -ENOMEM;
2877                 if (!u.xcrs)
2878                         break;
2879
2880                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2881
2882                 r = -EFAULT;
2883                 if (copy_to_user(argp, u.xcrs,
2884                                  sizeof(struct kvm_xcrs)))
2885                         break;
2886                 r = 0;
2887                 break;
2888         }
2889         case KVM_SET_XCRS: {
2890                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2891                 if (IS_ERR(u.xcrs)) {
2892                         r = PTR_ERR(u.xcrs);
2893                         goto out;
2894                 }
2895
2896                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2897                 break;
2898         }
2899         case KVM_SET_TSC_KHZ: {
2900                 u32 user_tsc_khz;
2901
2902                 r = -EINVAL;
2903                 user_tsc_khz = (u32)arg;
2904
2905                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2906                         goto out;
2907
2908                 if (user_tsc_khz == 0)
2909                         user_tsc_khz = tsc_khz;
2910
2911                 kvm_set_tsc_khz(vcpu, user_tsc_khz);
2912
2913                 r = 0;
2914                 goto out;
2915         }
2916         case KVM_GET_TSC_KHZ: {
2917                 r = vcpu->arch.virtual_tsc_khz;
2918                 goto out;
2919         }
2920         case KVM_KVMCLOCK_CTRL: {
2921                 r = kvm_set_guest_paused(vcpu);
2922                 goto out;
2923         }
2924         default:
2925                 r = -EINVAL;
2926         }
2927 out:
2928         kfree(u.buffer);
2929         return r;
2930 }
2931
2932 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2933 {
2934         return VM_FAULT_SIGBUS;
2935 }
2936
2937 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2938 {
2939         int ret;
2940
2941         if (addr > (unsigned int)(-3 * PAGE_SIZE))
2942                 return -1;
2943         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2944         return ret;
2945 }
2946
2947 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2948                                               u64 ident_addr)
2949 {
2950         kvm->arch.ept_identity_map_addr = ident_addr;
2951         return 0;
2952 }
2953
2954 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2955                                           u32 kvm_nr_mmu_pages)
2956 {
2957         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2958                 return -EINVAL;
2959
2960         mutex_lock(&kvm->slots_lock);
2961         spin_lock(&kvm->mmu_lock);
2962
2963         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2964         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2965
2966         spin_unlock(&kvm->mmu_lock);
2967         mutex_unlock(&kvm->slots_lock);
2968         return 0;
2969 }
2970
2971 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2972 {
2973         return kvm->arch.n_max_mmu_pages;
2974 }
2975
2976 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2977 {
2978         int r;
2979
2980         r = 0;
2981         switch (chip->chip_id) {
2982         case KVM_IRQCHIP_PIC_MASTER:
2983                 memcpy(&chip->chip.pic,
2984                         &pic_irqchip(kvm)->pics[0],
2985                         sizeof(struct kvm_pic_state));
2986                 break;
2987         case KVM_IRQCHIP_PIC_SLAVE:
2988                 memcpy(&chip->chip.pic,
2989                         &pic_irqchip(kvm)->pics[1],
2990                         sizeof(struct kvm_pic_state));
2991                 break;
2992         case KVM_IRQCHIP_IOAPIC:
2993                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
2994                 break;
2995         default:
2996                 r = -EINVAL;
2997                 break;
2998         }
2999         return r;
3000 }
3001
3002 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3003 {
3004         int r;
3005
3006         r = 0;
3007         switch (chip->chip_id) {
3008         case KVM_IRQCHIP_PIC_MASTER:
3009                 spin_lock(&pic_irqchip(kvm)->lock);
3010                 memcpy(&pic_irqchip(kvm)->pics[0],
3011                         &chip->chip.pic,
3012                         sizeof(struct kvm_pic_state));
3013                 spin_unlock(&pic_irqchip(kvm)->lock);
3014                 break;
3015         case KVM_IRQCHIP_PIC_SLAVE:
3016                 spin_lock(&pic_irqchip(kvm)->lock);
3017                 memcpy(&pic_irqchip(kvm)->pics[1],
3018                         &chip->chip.pic,
3019                         sizeof(struct kvm_pic_state));
3020                 spin_unlock(&pic_irqchip(kvm)->lock);
3021                 break;
3022         case KVM_IRQCHIP_IOAPIC:
3023                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3024                 break;
3025         default:
3026                 r = -EINVAL;
3027                 break;
3028         }
3029         kvm_pic_update_irq(pic_irqchip(kvm));
3030         return r;
3031 }
3032
3033 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3034 {
3035         int r = 0;
3036
3037         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3038         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3039         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3040         return r;
3041 }
3042
3043 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3044 {
3045         int r = 0;
3046
3047         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3048         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3049         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3050         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3051         return r;
3052 }
3053
3054 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3055 {
3056         int r = 0;
3057
3058         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3059         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3060                 sizeof(ps->channels));
3061         ps->flags = kvm->arch.vpit->pit_state.flags;
3062         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3063         memset(&ps->reserved, 0, sizeof(ps->reserved));
3064         return r;
3065 }
3066
3067 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3068 {
3069         int r = 0, start = 0;
3070         u32 prev_legacy, cur_legacy;
3071         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3072         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3073         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3074         if (!prev_legacy && cur_legacy)
3075                 start = 1;
3076         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3077                sizeof(kvm->arch.vpit->pit_state.channels));
3078         kvm->arch.vpit->pit_state.flags = ps->flags;
3079         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3080         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3081         return r;
3082 }
3083
3084 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3085                                  struct kvm_reinject_control *control)
3086 {
3087         if (!kvm->arch.vpit)
3088                 return -ENXIO;
3089         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3090         kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3091         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3092         return 0;
3093 }
3094
3095 /**
3096  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3097  * @kvm: kvm instance
3098  * @log: slot id and address to which we copy the log
3099  *
3100  * We need to keep it in mind that VCPU threads can write to the bitmap
3101  * concurrently.  So, to avoid losing data, we keep the following order for
3102  * each bit:
3103  *
3104  *   1. Take a snapshot of the bit and clear it if needed.
3105  *   2. Write protect the corresponding page.
3106  *   3. Flush TLB's if needed.
3107  *   4. Copy the snapshot to the userspace.
3108  *
3109  * Between 2 and 3, the guest may write to the page using the remaining TLB
3110  * entry.  This is not a problem because the page will be reported dirty at
3111  * step 4 using the snapshot taken before and step 3 ensures that successive
3112  * writes will be logged for the next call.
3113  */
3114 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3115 {
3116         int r;
3117         struct kvm_memory_slot *memslot;
3118         unsigned long n, i;
3119         unsigned long *dirty_bitmap;
3120         unsigned long *dirty_bitmap_buffer;
3121         bool is_dirty = false;
3122
3123         mutex_lock(&kvm->slots_lock);
3124
3125         r = -EINVAL;
3126         if (log->slot >= KVM_MEMORY_SLOTS)
3127                 goto out;
3128
3129         memslot = id_to_memslot(kvm->memslots, log->slot);
3130
3131         dirty_bitmap = memslot->dirty_bitmap;
3132         r = -ENOENT;
3133         if (!dirty_bitmap)
3134                 goto out;
3135
3136         n = kvm_dirty_bitmap_bytes(memslot);
3137
3138         dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3139         memset(dirty_bitmap_buffer, 0, n);
3140
3141         spin_lock(&kvm->mmu_lock);
3142
3143         for (i = 0; i < n / sizeof(long); i++) {
3144                 unsigned long mask;
3145                 gfn_t offset;
3146
3147                 if (!dirty_bitmap[i])
3148                         continue;
3149
3150                 is_dirty = true;
3151
3152                 mask = xchg(&dirty_bitmap[i], 0);
3153                 dirty_bitmap_buffer[i] = mask;
3154
3155                 offset = i * BITS_PER_LONG;
3156                 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3157         }
3158         if (is_dirty)
3159                 kvm_flush_remote_tlbs(kvm);
3160
3161         spin_unlock(&kvm->mmu_lock);
3162
3163         r = -EFAULT;
3164         if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3165                 goto out;
3166
3167         r = 0;
3168 out:
3169         mutex_unlock(&kvm->slots_lock);
3170         return r;
3171 }
3172
3173 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3174 {
3175         if (!irqchip_in_kernel(kvm))
3176                 return -ENXIO;
3177
3178         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3179                                         irq_event->irq, irq_event->level);
3180         return 0;
3181 }
3182
3183 long kvm_arch_vm_ioctl(struct file *filp,
3184                        unsigned int ioctl, unsigned long arg)
3185 {
3186         struct kvm *kvm = filp->private_data;
3187         void __user *argp = (void __user *)arg;
3188         int r = -ENOTTY;
3189         /*
3190          * This union makes it completely explicit to gcc-3.x
3191          * that these two variables' stack usage should be
3192          * combined, not added together.
3193          */
3194         union {
3195                 struct kvm_pit_state ps;
3196                 struct kvm_pit_state2 ps2;
3197                 struct kvm_pit_config pit_config;
3198         } u;
3199
3200         switch (ioctl) {
3201         case KVM_SET_TSS_ADDR:
3202                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3203                 if (r < 0)
3204                         goto out;
3205                 break;
3206         case KVM_SET_IDENTITY_MAP_ADDR: {
3207                 u64 ident_addr;
3208
3209                 r = -EFAULT;
3210                 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3211                         goto out;
3212                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3213                 if (r < 0)
3214                         goto out;
3215                 break;
3216         }
3217         case KVM_SET_NR_MMU_PAGES:
3218                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3219                 if (r)
3220                         goto out;
3221                 break;
3222         case KVM_GET_NR_MMU_PAGES:
3223                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3224                 break;
3225         case KVM_CREATE_IRQCHIP: {
3226                 struct kvm_pic *vpic;
3227
3228                 mutex_lock(&kvm->lock);
3229                 r = -EEXIST;
3230                 if (kvm->arch.vpic)
3231                         goto create_irqchip_unlock;
3232                 r = -EINVAL;
3233                 if (atomic_read(&kvm->online_vcpus))
3234                         goto create_irqchip_unlock;
3235                 r = -ENOMEM;
3236                 vpic = kvm_create_pic(kvm);
3237                 if (vpic) {
3238                         r = kvm_ioapic_init(kvm);
3239                         if (r) {
3240                                 mutex_lock(&kvm->slots_lock);
3241                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3242                                                           &vpic->dev_master);
3243                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3244                                                           &vpic->dev_slave);
3245                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3246                                                           &vpic->dev_eclr);
3247                                 mutex_unlock(&kvm->slots_lock);
3248                                 kfree(vpic);
3249                                 goto create_irqchip_unlock;
3250                         }
3251                 } else
3252                         goto create_irqchip_unlock;
3253                 smp_wmb();
3254                 kvm->arch.vpic = vpic;
3255                 smp_wmb();
3256                 r = kvm_setup_default_irq_routing(kvm);
3257                 if (r) {
3258                         mutex_lock(&kvm->slots_lock);
3259                         mutex_lock(&kvm->irq_lock);
3260                         kvm_ioapic_destroy(kvm);
3261                         kvm_destroy_pic(kvm);
3262                         mutex_unlock(&kvm->irq_lock);
3263                         mutex_unlock(&kvm->slots_lock);
3264                 }
3265         create_irqchip_unlock:
3266                 mutex_unlock(&kvm->lock);
3267                 break;
3268         }
3269         case KVM_CREATE_PIT:
3270                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3271                 goto create_pit;
3272         case KVM_CREATE_PIT2:
3273                 r = -EFAULT;
3274                 if (copy_from_user(&u.pit_config, argp,
3275                                    sizeof(struct kvm_pit_config)))
3276                         goto out;
3277         create_pit:
3278                 mutex_lock(&kvm->slots_lock);
3279                 r = -EEXIST;
3280                 if (kvm->arch.vpit)
3281                         goto create_pit_unlock;
3282                 r = -ENOMEM;
3283                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3284                 if (kvm->arch.vpit)
3285                         r = 0;
3286         create_pit_unlock:
3287                 mutex_unlock(&kvm->slots_lock);
3288                 break;
3289         case KVM_GET_IRQCHIP: {
3290                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3291                 struct kvm_irqchip *chip;
3292
3293                 chip = memdup_user(argp, sizeof(*chip));
3294                 if (IS_ERR(chip)) {
3295                         r = PTR_ERR(chip);
3296                         goto out;
3297                 }
3298
3299                 r = -ENXIO;
3300                 if (!irqchip_in_kernel(kvm))
3301                         goto get_irqchip_out;
3302                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3303                 if (r)
3304                         goto get_irqchip_out;
3305                 r = -EFAULT;
3306                 if (copy_to_user(argp, chip, sizeof *chip))
3307                         goto get_irqchip_out;
3308                 r = 0;
3309         get_irqchip_out:
3310                 kfree(chip);
3311                 if (r)
3312                         goto out;
3313                 break;
3314         }
3315         case KVM_SET_IRQCHIP: {
3316                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3317                 struct kvm_irqchip *chip;
3318
3319                 chip = memdup_user(argp, sizeof(*chip));
3320                 if (IS_ERR(chip)) {
3321                         r = PTR_ERR(chip);
3322                         goto out;
3323                 }
3324
3325                 r = -ENXIO;
3326                 if (!irqchip_in_kernel(kvm))
3327                         goto set_irqchip_out;
3328                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3329                 if (r)
3330                         goto set_irqchip_out;
3331                 r = 0;
3332         set_irqchip_out:
3333                 kfree(chip);
3334                 if (r)
3335                         goto out;
3336                 break;
3337         }
3338         case KVM_GET_PIT: {
3339                 r = -EFAULT;
3340                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3341                         goto out;
3342                 r = -ENXIO;
3343                 if (!kvm->arch.vpit)
3344                         goto out;
3345                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3346                 if (r)
3347                         goto out;
3348                 r = -EFAULT;
3349                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3350                         goto out;
3351                 r = 0;
3352                 break;
3353         }
3354         case KVM_SET_PIT: {
3355                 r = -EFAULT;
3356                 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3357                         goto out;
3358                 r = -ENXIO;
3359                 if (!kvm->arch.vpit)
3360                         goto out;
3361                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3362                 if (r)
3363                         goto out;
3364                 r = 0;
3365                 break;
3366         }
3367         case KVM_GET_PIT2: {
3368                 r = -ENXIO;
3369                 if (!kvm->arch.vpit)
3370                         goto out;
3371                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3372                 if (r)
3373                         goto out;
3374                 r = -EFAULT;
3375                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3376                         goto out;
3377                 r = 0;
3378                 break;
3379         }
3380         case KVM_SET_PIT2: {
3381                 r = -EFAULT;
3382                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3383                         goto out;
3384                 r = -ENXIO;
3385                 if (!kvm->arch.vpit)
3386                         goto out;
3387                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3388                 if (r)
3389                         goto out;
3390                 r = 0;
3391                 break;
3392         }
3393         case KVM_REINJECT_CONTROL: {
3394                 struct kvm_reinject_control control;
3395                 r =  -EFAULT;
3396                 if (copy_from_user(&control, argp, sizeof(control)))
3397                         goto out;
3398                 r = kvm_vm_ioctl_reinject(kvm, &control);
3399                 if (r)
3400                         goto out;
3401                 r = 0;
3402                 break;
3403         }
3404         case KVM_XEN_HVM_CONFIG: {
3405                 r = -EFAULT;
3406                 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3407                                    sizeof(struct kvm_xen_hvm_config)))
3408                         goto out;
3409                 r = -EINVAL;
3410                 if (kvm->arch.xen_hvm_config.flags)
3411                         goto out;
3412                 r = 0;
3413                 break;
3414         }
3415         case KVM_SET_CLOCK: {
3416                 struct kvm_clock_data user_ns;
3417                 u64 now_ns;
3418                 s64 delta;
3419
3420                 r = -EFAULT;
3421                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3422                         goto out;
3423
3424                 r = -EINVAL;
3425                 if (user_ns.flags)
3426                         goto out;
3427
3428                 r = 0;
3429                 local_irq_disable();
3430                 now_ns = get_kernel_ns();
3431                 delta = user_ns.clock - now_ns;
3432                 local_irq_enable();
3433                 kvm->arch.kvmclock_offset = delta;
3434                 break;
3435         }
3436         case KVM_GET_CLOCK: {
3437                 struct kvm_clock_data user_ns;
3438                 u64 now_ns;
3439
3440                 local_irq_disable();
3441                 now_ns = get_kernel_ns();
3442                 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3443                 local_irq_enable();
3444                 user_ns.flags = 0;
3445                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3446
3447                 r = -EFAULT;
3448                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3449                         goto out;
3450                 r = 0;
3451                 break;
3452         }
3453
3454         default:
3455                 ;
3456         }
3457 out:
3458         return r;
3459 }
3460
3461 static void kvm_init_msr_list(void)
3462 {
3463         u32 dummy[2];
3464         unsigned i, j;
3465
3466         /* skip the first msrs in the list. KVM-specific */
3467         for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3468                 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3469                         continue;
3470                 if (j < i)
3471                         msrs_to_save[j] = msrs_to_save[i];
3472                 j++;
3473         }
3474         num_msrs_to_save = j;
3475 }
3476
3477 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3478                            const void *v)
3479 {
3480         int handled = 0;
3481         int n;
3482
3483         do {
3484                 n = min(len, 8);
3485                 if (!(vcpu->arch.apic &&
3486                       !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3487                     && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3488                         break;
3489                 handled += n;
3490                 addr += n;
3491                 len -= n;
3492                 v += n;
3493         } while (len);
3494
3495         return handled;
3496 }
3497
3498 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3499 {
3500         int handled = 0;
3501         int n;
3502
3503         do {
3504                 n = min(len, 8);
3505                 if (!(vcpu->arch.apic &&
3506                       !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3507                     && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3508                         break;
3509                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3510                 handled += n;
3511                 addr += n;
3512                 len -= n;
3513                 v += n;
3514         } while (len);
3515
3516         return handled;
3517 }
3518
3519 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3520                         struct kvm_segment *var, int seg)
3521 {
3522         kvm_x86_ops->set_segment(vcpu, var, seg);
3523 }
3524
3525 void kvm_get_segment(struct kvm_vcpu *vcpu,
3526                      struct kvm_segment *var, int seg)
3527 {
3528         kvm_x86_ops->get_segment(vcpu, var, seg);
3529 }
3530
3531 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3532 {
3533         gpa_t t_gpa;
3534         struct x86_exception exception;
3535
3536         BUG_ON(!mmu_is_nested(vcpu));
3537
3538         /* NPT walks are always user-walks */
3539         access |= PFERR_USER_MASK;
3540         t_gpa  = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3541
3542         return t_gpa;
3543 }
3544
3545 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3546                               struct x86_exception *exception)
3547 {
3548         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3549         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3550 }
3551
3552  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3553                                 struct x86_exception *exception)
3554 {
3555         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3556         access |= PFERR_FETCH_MASK;
3557         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3558 }
3559
3560 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3561                                struct x86_exception *exception)
3562 {
3563         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3564         access |= PFERR_WRITE_MASK;
3565         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3566 }
3567
3568 /* uses this to access any guest's mapped memory without checking CPL */
3569 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3570                                 struct x86_exception *exception)
3571 {
3572         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3573 }
3574
3575 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3576                                       struct kvm_vcpu *vcpu, u32 access,
3577                                       struct x86_exception *exception)
3578 {
3579         void *data = val;
3580         int r = X86EMUL_CONTINUE;
3581
3582         while (bytes) {
3583                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3584                                                             exception);
3585                 unsigned offset = addr & (PAGE_SIZE-1);
3586                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3587                 int ret;
3588
3589                 if (gpa == UNMAPPED_GVA)
3590                         return X86EMUL_PROPAGATE_FAULT;
3591                 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3592                 if (ret < 0) {
3593                         r = X86EMUL_IO_NEEDED;
3594                         goto out;
3595                 }
3596
3597                 bytes -= toread;
3598                 data += toread;
3599                 addr += toread;
3600         }
3601 out:
3602         return r;
3603 }
3604
3605 /* used for instruction fetching */
3606 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3607                                 gva_t addr, void *val, unsigned int bytes,
3608                                 struct x86_exception *exception)
3609 {
3610         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3611         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3612
3613         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3614                                           access | PFERR_FETCH_MASK,
3615                                           exception);
3616 }
3617
3618 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3619                                gva_t addr, void *val, unsigned int bytes,
3620                                struct x86_exception *exception)
3621 {
3622         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3623         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3624
3625         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3626                                           exception);
3627 }
3628 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3629
3630 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3631                                       gva_t addr, void *val, unsigned int bytes,
3632                                       struct x86_exception *exception)
3633 {
3634         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3635         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3636 }
3637
3638 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3639                                        gva_t addr, void *val,
3640                                        unsigned int bytes,
3641                                        struct x86_exception *exception)
3642 {
3643         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3644         void *data = val;
3645         int r = X86EMUL_CONTINUE;
3646
3647         while (bytes) {
3648                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3649                                                              PFERR_WRITE_MASK,
3650                                                              exception);
3651                 unsigned offset = addr & (PAGE_SIZE-1);
3652                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3653                 int ret;
3654
3655                 if (gpa == UNMAPPED_GVA)
3656                         return X86EMUL_PROPAGATE_FAULT;
3657                 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3658                 if (ret < 0) {
3659                         r = X86EMUL_IO_NEEDED;
3660                         goto out;
3661                 }
3662
3663                 bytes -= towrite;
3664                 data += towrite;
3665                 addr += towrite;
3666         }
3667 out:
3668         return r;
3669 }
3670 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3671
3672 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3673                                 gpa_t *gpa, struct x86_exception *exception,
3674                                 bool write)
3675 {
3676         u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3677                 | (write ? PFERR_WRITE_MASK : 0);
3678
3679         if (vcpu_match_mmio_gva(vcpu, gva)
3680             && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
3681                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3682                                         (gva & (PAGE_SIZE - 1));
3683                 trace_vcpu_match_mmio(gva, *gpa, write, false);
3684                 return 1;
3685         }
3686
3687         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3688
3689         if (*gpa == UNMAPPED_GVA)
3690                 return -1;
3691
3692         /* For APIC access vmexit */
3693         if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3694                 return 1;
3695
3696         if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3697                 trace_vcpu_match_mmio(gva, *gpa, write, true);
3698                 return 1;
3699         }
3700
3701         return 0;
3702 }
3703
3704 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3705                         const void *val, int bytes)
3706 {
3707         int ret;
3708
3709         ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3710         if (ret < 0)
3711                 return 0;
3712         kvm_mmu_pte_write(vcpu, gpa, val, bytes);
3713         return 1;
3714 }
3715
3716 struct read_write_emulator_ops {
3717         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3718                                   int bytes);
3719         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3720                                   void *val, int bytes);
3721         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3722                                int bytes, void *val);
3723         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3724                                     void *val, int bytes);
3725         bool write;
3726 };
3727
3728 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3729 {
3730         if (vcpu->mmio_read_completed) {
3731                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3732                                vcpu->mmio_fragments[0].gpa, *(u64 *)val);
3733                 vcpu->mmio_read_completed = 0;
3734                 return 1;
3735         }
3736
3737         return 0;
3738 }
3739
3740 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3741                         void *val, int bytes)
3742 {
3743         return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3744 }
3745
3746 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3747                          void *val, int bytes)
3748 {
3749         return emulator_write_phys(vcpu, gpa, val, bytes);
3750 }
3751
3752 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3753 {
3754         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3755         return vcpu_mmio_write(vcpu, gpa, bytes, val);
3756 }
3757
3758 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3759                           void *val, int bytes)
3760 {
3761         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3762         return X86EMUL_IO_NEEDED;
3763 }
3764
3765 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3766                            void *val, int bytes)
3767 {
3768         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3769
3770         memcpy(vcpu->run->mmio.data, frag->data, frag->len);
3771         return X86EMUL_CONTINUE;
3772 }
3773
3774 static const struct read_write_emulator_ops read_emultor = {
3775         .read_write_prepare = read_prepare,
3776         .read_write_emulate = read_emulate,
3777         .read_write_mmio = vcpu_mmio_read,
3778         .read_write_exit_mmio = read_exit_mmio,
3779 };
3780
3781 static const struct read_write_emulator_ops write_emultor = {
3782         .read_write_emulate = write_emulate,
3783         .read_write_mmio = write_mmio,
3784         .read_write_exit_mmio = write_exit_mmio,
3785         .write = true,
3786 };
3787
3788 static int emulator_read_write_onepage(unsigned long addr, void *val,
3789                                        unsigned int bytes,
3790                                        struct x86_exception *exception,
3791                                        struct kvm_vcpu *vcpu,
3792                                        const struct read_write_emulator_ops *ops)
3793 {
3794         gpa_t gpa;
3795         int handled, ret;
3796         bool write = ops->write;
3797         struct kvm_mmio_fragment *frag;
3798
3799         ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
3800
3801         if (ret < 0)
3802                 return X86EMUL_PROPAGATE_FAULT;
3803
3804         /* For APIC access vmexit */
3805         if (ret)
3806                 goto mmio;
3807
3808         if (ops->read_write_emulate(vcpu, gpa, val, bytes))
3809                 return X86EMUL_CONTINUE;
3810
3811 mmio:
3812         /*
3813          * Is this MMIO handled locally?
3814          */
3815         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
3816         if (handled == bytes)
3817                 return X86EMUL_CONTINUE;
3818
3819         gpa += handled;
3820         bytes -= handled;
3821         val += handled;
3822
3823         while (bytes) {
3824                 unsigned now = min(bytes, 8U);
3825
3826                 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3827                 frag->gpa = gpa;
3828                 frag->data = val;
3829                 frag->len = now;
3830
3831                 gpa += now;
3832                 val += now;
3833                 bytes -= now;
3834         }
3835         return X86EMUL_CONTINUE;
3836 }
3837
3838 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3839                         void *val, unsigned int bytes,
3840                         struct x86_exception *exception,
3841                         const struct read_write_emulator_ops *ops)
3842 {
3843         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3844         gpa_t gpa;
3845         int rc;
3846
3847         if (ops->read_write_prepare &&
3848                   ops->read_write_prepare(vcpu, val, bytes))
3849                 return X86EMUL_CONTINUE;
3850
3851         vcpu->mmio_nr_fragments = 0;
3852
3853         /* Crossing a page boundary? */
3854         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3855                 int now;
3856
3857                 now = -addr & ~PAGE_MASK;
3858                 rc = emulator_read_write_onepage(addr, val, now, exception,
3859                                                  vcpu, ops);
3860
3861                 if (rc != X86EMUL_CONTINUE)
3862                         return rc;
3863                 addr += now;
3864                 val += now;
3865                 bytes -= now;
3866         }
3867
3868         rc = emulator_read_write_onepage(addr, val, bytes, exception,
3869                                          vcpu, ops);
3870         if (rc != X86EMUL_CONTINUE)
3871                 return rc;
3872
3873         if (!vcpu->mmio_nr_fragments)
3874                 return rc;
3875
3876         gpa = vcpu->mmio_fragments[0].gpa;
3877
3878         vcpu->mmio_needed = 1;
3879         vcpu->mmio_cur_fragment = 0;
3880
3881         vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3882         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3883         vcpu->run->exit_reason = KVM_EXIT_MMIO;
3884         vcpu->run->mmio.phys_addr = gpa;
3885
3886         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
3887 }
3888
3889 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3890                                   unsigned long addr,
3891                                   void *val,
3892                                   unsigned int bytes,
3893                                   struct x86_exception *exception)
3894 {
3895         return emulator_read_write(ctxt, addr, val, bytes,
3896                                    exception, &read_emultor);
3897 }
3898
3899 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3900                             unsigned long addr,
3901                             const void *val,
3902                             unsigned int bytes,
3903                             struct x86_exception *exception)
3904 {
3905         return emulator_read_write(ctxt, addr, (void *)val, bytes,
3906                                    exception, &write_emultor);
3907 }
3908
3909 #define CMPXCHG_TYPE(t, ptr, old, new) \
3910         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3911
3912 #ifdef CONFIG_X86_64
3913 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3914 #else
3915 #  define CMPXCHG64(ptr, old, new) \
3916         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3917 #endif
3918
3919 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3920                                      unsigned long addr,
3921                                      const void *old,
3922                                      const void *new,
3923                                      unsigned int bytes,
3924                                      struct x86_exception *exception)
3925 {
3926         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3927         gpa_t gpa;
3928         struct page *page;
3929         char *kaddr;
3930         bool exchanged;
3931
3932         /* guests cmpxchg8b have to be emulated atomically */
3933         if (bytes > 8 || (bytes & (bytes - 1)))
3934                 goto emul_write;
3935
3936         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3937
3938         if (gpa == UNMAPPED_GVA ||
3939             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3940                 goto emul_write;
3941
3942         if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3943                 goto emul_write;
3944
3945         page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3946         if (is_error_page(page))
3947                 goto emul_write;
3948
3949         kaddr = kmap_atomic(page);
3950         kaddr += offset_in_page(gpa);
3951         switch (bytes) {
3952         case 1:
3953                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3954                 break;
3955         case 2:
3956                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3957                 break;
3958         case 4:
3959                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3960                 break;
3961         case 8:
3962                 exchanged = CMPXCHG64(kaddr, old, new);
3963                 break;
3964         default:
3965                 BUG();
3966         }
3967         kunmap_atomic(kaddr);
3968         kvm_release_page_dirty(page);
3969
3970         if (!exchanged)
3971                 return X86EMUL_CMPXCHG_FAILED;
3972
3973         kvm_mmu_pte_write(vcpu, gpa, new, bytes);
3974
3975         return X86EMUL_CONTINUE;
3976
3977 emul_write:
3978         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3979
3980         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
3981 }
3982
3983 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3984 {
3985         /* TODO: String I/O for in kernel device */
3986         int r;
3987
3988         if (vcpu->arch.pio.in)
3989                 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3990                                     vcpu->arch.pio.size, pd);
3991         else
3992                 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3993                                      vcpu->arch.pio.port, vcpu->arch.pio.size,
3994                                      pd);
3995         return r;
3996 }
3997
3998 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3999                                unsigned short port, void *val,
4000                                unsigned int count, bool in)
4001 {
4002         trace_kvm_pio(!in, port, size, count);
4003
4004         vcpu->arch.pio.port = port;
4005         vcpu->arch.pio.in = in;
4006         vcpu->arch.pio.count  = count;
4007         vcpu->arch.pio.size = size;
4008
4009         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4010                 vcpu->arch.pio.count = 0;
4011                 return 1;
4012         }
4013
4014         vcpu->run->exit_reason = KVM_EXIT_IO;
4015         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4016         vcpu->run->io.size = size;
4017         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4018         vcpu->run->io.count = count;
4019         vcpu->run->io.port = port;
4020
4021         return 0;
4022 }
4023
4024 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4025                                     int size, unsigned short port, void *val,
4026                                     unsigned int count)
4027 {
4028         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4029         int ret;
4030
4031         if (vcpu->arch.pio.count)
4032                 goto data_avail;
4033
4034         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4035         if (ret) {
4036 data_avail:
4037                 memcpy(val, vcpu->arch.pio_data, size * count);
4038                 vcpu->arch.pio.count = 0;
4039                 return 1;
4040         }
4041
4042         return 0;
4043 }
4044
4045 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4046                                      int size, unsigned short port,
4047                                      const void *val, unsigned int count)
4048 {
4049         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4050
4051         memcpy(vcpu->arch.pio_data, val, size * count);
4052         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4053 }
4054
4055 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4056 {
4057         return kvm_x86_ops->get_segment_base(vcpu, seg);
4058 }
4059
4060 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4061 {
4062         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4063 }
4064
4065 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4066 {
4067         if (!need_emulate_wbinvd(vcpu))
4068                 return X86EMUL_CONTINUE;
4069
4070         if (kvm_x86_ops->has_wbinvd_exit()) {
4071                 int cpu = get_cpu();
4072
4073                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4074                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4075                                 wbinvd_ipi, NULL, 1);
4076                 put_cpu();
4077                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4078         } else
4079                 wbinvd();
4080         return X86EMUL_CONTINUE;
4081 }
4082 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4083
4084 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4085 {
4086         kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4087 }
4088
4089 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4090 {
4091         return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4092 }
4093
4094 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4095 {
4096
4097         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4098 }
4099
4100 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4101 {
4102         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4103 }
4104
4105 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4106 {
4107         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4108         unsigned long value;
4109
4110         switch (cr) {
4111         case 0:
4112                 value = kvm_read_cr0(vcpu);
4113                 break;
4114         case 2:
4115                 value = vcpu->arch.cr2;
4116                 break;
4117         case 3:
4118                 value = kvm_read_cr3(vcpu);
4119                 break;
4120         case 4:
4121                 value = kvm_read_cr4(vcpu);
4122                 break;
4123         case 8:
4124                 value = kvm_get_cr8(vcpu);
4125                 break;
4126         default:
4127                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4128                 return 0;
4129         }
4130
4131         return value;
4132 }
4133
4134 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4135 {
4136         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4137         int res = 0;
4138
4139         switch (cr) {
4140         case 0:
4141                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4142                 break;
4143         case 2:
4144                 vcpu->arch.cr2 = val;
4145                 break;
4146         case 3:
4147                 res = kvm_set_cr3(vcpu, val);
4148                 break;
4149         case 4:
4150                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4151                 break;
4152         case 8:
4153                 res = kvm_set_cr8(vcpu, val);
4154                 break;
4155         default:
4156                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4157                 res = -1;
4158         }
4159
4160         return res;
4161 }
4162
4163 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4164 {
4165         kvm_set_rflags(emul_to_vcpu(ctxt), val);
4166 }
4167
4168 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4169 {
4170         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4171 }
4172
4173 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4174 {
4175         kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4176 }
4177
4178 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4179 {
4180         kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4181 }
4182
4183 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4184 {
4185         kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4186 }
4187
4188 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4189 {
4190         kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4191 }
4192
4193 static unsigned long emulator_get_cached_segment_base(
4194         struct x86_emulate_ctxt *ctxt, int seg)
4195 {
4196         return get_segment_base(emul_to_vcpu(ctxt), seg);
4197 }
4198
4199 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4200                                  struct desc_struct *desc, u32 *base3,
4201                                  int seg)
4202 {
4203         struct kvm_segment var;
4204
4205         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4206         *selector = var.selector;
4207
4208         if (var.unusable)
4209                 return false;
4210
4211         if (var.g)
4212                 var.limit >>= 12;
4213         set_desc_limit(desc, var.limit);
4214         set_desc_base(desc, (unsigned long)var.base);
4215 #ifdef CONFIG_X86_64
4216         if (base3)
4217                 *base3 = var.base >> 32;
4218 #endif
4219         desc->type = var.type;
4220         desc->s = var.s;
4221         desc->dpl = var.dpl;
4222         desc->p = var.present;
4223         desc->avl = var.avl;
4224         desc->l = var.l;
4225         desc->d = var.db;
4226         desc->g = var.g;
4227
4228         return true;
4229 }
4230
4231 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4232                                  struct desc_struct *desc, u32 base3,
4233                                  int seg)
4234 {
4235         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4236         struct kvm_segment var;
4237
4238         var.selector = selector;
4239         var.base = get_desc_base(desc);
4240 #ifdef CONFIG_X86_64
4241         var.base |= ((u64)base3) << 32;
4242 #endif
4243         var.limit = get_desc_limit(desc);
4244         if (desc->g)
4245                 var.limit = (var.limit << 12) | 0xfff;
4246         var.type = desc->type;
4247         var.present = desc->p;
4248         var.dpl = desc->dpl;
4249         var.db = desc->d;
4250         var.s = desc->s;
4251         var.l = desc->l;
4252         var.g = desc->g;
4253         var.avl = desc->avl;
4254         var.present = desc->p;
4255         var.unusable = !var.present;
4256         var.padding = 0;
4257
4258         kvm_set_segment(vcpu, &var, seg);
4259         return;
4260 }
4261
4262 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4263                             u32 msr_index, u64 *pdata)
4264 {
4265         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4266 }
4267
4268 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4269                             u32 msr_index, u64 data)
4270 {
4271         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4272 }
4273
4274 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4275                              u32 pmc, u64 *pdata)
4276 {
4277         return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4278 }
4279
4280 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4281 {
4282         emul_to_vcpu(ctxt)->arch.halt_request = 1;
4283 }
4284
4285 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4286 {
4287         preempt_disable();
4288         kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4289         /*
4290          * CR0.TS may reference the host fpu state, not the guest fpu state,
4291          * so it may be clear at this point.
4292          */
4293         clts();
4294 }
4295
4296 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4297 {
4298         preempt_enable();
4299 }
4300
4301 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4302                               struct x86_instruction_info *info,
4303                               enum x86_intercept_stage stage)
4304 {
4305         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4306 }
4307
4308 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4309                                u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4310 {
4311         kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4312 }
4313
4314 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4315 {
4316         return kvm_register_read(emul_to_vcpu(ctxt), reg);
4317 }
4318
4319 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4320 {
4321         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4322 }
4323
4324 static const struct x86_emulate_ops emulate_ops = {
4325         .read_gpr            = emulator_read_gpr,
4326         .write_gpr           = emulator_write_gpr,
4327         .read_std            = kvm_read_guest_virt_system,
4328         .write_std           = kvm_write_guest_virt_system,
4329         .fetch               = kvm_fetch_guest_virt,
4330         .read_emulated       = emulator_read_emulated,
4331         .write_emulated      = emulator_write_emulated,
4332         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
4333         .invlpg              = emulator_invlpg,
4334         .pio_in_emulated     = emulator_pio_in_emulated,
4335         .pio_out_emulated    = emulator_pio_out_emulated,
4336         .get_segment         = emulator_get_segment,
4337         .set_segment         = emulator_set_segment,
4338         .get_cached_segment_base = emulator_get_cached_segment_base,
4339         .get_gdt             = emulator_get_gdt,
4340         .get_idt             = emulator_get_idt,
4341         .set_gdt             = emulator_set_gdt,
4342         .set_idt             = emulator_set_idt,
4343         .get_cr              = emulator_get_cr,
4344         .set_cr              = emulator_set_cr,
4345         .set_rflags          = emulator_set_rflags,
4346         .cpl                 = emulator_get_cpl,
4347         .get_dr              = emulator_get_dr,
4348         .set_dr              = emulator_set_dr,
4349         .set_msr             = emulator_set_msr,
4350         .get_msr             = emulator_get_msr,
4351         .read_pmc            = emulator_read_pmc,
4352         .halt                = emulator_halt,
4353         .wbinvd              = emulator_wbinvd,
4354         .fix_hypercall       = emulator_fix_hypercall,
4355         .get_fpu             = emulator_get_fpu,
4356         .put_fpu             = emulator_put_fpu,
4357         .intercept           = emulator_intercept,
4358         .get_cpuid           = emulator_get_cpuid,
4359 };
4360
4361 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4362 {
4363         u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4364         /*
4365          * an sti; sti; sequence only disable interrupts for the first
4366          * instruction. So, if the last instruction, be it emulated or
4367          * not, left the system with the INT_STI flag enabled, it
4368          * means that the last instruction is an sti. We should not
4369          * leave the flag on in this case. The same goes for mov ss
4370          */
4371         if (!(int_shadow & mask))
4372                 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4373 }
4374
4375 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4376 {
4377         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4378         if (ctxt->exception.vector == PF_VECTOR)
4379                 kvm_propagate_fault(vcpu, &ctxt->exception);
4380         else if (ctxt->exception.error_code_valid)
4381                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4382                                       ctxt->exception.error_code);
4383         else
4384                 kvm_queue_exception(vcpu, ctxt->exception.vector);
4385 }
4386
4387 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4388 {
4389         memset(&ctxt->twobyte, 0,
4390                (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
4391
4392         ctxt->fetch.start = 0;
4393         ctxt->fetch.end = 0;
4394         ctxt->io_read.pos = 0;
4395         ctxt->io_read.end = 0;
4396         ctxt->mem_read.pos = 0;
4397         ctxt->mem_read.end = 0;
4398 }
4399
4400 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4401 {
4402         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4403         int cs_db, cs_l;
4404
4405         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4406
4407         ctxt->eflags = kvm_get_rflags(vcpu);
4408         ctxt->eip = kvm_rip_read(vcpu);
4409         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
4410                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
4411                      cs_l                               ? X86EMUL_MODE_PROT64 :
4412                      cs_db                              ? X86EMUL_MODE_PROT32 :
4413                                                           X86EMUL_MODE_PROT16;
4414         ctxt->guest_mode = is_guest_mode(vcpu);
4415
4416         init_decode_cache(ctxt);
4417         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4418 }
4419
4420 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4421 {
4422         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4423         int ret;
4424
4425         init_emulate_ctxt(vcpu);
4426
4427         ctxt->op_bytes = 2;
4428         ctxt->ad_bytes = 2;
4429         ctxt->_eip = ctxt->eip + inc_eip;
4430         ret = emulate_int_real(ctxt, irq);
4431
4432         if (ret != X86EMUL_CONTINUE)
4433                 return EMULATE_FAIL;
4434
4435         ctxt->eip = ctxt->_eip;
4436         kvm_rip_write(vcpu, ctxt->eip);
4437         kvm_set_rflags(vcpu, ctxt->eflags);
4438
4439         if (irq == NMI_VECTOR)
4440                 vcpu->arch.nmi_pending = 0;
4441         else
4442                 vcpu->arch.interrupt.pending = false;
4443
4444         return EMULATE_DONE;
4445 }
4446 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4447
4448 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4449 {
4450         int r = EMULATE_DONE;
4451
4452         ++vcpu->stat.insn_emulation_fail;
4453         trace_kvm_emulate_insn_failed(vcpu);
4454         if (!is_guest_mode(vcpu)) {
4455                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4456                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4457                 vcpu->run->internal.ndata = 0;
4458                 r = EMULATE_FAIL;
4459         }
4460         kvm_queue_exception(vcpu, UD_VECTOR);
4461
4462         return r;
4463 }
4464
4465 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4466 {
4467         gpa_t gpa;
4468         pfn_t pfn;
4469
4470         if (tdp_enabled)
4471                 return false;
4472
4473         /*
4474          * if emulation was due to access to shadowed page table
4475          * and it failed try to unshadow page and re-enter the
4476          * guest to let CPU execute the instruction.
4477          */
4478         if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4479                 return true;
4480
4481         gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4482
4483         if (gpa == UNMAPPED_GVA)
4484                 return true; /* let cpu generate fault */
4485
4486         /*
4487          * Do not retry the unhandleable instruction if it faults on the
4488          * readonly host memory, otherwise it will goto a infinite loop:
4489          * retry instruction -> write #PF -> emulation fail -> retry
4490          * instruction -> ...
4491          */
4492         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4493         if (!is_error_pfn(pfn)) {
4494                 kvm_release_pfn_clean(pfn);
4495                 return true;
4496         }
4497
4498         return false;
4499 }
4500
4501 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4502                               unsigned long cr2,  int emulation_type)
4503 {
4504         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4505         unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4506
4507         last_retry_eip = vcpu->arch.last_retry_eip;
4508         last_retry_addr = vcpu->arch.last_retry_addr;
4509
4510         /*
4511          * If the emulation is caused by #PF and it is non-page_table
4512          * writing instruction, it means the VM-EXIT is caused by shadow
4513          * page protected, we can zap the shadow page and retry this
4514          * instruction directly.
4515          *
4516          * Note: if the guest uses a non-page-table modifying instruction
4517          * on the PDE that points to the instruction, then we will unmap
4518          * the instruction and go to an infinite loop. So, we cache the
4519          * last retried eip and the last fault address, if we meet the eip
4520          * and the address again, we can break out of the potential infinite
4521          * loop.
4522          */
4523         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4524
4525         if (!(emulation_type & EMULTYPE_RETRY))
4526                 return false;
4527
4528         if (x86_page_table_writing_insn(ctxt))
4529                 return false;
4530
4531         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4532                 return false;
4533
4534         vcpu->arch.last_retry_eip = ctxt->eip;
4535         vcpu->arch.last_retry_addr = cr2;
4536
4537         if (!vcpu->arch.mmu.direct_map)
4538                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4539
4540         kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4541
4542         return true;
4543 }
4544
4545 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4546 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4547
4548 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4549                             unsigned long cr2,
4550                             int emulation_type,
4551                             void *insn,
4552                             int insn_len)
4553 {
4554         int r;
4555         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4556         bool writeback = true;
4557
4558         kvm_clear_exception_queue(vcpu);
4559
4560         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4561                 init_emulate_ctxt(vcpu);
4562                 ctxt->interruptibility = 0;
4563                 ctxt->have_exception = false;
4564                 ctxt->perm_ok = false;
4565
4566                 ctxt->only_vendor_specific_insn
4567                         = emulation_type & EMULTYPE_TRAP_UD;
4568
4569                 r = x86_decode_insn(ctxt, insn, insn_len);
4570
4571                 trace_kvm_emulate_insn_start(vcpu);
4572                 ++vcpu->stat.insn_emulation;
4573                 if (r != EMULATION_OK)  {
4574                         if (emulation_type & EMULTYPE_TRAP_UD)
4575                                 return EMULATE_FAIL;
4576                         if (reexecute_instruction(vcpu, cr2))
4577                                 return EMULATE_DONE;
4578                         if (emulation_type & EMULTYPE_SKIP)
4579                                 return EMULATE_FAIL;
4580                         return handle_emulation_failure(vcpu);
4581                 }
4582         }
4583
4584         if (emulation_type & EMULTYPE_SKIP) {
4585                 kvm_rip_write(vcpu, ctxt->_eip);
4586                 return EMULATE_DONE;
4587         }
4588
4589         if (retry_instruction(ctxt, cr2, emulation_type))
4590                 return EMULATE_DONE;
4591
4592         /* this is needed for vmware backdoor interface to work since it
4593            changes registers values  during IO operation */
4594         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4595                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4596                 emulator_invalidate_register_cache(ctxt);
4597         }
4598
4599 restart:
4600         r = x86_emulate_insn(ctxt);
4601
4602         if (r == EMULATION_INTERCEPTED)
4603                 return EMULATE_DONE;
4604
4605         if (r == EMULATION_FAILED) {
4606                 if (reexecute_instruction(vcpu, cr2))
4607                         return EMULATE_DONE;
4608
4609                 return handle_emulation_failure(vcpu);
4610         }
4611
4612         if (ctxt->have_exception) {
4613                 inject_emulated_exception(vcpu);
4614                 r = EMULATE_DONE;
4615         } else if (vcpu->arch.pio.count) {
4616                 if (!vcpu->arch.pio.in)
4617                         vcpu->arch.pio.count = 0;
4618                 else {
4619                         writeback = false;
4620                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
4621                 }
4622                 r = EMULATE_DO_MMIO;
4623         } else if (vcpu->mmio_needed) {
4624                 if (!vcpu->mmio_is_write)
4625                         writeback = false;
4626                 r = EMULATE_DO_MMIO;
4627                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
4628         } else if (r == EMULATION_RESTART)
4629                 goto restart;
4630         else
4631                 r = EMULATE_DONE;
4632
4633         if (writeback) {
4634                 toggle_interruptibility(vcpu, ctxt->interruptibility);
4635                 kvm_set_rflags(vcpu, ctxt->eflags);
4636                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4637                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4638                 kvm_rip_write(vcpu, ctxt->eip);
4639         } else
4640                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4641
4642         return r;
4643 }
4644 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4645
4646 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4647 {
4648         unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4649         int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4650                                             size, port, &val, 1);
4651         /* do not return to emulator after return from userspace */
4652         vcpu->arch.pio.count = 0;
4653         return ret;
4654 }
4655 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4656
4657 static void tsc_bad(void *info)
4658 {
4659         __this_cpu_write(cpu_tsc_khz, 0);
4660 }
4661
4662 static void tsc_khz_changed(void *data)
4663 {
4664         struct cpufreq_freqs *freq = data;
4665         unsigned long khz = 0;
4666
4667         if (data)
4668                 khz = freq->new;
4669         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4670                 khz = cpufreq_quick_get(raw_smp_processor_id());
4671         if (!khz)
4672                 khz = tsc_khz;
4673         __this_cpu_write(cpu_tsc_khz, khz);
4674 }
4675
4676 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4677                                      void *data)
4678 {
4679         struct cpufreq_freqs *freq = data;
4680         struct kvm *kvm;
4681         struct kvm_vcpu *vcpu;
4682         int i, send_ipi = 0;
4683
4684         /*
4685          * We allow guests to temporarily run on slowing clocks,
4686          * provided we notify them after, or to run on accelerating
4687          * clocks, provided we notify them before.  Thus time never
4688          * goes backwards.
4689          *
4690          * However, we have a problem.  We can't atomically update
4691          * the frequency of a given CPU from this function; it is
4692          * merely a notifier, which can be called from any CPU.
4693          * Changing the TSC frequency at arbitrary points in time
4694          * requires a recomputation of local variables related to
4695          * the TSC for each VCPU.  We must flag these local variables
4696          * to be updated and be sure the update takes place with the
4697          * new frequency before any guests proceed.
4698          *
4699          * Unfortunately, the combination of hotplug CPU and frequency
4700          * change creates an intractable locking scenario; the order
4701          * of when these callouts happen is undefined with respect to
4702          * CPU hotplug, and they can race with each other.  As such,
4703          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4704          * undefined; you can actually have a CPU frequency change take
4705          * place in between the computation of X and the setting of the
4706          * variable.  To protect against this problem, all updates of
4707          * the per_cpu tsc_khz variable are done in an interrupt
4708          * protected IPI, and all callers wishing to update the value
4709          * must wait for a synchronous IPI to complete (which is trivial
4710          * if the caller is on the CPU already).  This establishes the
4711          * necessary total order on variable updates.
4712          *
4713          * Note that because a guest time update may take place
4714          * anytime after the setting of the VCPU's request bit, the
4715          * correct TSC value must be set before the request.  However,
4716          * to ensure the update actually makes it to any guest which
4717          * starts running in hardware virtualization between the set
4718          * and the acquisition of the spinlock, we must also ping the
4719          * CPU after setting the request bit.
4720          *
4721          */
4722
4723         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4724                 return 0;
4725         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4726                 return 0;
4727
4728         smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4729
4730         raw_spin_lock(&kvm_lock);
4731         list_for_each_entry(kvm, &vm_list, vm_list) {
4732                 kvm_for_each_vcpu(i, vcpu, kvm) {
4733                         if (vcpu->cpu != freq->cpu)
4734                                 continue;
4735                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4736                         if (vcpu->cpu != smp_processor_id())
4737                                 send_ipi = 1;
4738                 }
4739         }
4740         raw_spin_unlock(&kvm_lock);
4741
4742         if (freq->old < freq->new && send_ipi) {
4743                 /*
4744                  * We upscale the frequency.  Must make the guest
4745                  * doesn't see old kvmclock values while running with
4746                  * the new frequency, otherwise we risk the guest sees
4747                  * time go backwards.
4748                  *
4749                  * In case we update the frequency for another cpu
4750                  * (which might be in guest context) send an interrupt
4751                  * to kick the cpu out of guest context.  Next time
4752                  * guest context is entered kvmclock will be updated,
4753                  * so the guest will not see stale values.
4754                  */
4755                 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4756         }
4757         return 0;
4758 }
4759
4760 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4761         .notifier_call  = kvmclock_cpufreq_notifier
4762 };
4763
4764 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4765                                         unsigned long action, void *hcpu)
4766 {
4767         unsigned int cpu = (unsigned long)hcpu;
4768
4769         switch (action) {
4770                 case CPU_ONLINE:
4771                 case CPU_DOWN_FAILED:
4772                         smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4773                         break;
4774                 case CPU_DOWN_PREPARE:
4775                         smp_call_function_single(cpu, tsc_bad, NULL, 1);
4776                         break;
4777         }
4778         return NOTIFY_OK;
4779 }
4780
4781 static struct notifier_block kvmclock_cpu_notifier_block = {
4782         .notifier_call  = kvmclock_cpu_notifier,
4783         .priority = -INT_MAX
4784 };
4785
4786 static void kvm_timer_init(void)
4787 {
4788         int cpu;
4789
4790         max_tsc_khz = tsc_khz;
4791         register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4792         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4793 #ifdef CONFIG_CPU_FREQ
4794                 struct cpufreq_policy policy;
4795                 memset(&policy, 0, sizeof(policy));
4796                 cpu = get_cpu();
4797                 cpufreq_get_policy(&policy, cpu);
4798                 if (policy.cpuinfo.max_freq)
4799                         max_tsc_khz = policy.cpuinfo.max_freq;
4800                 put_cpu();
4801 #endif
4802                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4803                                           CPUFREQ_TRANSITION_NOTIFIER);
4804         }
4805         pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
4806         for_each_online_cpu(cpu)
4807                 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4808 }
4809
4810 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4811
4812 int kvm_is_in_guest(void)
4813 {
4814         return __this_cpu_read(current_vcpu) != NULL;
4815 }
4816
4817 static int kvm_is_user_mode(void)
4818 {
4819         int user_mode = 3;
4820
4821         if (__this_cpu_read(current_vcpu))
4822                 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
4823
4824         return user_mode != 0;
4825 }
4826
4827 static unsigned long kvm_get_guest_ip(void)
4828 {
4829         unsigned long ip = 0;
4830
4831         if (__this_cpu_read(current_vcpu))
4832                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
4833
4834         return ip;
4835 }
4836
4837 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4838         .is_in_guest            = kvm_is_in_guest,
4839         .is_user_mode           = kvm_is_user_mode,
4840         .get_guest_ip           = kvm_get_guest_ip,
4841 };
4842
4843 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4844 {
4845         __this_cpu_write(current_vcpu, vcpu);
4846 }
4847 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4848
4849 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4850 {
4851         __this_cpu_write(current_vcpu, NULL);
4852 }
4853 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4854
4855 static void kvm_set_mmio_spte_mask(void)
4856 {
4857         u64 mask;
4858         int maxphyaddr = boot_cpu_data.x86_phys_bits;
4859
4860         /*
4861          * Set the reserved bits and the present bit of an paging-structure
4862          * entry to generate page fault with PFER.RSV = 1.
4863          */
4864         mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4865         mask |= 1ull;
4866
4867 #ifdef CONFIG_X86_64
4868         /*
4869          * If reserved bit is not supported, clear the present bit to disable
4870          * mmio page fault.
4871          */
4872         if (maxphyaddr == 52)
4873                 mask &= ~1ull;
4874 #endif
4875
4876         kvm_mmu_set_mmio_spte_mask(mask);
4877 }
4878
4879 int kvm_arch_init(void *opaque)
4880 {
4881         int r;
4882         struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4883
4884         if (kvm_x86_ops) {
4885                 printk(KERN_ERR "kvm: already loaded the other module\n");
4886                 r = -EEXIST;
4887                 goto out;
4888         }
4889
4890         if (!ops->cpu_has_kvm_support()) {
4891                 printk(KERN_ERR "kvm: no hardware support\n");
4892                 r = -EOPNOTSUPP;
4893                 goto out;
4894         }
4895         if (ops->disabled_by_bios()) {
4896                 printk(KERN_ERR "kvm: disabled by bios\n");
4897                 r = -EOPNOTSUPP;
4898                 goto out;
4899         }
4900
4901         r = kvm_mmu_module_init();
4902         if (r)
4903                 goto out;
4904
4905         kvm_set_mmio_spte_mask();
4906         kvm_init_msr_list();
4907
4908         kvm_x86_ops = ops;
4909         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4910                         PT_DIRTY_MASK, PT64_NX_MASK, 0);
4911
4912         kvm_timer_init();
4913
4914         perf_register_guest_info_callbacks(&kvm_guest_cbs);
4915
4916         if (cpu_has_xsave)
4917                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4918
4919         kvm_lapic_init();
4920         return 0;
4921
4922 out:
4923         return r;
4924 }
4925
4926 void kvm_arch_exit(void)
4927 {
4928         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4929
4930         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4931                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4932                                             CPUFREQ_TRANSITION_NOTIFIER);
4933         unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4934         kvm_x86_ops = NULL;
4935         kvm_mmu_module_exit();
4936 }
4937
4938 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4939 {
4940         ++vcpu->stat.halt_exits;
4941         if (irqchip_in_kernel(vcpu->kvm)) {
4942                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4943                 return 1;
4944         } else {
4945                 vcpu->run->exit_reason = KVM_EXIT_HLT;
4946                 return 0;
4947         }
4948 }
4949 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4950
4951 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4952 {
4953         u64 param, ingpa, outgpa, ret;
4954         uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4955         bool fast, longmode;
4956         int cs_db, cs_l;
4957
4958         /*
4959          * hypercall generates UD from non zero cpl and real mode
4960          * per HYPER-V spec
4961          */
4962         if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4963                 kvm_queue_exception(vcpu, UD_VECTOR);
4964                 return 0;
4965         }
4966
4967         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4968         longmode = is_long_mode(vcpu) && cs_l == 1;
4969
4970         if (!longmode) {
4971                 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4972                         (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4973                 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4974                         (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4975                 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4976                         (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4977         }
4978 #ifdef CONFIG_X86_64
4979         else {
4980                 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4981                 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4982                 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4983         }
4984 #endif
4985
4986         code = param & 0xffff;
4987         fast = (param >> 16) & 0x1;
4988         rep_cnt = (param >> 32) & 0xfff;
4989         rep_idx = (param >> 48) & 0xfff;
4990
4991         trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4992
4993         switch (code) {
4994         case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4995                 kvm_vcpu_on_spin(vcpu);
4996                 break;
4997         default:
4998                 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4999                 break;
5000         }
5001
5002         ret = res | (((u64)rep_done & 0xfff) << 32);
5003         if (longmode) {
5004                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5005         } else {
5006                 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5007                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5008         }
5009
5010         return 1;
5011 }
5012
5013 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5014 {
5015         unsigned long nr, a0, a1, a2, a3, ret;
5016         int r = 1;
5017
5018         if (kvm_hv_hypercall_enabled(vcpu->kvm))
5019                 return kvm_hv_hypercall(vcpu);
5020
5021         nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5022         a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5023         a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5024         a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5025         a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5026
5027         trace_kvm_hypercall(nr, a0, a1, a2, a3);
5028
5029         if (!is_long_mode(vcpu)) {
5030                 nr &= 0xFFFFFFFF;
5031                 a0 &= 0xFFFFFFFF;
5032                 a1 &= 0xFFFFFFFF;
5033                 a2 &= 0xFFFFFFFF;
5034                 a3 &= 0xFFFFFFFF;
5035         }
5036
5037         if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5038                 ret = -KVM_EPERM;
5039                 goto out;
5040         }
5041
5042         switch (nr) {
5043         case KVM_HC_VAPIC_POLL_IRQ:
5044                 ret = 0;
5045                 break;
5046         default:
5047                 ret = -KVM_ENOSYS;
5048                 break;
5049         }
5050 out:
5051         kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5052         ++vcpu->stat.hypercalls;
5053         return r;
5054 }
5055 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5056
5057 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5058 {
5059         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5060         char instruction[3];
5061         unsigned long rip = kvm_rip_read(vcpu);
5062
5063         /*
5064          * Blow out the MMU to ensure that no other VCPU has an active mapping
5065          * to ensure that the updated hypercall appears atomically across all
5066          * VCPUs.
5067          */
5068         kvm_mmu_zap_all(vcpu->kvm);
5069
5070         kvm_x86_ops->patch_hypercall(vcpu, instruction);
5071
5072         return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5073 }
5074
5075 /*
5076  * Check if userspace requested an interrupt window, and that the
5077  * interrupt window is open.
5078  *
5079  * No need to exit to userspace if we already have an interrupt queued.
5080  */
5081 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5082 {
5083         return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5084                 vcpu->run->request_interrupt_window &&
5085                 kvm_arch_interrupt_allowed(vcpu));
5086 }
5087
5088 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5089 {
5090         struct kvm_run *kvm_run = vcpu->run;
5091
5092         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5093         kvm_run->cr8 = kvm_get_cr8(vcpu);
5094         kvm_run->apic_base = kvm_get_apic_base(vcpu);
5095         if (irqchip_in_kernel(vcpu->kvm))
5096                 kvm_run->ready_for_interrupt_injection = 1;
5097         else
5098                 kvm_run->ready_for_interrupt_injection =
5099                         kvm_arch_interrupt_allowed(vcpu) &&
5100                         !kvm_cpu_has_interrupt(vcpu) &&
5101                         !kvm_event_needs_reinjection(vcpu);
5102 }
5103
5104 static void vapic_enter(struct kvm_vcpu *vcpu)
5105 {
5106         struct kvm_lapic *apic = vcpu->arch.apic;
5107         struct page *page;
5108
5109         if (!apic || !apic->vapic_addr)
5110                 return;
5111
5112         page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5113
5114         vcpu->arch.apic->vapic_page = page;
5115 }
5116
5117 static void vapic_exit(struct kvm_vcpu *vcpu)
5118 {
5119         struct kvm_lapic *apic = vcpu->arch.apic;
5120         int idx;
5121
5122         if (!apic || !apic->vapic_addr)
5123                 return;
5124
5125         idx = srcu_read_lock(&vcpu->kvm->srcu);
5126         kvm_release_page_dirty(apic->vapic_page);
5127         mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5128         srcu_read_unlock(&vcpu->kvm->srcu, idx);
5129 }
5130
5131 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5132 {
5133         int max_irr, tpr;
5134
5135         if (!kvm_x86_ops->update_cr8_intercept)
5136                 return;
5137
5138         if (!vcpu->arch.apic)
5139                 return;
5140
5141         if (!vcpu->arch.apic->vapic_addr)
5142                 max_irr = kvm_lapic_find_highest_irr(vcpu);
5143         else
5144                 max_irr = -1;
5145
5146         if (max_irr != -1)
5147                 max_irr >>= 4;
5148
5149         tpr = kvm_lapic_get_cr8(vcpu);
5150
5151         kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5152 }
5153
5154 static void inject_pending_event(struct kvm_vcpu *vcpu)
5155 {
5156         /* try to reinject previous events if any */
5157         if (vcpu->arch.exception.pending) {
5158                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5159                                         vcpu->arch.exception.has_error_code,
5160                                         vcpu->arch.exception.error_code);
5161                 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5162                                           vcpu->arch.exception.has_error_code,
5163                                           vcpu->arch.exception.error_code,
5164                                           vcpu->arch.exception.reinject);
5165                 return;
5166         }
5167
5168         if (vcpu->arch.nmi_injected) {
5169                 kvm_x86_ops->set_nmi(vcpu);
5170                 return;
5171         }
5172
5173         if (vcpu->arch.interrupt.pending) {
5174                 kvm_x86_ops->set_irq(vcpu);
5175                 return;
5176         }
5177
5178         /* try to inject new event if pending */
5179         if (vcpu->arch.nmi_pending) {
5180                 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5181                         --vcpu->arch.nmi_pending;
5182                         vcpu->arch.nmi_injected = true;
5183                         kvm_x86_ops->set_nmi(vcpu);
5184                 }
5185         } else if (kvm_cpu_has_interrupt(vcpu)) {
5186                 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5187                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5188                                             false);
5189                         kvm_x86_ops->set_irq(vcpu);
5190                 }
5191         }
5192 }
5193
5194 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5195 {
5196         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5197                         !vcpu->guest_xcr0_loaded) {
5198                 /* kvm_set_xcr() also depends on this */
5199                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5200                 vcpu->guest_xcr0_loaded = 1;
5201         }
5202 }
5203
5204 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5205 {
5206         if (vcpu->guest_xcr0_loaded) {
5207                 if (vcpu->arch.xcr0 != host_xcr0)
5208                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5209                 vcpu->guest_xcr0_loaded = 0;
5210         }
5211 }
5212
5213 static void process_nmi(struct kvm_vcpu *vcpu)
5214 {
5215         unsigned limit = 2;
5216
5217         /*
5218          * x86 is limited to one NMI running, and one NMI pending after it.
5219          * If an NMI is already in progress, limit further NMIs to just one.
5220          * Otherwise, allow two (and we'll inject the first one immediately).
5221          */
5222         if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5223                 limit = 1;
5224
5225         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5226         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5227         kvm_make_request(KVM_REQ_EVENT, vcpu);
5228 }
5229
5230 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5231 {
5232         int r;
5233         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5234                 vcpu->run->request_interrupt_window;
5235         bool req_immediate_exit = 0;
5236
5237         if (vcpu->requests) {
5238                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5239                         kvm_mmu_unload(vcpu);
5240                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5241                         __kvm_migrate_timers(vcpu);
5242                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5243                         r = kvm_guest_time_update(vcpu);
5244                         if (unlikely(r))
5245                                 goto out;
5246                 }
5247                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5248                         kvm_mmu_sync_roots(vcpu);
5249                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5250                         kvm_x86_ops->tlb_flush(vcpu);
5251                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5252                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5253                         r = 0;
5254                         goto out;
5255                 }
5256                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5257                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5258                         r = 0;
5259                         goto out;
5260                 }
5261                 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5262                         vcpu->fpu_active = 0;
5263                         kvm_x86_ops->fpu_deactivate(vcpu);
5264                 }
5265                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5266                         /* Page is swapped out. Do synthetic halt */
5267                         vcpu->arch.apf.halted = true;
5268                         r = 1;
5269                         goto out;
5270                 }
5271                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5272                         record_steal_time(vcpu);
5273                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5274                         process_nmi(vcpu);
5275                 req_immediate_exit =
5276                         kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5277                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5278                         kvm_handle_pmu_event(vcpu);
5279                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5280                         kvm_deliver_pmi(vcpu);
5281         }
5282
5283         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5284                 inject_pending_event(vcpu);
5285
5286                 /* enable NMI/IRQ window open exits if needed */
5287                 if (vcpu->arch.nmi_pending)
5288                         kvm_x86_ops->enable_nmi_window(vcpu);
5289                 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5290                         kvm_x86_ops->enable_irq_window(vcpu);
5291
5292                 if (kvm_lapic_enabled(vcpu)) {
5293                         update_cr8_intercept(vcpu);
5294                         kvm_lapic_sync_to_vapic(vcpu);
5295                 }
5296         }
5297
5298         r = kvm_mmu_reload(vcpu);
5299         if (unlikely(r)) {
5300                 goto cancel_injection;
5301         }
5302
5303         preempt_disable();
5304
5305         kvm_x86_ops->prepare_guest_switch(vcpu);
5306         if (vcpu->fpu_active)
5307                 kvm_load_guest_fpu(vcpu);
5308         kvm_load_guest_xcr0(vcpu);
5309
5310         vcpu->mode = IN_GUEST_MODE;
5311
5312         /* We should set ->mode before check ->requests,
5313          * see the comment in make_all_cpus_request.
5314          */
5315         smp_mb();
5316
5317         local_irq_disable();
5318
5319         if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5320             || need_resched() || signal_pending(current)) {
5321                 vcpu->mode = OUTSIDE_GUEST_MODE;
5322                 smp_wmb();
5323                 local_irq_enable();
5324                 preempt_enable();
5325                 r = 1;
5326                 goto cancel_injection;
5327         }
5328
5329         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5330
5331         if (req_immediate_exit)
5332                 smp_send_reschedule(vcpu->cpu);
5333
5334         kvm_guest_enter();
5335
5336         if (unlikely(vcpu->arch.switch_db_regs)) {
5337                 set_debugreg(0, 7);
5338                 set_debugreg(vcpu->arch.eff_db[0], 0);
5339                 set_debugreg(vcpu->arch.eff_db[1], 1);
5340                 set_debugreg(vcpu->arch.eff_db[2], 2);
5341                 set_debugreg(vcpu->arch.eff_db[3], 3);
5342         }
5343
5344         trace_kvm_entry(vcpu->vcpu_id);
5345         kvm_x86_ops->run(vcpu);
5346
5347         /*
5348          * If the guest has used debug registers, at least dr7
5349          * will be disabled while returning to the host.
5350          * If we don't have active breakpoints in the host, we don't
5351          * care about the messed up debug address registers. But if
5352          * we have some of them active, restore the old state.
5353          */
5354         if (hw_breakpoint_active())
5355                 hw_breakpoint_restore();
5356
5357         vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
5358
5359         vcpu->mode = OUTSIDE_GUEST_MODE;
5360         smp_wmb();
5361         local_irq_enable();
5362
5363         ++vcpu->stat.exits;
5364
5365         /*
5366          * We must have an instruction between local_irq_enable() and
5367          * kvm_guest_exit(), so the timer interrupt isn't delayed by
5368          * the interrupt shadow.  The stat.exits increment will do nicely.
5369          * But we need to prevent reordering, hence this barrier():
5370          */
5371         barrier();
5372
5373         kvm_guest_exit();
5374
5375         preempt_enable();
5376
5377         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5378
5379         /*
5380          * Profile KVM exit RIPs:
5381          */
5382         if (unlikely(prof_on == KVM_PROFILING)) {
5383                 unsigned long rip = kvm_rip_read(vcpu);
5384                 profile_hit(KVM_PROFILING, (void *)rip);
5385         }
5386
5387         if (unlikely(vcpu->arch.tsc_always_catchup))
5388                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5389
5390         if (vcpu->arch.apic_attention)
5391                 kvm_lapic_sync_from_vapic(vcpu);
5392
5393         r = kvm_x86_ops->handle_exit(vcpu);
5394         return r;
5395
5396 cancel_injection:
5397         kvm_x86_ops->cancel_injection(vcpu);
5398         if (unlikely(vcpu->arch.apic_attention))
5399                 kvm_lapic_sync_from_vapic(vcpu);
5400 out:
5401         return r;
5402 }
5403
5404
5405 static int __vcpu_run(struct kvm_vcpu *vcpu)
5406 {
5407         int r;
5408         struct kvm *kvm = vcpu->kvm;
5409
5410         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5411                 pr_debug("vcpu %d received sipi with vector # %x\n",
5412                          vcpu->vcpu_id, vcpu->arch.sipi_vector);
5413                 kvm_lapic_reset(vcpu);
5414                 r = kvm_arch_vcpu_reset(vcpu);
5415                 if (r)
5416                         return r;
5417                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5418         }
5419
5420         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5421         vapic_enter(vcpu);
5422
5423         r = 1;
5424         while (r > 0) {
5425                 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5426                     !vcpu->arch.apf.halted)
5427                         r = vcpu_enter_guest(vcpu);
5428                 else {
5429                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5430                         kvm_vcpu_block(vcpu);
5431                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5432                         if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5433                         {
5434                                 switch(vcpu->arch.mp_state) {
5435                                 case KVM_MP_STATE_HALTED:
5436                                         vcpu->arch.mp_state =
5437                                                 KVM_MP_STATE_RUNNABLE;
5438                                 case KVM_MP_STATE_RUNNABLE:
5439                                         vcpu->arch.apf.halted = false;
5440                                         break;
5441                                 case KVM_MP_STATE_SIPI_RECEIVED:
5442                                 default:
5443                                         r = -EINTR;
5444                                         break;
5445                                 }
5446                         }
5447                 }
5448
5449                 if (r <= 0)
5450                         break;
5451
5452                 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5453                 if (kvm_cpu_has_pending_timer(vcpu))
5454                         kvm_inject_pending_timer_irqs(vcpu);
5455
5456                 if (dm_request_for_irq_injection(vcpu)) {
5457                         r = -EINTR;
5458                         vcpu->run->exit_reason = KVM_EXIT_INTR;
5459                         ++vcpu->stat.request_irq_exits;
5460                 }
5461
5462                 kvm_check_async_pf_completion(vcpu);
5463
5464                 if (signal_pending(current)) {
5465                         r = -EINTR;
5466                         vcpu->run->exit_reason = KVM_EXIT_INTR;
5467                         ++vcpu->stat.signal_exits;
5468                 }
5469                 if (need_resched()) {
5470                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5471                         kvm_resched(vcpu);
5472                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5473                 }
5474         }
5475
5476         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5477
5478         vapic_exit(vcpu);
5479
5480         return r;
5481 }
5482
5483 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5484 {
5485         int r;
5486         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5487         r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5488         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5489         if (r != EMULATE_DONE)
5490                 return 0;
5491         return 1;
5492 }
5493
5494 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5495 {
5496         BUG_ON(!vcpu->arch.pio.count);
5497
5498         return complete_emulated_io(vcpu);
5499 }
5500
5501 /*
5502  * Implements the following, as a state machine:
5503  *
5504  * read:
5505  *   for each fragment
5506  *     write gpa, len
5507  *     exit
5508  *     copy data
5509  *   execute insn
5510  *
5511  * write:
5512  *   for each fragment
5513  *      write gpa, len
5514  *      copy data
5515  *      exit
5516  */
5517 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5518 {
5519         struct kvm_run *run = vcpu->run;
5520         struct kvm_mmio_fragment *frag;
5521
5522         BUG_ON(!vcpu->mmio_needed);
5523
5524         /* Complete previous fragment */
5525         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5526         if (!vcpu->mmio_is_write)
5527                 memcpy(frag->data, run->mmio.data, frag->len);
5528         if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5529                 vcpu->mmio_needed = 0;
5530                 if (vcpu->mmio_is_write)
5531                         return 1;
5532                 vcpu->mmio_read_completed = 1;
5533                 return complete_emulated_io(vcpu);
5534         }
5535         /* Initiate next fragment */
5536         ++frag;
5537         run->exit_reason = KVM_EXIT_MMIO;
5538         run->mmio.phys_addr = frag->gpa;
5539         if (vcpu->mmio_is_write)
5540                 memcpy(run->mmio.data, frag->data, frag->len);
5541         run->mmio.len = frag->len;
5542         run->mmio.is_write = vcpu->mmio_is_write;
5543         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5544         return 0;
5545 }
5546
5547
5548 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5549 {
5550         int r;
5551         sigset_t sigsaved;
5552
5553         if (!tsk_used_math(current) && init_fpu(current))
5554                 return -ENOMEM;
5555
5556         if (vcpu->sigset_active)
5557                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5558
5559         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5560                 kvm_vcpu_block(vcpu);
5561                 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5562                 r = -EAGAIN;
5563                 goto out;
5564         }
5565
5566         /* re-sync apic's tpr */
5567         if (!irqchip_in_kernel(vcpu->kvm)) {
5568                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5569                         r = -EINVAL;
5570                         goto out;
5571                 }
5572         }
5573
5574         if (unlikely(vcpu->arch.complete_userspace_io)) {
5575                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
5576                 vcpu->arch.complete_userspace_io = NULL;
5577                 r = cui(vcpu);
5578                 if (r <= 0)
5579                         goto out;
5580         } else
5581                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5582
5583         r = __vcpu_run(vcpu);
5584
5585 out:
5586         post_kvm_run_save(vcpu);
5587         if (vcpu->sigset_active)
5588                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5589
5590         return r;
5591 }
5592
5593 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5594 {
5595         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5596                 /*
5597                  * We are here if userspace calls get_regs() in the middle of
5598                  * instruction emulation. Registers state needs to be copied
5599                  * back from emulation context to vcpu. Userspace shouldn't do
5600                  * that usually, but some bad designed PV devices (vmware
5601                  * backdoor interface) need this to work
5602                  */
5603                 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
5604                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5605         }
5606         regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5607         regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5608         regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5609         regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5610         regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5611         regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5612         regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5613         regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5614 #ifdef CONFIG_X86_64
5615         regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5616         regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5617         regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5618         regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5619         regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5620         regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5621         regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5622         regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5623 #endif
5624
5625         regs->rip = kvm_rip_read(vcpu);
5626         regs->rflags = kvm_get_rflags(vcpu);
5627
5628         return 0;
5629 }
5630
5631 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5632 {
5633         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5634         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5635
5636         kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5637         kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5638         kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5639         kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5640         kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5641         kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5642         kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5643         kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5644 #ifdef CONFIG_X86_64
5645         kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5646         kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5647         kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5648         kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5649         kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5650         kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5651         kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5652         kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5653 #endif
5654
5655         kvm_rip_write(vcpu, regs->rip);
5656         kvm_set_rflags(vcpu, regs->rflags);
5657
5658         vcpu->arch.exception.pending = false;
5659
5660         kvm_make_request(KVM_REQ_EVENT, vcpu);
5661
5662         return 0;
5663 }
5664
5665 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5666 {
5667         struct kvm_segment cs;
5668
5669         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5670         *db = cs.db;
5671         *l = cs.l;
5672 }
5673 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5674
5675 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5676                                   struct kvm_sregs *sregs)
5677 {
5678         struct desc_ptr dt;
5679
5680         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5681         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5682         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5683         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5684         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5685         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5686
5687         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5688         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5689
5690         kvm_x86_ops->get_idt(vcpu, &dt);
5691         sregs->idt.limit = dt.size;
5692         sregs->idt.base = dt.address;
5693         kvm_x86_ops->get_gdt(vcpu, &dt);
5694         sregs->gdt.limit = dt.size;
5695         sregs->gdt.base = dt.address;
5696
5697         sregs->cr0 = kvm_read_cr0(vcpu);
5698         sregs->cr2 = vcpu->arch.cr2;
5699         sregs->cr3 = kvm_read_cr3(vcpu);
5700         sregs->cr4 = kvm_read_cr4(vcpu);
5701         sregs->cr8 = kvm_get_cr8(vcpu);
5702         sregs->efer = vcpu->arch.efer;
5703         sregs->apic_base = kvm_get_apic_base(vcpu);
5704
5705         memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5706
5707         if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5708                 set_bit(vcpu->arch.interrupt.nr,
5709                         (unsigned long *)sregs->interrupt_bitmap);
5710
5711         return 0;
5712 }
5713
5714 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5715                                     struct kvm_mp_state *mp_state)
5716 {
5717         mp_state->mp_state = vcpu->arch.mp_state;
5718         return 0;
5719 }
5720
5721 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5722                                     struct kvm_mp_state *mp_state)
5723 {
5724         vcpu->arch.mp_state = mp_state->mp_state;
5725         kvm_make_request(KVM_REQ_EVENT, vcpu);
5726         return 0;
5727 }
5728
5729 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5730                     int reason, bool has_error_code, u32 error_code)
5731 {
5732         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5733         int ret;
5734
5735         init_emulate_ctxt(vcpu);
5736
5737         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
5738                                    has_error_code, error_code);
5739
5740         if (ret)
5741                 return EMULATE_FAIL;
5742
5743         kvm_rip_write(vcpu, ctxt->eip);
5744         kvm_set_rflags(vcpu, ctxt->eflags);
5745         kvm_make_request(KVM_REQ_EVENT, vcpu);
5746         return EMULATE_DONE;
5747 }
5748 EXPORT_SYMBOL_GPL(kvm_task_switch);
5749
5750 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5751                                   struct kvm_sregs *sregs)
5752 {
5753         int mmu_reset_needed = 0;
5754         int pending_vec, max_bits, idx;
5755         struct desc_ptr dt;
5756
5757         dt.size = sregs->idt.limit;
5758         dt.address = sregs->idt.base;
5759         kvm_x86_ops->set_idt(vcpu, &dt);
5760         dt.size = sregs->gdt.limit;
5761         dt.address = sregs->gdt.base;
5762         kvm_x86_ops->set_gdt(vcpu, &dt);
5763
5764         vcpu->arch.cr2 = sregs->cr2;
5765         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
5766         vcpu->arch.cr3 = sregs->cr3;
5767         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5768
5769         kvm_set_cr8(vcpu, sregs->cr8);
5770
5771         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5772         kvm_x86_ops->set_efer(vcpu, sregs->efer);
5773         kvm_set_apic_base(vcpu, sregs->apic_base);
5774
5775         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5776         kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5777         vcpu->arch.cr0 = sregs->cr0;
5778
5779         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5780         kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5781         if (sregs->cr4 & X86_CR4_OSXSAVE)
5782                 kvm_update_cpuid(vcpu);
5783
5784         idx = srcu_read_lock(&vcpu->kvm->srcu);
5785         if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5786                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
5787                 mmu_reset_needed = 1;
5788         }
5789         srcu_read_unlock(&vcpu->kvm->srcu, idx);
5790
5791         if (mmu_reset_needed)
5792                 kvm_mmu_reset_context(vcpu);
5793
5794         max_bits = KVM_NR_INTERRUPTS;
5795         pending_vec = find_first_bit(
5796                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5797         if (pending_vec < max_bits) {
5798                 kvm_queue_interrupt(vcpu, pending_vec, false);
5799                 pr_debug("Set back pending irq %d\n", pending_vec);
5800         }
5801
5802         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5803         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5804         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5805         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5806         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5807         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5808
5809         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5810         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5811
5812         update_cr8_intercept(vcpu);
5813
5814         /* Older userspace won't unhalt the vcpu on reset. */
5815         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5816             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5817             !is_protmode(vcpu))
5818                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5819
5820         kvm_make_request(KVM_REQ_EVENT, vcpu);
5821
5822         return 0;
5823 }
5824
5825 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5826                                         struct kvm_guest_debug *dbg)
5827 {
5828         unsigned long rflags;
5829         int i, r;
5830
5831         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5832                 r = -EBUSY;
5833                 if (vcpu->arch.exception.pending)
5834                         goto out;
5835                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5836                         kvm_queue_exception(vcpu, DB_VECTOR);
5837                 else
5838                         kvm_queue_exception(vcpu, BP_VECTOR);
5839         }
5840
5841         /*
5842          * Read rflags as long as potentially injected trace flags are still
5843          * filtered out.
5844          */
5845         rflags = kvm_get_rflags(vcpu);
5846
5847         vcpu->guest_debug = dbg->control;
5848         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5849                 vcpu->guest_debug = 0;
5850
5851         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5852                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5853                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5854                 vcpu->arch.switch_db_regs =
5855                         (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5856         } else {
5857                 for (i = 0; i < KVM_NR_DB_REGS; i++)
5858                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5859                 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5860         }
5861
5862         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5863                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5864                         get_segment_base(vcpu, VCPU_SREG_CS);
5865
5866         /*
5867          * Trigger an rflags update that will inject or remove the trace
5868          * flags.
5869          */
5870         kvm_set_rflags(vcpu, rflags);
5871
5872         kvm_x86_ops->set_guest_debug(vcpu, dbg);
5873
5874         r = 0;
5875
5876 out:
5877
5878         return r;
5879 }
5880
5881 /*
5882  * Translate a guest virtual address to a guest physical address.
5883  */
5884 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5885                                     struct kvm_translation *tr)
5886 {
5887         unsigned long vaddr = tr->linear_address;
5888         gpa_t gpa;
5889         int idx;
5890
5891         idx = srcu_read_lock(&vcpu->kvm->srcu);
5892         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5893         srcu_read_unlock(&vcpu->kvm->srcu, idx);
5894         tr->physical_address = gpa;
5895         tr->valid = gpa != UNMAPPED_GVA;
5896         tr->writeable = 1;
5897         tr->usermode = 0;
5898
5899         return 0;
5900 }
5901
5902 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5903 {
5904         struct i387_fxsave_struct *fxsave =
5905                         &vcpu->arch.guest_fpu.state->fxsave;
5906
5907         memcpy(fpu->fpr, fxsave->st_space, 128);
5908         fpu->fcw = fxsave->cwd;
5909         fpu->fsw = fxsave->swd;
5910         fpu->ftwx = fxsave->twd;
5911         fpu->last_opcode = fxsave->fop;
5912         fpu->last_ip = fxsave->rip;
5913         fpu->last_dp = fxsave->rdp;
5914         memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5915
5916         return 0;
5917 }
5918
5919 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5920 {
5921         struct i387_fxsave_struct *fxsave =
5922                         &vcpu->arch.guest_fpu.state->fxsave;
5923
5924         memcpy(fxsave->st_space, fpu->fpr, 128);
5925         fxsave->cwd = fpu->fcw;
5926         fxsave->swd = fpu->fsw;
5927         fxsave->twd = fpu->ftwx;
5928         fxsave->fop = fpu->last_opcode;
5929         fxsave->rip = fpu->last_ip;
5930         fxsave->rdp = fpu->last_dp;
5931         memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5932
5933         return 0;
5934 }
5935
5936 int fx_init(struct kvm_vcpu *vcpu)
5937 {
5938         int err;
5939
5940         err = fpu_alloc(&vcpu->arch.guest_fpu);
5941         if (err)
5942                 return err;
5943
5944         fpu_finit(&vcpu->arch.guest_fpu);
5945
5946         /*
5947          * Ensure guest xcr0 is valid for loading
5948          */
5949         vcpu->arch.xcr0 = XSTATE_FP;
5950
5951         vcpu->arch.cr0 |= X86_CR0_ET;
5952
5953         return 0;
5954 }
5955 EXPORT_SYMBOL_GPL(fx_init);
5956
5957 static void fx_free(struct kvm_vcpu *vcpu)
5958 {
5959         fpu_free(&vcpu->arch.guest_fpu);
5960 }
5961
5962 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5963 {
5964         if (vcpu->guest_fpu_loaded)
5965                 return;
5966
5967         /*
5968          * Restore all possible states in the guest,
5969          * and assume host would use all available bits.
5970          * Guest xcr0 would be loaded later.
5971          */
5972         kvm_put_guest_xcr0(vcpu);
5973         vcpu->guest_fpu_loaded = 1;
5974         unlazy_fpu(current);
5975         fpu_restore_checking(&vcpu->arch.guest_fpu);
5976         trace_kvm_fpu(1);
5977 }
5978
5979 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5980 {
5981         kvm_put_guest_xcr0(vcpu);
5982
5983         if (!vcpu->guest_fpu_loaded)
5984                 return;
5985
5986         vcpu->guest_fpu_loaded = 0;
5987         fpu_save_init(&vcpu->arch.guest_fpu);
5988         ++vcpu->stat.fpu_reload;
5989         kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5990         trace_kvm_fpu(0);
5991 }
5992
5993 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5994 {
5995         kvmclock_reset(vcpu);
5996
5997         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5998         fx_free(vcpu);
5999         kvm_x86_ops->vcpu_free(vcpu);
6000 }
6001
6002 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6003                                                 unsigned int id)
6004 {
6005         if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6006                 printk_once(KERN_WARNING
6007                 "kvm: SMP vm created on host with unstable TSC; "
6008                 "guest TSC will not be reliable\n");
6009         return kvm_x86_ops->vcpu_create(kvm, id);
6010 }
6011
6012 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6013 {
6014         int r;
6015
6016         vcpu->arch.mtrr_state.have_fixed = 1;
6017         r = vcpu_load(vcpu);
6018         if (r)
6019                 return r;
6020         r = kvm_arch_vcpu_reset(vcpu);
6021         if (r == 0)
6022                 r = kvm_mmu_setup(vcpu);
6023         vcpu_put(vcpu);
6024
6025         return r;
6026 }
6027
6028 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6029 {
6030         int r;
6031         vcpu->arch.apf.msr_val = 0;
6032
6033         r = vcpu_load(vcpu);
6034         BUG_ON(r);
6035         kvm_mmu_unload(vcpu);
6036         vcpu_put(vcpu);
6037
6038         fx_free(vcpu);
6039         kvm_x86_ops->vcpu_free(vcpu);
6040 }
6041
6042 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6043 {
6044         atomic_set(&vcpu->arch.nmi_queued, 0);
6045         vcpu->arch.nmi_pending = 0;
6046         vcpu->arch.nmi_injected = false;
6047
6048         vcpu->arch.switch_db_regs = 0;
6049         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6050         vcpu->arch.dr6 = DR6_FIXED_1;
6051         vcpu->arch.dr7 = DR7_FIXED_1;
6052
6053         kvm_make_request(KVM_REQ_EVENT, vcpu);
6054         vcpu->arch.apf.msr_val = 0;
6055         vcpu->arch.st.msr_val = 0;
6056
6057         kvmclock_reset(vcpu);
6058
6059         kvm_clear_async_pf_completion_queue(vcpu);
6060         kvm_async_pf_hash_reset(vcpu);
6061         vcpu->arch.apf.halted = false;
6062
6063         kvm_pmu_reset(vcpu);
6064
6065         return kvm_x86_ops->vcpu_reset(vcpu);
6066 }
6067
6068 int kvm_arch_hardware_enable(void *garbage)
6069 {
6070         struct kvm *kvm;
6071         struct kvm_vcpu *vcpu;
6072         int i;
6073         int ret;
6074         u64 local_tsc;
6075         u64 max_tsc = 0;
6076         bool stable, backwards_tsc = false;
6077
6078         kvm_shared_msr_cpu_online();
6079         ret = kvm_x86_ops->hardware_enable(garbage);
6080         if (ret != 0)
6081                 return ret;
6082
6083         local_tsc = native_read_tsc();
6084         stable = !check_tsc_unstable();
6085         list_for_each_entry(kvm, &vm_list, vm_list) {
6086                 kvm_for_each_vcpu(i, vcpu, kvm) {
6087                         if (!stable && vcpu->cpu == smp_processor_id())
6088                                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6089                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6090                                 backwards_tsc = true;
6091                                 if (vcpu->arch.last_host_tsc > max_tsc)
6092                                         max_tsc = vcpu->arch.last_host_tsc;
6093                         }
6094                 }
6095         }
6096
6097         /*
6098          * Sometimes, even reliable TSCs go backwards.  This happens on
6099          * platforms that reset TSC during suspend or hibernate actions, but
6100          * maintain synchronization.  We must compensate.  Fortunately, we can
6101          * detect that condition here, which happens early in CPU bringup,
6102          * before any KVM threads can be running.  Unfortunately, we can't
6103          * bring the TSCs fully up to date with real time, as we aren't yet far
6104          * enough into CPU bringup that we know how much real time has actually
6105          * elapsed; our helper function, get_kernel_ns() will be using boot
6106          * variables that haven't been updated yet.
6107          *
6108          * So we simply find the maximum observed TSC above, then record the
6109          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
6110          * the adjustment will be applied.  Note that we accumulate
6111          * adjustments, in case multiple suspend cycles happen before some VCPU
6112          * gets a chance to run again.  In the event that no KVM threads get a
6113          * chance to run, we will miss the entire elapsed period, as we'll have
6114          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6115          * loose cycle time.  This isn't too big a deal, since the loss will be
6116          * uniform across all VCPUs (not to mention the scenario is extremely
6117          * unlikely). It is possible that a second hibernate recovery happens
6118          * much faster than a first, causing the observed TSC here to be
6119          * smaller; this would require additional padding adjustment, which is
6120          * why we set last_host_tsc to the local tsc observed here.
6121          *
6122          * N.B. - this code below runs only on platforms with reliable TSC,
6123          * as that is the only way backwards_tsc is set above.  Also note
6124          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6125          * have the same delta_cyc adjustment applied if backwards_tsc
6126          * is detected.  Note further, this adjustment is only done once,
6127          * as we reset last_host_tsc on all VCPUs to stop this from being
6128          * called multiple times (one for each physical CPU bringup).
6129          *
6130          * Platforms with unreliable TSCs don't have to deal with this, they
6131          * will be compensated by the logic in vcpu_load, which sets the TSC to
6132          * catchup mode.  This will catchup all VCPUs to real time, but cannot
6133          * guarantee that they stay in perfect synchronization.
6134          */
6135         if (backwards_tsc) {
6136                 u64 delta_cyc = max_tsc - local_tsc;
6137                 list_for_each_entry(kvm, &vm_list, vm_list) {
6138                         kvm_for_each_vcpu(i, vcpu, kvm) {
6139                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6140                                 vcpu->arch.last_host_tsc = local_tsc;
6141                         }
6142
6143                         /*
6144                          * We have to disable TSC offset matching.. if you were
6145                          * booting a VM while issuing an S4 host suspend....
6146                          * you may have some problem.  Solving this issue is
6147                          * left as an exercise to the reader.
6148                          */
6149                         kvm->arch.last_tsc_nsec = 0;
6150                         kvm->arch.last_tsc_write = 0;
6151                 }
6152
6153         }
6154         return 0;
6155 }
6156
6157 void kvm_arch_hardware_disable(void *garbage)
6158 {
6159         kvm_x86_ops->hardware_disable(garbage);
6160         drop_user_return_notifiers(garbage);
6161 }
6162
6163 int kvm_arch_hardware_setup(void)
6164 {
6165         return kvm_x86_ops->hardware_setup();
6166 }
6167
6168 void kvm_arch_hardware_unsetup(void)
6169 {
6170         kvm_x86_ops->hardware_unsetup();
6171 }
6172
6173 void kvm_arch_check_processor_compat(void *rtn)
6174 {
6175         kvm_x86_ops->check_processor_compatibility(rtn);
6176 }
6177
6178 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6179 {
6180         return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6181 }
6182
6183 struct static_key kvm_no_apic_vcpu __read_mostly;
6184
6185 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6186 {
6187         struct page *page;
6188         struct kvm *kvm;
6189         int r;
6190
6191         BUG_ON(vcpu->kvm == NULL);
6192         kvm = vcpu->kvm;
6193
6194         vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6195         if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6196                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6197         else
6198                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6199
6200         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6201         if (!page) {
6202                 r = -ENOMEM;
6203                 goto fail;
6204         }
6205         vcpu->arch.pio_data = page_address(page);
6206
6207         kvm_set_tsc_khz(vcpu, max_tsc_khz);
6208
6209         r = kvm_mmu_create(vcpu);
6210         if (r < 0)
6211                 goto fail_free_pio_data;
6212
6213         if (irqchip_in_kernel(kvm)) {
6214                 r = kvm_create_lapic(vcpu);
6215                 if (r < 0)
6216                         goto fail_mmu_destroy;
6217         } else
6218                 static_key_slow_inc(&kvm_no_apic_vcpu);
6219
6220         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6221                                        GFP_KERNEL);
6222         if (!vcpu->arch.mce_banks) {
6223                 r = -ENOMEM;
6224                 goto fail_free_lapic;
6225         }
6226         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6227
6228         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6229                 goto fail_free_mce_banks;
6230
6231         kvm_async_pf_hash_reset(vcpu);
6232         kvm_pmu_init(vcpu);
6233
6234         return 0;
6235 fail_free_mce_banks:
6236         kfree(vcpu->arch.mce_banks);
6237 fail_free_lapic:
6238         kvm_free_lapic(vcpu);
6239 fail_mmu_destroy:
6240         kvm_mmu_destroy(vcpu);
6241 fail_free_pio_data:
6242         free_page((unsigned long)vcpu->arch.pio_data);
6243 fail:
6244         return r;
6245 }
6246
6247 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6248 {
6249         int idx;
6250
6251         kvm_pmu_destroy(vcpu);
6252         kfree(vcpu->arch.mce_banks);
6253         kvm_free_lapic(vcpu);
6254         idx = srcu_read_lock(&vcpu->kvm->srcu);
6255         kvm_mmu_destroy(vcpu);
6256         srcu_read_unlock(&vcpu->kvm->srcu, idx);
6257         free_page((unsigned long)vcpu->arch.pio_data);
6258         if (!irqchip_in_kernel(vcpu->kvm))
6259                 static_key_slow_dec(&kvm_no_apic_vcpu);
6260 }
6261
6262 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6263 {
6264         if (type)
6265                 return -EINVAL;
6266
6267         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6268         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6269
6270         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6271         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6272         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */</