3d9d08edbf29c8eecd2521e535771c56be21fa62
[linux-3.10.git] / arch / x86 / kvm / x86.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * derived from drivers/kvm/kvm_main.c
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright (C) 2008 Qumranet, Inc.
8  * Copyright IBM Corporation, 2008
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Amit Shah    <amit.shah@qumranet.com>
15  *   Ben-Ami Yassour <benami@il.ibm.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <trace/events/kvm.h>
50
51 #define CREATE_TRACE_POINTS
52 #include "trace.h"
53
54 #include <asm/debugreg.h>
55 #include <asm/msr.h>
56 #include <asm/desc.h>
57 #include <asm/mtrr.h>
58 #include <asm/mce.h>
59 #include <asm/i387.h>
60 #include <asm/fpu-internal.h> /* Ugh! */
61 #include <asm/xcr.h>
62 #include <asm/pvclock.h>
63 #include <asm/div64.h>
64
65 #define MAX_IO_MSRS 256
66 #define KVM_MAX_MCE_BANKS 32
67 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
68
69 #define emul_to_vcpu(ctxt) \
70         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
72 /* EFER defaults:
73  * - enable syscall per default because its emulated by KVM
74  * - enable LME and LMA per default on 64 bit KVM
75  */
76 #ifdef CONFIG_X86_64
77 static
78 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
79 #else
80 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
81 #endif
82
83 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
85
86 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
87 static void process_nmi(struct kvm_vcpu *vcpu);
88
89 struct kvm_x86_ops *kvm_x86_ops;
90 EXPORT_SYMBOL_GPL(kvm_x86_ops);
91
92 static bool ignore_msrs = 0;
93 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
95 bool kvm_has_tsc_control;
96 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97 u32  kvm_max_guest_tsc_khz;
98 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
100 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101 static u32 tsc_tolerance_ppm = 250;
102 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
104 #define KVM_NR_SHARED_MSRS 16
105
106 struct kvm_shared_msrs_global {
107         int nr;
108         u32 msrs[KVM_NR_SHARED_MSRS];
109 };
110
111 struct kvm_shared_msrs {
112         struct user_return_notifier urn;
113         bool registered;
114         struct kvm_shared_msr_values {
115                 u64 host;
116                 u64 curr;
117         } values[KVM_NR_SHARED_MSRS];
118 };
119
120 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
123 struct kvm_stats_debugfs_item debugfs_entries[] = {
124         { "pf_fixed", VCPU_STAT(pf_fixed) },
125         { "pf_guest", VCPU_STAT(pf_guest) },
126         { "tlb_flush", VCPU_STAT(tlb_flush) },
127         { "invlpg", VCPU_STAT(invlpg) },
128         { "exits", VCPU_STAT(exits) },
129         { "io_exits", VCPU_STAT(io_exits) },
130         { "mmio_exits", VCPU_STAT(mmio_exits) },
131         { "signal_exits", VCPU_STAT(signal_exits) },
132         { "irq_window", VCPU_STAT(irq_window_exits) },
133         { "nmi_window", VCPU_STAT(nmi_window_exits) },
134         { "halt_exits", VCPU_STAT(halt_exits) },
135         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
136         { "hypercalls", VCPU_STAT(hypercalls) },
137         { "request_irq", VCPU_STAT(request_irq_exits) },
138         { "irq_exits", VCPU_STAT(irq_exits) },
139         { "host_state_reload", VCPU_STAT(host_state_reload) },
140         { "efer_reload", VCPU_STAT(efer_reload) },
141         { "fpu_reload", VCPU_STAT(fpu_reload) },
142         { "insn_emulation", VCPU_STAT(insn_emulation) },
143         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
144         { "irq_injections", VCPU_STAT(irq_injections) },
145         { "nmi_injections", VCPU_STAT(nmi_injections) },
146         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150         { "mmu_flooded", VM_STAT(mmu_flooded) },
151         { "mmu_recycled", VM_STAT(mmu_recycled) },
152         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
153         { "mmu_unsync", VM_STAT(mmu_unsync) },
154         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
155         { "largepages", VM_STAT(lpages) },
156         { NULL }
157 };
158
159 u64 __read_mostly host_xcr0;
160
161 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162
163 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
164 {
165         int i;
166         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167                 vcpu->arch.apf.gfns[i] = ~0;
168 }
169
170 static void kvm_on_user_return(struct user_return_notifier *urn)
171 {
172         unsigned slot;
173         struct kvm_shared_msrs *locals
174                 = container_of(urn, struct kvm_shared_msrs, urn);
175         struct kvm_shared_msr_values *values;
176
177         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
178                 values = &locals->values[slot];
179                 if (values->host != values->curr) {
180                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
181                         values->curr = values->host;
182                 }
183         }
184         locals->registered = false;
185         user_return_notifier_unregister(urn);
186 }
187
188 static void shared_msr_update(unsigned slot, u32 msr)
189 {
190         struct kvm_shared_msrs *smsr;
191         u64 value;
192
193         smsr = &__get_cpu_var(shared_msrs);
194         /* only read, and nobody should modify it at this time,
195          * so don't need lock */
196         if (slot >= shared_msrs_global.nr) {
197                 printk(KERN_ERR "kvm: invalid MSR slot!");
198                 return;
199         }
200         rdmsrl_safe(msr, &value);
201         smsr->values[slot].host = value;
202         smsr->values[slot].curr = value;
203 }
204
205 void kvm_define_shared_msr(unsigned slot, u32 msr)
206 {
207         if (slot >= shared_msrs_global.nr)
208                 shared_msrs_global.nr = slot + 1;
209         shared_msrs_global.msrs[slot] = msr;
210         /* we need ensured the shared_msr_global have been updated */
211         smp_wmb();
212 }
213 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214
215 static void kvm_shared_msr_cpu_online(void)
216 {
217         unsigned i;
218
219         for (i = 0; i < shared_msrs_global.nr; ++i)
220                 shared_msr_update(i, shared_msrs_global.msrs[i]);
221 }
222
223 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
224 {
225         struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
227         if (((value ^ smsr->values[slot].curr) & mask) == 0)
228                 return;
229         smsr->values[slot].curr = value;
230         wrmsrl(shared_msrs_global.msrs[slot], value);
231         if (!smsr->registered) {
232                 smsr->urn.on_user_return = kvm_on_user_return;
233                 user_return_notifier_register(&smsr->urn);
234                 smsr->registered = true;
235         }
236 }
237 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238
239 static void drop_user_return_notifiers(void *ignore)
240 {
241         struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242
243         if (smsr->registered)
244                 kvm_on_user_return(&smsr->urn);
245 }
246
247 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248 {
249         if (irqchip_in_kernel(vcpu->kvm))
250                 return vcpu->arch.apic_base;
251         else
252                 return vcpu->arch.apic_base;
253 }
254 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
255
256 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
257 {
258         /* TODO: reserve bits check */
259         if (irqchip_in_kernel(vcpu->kvm))
260                 kvm_lapic_set_base(vcpu, data);
261         else
262                 vcpu->arch.apic_base = data;
263 }
264 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
265
266 #define EXCPT_BENIGN            0
267 #define EXCPT_CONTRIBUTORY      1
268 #define EXCPT_PF                2
269
270 static int exception_class(int vector)
271 {
272         switch (vector) {
273         case PF_VECTOR:
274                 return EXCPT_PF;
275         case DE_VECTOR:
276         case TS_VECTOR:
277         case NP_VECTOR:
278         case SS_VECTOR:
279         case GP_VECTOR:
280                 return EXCPT_CONTRIBUTORY;
281         default:
282                 break;
283         }
284         return EXCPT_BENIGN;
285 }
286
287 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
288                 unsigned nr, bool has_error, u32 error_code,
289                 bool reinject)
290 {
291         u32 prev_nr;
292         int class1, class2;
293
294         kvm_make_request(KVM_REQ_EVENT, vcpu);
295
296         if (!vcpu->arch.exception.pending) {
297         queue:
298                 vcpu->arch.exception.pending = true;
299                 vcpu->arch.exception.has_error_code = has_error;
300                 vcpu->arch.exception.nr = nr;
301                 vcpu->arch.exception.error_code = error_code;
302                 vcpu->arch.exception.reinject = reinject;
303                 return;
304         }
305
306         /* to check exception */
307         prev_nr = vcpu->arch.exception.nr;
308         if (prev_nr == DF_VECTOR) {
309                 /* triple fault -> shutdown */
310                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
311                 return;
312         }
313         class1 = exception_class(prev_nr);
314         class2 = exception_class(nr);
315         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317                 /* generate double fault per SDM Table 5-5 */
318                 vcpu->arch.exception.pending = true;
319                 vcpu->arch.exception.has_error_code = true;
320                 vcpu->arch.exception.nr = DF_VECTOR;
321                 vcpu->arch.exception.error_code = 0;
322         } else
323                 /* replace previous exception with a new one in a hope
324                    that instruction re-execution will regenerate lost
325                    exception */
326                 goto queue;
327 }
328
329 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330 {
331         kvm_multiple_exception(vcpu, nr, false, 0, false);
332 }
333 EXPORT_SYMBOL_GPL(kvm_queue_exception);
334
335 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336 {
337         kvm_multiple_exception(vcpu, nr, false, 0, true);
338 }
339 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
340
341 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
342 {
343         if (err)
344                 kvm_inject_gp(vcpu, 0);
345         else
346                 kvm_x86_ops->skip_emulated_instruction(vcpu);
347 }
348 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
349
350 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
351 {
352         ++vcpu->stat.pf_guest;
353         vcpu->arch.cr2 = fault->address;
354         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
355 }
356 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
357
358 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
359 {
360         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
362         else
363                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
364 }
365
366 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
367 {
368         atomic_inc(&vcpu->arch.nmi_queued);
369         kvm_make_request(KVM_REQ_NMI, vcpu);
370 }
371 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
372
373 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374 {
375         kvm_multiple_exception(vcpu, nr, true, error_code, false);
376 }
377 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
378
379 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380 {
381         kvm_multiple_exception(vcpu, nr, true, error_code, true);
382 }
383 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
384
385 /*
386  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
387  * a #GP and return false.
388  */
389 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
390 {
391         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
392                 return true;
393         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
394         return false;
395 }
396 EXPORT_SYMBOL_GPL(kvm_require_cpl);
397
398 /*
399  * This function will be used to read from the physical memory of the currently
400  * running guest. The difference to kvm_read_guest_page is that this function
401  * can read from guest physical or from the guest's guest physical memory.
402  */
403 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404                             gfn_t ngfn, void *data, int offset, int len,
405                             u32 access)
406 {
407         gfn_t real_gfn;
408         gpa_t ngpa;
409
410         ngpa     = gfn_to_gpa(ngfn);
411         real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412         if (real_gfn == UNMAPPED_GVA)
413                 return -EFAULT;
414
415         real_gfn = gpa_to_gfn(real_gfn);
416
417         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
418 }
419 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
420
421 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422                                void *data, int offset, int len, u32 access)
423 {
424         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425                                        data, offset, len, access);
426 }
427
428 /*
429  * Load the pae pdptrs.  Return true is they are all valid.
430  */
431 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
432 {
433         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
435         int i;
436         int ret;
437         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
438
439         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440                                       offset * sizeof(u64), sizeof(pdpte),
441                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
442         if (ret < 0) {
443                 ret = 0;
444                 goto out;
445         }
446         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
447                 if (is_present_gpte(pdpte[i]) &&
448                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
449                         ret = 0;
450                         goto out;
451                 }
452         }
453         ret = 1;
454
455         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
456         __set_bit(VCPU_EXREG_PDPTR,
457                   (unsigned long *)&vcpu->arch.regs_avail);
458         __set_bit(VCPU_EXREG_PDPTR,
459                   (unsigned long *)&vcpu->arch.regs_dirty);
460 out:
461
462         return ret;
463 }
464 EXPORT_SYMBOL_GPL(load_pdptrs);
465
466 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
467 {
468         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
469         bool changed = true;
470         int offset;
471         gfn_t gfn;
472         int r;
473
474         if (is_long_mode(vcpu) || !is_pae(vcpu))
475                 return false;
476
477         if (!test_bit(VCPU_EXREG_PDPTR,
478                       (unsigned long *)&vcpu->arch.regs_avail))
479                 return true;
480
481         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
483         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
485         if (r < 0)
486                 goto out;
487         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
488 out:
489
490         return changed;
491 }
492
493 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
494 {
495         unsigned long old_cr0 = kvm_read_cr0(vcpu);
496         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497                                     X86_CR0_CD | X86_CR0_NW;
498
499         cr0 |= X86_CR0_ET;
500
501 #ifdef CONFIG_X86_64
502         if (cr0 & 0xffffffff00000000UL)
503                 return 1;
504 #endif
505
506         cr0 &= ~CR0_RESERVED_BITS;
507
508         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
509                 return 1;
510
511         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
512                 return 1;
513
514         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515 #ifdef CONFIG_X86_64
516                 if ((vcpu->arch.efer & EFER_LME)) {
517                         int cs_db, cs_l;
518
519                         if (!is_pae(vcpu))
520                                 return 1;
521                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
522                         if (cs_l)
523                                 return 1;
524                 } else
525 #endif
526                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
527                                                  kvm_read_cr3(vcpu)))
528                         return 1;
529         }
530
531         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
532                 return 1;
533
534         kvm_x86_ops->set_cr0(vcpu, cr0);
535
536         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
537                 kvm_clear_async_pf_completion_queue(vcpu);
538                 kvm_async_pf_hash_reset(vcpu);
539         }
540
541         if ((cr0 ^ old_cr0) & update_bits)
542                 kvm_mmu_reset_context(vcpu);
543         return 0;
544 }
545 EXPORT_SYMBOL_GPL(kvm_set_cr0);
546
547 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
548 {
549         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
550 }
551 EXPORT_SYMBOL_GPL(kvm_lmsw);
552
553 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
554 {
555         u64 xcr0;
556
557         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
558         if (index != XCR_XFEATURE_ENABLED_MASK)
559                 return 1;
560         xcr0 = xcr;
561         if (kvm_x86_ops->get_cpl(vcpu) != 0)
562                 return 1;
563         if (!(xcr0 & XSTATE_FP))
564                 return 1;
565         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
566                 return 1;
567         if (xcr0 & ~host_xcr0)
568                 return 1;
569         vcpu->arch.xcr0 = xcr0;
570         vcpu->guest_xcr0_loaded = 0;
571         return 0;
572 }
573
574 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
575 {
576         if (__kvm_set_xcr(vcpu, index, xcr)) {
577                 kvm_inject_gp(vcpu, 0);
578                 return 1;
579         }
580         return 0;
581 }
582 EXPORT_SYMBOL_GPL(kvm_set_xcr);
583
584 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
585 {
586         unsigned long old_cr4 = kvm_read_cr4(vcpu);
587         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
588                                    X86_CR4_PAE | X86_CR4_SMEP;
589         if (cr4 & CR4_RESERVED_BITS)
590                 return 1;
591
592         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
593                 return 1;
594
595         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
596                 return 1;
597
598         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
599                 return 1;
600
601         if (is_long_mode(vcpu)) {
602                 if (!(cr4 & X86_CR4_PAE))
603                         return 1;
604         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605                    && ((cr4 ^ old_cr4) & pdptr_bits)
606                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
607                                    kvm_read_cr3(vcpu)))
608                 return 1;
609
610         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
611                 if (!guest_cpuid_has_pcid(vcpu))
612                         return 1;
613
614                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
615                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
616                         return 1;
617         }
618
619         if (kvm_x86_ops->set_cr4(vcpu, cr4))
620                 return 1;
621
622         if (((cr4 ^ old_cr4) & pdptr_bits) ||
623             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
624                 kvm_mmu_reset_context(vcpu);
625
626         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
627                 kvm_update_cpuid(vcpu);
628
629         return 0;
630 }
631 EXPORT_SYMBOL_GPL(kvm_set_cr4);
632
633 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
634 {
635         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
636                 kvm_mmu_sync_roots(vcpu);
637                 kvm_mmu_flush_tlb(vcpu);
638                 return 0;
639         }
640
641         if (is_long_mode(vcpu)) {
642                 if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) {
643                         if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
644                                 return 1;
645                 } else
646                         if (cr3 & CR3_L_MODE_RESERVED_BITS)
647                                 return 1;
648         } else {
649                 if (is_pae(vcpu)) {
650                         if (cr3 & CR3_PAE_RESERVED_BITS)
651                                 return 1;
652                         if (is_paging(vcpu) &&
653                             !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
654                                 return 1;
655                 }
656                 /*
657                  * We don't check reserved bits in nonpae mode, because
658                  * this isn't enforced, and VMware depends on this.
659                  */
660         }
661
662         /*
663          * Does the new cr3 value map to physical memory? (Note, we
664          * catch an invalid cr3 even in real-mode, because it would
665          * cause trouble later on when we turn on paging anyway.)
666          *
667          * A real CPU would silently accept an invalid cr3 and would
668          * attempt to use it - with largely undefined (and often hard
669          * to debug) behavior on the guest side.
670          */
671         if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
672                 return 1;
673         vcpu->arch.cr3 = cr3;
674         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
675         vcpu->arch.mmu.new_cr3(vcpu);
676         return 0;
677 }
678 EXPORT_SYMBOL_GPL(kvm_set_cr3);
679
680 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
681 {
682         if (cr8 & CR8_RESERVED_BITS)
683                 return 1;
684         if (irqchip_in_kernel(vcpu->kvm))
685                 kvm_lapic_set_tpr(vcpu, cr8);
686         else
687                 vcpu->arch.cr8 = cr8;
688         return 0;
689 }
690 EXPORT_SYMBOL_GPL(kvm_set_cr8);
691
692 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
693 {
694         if (irqchip_in_kernel(vcpu->kvm))
695                 return kvm_lapic_get_cr8(vcpu);
696         else
697                 return vcpu->arch.cr8;
698 }
699 EXPORT_SYMBOL_GPL(kvm_get_cr8);
700
701 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
702 {
703         switch (dr) {
704         case 0 ... 3:
705                 vcpu->arch.db[dr] = val;
706                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
707                         vcpu->arch.eff_db[dr] = val;
708                 break;
709         case 4:
710                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
711                         return 1; /* #UD */
712                 /* fall through */
713         case 6:
714                 if (val & 0xffffffff00000000ULL)
715                         return -1; /* #GP */
716                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
717                 break;
718         case 5:
719                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
720                         return 1; /* #UD */
721                 /* fall through */
722         default: /* 7 */
723                 if (val & 0xffffffff00000000ULL)
724                         return -1; /* #GP */
725                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
726                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
727                         kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
728                         vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
729                 }
730                 break;
731         }
732
733         return 0;
734 }
735
736 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
737 {
738         int res;
739
740         res = __kvm_set_dr(vcpu, dr, val);
741         if (res > 0)
742                 kvm_queue_exception(vcpu, UD_VECTOR);
743         else if (res < 0)
744                 kvm_inject_gp(vcpu, 0);
745
746         return res;
747 }
748 EXPORT_SYMBOL_GPL(kvm_set_dr);
749
750 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
751 {
752         switch (dr) {
753         case 0 ... 3:
754                 *val = vcpu->arch.db[dr];
755                 break;
756         case 4:
757                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
758                         return 1;
759                 /* fall through */
760         case 6:
761                 *val = vcpu->arch.dr6;
762                 break;
763         case 5:
764                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
765                         return 1;
766                 /* fall through */
767         default: /* 7 */
768                 *val = vcpu->arch.dr7;
769                 break;
770         }
771
772         return 0;
773 }
774
775 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
776 {
777         if (_kvm_get_dr(vcpu, dr, val)) {
778                 kvm_queue_exception(vcpu, UD_VECTOR);
779                 return 1;
780         }
781         return 0;
782 }
783 EXPORT_SYMBOL_GPL(kvm_get_dr);
784
785 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
786 {
787         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
788         u64 data;
789         int err;
790
791         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
792         if (err)
793                 return err;
794         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
795         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
796         return err;
797 }
798 EXPORT_SYMBOL_GPL(kvm_rdpmc);
799
800 /*
801  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
802  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
803  *
804  * This list is modified at module load time to reflect the
805  * capabilities of the host cpu. This capabilities test skips MSRs that are
806  * kvm-specific. Those are put in the beginning of the list.
807  */
808
809 #define KVM_SAVE_MSRS_BEGIN     9
810 static u32 msrs_to_save[] = {
811         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
812         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
813         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
814         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
815         MSR_KVM_PV_EOI_EN,
816         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
817         MSR_STAR,
818 #ifdef CONFIG_X86_64
819         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
820 #endif
821         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
822 };
823
824 static unsigned num_msrs_to_save;
825
826 static u32 emulated_msrs[] = {
827         MSR_IA32_TSCDEADLINE,
828         MSR_IA32_MISC_ENABLE,
829         MSR_IA32_MCG_STATUS,
830         MSR_IA32_MCG_CTL,
831 };
832
833 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
834 {
835         u64 old_efer = vcpu->arch.efer;
836
837         if (efer & efer_reserved_bits)
838                 return 1;
839
840         if (is_paging(vcpu)
841             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
842                 return 1;
843
844         if (efer & EFER_FFXSR) {
845                 struct kvm_cpuid_entry2 *feat;
846
847                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
848                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
849                         return 1;
850         }
851
852         if (efer & EFER_SVME) {
853                 struct kvm_cpuid_entry2 *feat;
854
855                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
856                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
857                         return 1;
858         }
859
860         efer &= ~EFER_LMA;
861         efer |= vcpu->arch.efer & EFER_LMA;
862
863         kvm_x86_ops->set_efer(vcpu, efer);
864
865         vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
866
867         /* Update reserved bits */
868         if ((efer ^ old_efer) & EFER_NX)
869                 kvm_mmu_reset_context(vcpu);
870
871         return 0;
872 }
873
874 void kvm_enable_efer_bits(u64 mask)
875 {
876        efer_reserved_bits &= ~mask;
877 }
878 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
879
880
881 /*
882  * Writes msr value into into the appropriate "register".
883  * Returns 0 on success, non-0 otherwise.
884  * Assumes vcpu_load() was already called.
885  */
886 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
887 {
888         return kvm_x86_ops->set_msr(vcpu, msr_index, data);
889 }
890
891 /*
892  * Adapt set_msr() to msr_io()'s calling convention
893  */
894 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
895 {
896         return kvm_set_msr(vcpu, index, *data);
897 }
898
899 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
900 {
901         int version;
902         int r;
903         struct pvclock_wall_clock wc;
904         struct timespec boot;
905
906         if (!wall_clock)
907                 return;
908
909         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
910         if (r)
911                 return;
912
913         if (version & 1)
914                 ++version;  /* first time write, random junk */
915
916         ++version;
917
918         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
919
920         /*
921          * The guest calculates current wall clock time by adding
922          * system time (updated by kvm_guest_time_update below) to the
923          * wall clock specified here.  guest system time equals host
924          * system time for us, thus we must fill in host boot time here.
925          */
926         getboottime(&boot);
927
928         wc.sec = boot.tv_sec;
929         wc.nsec = boot.tv_nsec;
930         wc.version = version;
931
932         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
933
934         version++;
935         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
936 }
937
938 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
939 {
940         uint32_t quotient, remainder;
941
942         /* Don't try to replace with do_div(), this one calculates
943          * "(dividend << 32) / divisor" */
944         __asm__ ( "divl %4"
945                   : "=a" (quotient), "=d" (remainder)
946                   : "0" (0), "1" (dividend), "r" (divisor) );
947         return quotient;
948 }
949
950 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
951                                s8 *pshift, u32 *pmultiplier)
952 {
953         uint64_t scaled64;
954         int32_t  shift = 0;
955         uint64_t tps64;
956         uint32_t tps32;
957
958         tps64 = base_khz * 1000LL;
959         scaled64 = scaled_khz * 1000LL;
960         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
961                 tps64 >>= 1;
962                 shift--;
963         }
964
965         tps32 = (uint32_t)tps64;
966         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
967                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
968                         scaled64 >>= 1;
969                 else
970                         tps32 <<= 1;
971                 shift++;
972         }
973
974         *pshift = shift;
975         *pmultiplier = div_frac(scaled64, tps32);
976
977         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
978                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
979 }
980
981 static inline u64 get_kernel_ns(void)
982 {
983         struct timespec ts;
984
985         WARN_ON(preemptible());
986         ktime_get_ts(&ts);
987         monotonic_to_bootbased(&ts);
988         return timespec_to_ns(&ts);
989 }
990
991 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
992 unsigned long max_tsc_khz;
993
994 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
995 {
996         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
997                                    vcpu->arch.virtual_tsc_shift);
998 }
999
1000 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1001 {
1002         u64 v = (u64)khz * (1000000 + ppm);
1003         do_div(v, 1000000);
1004         return v;
1005 }
1006
1007 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1008 {
1009         u32 thresh_lo, thresh_hi;
1010         int use_scaling = 0;
1011
1012         /* Compute a scale to convert nanoseconds in TSC cycles */
1013         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1014                            &vcpu->arch.virtual_tsc_shift,
1015                            &vcpu->arch.virtual_tsc_mult);
1016         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1017
1018         /*
1019          * Compute the variation in TSC rate which is acceptable
1020          * within the range of tolerance and decide if the
1021          * rate being applied is within that bounds of the hardware
1022          * rate.  If so, no scaling or compensation need be done.
1023          */
1024         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1025         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1026         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1027                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1028                 use_scaling = 1;
1029         }
1030         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1031 }
1032
1033 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1034 {
1035         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1036                                       vcpu->arch.virtual_tsc_mult,
1037                                       vcpu->arch.virtual_tsc_shift);
1038         tsc += vcpu->arch.this_tsc_write;
1039         return tsc;
1040 }
1041
1042 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1043 {
1044         struct kvm *kvm = vcpu->kvm;
1045         u64 offset, ns, elapsed;
1046         unsigned long flags;
1047         s64 usdiff;
1048
1049         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1050         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1051         ns = get_kernel_ns();
1052         elapsed = ns - kvm->arch.last_tsc_nsec;
1053
1054         /* n.b - signed multiplication and division required */
1055         usdiff = data - kvm->arch.last_tsc_write;
1056 #ifdef CONFIG_X86_64
1057         usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1058 #else
1059         /* do_div() only does unsigned */
1060         asm("idivl %2; xor %%edx, %%edx"
1061             : "=A"(usdiff)
1062             : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1063 #endif
1064         do_div(elapsed, 1000);
1065         usdiff -= elapsed;
1066         if (usdiff < 0)
1067                 usdiff = -usdiff;
1068
1069         /*
1070          * Special case: TSC write with a small delta (1 second) of virtual
1071          * cycle time against real time is interpreted as an attempt to
1072          * synchronize the CPU.
1073          *
1074          * For a reliable TSC, we can match TSC offsets, and for an unstable
1075          * TSC, we add elapsed time in this computation.  We could let the
1076          * compensation code attempt to catch up if we fall behind, but
1077          * it's better to try to match offsets from the beginning.
1078          */
1079         if (usdiff < USEC_PER_SEC &&
1080             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1081                 if (!check_tsc_unstable()) {
1082                         offset = kvm->arch.cur_tsc_offset;
1083                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1084                 } else {
1085                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1086                         data += delta;
1087                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1088                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1089                 }
1090         } else {
1091                 /*
1092                  * We split periods of matched TSC writes into generations.
1093                  * For each generation, we track the original measured
1094                  * nanosecond time, offset, and write, so if TSCs are in
1095                  * sync, we can match exact offset, and if not, we can match
1096                  * exact software computation in compute_guest_tsc()
1097                  *
1098                  * These values are tracked in kvm->arch.cur_xxx variables.
1099                  */
1100                 kvm->arch.cur_tsc_generation++;
1101                 kvm->arch.cur_tsc_nsec = ns;
1102                 kvm->arch.cur_tsc_write = data;
1103                 kvm->arch.cur_tsc_offset = offset;
1104                 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1105                          kvm->arch.cur_tsc_generation, data);
1106         }
1107
1108         /*
1109          * We also track th most recent recorded KHZ, write and time to
1110          * allow the matching interval to be extended at each write.
1111          */
1112         kvm->arch.last_tsc_nsec = ns;
1113         kvm->arch.last_tsc_write = data;
1114         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1115
1116         /* Reset of TSC must disable overshoot protection below */
1117         vcpu->arch.hv_clock.tsc_timestamp = 0;
1118         vcpu->arch.last_guest_tsc = data;
1119
1120         /* Keep track of which generation this VCPU has synchronized to */
1121         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1122         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1123         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1124
1125         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1126         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1127 }
1128
1129 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1130
1131 static int kvm_guest_time_update(struct kvm_vcpu *v)
1132 {
1133         unsigned long flags;
1134         struct kvm_vcpu_arch *vcpu = &v->arch;
1135         void *shared_kaddr;
1136         unsigned long this_tsc_khz;
1137         s64 kernel_ns, max_kernel_ns;
1138         u64 tsc_timestamp;
1139
1140         /* Keep irq disabled to prevent changes to the clock */
1141         local_irq_save(flags);
1142         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1143         kernel_ns = get_kernel_ns();
1144         this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1145         if (unlikely(this_tsc_khz == 0)) {
1146                 local_irq_restore(flags);
1147                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1148                 return 1;
1149         }
1150
1151         /*
1152          * We may have to catch up the TSC to match elapsed wall clock
1153          * time for two reasons, even if kvmclock is used.
1154          *   1) CPU could have been running below the maximum TSC rate
1155          *   2) Broken TSC compensation resets the base at each VCPU
1156          *      entry to avoid unknown leaps of TSC even when running
1157          *      again on the same CPU.  This may cause apparent elapsed
1158          *      time to disappear, and the guest to stand still or run
1159          *      very slowly.
1160          */
1161         if (vcpu->tsc_catchup) {
1162                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1163                 if (tsc > tsc_timestamp) {
1164                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1165                         tsc_timestamp = tsc;
1166                 }
1167         }
1168
1169         local_irq_restore(flags);
1170
1171         if (!vcpu->time_page)
1172                 return 0;
1173
1174         /*
1175          * Time as measured by the TSC may go backwards when resetting the base
1176          * tsc_timestamp.  The reason for this is that the TSC resolution is
1177          * higher than the resolution of the other clock scales.  Thus, many
1178          * possible measurments of the TSC correspond to one measurement of any
1179          * other clock, and so a spread of values is possible.  This is not a
1180          * problem for the computation of the nanosecond clock; with TSC rates
1181          * around 1GHZ, there can only be a few cycles which correspond to one
1182          * nanosecond value, and any path through this code will inevitably
1183          * take longer than that.  However, with the kernel_ns value itself,
1184          * the precision may be much lower, down to HZ granularity.  If the
1185          * first sampling of TSC against kernel_ns ends in the low part of the
1186          * range, and the second in the high end of the range, we can get:
1187          *
1188          * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1189          *
1190          * As the sampling errors potentially range in the thousands of cycles,
1191          * it is possible such a time value has already been observed by the
1192          * guest.  To protect against this, we must compute the system time as
1193          * observed by the guest and ensure the new system time is greater.
1194          */
1195         max_kernel_ns = 0;
1196         if (vcpu->hv_clock.tsc_timestamp) {
1197                 max_kernel_ns = vcpu->last_guest_tsc -
1198                                 vcpu->hv_clock.tsc_timestamp;
1199                 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1200                                     vcpu->hv_clock.tsc_to_system_mul,
1201                                     vcpu->hv_clock.tsc_shift);
1202                 max_kernel_ns += vcpu->last_kernel_ns;
1203         }
1204
1205         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1206                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1207                                    &vcpu->hv_clock.tsc_shift,
1208                                    &vcpu->hv_clock.tsc_to_system_mul);
1209                 vcpu->hw_tsc_khz = this_tsc_khz;
1210         }
1211
1212         if (max_kernel_ns > kernel_ns)
1213                 kernel_ns = max_kernel_ns;
1214
1215         /* With all the info we got, fill in the values */
1216         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1217         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1218         vcpu->last_kernel_ns = kernel_ns;
1219         vcpu->last_guest_tsc = tsc_timestamp;
1220         vcpu->hv_clock.flags = 0;
1221
1222         /*
1223          * The interface expects us to write an even number signaling that the
1224          * update is finished. Since the guest won't see the intermediate
1225          * state, we just increase by 2 at the end.
1226          */
1227         vcpu->hv_clock.version += 2;
1228
1229         shared_kaddr = kmap_atomic(vcpu->time_page);
1230
1231         memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1232                sizeof(vcpu->hv_clock));
1233
1234         kunmap_atomic(shared_kaddr);
1235
1236         mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1237         return 0;
1238 }
1239
1240 static bool msr_mtrr_valid(unsigned msr)
1241 {
1242         switch (msr) {
1243         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1244         case MSR_MTRRfix64K_00000:
1245         case MSR_MTRRfix16K_80000:
1246         case MSR_MTRRfix16K_A0000:
1247         case MSR_MTRRfix4K_C0000:
1248         case MSR_MTRRfix4K_C8000:
1249         case MSR_MTRRfix4K_D0000:
1250         case MSR_MTRRfix4K_D8000:
1251         case MSR_MTRRfix4K_E0000:
1252         case MSR_MTRRfix4K_E8000:
1253         case MSR_MTRRfix4K_F0000:
1254         case MSR_MTRRfix4K_F8000:
1255         case MSR_MTRRdefType:
1256         case MSR_IA32_CR_PAT:
1257                 return true;
1258         case 0x2f8:
1259                 return true;
1260         }
1261         return false;
1262 }
1263
1264 static bool valid_pat_type(unsigned t)
1265 {
1266         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1267 }
1268
1269 static bool valid_mtrr_type(unsigned t)
1270 {
1271         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1272 }
1273
1274 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1275 {
1276         int i;
1277
1278         if (!msr_mtrr_valid(msr))
1279                 return false;
1280
1281         if (msr == MSR_IA32_CR_PAT) {
1282                 for (i = 0; i < 8; i++)
1283                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1284                                 return false;
1285                 return true;
1286         } else if (msr == MSR_MTRRdefType) {
1287                 if (data & ~0xcff)
1288                         return false;
1289                 return valid_mtrr_type(data & 0xff);
1290         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1291                 for (i = 0; i < 8 ; i++)
1292                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1293                                 return false;
1294                 return true;
1295         }
1296
1297         /* variable MTRRs */
1298         return valid_mtrr_type(data & 0xff);
1299 }
1300
1301 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1302 {
1303         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1304
1305         if (!mtrr_valid(vcpu, msr, data))
1306                 return 1;
1307
1308         if (msr == MSR_MTRRdefType) {
1309                 vcpu->arch.mtrr_state.def_type = data;
1310                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1311         } else if (msr == MSR_MTRRfix64K_00000)
1312                 p[0] = data;
1313         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1314                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1315         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1316                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1317         else if (msr == MSR_IA32_CR_PAT)
1318                 vcpu->arch.pat = data;
1319         else {  /* Variable MTRRs */
1320                 int idx, is_mtrr_mask;
1321                 u64 *pt;
1322
1323                 idx = (msr - 0x200) / 2;
1324                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1325                 if (!is_mtrr_mask)
1326                         pt =
1327                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1328                 else
1329                         pt =
1330                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1331                 *pt = data;
1332         }
1333
1334         kvm_mmu_reset_context(vcpu);
1335         return 0;
1336 }
1337
1338 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1339 {
1340         u64 mcg_cap = vcpu->arch.mcg_cap;
1341         unsigned bank_num = mcg_cap & 0xff;
1342
1343         switch (msr) {
1344         case MSR_IA32_MCG_STATUS:
1345                 vcpu->arch.mcg_status = data;
1346                 break;
1347         case MSR_IA32_MCG_CTL:
1348                 if (!(mcg_cap & MCG_CTL_P))
1349                         return 1;
1350                 if (data != 0 && data != ~(u64)0)
1351                         return -1;
1352                 vcpu->arch.mcg_ctl = data;
1353                 break;
1354         default:
1355                 if (msr >= MSR_IA32_MC0_CTL &&
1356                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1357                         u32 offset = msr - MSR_IA32_MC0_CTL;
1358                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1359                          * some Linux kernels though clear bit 10 in bank 4 to
1360                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1361                          * this to avoid an uncatched #GP in the guest
1362                          */
1363                         if ((offset & 0x3) == 0 &&
1364                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1365                                 return -1;
1366                         vcpu->arch.mce_banks[offset] = data;
1367                         break;
1368                 }
1369                 return 1;
1370         }
1371         return 0;
1372 }
1373
1374 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1375 {
1376         struct kvm *kvm = vcpu->kvm;
1377         int lm = is_long_mode(vcpu);
1378         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1379                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1380         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1381                 : kvm->arch.xen_hvm_config.blob_size_32;
1382         u32 page_num = data & ~PAGE_MASK;
1383         u64 page_addr = data & PAGE_MASK;
1384         u8 *page;
1385         int r;
1386
1387         r = -E2BIG;
1388         if (page_num >= blob_size)
1389                 goto out;
1390         r = -ENOMEM;
1391         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1392         if (IS_ERR(page)) {
1393                 r = PTR_ERR(page);
1394                 goto out;
1395         }
1396         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1397                 goto out_free;
1398         r = 0;
1399 out_free:
1400         kfree(page);
1401 out:
1402         return r;
1403 }
1404
1405 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1406 {
1407         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1408 }
1409
1410 static bool kvm_hv_msr_partition_wide(u32 msr)
1411 {
1412         bool r = false;
1413         switch (msr) {
1414         case HV_X64_MSR_GUEST_OS_ID:
1415         case HV_X64_MSR_HYPERCALL:
1416                 r = true;
1417                 break;
1418         }
1419
1420         return r;
1421 }
1422
1423 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1424 {
1425         struct kvm *kvm = vcpu->kvm;
1426
1427         switch (msr) {
1428         case HV_X64_MSR_GUEST_OS_ID:
1429                 kvm->arch.hv_guest_os_id = data;
1430                 /* setting guest os id to zero disables hypercall page */
1431                 if (!kvm->arch.hv_guest_os_id)
1432                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1433                 break;
1434         case HV_X64_MSR_HYPERCALL: {
1435                 u64 gfn;
1436                 unsigned long addr;
1437                 u8 instructions[4];
1438
1439                 /* if guest os id is not set hypercall should remain disabled */
1440                 if (!kvm->arch.hv_guest_os_id)
1441                         break;
1442                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1443                         kvm->arch.hv_hypercall = data;
1444                         break;
1445                 }
1446                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1447                 addr = gfn_to_hva(kvm, gfn);
1448                 if (kvm_is_error_hva(addr))
1449                         return 1;
1450                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1451                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1452                 if (__copy_to_user((void __user *)addr, instructions, 4))
1453                         return 1;
1454                 kvm->arch.hv_hypercall = data;
1455                 break;
1456         }
1457         default:
1458                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1459                             "data 0x%llx\n", msr, data);
1460                 return 1;
1461         }
1462         return 0;
1463 }
1464
1465 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1466 {
1467         switch (msr) {
1468         case HV_X64_MSR_APIC_ASSIST_PAGE: {
1469                 unsigned long addr;
1470
1471                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1472                         vcpu->arch.hv_vapic = data;
1473                         break;
1474                 }
1475                 addr = gfn_to_hva(vcpu->kvm, data >>
1476                                   HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1477                 if (kvm_is_error_hva(addr))
1478                         return 1;
1479                 if (__clear_user((void __user *)addr, PAGE_SIZE))
1480                         return 1;
1481                 vcpu->arch.hv_vapic = data;
1482                 break;
1483         }
1484         case HV_X64_MSR_EOI:
1485                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1486         case HV_X64_MSR_ICR:
1487                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1488         case HV_X64_MSR_TPR:
1489                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1490         default:
1491                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1492                             "data 0x%llx\n", msr, data);
1493                 return 1;
1494         }
1495
1496         return 0;
1497 }
1498
1499 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1500 {
1501         gpa_t gpa = data & ~0x3f;
1502
1503         /* Bits 2:5 are reserved, Should be zero */
1504         if (data & 0x3c)
1505                 return 1;
1506
1507         vcpu->arch.apf.msr_val = data;
1508
1509         if (!(data & KVM_ASYNC_PF_ENABLED)) {
1510                 kvm_clear_async_pf_completion_queue(vcpu);
1511                 kvm_async_pf_hash_reset(vcpu);
1512                 return 0;
1513         }
1514
1515         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1516                 return 1;
1517
1518         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1519         kvm_async_pf_wakeup_all(vcpu);
1520         return 0;
1521 }
1522
1523 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1524 {
1525         if (vcpu->arch.time_page) {
1526                 kvm_release_page_dirty(vcpu->arch.time_page);
1527                 vcpu->arch.time_page = NULL;
1528         }
1529 }
1530
1531 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1532 {
1533         u64 delta;
1534
1535         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1536                 return;
1537
1538         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1539         vcpu->arch.st.last_steal = current->sched_info.run_delay;
1540         vcpu->arch.st.accum_steal = delta;
1541 }
1542
1543 static void record_steal_time(struct kvm_vcpu *vcpu)
1544 {
1545         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1546                 return;
1547
1548         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1549                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1550                 return;
1551
1552         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1553         vcpu->arch.st.steal.version += 2;
1554         vcpu->arch.st.accum_steal = 0;
1555
1556         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1557                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1558 }
1559
1560 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1561 {
1562         bool pr = false;
1563
1564         switch (msr) {
1565         case MSR_EFER:
1566                 return set_efer(vcpu, data);
1567         case MSR_K7_HWCR:
1568                 data &= ~(u64)0x40;     /* ignore flush filter disable */
1569                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
1570                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
1571                 if (data != 0) {
1572                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1573                                     data);
1574                         return 1;
1575                 }
1576                 break;
1577         case MSR_FAM10H_MMIO_CONF_BASE:
1578                 if (data != 0) {
1579                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1580                                     "0x%llx\n", data);
1581                         return 1;
1582                 }
1583                 break;
1584         case MSR_AMD64_NB_CFG:
1585                 break;
1586         case MSR_IA32_DEBUGCTLMSR:
1587                 if (!data) {
1588                         /* We support the non-activated case already */
1589                         break;
1590                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1591                         /* Values other than LBR and BTF are vendor-specific,
1592                            thus reserved and should throw a #GP */
1593                         return 1;
1594                 }
1595                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1596                             __func__, data);
1597                 break;
1598         case MSR_IA32_UCODE_REV:
1599         case MSR_IA32_UCODE_WRITE:
1600         case MSR_VM_HSAVE_PA:
1601         case MSR_AMD64_PATCH_LOADER:
1602                 break;
1603         case 0x200 ... 0x2ff:
1604                 return set_msr_mtrr(vcpu, msr, data);
1605         case MSR_IA32_APICBASE:
1606                 kvm_set_apic_base(vcpu, data);
1607                 break;
1608         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1609                 return kvm_x2apic_msr_write(vcpu, msr, data);
1610         case MSR_IA32_TSCDEADLINE:
1611                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1612                 break;
1613         case MSR_IA32_MISC_ENABLE:
1614                 vcpu->arch.ia32_misc_enable_msr = data;
1615                 break;
1616         case MSR_KVM_WALL_CLOCK_NEW:
1617         case MSR_KVM_WALL_CLOCK:
1618                 vcpu->kvm->arch.wall_clock = data;
1619                 kvm_write_wall_clock(vcpu->kvm, data);
1620                 break;
1621         case MSR_KVM_SYSTEM_TIME_NEW:
1622         case MSR_KVM_SYSTEM_TIME: {
1623                 kvmclock_reset(vcpu);
1624
1625                 vcpu->arch.time = data;
1626                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1627
1628                 /* we verify if the enable bit is set... */
1629                 if (!(data & 1))
1630                         break;
1631
1632                 /* ...but clean it before doing the actual write */
1633                 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1634
1635                 vcpu->arch.time_page =
1636                                 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1637
1638                 if (is_error_page(vcpu->arch.time_page)) {
1639                         kvm_release_page_clean(vcpu->arch.time_page);
1640                         vcpu->arch.time_page = NULL;
1641                 }
1642                 break;
1643         }
1644         case MSR_KVM_ASYNC_PF_EN:
1645                 if (kvm_pv_enable_async_pf(vcpu, data))
1646                         return 1;
1647                 break;
1648         case MSR_KVM_STEAL_TIME:
1649
1650                 if (unlikely(!sched_info_on()))
1651                         return 1;
1652
1653                 if (data & KVM_STEAL_RESERVED_MASK)
1654                         return 1;
1655
1656                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1657                                                         data & KVM_STEAL_VALID_BITS))
1658                         return 1;
1659
1660                 vcpu->arch.st.msr_val = data;
1661
1662                 if (!(data & KVM_MSR_ENABLED))
1663                         break;
1664
1665                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1666
1667                 preempt_disable();
1668                 accumulate_steal_time(vcpu);
1669                 preempt_enable();
1670
1671                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1672
1673                 break;
1674         case MSR_KVM_PV_EOI_EN:
1675                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1676                         return 1;
1677                 break;
1678
1679         case MSR_IA32_MCG_CTL:
1680         case MSR_IA32_MCG_STATUS:
1681         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1682                 return set_msr_mce(vcpu, msr, data);
1683
1684         /* Performance counters are not protected by a CPUID bit,
1685          * so we should check all of them in the generic path for the sake of
1686          * cross vendor migration.
1687          * Writing a zero into the event select MSRs disables them,
1688          * which we perfectly emulate ;-). Any other value should be at least
1689          * reported, some guests depend on them.
1690          */
1691         case MSR_K7_EVNTSEL0:
1692         case MSR_K7_EVNTSEL1:
1693         case MSR_K7_EVNTSEL2:
1694         case MSR_K7_EVNTSEL3:
1695                 if (data != 0)
1696                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1697                                     "0x%x data 0x%llx\n", msr, data);
1698                 break;
1699         /* at least RHEL 4 unconditionally writes to the perfctr registers,
1700          * so we ignore writes to make it happy.
1701          */
1702         case MSR_K7_PERFCTR0:
1703         case MSR_K7_PERFCTR1:
1704         case MSR_K7_PERFCTR2:
1705         case MSR_K7_PERFCTR3:
1706                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1707                             "0x%x data 0x%llx\n", msr, data);
1708                 break;
1709         case MSR_P6_PERFCTR0:
1710         case MSR_P6_PERFCTR1:
1711                 pr = true;
1712         case MSR_P6_EVNTSEL0:
1713         case MSR_P6_EVNTSEL1:
1714                 if (kvm_pmu_msr(vcpu, msr))
1715                         return kvm_pmu_set_msr(vcpu, msr, data);
1716
1717                 if (pr || data != 0)
1718                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1719                                     "0x%x data 0x%llx\n", msr, data);
1720                 break;
1721         case MSR_K7_CLK_CTL:
1722                 /*
1723                  * Ignore all writes to this no longer documented MSR.
1724                  * Writes are only relevant for old K7 processors,
1725                  * all pre-dating SVM, but a recommended workaround from
1726                  * AMD for these chips. It is possible to specify the
1727                  * affected processor models on the command line, hence
1728                  * the need to ignore the workaround.
1729                  */
1730                 break;
1731         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1732                 if (kvm_hv_msr_partition_wide(msr)) {
1733                         int r;
1734                         mutex_lock(&vcpu->kvm->lock);
1735                         r = set_msr_hyperv_pw(vcpu, msr, data);
1736                         mutex_unlock(&vcpu->kvm->lock);
1737                         return r;
1738                 } else
1739                         return set_msr_hyperv(vcpu, msr, data);
1740                 break;
1741         case MSR_IA32_BBL_CR_CTL3:
1742                 /* Drop writes to this legacy MSR -- see rdmsr
1743                  * counterpart for further detail.
1744                  */
1745                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1746                 break;
1747         case MSR_AMD64_OSVW_ID_LENGTH:
1748                 if (!guest_cpuid_has_osvw(vcpu))
1749                         return 1;
1750                 vcpu->arch.osvw.length = data;
1751                 break;
1752         case MSR_AMD64_OSVW_STATUS:
1753                 if (!guest_cpuid_has_osvw(vcpu))
1754                         return 1;
1755                 vcpu->arch.osvw.status = data;
1756                 break;
1757         default:
1758                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1759                         return xen_hvm_config(vcpu, data);
1760                 if (kvm_pmu_msr(vcpu, msr))
1761                         return kvm_pmu_set_msr(vcpu, msr, data);
1762                 if (!ignore_msrs) {
1763                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1764                                     msr, data);
1765                         return 1;
1766                 } else {
1767                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1768                                     msr, data);
1769                         break;
1770                 }
1771         }
1772         return 0;
1773 }
1774 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1775
1776
1777 /*
1778  * Reads an msr value (of 'msr_index') into 'pdata'.
1779  * Returns 0 on success, non-0 otherwise.
1780  * Assumes vcpu_load() was already called.
1781  */
1782 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1783 {
1784         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1785 }
1786
1787 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1788 {
1789         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1790
1791         if (!msr_mtrr_valid(msr))
1792                 return 1;
1793
1794         if (msr == MSR_MTRRdefType)
1795                 *pdata = vcpu->arch.mtrr_state.def_type +
1796                          (vcpu->arch.mtrr_state.enabled << 10);
1797         else if (msr == MSR_MTRRfix64K_00000)
1798                 *pdata = p[0];
1799         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1800                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1801         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1802                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1803         else if (msr == MSR_IA32_CR_PAT)
1804                 *pdata = vcpu->arch.pat;
1805         else {  /* Variable MTRRs */
1806                 int idx, is_mtrr_mask;
1807                 u64 *pt;
1808
1809                 idx = (msr - 0x200) / 2;
1810                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1811                 if (!is_mtrr_mask)
1812                         pt =
1813                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1814                 else
1815                         pt =
1816                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1817                 *pdata = *pt;
1818         }
1819
1820         return 0;
1821 }
1822
1823 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1824 {
1825         u64 data;
1826         u64 mcg_cap = vcpu->arch.mcg_cap;
1827         unsigned bank_num = mcg_cap & 0xff;
1828
1829         switch (msr) {
1830         case MSR_IA32_P5_MC_ADDR:
1831         case MSR_IA32_P5_MC_TYPE:
1832                 data = 0;
1833                 break;
1834         case MSR_IA32_MCG_CAP:
1835                 data = vcpu->arch.mcg_cap;
1836                 break;
1837         case MSR_IA32_MCG_CTL:
1838                 if (!(mcg_cap & MCG_CTL_P))
1839                         return 1;
1840                 data = vcpu->arch.mcg_ctl;
1841                 break;
1842         case MSR_IA32_MCG_STATUS:
1843                 data = vcpu->arch.mcg_status;
1844                 break;
1845         default:
1846                 if (msr >= MSR_IA32_MC0_CTL &&
1847                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1848                         u32 offset = msr - MSR_IA32_MC0_CTL;
1849                         data = vcpu->arch.mce_banks[offset];
1850                         break;
1851                 }
1852                 return 1;
1853         }
1854         *pdata = data;
1855         return 0;
1856 }
1857
1858 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1859 {
1860         u64 data = 0;
1861         struct kvm *kvm = vcpu->kvm;
1862
1863         switch (msr) {
1864         case HV_X64_MSR_GUEST_OS_ID:
1865                 data = kvm->arch.hv_guest_os_id;
1866                 break;
1867         case HV_X64_MSR_HYPERCALL:
1868                 data = kvm->arch.hv_hypercall;
1869                 break;
1870         default:
1871                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1872                 return 1;
1873         }
1874
1875         *pdata = data;
1876         return 0;
1877 }
1878
1879 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1880 {
1881         u64 data = 0;
1882
1883         switch (msr) {
1884         case HV_X64_MSR_VP_INDEX: {
1885                 int r;
1886                 struct kvm_vcpu *v;
1887                 kvm_for_each_vcpu(r, v, vcpu->kvm)
1888                         if (v == vcpu)
1889                                 data = r;
1890                 break;
1891         }
1892         case HV_X64_MSR_EOI:
1893                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1894         case HV_X64_MSR_ICR:
1895                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1896         case HV_X64_MSR_TPR:
1897                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1898         case HV_X64_MSR_APIC_ASSIST_PAGE:
1899                 data = vcpu->arch.hv_vapic;
1900                 break;
1901         default:
1902                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1903                 return 1;
1904         }
1905         *pdata = data;
1906         return 0;
1907 }
1908
1909 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1910 {
1911         u64 data;
1912
1913         switch (msr) {
1914         case MSR_IA32_PLATFORM_ID:
1915         case MSR_IA32_EBL_CR_POWERON:
1916         case MSR_IA32_DEBUGCTLMSR:
1917         case MSR_IA32_LASTBRANCHFROMIP:
1918         case MSR_IA32_LASTBRANCHTOIP:
1919         case MSR_IA32_LASTINTFROMIP:
1920         case MSR_IA32_LASTINTTOIP:
1921         case MSR_K8_SYSCFG:
1922         case MSR_K7_HWCR:
1923         case MSR_VM_HSAVE_PA:
1924         case MSR_K7_EVNTSEL0:
1925         case MSR_K7_PERFCTR0:
1926         case MSR_K8_INT_PENDING_MSG:
1927         case MSR_AMD64_NB_CFG:
1928         case MSR_FAM10H_MMIO_CONF_BASE:
1929                 data = 0;
1930                 break;
1931         case MSR_P6_PERFCTR0:
1932         case MSR_P6_PERFCTR1:
1933         case MSR_P6_EVNTSEL0:
1934         case MSR_P6_EVNTSEL1:
1935                 if (kvm_pmu_msr(vcpu, msr))
1936                         return kvm_pmu_get_msr(vcpu, msr, pdata);
1937                 data = 0;
1938                 break;
1939         case MSR_IA32_UCODE_REV:
1940                 data = 0x100000000ULL;
1941                 break;
1942         case MSR_MTRRcap:
1943                 data = 0x500 | KVM_NR_VAR_MTRR;
1944                 break;
1945         case 0x200 ... 0x2ff:
1946                 return get_msr_mtrr(vcpu, msr, pdata);
1947         case 0xcd: /* fsb frequency */
1948                 data = 3;
1949                 break;
1950                 /*
1951                  * MSR_EBC_FREQUENCY_ID
1952                  * Conservative value valid for even the basic CPU models.
1953                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1954                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1955                  * and 266MHz for model 3, or 4. Set Core Clock
1956                  * Frequency to System Bus Frequency Ratio to 1 (bits
1957                  * 31:24) even though these are only valid for CPU
1958                  * models > 2, however guests may end up dividing or
1959                  * multiplying by zero otherwise.
1960                  */
1961         case MSR_EBC_FREQUENCY_ID:
1962                 data = 1 << 24;
1963                 break;
1964         case MSR_IA32_APICBASE:
1965                 data = kvm_get_apic_base(vcpu);
1966                 break;
1967         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1968                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1969                 break;
1970         case MSR_IA32_TSCDEADLINE:
1971                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1972                 break;
1973         case MSR_IA32_MISC_ENABLE:
1974                 data = vcpu->arch.ia32_misc_enable_msr;
1975                 break;
1976         case MSR_IA32_PERF_STATUS:
1977                 /* TSC increment by tick */
1978                 data = 1000ULL;
1979                 /* CPU multiplier */
1980                 data |= (((uint64_t)4ULL) << 40);
1981                 break;
1982         case MSR_EFER:
1983                 data = vcpu->arch.efer;
1984                 break;
1985         case MSR_KVM_WALL_CLOCK:
1986         case MSR_KVM_WALL_CLOCK_NEW:
1987                 data = vcpu->kvm->arch.wall_clock;
1988                 break;
1989         case MSR_KVM_SYSTEM_TIME:
1990         case MSR_KVM_SYSTEM_TIME_NEW:
1991                 data = vcpu->arch.time;
1992                 break;
1993         case MSR_KVM_ASYNC_PF_EN:
1994                 data = vcpu->arch.apf.msr_val;
1995                 break;
1996         case MSR_KVM_STEAL_TIME:
1997                 data = vcpu->arch.st.msr_val;
1998                 break;
1999         case MSR_IA32_P5_MC_ADDR:
2000         case MSR_IA32_P5_MC_TYPE:
2001         case MSR_IA32_MCG_CAP:
2002         case MSR_IA32_MCG_CTL:
2003         case MSR_IA32_MCG_STATUS:
2004         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2005                 return get_msr_mce(vcpu, msr, pdata);
2006         case MSR_K7_CLK_CTL:
2007                 /*
2008                  * Provide expected ramp-up count for K7. All other
2009                  * are set to zero, indicating minimum divisors for
2010                  * every field.
2011                  *
2012                  * This prevents guest kernels on AMD host with CPU
2013                  * type 6, model 8 and higher from exploding due to
2014                  * the rdmsr failing.
2015                  */
2016                 data = 0x20000000;
2017                 break;
2018         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2019                 if (kvm_hv_msr_partition_wide(msr)) {
2020                         int r;
2021                         mutex_lock(&vcpu->kvm->lock);
2022                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2023                         mutex_unlock(&vcpu->kvm->lock);
2024                         return r;
2025                 } else
2026                         return get_msr_hyperv(vcpu, msr, pdata);
2027                 break;
2028         case MSR_IA32_BBL_CR_CTL3:
2029                 /* This legacy MSR exists but isn't fully documented in current
2030                  * silicon.  It is however accessed by winxp in very narrow
2031                  * scenarios where it sets bit #19, itself documented as
2032                  * a "reserved" bit.  Best effort attempt to source coherent
2033                  * read data here should the balance of the register be
2034                  * interpreted by the guest:
2035                  *
2036                  * L2 cache control register 3: 64GB range, 256KB size,
2037                  * enabled, latency 0x1, configured
2038                  */
2039                 data = 0xbe702111;
2040                 break;
2041         case MSR_AMD64_OSVW_ID_LENGTH:
2042                 if (!guest_cpuid_has_osvw(vcpu))
2043                         return 1;
2044                 data = vcpu->arch.osvw.length;
2045                 break;
2046         case MSR_AMD64_OSVW_STATUS:
2047                 if (!guest_cpuid_has_osvw(vcpu))
2048                         return 1;
2049                 data = vcpu->arch.osvw.status;
2050                 break;
2051         default:
2052                 if (kvm_pmu_msr(vcpu, msr))
2053                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2054                 if (!ignore_msrs) {
2055                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2056                         return 1;
2057                 } else {
2058                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2059                         data = 0;
2060                 }
2061                 break;
2062         }
2063         *pdata = data;
2064         return 0;
2065 }
2066 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2067
2068 /*
2069  * Read or write a bunch of msrs. All parameters are kernel addresses.
2070  *
2071  * @return number of msrs set successfully.
2072  */
2073 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2074                     struct kvm_msr_entry *entries,
2075                     int (*do_msr)(struct kvm_vcpu *vcpu,
2076                                   unsigned index, u64 *data))
2077 {
2078         int i, idx;
2079
2080         idx = srcu_read_lock(&vcpu->kvm->srcu);
2081         for (i = 0; i < msrs->nmsrs; ++i)
2082                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2083                         break;
2084         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2085
2086         return i;
2087 }
2088
2089 /*
2090  * Read or write a bunch of msrs. Parameters are user addresses.
2091  *
2092  * @return number of msrs set successfully.
2093  */
2094 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2095                   int (*do_msr)(struct kvm_vcpu *vcpu,
2096                                 unsigned index, u64 *data),
2097                   int writeback)
2098 {
2099         struct kvm_msrs msrs;
2100         struct kvm_msr_entry *entries;
2101         int r, n;
2102         unsigned size;
2103
2104         r = -EFAULT;
2105         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2106                 goto out;
2107
2108         r = -E2BIG;
2109         if (msrs.nmsrs >= MAX_IO_MSRS)
2110                 goto out;
2111
2112         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2113         entries = memdup_user(user_msrs->entries, size);
2114         if (IS_ERR(entries)) {
2115                 r = PTR_ERR(entries);
2116                 goto out;
2117         }
2118
2119         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2120         if (r < 0)
2121                 goto out_free;
2122
2123         r = -EFAULT;
2124         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2125                 goto out_free;
2126
2127         r = n;
2128
2129 out_free:
2130         kfree(entries);
2131 out:
2132         return r;
2133 }
2134
2135 int kvm_dev_ioctl_check_extension(long ext)
2136 {
2137         int r;
2138
2139         switch (ext) {
2140         case KVM_CAP_IRQCHIP:
2141         case KVM_CAP_HLT:
2142         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2143         case KVM_CAP_SET_TSS_ADDR:
2144         case KVM_CAP_EXT_CPUID:
2145         case KVM_CAP_CLOCKSOURCE:
2146         case KVM_CAP_PIT:
2147         case KVM_CAP_NOP_IO_DELAY:
2148         case KVM_CAP_MP_STATE:
2149         case KVM_CAP_SYNC_MMU:
2150         case KVM_CAP_USER_NMI:
2151         case KVM_CAP_REINJECT_CONTROL:
2152         case KVM_CAP_IRQ_INJECT_STATUS:
2153         case KVM_CAP_ASSIGN_DEV_IRQ:
2154         case KVM_CAP_IRQFD:
2155         case KVM_CAP_IOEVENTFD:
2156         case KVM_CAP_PIT2:
2157         case KVM_CAP_PIT_STATE2:
2158         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2159         case KVM_CAP_XEN_HVM:
2160         case KVM_CAP_ADJUST_CLOCK:
2161         case KVM_CAP_VCPU_EVENTS:
2162         case KVM_CAP_HYPERV:
2163         case KVM_CAP_HYPERV_VAPIC:
2164         case KVM_CAP_HYPERV_SPIN:
2165         case KVM_CAP_PCI_SEGMENT:
2166         case KVM_CAP_DEBUGREGS:
2167         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2168         case KVM_CAP_XSAVE:
2169         case KVM_CAP_ASYNC_PF:
2170         case KVM_CAP_GET_TSC_KHZ:
2171         case KVM_CAP_PCI_2_3:
2172         case KVM_CAP_KVMCLOCK_CTRL:
2173                 r = 1;
2174                 break;
2175         case KVM_CAP_COALESCED_MMIO:
2176                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2177                 break;
2178         case KVM_CAP_VAPIC:
2179                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2180                 break;
2181         case KVM_CAP_NR_VCPUS:
2182                 r = KVM_SOFT_MAX_VCPUS;
2183                 break;
2184         case KVM_CAP_MAX_VCPUS:
2185                 r = KVM_MAX_VCPUS;
2186                 break;
2187         case KVM_CAP_NR_MEMSLOTS:
2188                 r = KVM_MEMORY_SLOTS;
2189                 break;
2190         case KVM_CAP_PV_MMU:    /* obsolete */
2191                 r = 0;
2192                 break;
2193         case KVM_CAP_IOMMU:
2194                 r = iommu_present(&pci_bus_type);
2195                 break;
2196         case KVM_CAP_MCE:
2197                 r = KVM_MAX_MCE_BANKS;
2198                 break;
2199         case KVM_CAP_XCRS:
2200                 r = cpu_has_xsave;
2201                 break;
2202         case KVM_CAP_TSC_CONTROL:
2203                 r = kvm_has_tsc_control;
2204                 break;
2205         case KVM_CAP_TSC_DEADLINE_TIMER:
2206                 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2207                 break;
2208         default:
2209                 r = 0;
2210                 break;
2211         }
2212         return r;
2213
2214 }
2215
2216 long kvm_arch_dev_ioctl(struct file *filp,
2217                         unsigned int ioctl, unsigned long arg)
2218 {
2219         void __user *argp = (void __user *)arg;
2220         long r;
2221
2222         switch (ioctl) {
2223         case KVM_GET_MSR_INDEX_LIST: {
2224                 struct kvm_msr_list __user *user_msr_list = argp;
2225                 struct kvm_msr_list msr_list;
2226                 unsigned n;
2227
2228                 r = -EFAULT;
2229                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2230                         goto out;
2231                 n = msr_list.nmsrs;
2232                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2233                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2234                         goto out;
2235                 r = -E2BIG;
2236                 if (n < msr_list.nmsrs)
2237                         goto out;
2238                 r = -EFAULT;
2239                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2240                                  num_msrs_to_save * sizeof(u32)))
2241                         goto out;
2242                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2243                                  &emulated_msrs,
2244                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2245                         goto out;
2246                 r = 0;
2247                 break;
2248         }
2249         case KVM_GET_SUPPORTED_CPUID: {
2250                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2251                 struct kvm_cpuid2 cpuid;
2252
2253                 r = -EFAULT;
2254                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2255                         goto out;
2256                 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2257                                                       cpuid_arg->entries);
2258                 if (r)
2259                         goto out;
2260
2261                 r = -EFAULT;
2262                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2263                         goto out;
2264                 r = 0;
2265                 break;
2266         }
2267         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2268                 u64 mce_cap;
2269
2270                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2271                 r = -EFAULT;
2272                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2273                         goto out;
2274                 r = 0;
2275                 break;
2276         }
2277         default:
2278                 r = -EINVAL;
2279         }
2280 out:
2281         return r;
2282 }
2283
2284 static void wbinvd_ipi(void *garbage)
2285 {
2286         wbinvd();
2287 }
2288
2289 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2290 {
2291         return vcpu->kvm->arch.iommu_domain &&
2292                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2293 }
2294
2295 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2296 {
2297         /* Address WBINVD may be executed by guest */
2298         if (need_emulate_wbinvd(vcpu)) {
2299                 if (kvm_x86_ops->has_wbinvd_exit())
2300                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2301                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2302                         smp_call_function_single(vcpu->cpu,
2303                                         wbinvd_ipi, NULL, 1);
2304         }
2305
2306         kvm_x86_ops->vcpu_load(vcpu, cpu);
2307
2308         /* Apply any externally detected TSC adjustments (due to suspend) */
2309         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2310                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2311                 vcpu->arch.tsc_offset_adjustment = 0;
2312                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2313         }
2314
2315         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2316                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2317                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2318                 if (tsc_delta < 0)
2319                         mark_tsc_unstable("KVM discovered backwards TSC");
2320                 if (check_tsc_unstable()) {
2321                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2322                                                 vcpu->arch.last_guest_tsc);
2323                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2324                         vcpu->arch.tsc_catchup = 1;
2325                 }
2326                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2327                 if (vcpu->cpu != cpu)
2328                         kvm_migrate_timers(vcpu);
2329                 vcpu->cpu = cpu;
2330         }
2331
2332         accumulate_steal_time(vcpu);
2333         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2334 }
2335
2336 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2337 {
2338         kvm_x86_ops->vcpu_put(vcpu);
2339         kvm_put_guest_fpu(vcpu);
2340         vcpu->arch.last_host_tsc = native_read_tsc();
2341 }
2342
2343 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2344                                     struct kvm_lapic_state *s)
2345 {
2346         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2347
2348         return 0;
2349 }
2350
2351 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2352                                     struct kvm_lapic_state *s)
2353 {
2354         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2355         kvm_apic_post_state_restore(vcpu);
2356         update_cr8_intercept(vcpu);
2357
2358         return 0;
2359 }
2360
2361 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2362                                     struct kvm_interrupt *irq)
2363 {
2364         if (irq->irq < 0 || irq->irq >= 256)
2365                 return -EINVAL;
2366         if (irqchip_in_kernel(vcpu->kvm))
2367                 return -ENXIO;
2368
2369         kvm_queue_interrupt(vcpu, irq->irq, false);
2370         kvm_make_request(KVM_REQ_EVENT, vcpu);
2371
2372         return 0;
2373 }
2374
2375 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2376 {
2377         kvm_inject_nmi(vcpu);
2378
2379         return 0;
2380 }
2381
2382 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2383                                            struct kvm_tpr_access_ctl *tac)
2384 {
2385         if (tac->flags)
2386                 return -EINVAL;
2387         vcpu->arch.tpr_access_reporting = !!tac->enabled;
2388         return 0;
2389 }
2390
2391 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2392                                         u64 mcg_cap)
2393 {
2394         int r;
2395         unsigned bank_num = mcg_cap & 0xff, bank;
2396
2397         r = -EINVAL;
2398         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2399                 goto out;
2400         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2401                 goto out;
2402         r = 0;
2403         vcpu->arch.mcg_cap = mcg_cap;
2404         /* Init IA32_MCG_CTL to all 1s */
2405         if (mcg_cap & MCG_CTL_P)
2406                 vcpu->arch.mcg_ctl = ~(u64)0;
2407         /* Init IA32_MCi_CTL to all 1s */
2408         for (bank = 0; bank < bank_num; bank++)
2409                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2410 out:
2411         return r;
2412 }
2413
2414 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2415                                       struct kvm_x86_mce *mce)
2416 {
2417         u64 mcg_cap = vcpu->arch.mcg_cap;
2418         unsigned bank_num = mcg_cap & 0xff;
2419         u64 *banks = vcpu->arch.mce_banks;
2420
2421         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2422                 return -EINVAL;
2423         /*
2424          * if IA32_MCG_CTL is not all 1s, the uncorrected error
2425          * reporting is disabled
2426          */
2427         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2428             vcpu->arch.mcg_ctl != ~(u64)0)
2429                 return 0;
2430         banks += 4 * mce->bank;
2431         /*
2432          * if IA32_MCi_CTL is not all 1s, the uncorrected error
2433          * reporting is disabled for the bank
2434          */
2435         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2436                 return 0;
2437         if (mce->status & MCI_STATUS_UC) {
2438                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2439                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2440                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2441                         return 0;
2442                 }
2443                 if (banks[1] & MCI_STATUS_VAL)
2444                         mce->status |= MCI_STATUS_OVER;
2445                 banks[2] = mce->addr;
2446                 banks[3] = mce->misc;
2447                 vcpu->arch.mcg_status = mce->mcg_status;
2448                 banks[1] = mce->status;
2449                 kvm_queue_exception(vcpu, MC_VECTOR);
2450         } else if (!(banks[1] & MCI_STATUS_VAL)
2451                    || !(banks[1] & MCI_STATUS_UC)) {
2452                 if (banks[1] & MCI_STATUS_VAL)
2453                         mce->status |= MCI_STATUS_OVER;
2454                 banks[2] = mce->addr;
2455                 banks[3] = mce->misc;
2456                 banks[1] = mce->status;
2457         } else
2458                 banks[1] |= MCI_STATUS_OVER;
2459         return 0;
2460 }
2461
2462 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2463                                                struct kvm_vcpu_events *events)
2464 {
2465         process_nmi(vcpu);
2466         events->exception.injected =
2467                 vcpu->arch.exception.pending &&
2468                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2469         events->exception.nr = vcpu->arch.exception.nr;
2470         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2471         events->exception.pad = 0;
2472         events->exception.error_code = vcpu->arch.exception.error_code;
2473
2474         events->interrupt.injected =
2475                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2476         events->interrupt.nr = vcpu->arch.interrupt.nr;
2477         events->interrupt.soft = 0;
2478         events->interrupt.shadow =
2479                 kvm_x86_ops->get_interrupt_shadow(vcpu,
2480                         KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2481
2482         events->nmi.injected = vcpu->arch.nmi_injected;
2483         events->nmi.pending = vcpu->arch.nmi_pending != 0;
2484         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2485         events->nmi.pad = 0;
2486
2487         events->sipi_vector = vcpu->arch.sipi_vector;
2488
2489         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2490                          | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2491                          | KVM_VCPUEVENT_VALID_SHADOW);
2492         memset(&events->reserved, 0, sizeof(events->reserved));
2493 }
2494
2495 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2496                                               struct kvm_vcpu_events *events)
2497 {
2498         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2499                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2500                               | KVM_VCPUEVENT_VALID_SHADOW))
2501                 return -EINVAL;
2502
2503         process_nmi(vcpu);
2504         vcpu->arch.exception.pending = events->exception.injected;
2505         vcpu->arch.exception.nr = events->exception.nr;
2506         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2507         vcpu->arch.exception.error_code = events->exception.error_code;
2508
2509         vcpu->arch.interrupt.pending = events->interrupt.injected;
2510         vcpu->arch.interrupt.nr = events->interrupt.nr;
2511         vcpu->arch.interrupt.soft = events->interrupt.soft;
2512         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2513                 kvm_x86_ops->set_interrupt_shadow(vcpu,
2514                                                   events->interrupt.shadow);
2515
2516         vcpu->arch.nmi_injected = events->nmi.injected;
2517         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2518                 vcpu->arch.nmi_pending = events->nmi.pending;
2519         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2520
2521         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2522                 vcpu->arch.sipi_vector = events->sipi_vector;
2523
2524         kvm_make_request(KVM_REQ_EVENT, vcpu);
2525
2526         return 0;
2527 }
2528
2529 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2530                                              struct kvm_debugregs *dbgregs)
2531 {
2532         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2533         dbgregs->dr6 = vcpu->arch.dr6;
2534         dbgregs->dr7 = vcpu->arch.dr7;
2535         dbgregs->flags = 0;
2536         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2537 }
2538
2539 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2540                                             struct kvm_debugregs *dbgregs)
2541 {
2542         if (dbgregs->flags)
2543                 return -EINVAL;
2544
2545         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2546         vcpu->arch.dr6 = dbgregs->dr6;
2547         vcpu->arch.dr7 = dbgregs->dr7;
2548
2549         return 0;
2550 }
2551
2552 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2553                                          struct kvm_xsave *guest_xsave)
2554 {
2555         if (cpu_has_xsave)
2556                 memcpy(guest_xsave->region,
2557                         &vcpu->arch.guest_fpu.state->xsave,
2558                         xstate_size);
2559         else {
2560                 memcpy(guest_xsave->region,
2561                         &vcpu->arch.guest_fpu.state->fxsave,
2562                         sizeof(struct i387_fxsave_struct));
2563                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2564                         XSTATE_FPSSE;
2565         }
2566 }
2567
2568 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2569                                         struct kvm_xsave *guest_xsave)
2570 {
2571         u64 xstate_bv =
2572                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2573
2574         if (cpu_has_xsave)
2575                 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2576                         guest_xsave->region, xstate_size);
2577         else {
2578                 if (xstate_bv & ~XSTATE_FPSSE)
2579                         return -EINVAL;
2580                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2581                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
2582         }
2583         return 0;
2584 }
2585
2586 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2587                                         struct kvm_xcrs *guest_xcrs)
2588 {
2589         if (!cpu_has_xsave) {
2590                 guest_xcrs->nr_xcrs = 0;
2591                 return;
2592         }
2593
2594         guest_xcrs->nr_xcrs = 1;
2595         guest_xcrs->flags = 0;
2596         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2597         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2598 }
2599
2600 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2601                                        struct kvm_xcrs *guest_xcrs)
2602 {
2603         int i, r = 0;
2604
2605         if (!cpu_has_xsave)
2606                 return -EINVAL;
2607
2608         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2609                 return -EINVAL;
2610
2611         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2612                 /* Only support XCR0 currently */
2613                 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2614                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2615                                 guest_xcrs->xcrs[0].value);
2616                         break;
2617                 }
2618         if (r)
2619                 r = -EINVAL;
2620         return r;
2621 }
2622
2623 /*
2624  * kvm_set_guest_paused() indicates to the guest kernel that it has been
2625  * stopped by the hypervisor.  This function will be called from the host only.
2626  * EINVAL is returned when the host attempts to set the flag for a guest that
2627  * does not support pv clocks.
2628  */
2629 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2630 {
2631         struct pvclock_vcpu_time_info *src = &vcpu->arch.hv_clock;
2632         if (!vcpu->arch.time_page)
2633                 return -EINVAL;
2634         src->flags |= PVCLOCK_GUEST_STOPPED;
2635         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2636         return 0;
2637 }
2638
2639 long kvm_arch_vcpu_ioctl(struct file *filp,
2640                          unsigned int ioctl, unsigned long arg)
2641 {
2642         struct kvm_vcpu *vcpu = filp->private_data;
2643         void __user *argp = (void __user *)arg;
2644         int r;
2645         union {
2646                 struct kvm_lapic_state *lapic;
2647                 struct kvm_xsave *xsave;
2648                 struct kvm_xcrs *xcrs;
2649                 void *buffer;
2650         } u;
2651
2652         u.buffer = NULL;
2653         switch (ioctl) {
2654         case KVM_GET_LAPIC: {
2655                 r = -EINVAL;
2656                 if (!vcpu->arch.apic)
2657                         goto out;
2658                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2659
2660                 r = -ENOMEM;
2661                 if (!u.lapic)
2662                         goto out;
2663                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2664                 if (r)
2665                         goto out;
2666                 r = -EFAULT;
2667                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2668                         goto out;
2669                 r = 0;
2670                 break;
2671         }
2672         case KVM_SET_LAPIC: {
2673                 r = -EINVAL;
2674                 if (!vcpu->arch.apic)
2675                         goto out;
2676                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2677                 if (IS_ERR(u.lapic)) {
2678                         r = PTR_ERR(u.lapic);
2679                         goto out;
2680                 }
2681
2682                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2683                 if (r)
2684                         goto out;
2685                 r = 0;
2686                 break;
2687         }
2688         case KVM_INTERRUPT: {
2689                 struct kvm_interrupt irq;
2690
2691                 r = -EFAULT;
2692                 if (copy_from_user(&irq, argp, sizeof irq))
2693                         goto out;
2694                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2695                 if (r)
2696                         goto out;
2697                 r = 0;
2698                 break;
2699         }
2700         case KVM_NMI: {
2701                 r = kvm_vcpu_ioctl_nmi(vcpu);
2702                 if (r)
2703                         goto out;
2704                 r = 0;
2705                 break;
2706         }
2707         case KVM_SET_CPUID: {
2708                 struct kvm_cpuid __user *cpuid_arg = argp;
2709                 struct kvm_cpuid cpuid;
2710
2711                 r = -EFAULT;
2712                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2713                         goto out;
2714                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2715                 if (r)
2716                         goto out;
2717                 break;
2718         }
2719         case KVM_SET_CPUID2: {
2720                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2721                 struct kvm_cpuid2 cpuid;
2722
2723                 r = -EFAULT;
2724                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2725                         goto out;
2726                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2727                                               cpuid_arg->entries);
2728                 if (r)
2729                         goto out;
2730                 break;
2731         }
2732         case KVM_GET_CPUID2: {
2733                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2734                 struct kvm_cpuid2 cpuid;
2735
2736                 r = -EFAULT;
2737                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2738                         goto out;
2739                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2740                                               cpuid_arg->entries);
2741                 if (r)
2742                         goto out;
2743                 r = -EFAULT;
2744                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2745                         goto out;
2746                 r = 0;
2747                 break;
2748         }
2749         case KVM_GET_MSRS:
2750                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2751                 break;
2752         case KVM_SET_MSRS:
2753                 r = msr_io(vcpu, argp, do_set_msr, 0);
2754                 break;
2755         case KVM_TPR_ACCESS_REPORTING: {
2756                 struct kvm_tpr_access_ctl tac;
2757
2758                 r = -EFAULT;
2759                 if (copy_from_user(&tac, argp, sizeof tac))
2760                         goto out;
2761                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2762                 if (r)
2763                         goto out;
2764                 r = -EFAULT;
2765                 if (copy_to_user(argp, &tac, sizeof tac))
2766                         goto out;
2767                 r = 0;
2768                 break;
2769         };
2770         case KVM_SET_VAPIC_ADDR: {
2771                 struct kvm_vapic_addr va;
2772
2773                 r = -EINVAL;
2774                 if (!irqchip_in_kernel(vcpu->kvm))
2775                         goto out;
2776                 r = -EFAULT;
2777                 if (copy_from_user(&va, argp, sizeof va))
2778                         goto out;
2779                 r = 0;
2780                 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2781                 break;
2782         }
2783         case KVM_X86_SETUP_MCE: {
2784                 u64 mcg_cap;
2785
2786                 r = -EFAULT;
2787                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2788                         goto out;
2789                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2790                 break;
2791         }
2792         case KVM_X86_SET_MCE: {
2793                 struct kvm_x86_mce mce;
2794
2795                 r = -EFAULT;
2796                 if (copy_from_user(&mce, argp, sizeof mce))
2797                         goto out;
2798                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2799                 break;
2800         }
2801         case KVM_GET_VCPU_EVENTS: {
2802                 struct kvm_vcpu_events events;
2803
2804                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2805
2806                 r = -EFAULT;
2807                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2808                         break;
2809                 r = 0;
2810                 break;
2811         }
2812         case KVM_SET_VCPU_EVENTS: {
2813                 struct kvm_vcpu_events events;
2814
2815                 r = -EFAULT;
2816                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2817                         break;
2818
2819                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2820                 break;
2821         }
2822         case KVM_GET_DEBUGREGS: {
2823                 struct kvm_debugregs dbgregs;
2824
2825                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2826
2827                 r = -EFAULT;
2828                 if (copy_to_user(argp, &dbgregs,
2829                                  sizeof(struct kvm_debugregs)))
2830                         break;
2831                 r = 0;
2832                 break;
2833         }
2834         case KVM_SET_DEBUGREGS: {
2835                 struct kvm_debugregs dbgregs;
2836
2837                 r = -EFAULT;
2838                 if (copy_from_user(&dbgregs, argp,
2839                                    sizeof(struct kvm_debugregs)))
2840                         break;
2841
2842                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2843                 break;
2844         }
2845         case KVM_GET_XSAVE: {
2846                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2847                 r = -ENOMEM;
2848                 if (!u.xsave)
2849                         break;
2850
2851                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2852
2853                 r = -EFAULT;
2854                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2855                         break;
2856                 r = 0;
2857                 break;
2858         }
2859         case KVM_SET_XSAVE: {
2860                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2861                 if (IS_ERR(u.xsave)) {
2862                         r = PTR_ERR(u.xsave);
2863                         goto out;
2864                 }
2865
2866                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2867                 break;
2868         }
2869         case KVM_GET_XCRS: {
2870                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2871                 r = -ENOMEM;
2872                 if (!u.xcrs)
2873                         break;
2874
2875                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2876
2877                 r = -EFAULT;
2878                 if (copy_to_user(argp, u.xcrs,
2879                                  sizeof(struct kvm_xcrs)))
2880                         break;
2881                 r = 0;
2882                 break;
2883         }
2884         case KVM_SET_XCRS: {
2885                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2886                 if (IS_ERR(u.xcrs)) {
2887                         r = PTR_ERR(u.xcrs);
2888                         goto out;
2889                 }
2890
2891                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2892                 break;
2893         }
2894         case KVM_SET_TSC_KHZ: {
2895                 u32 user_tsc_khz;
2896
2897                 r = -EINVAL;
2898                 user_tsc_khz = (u32)arg;
2899
2900                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2901                         goto out;
2902
2903                 if (user_tsc_khz == 0)
2904                         user_tsc_khz = tsc_khz;
2905
2906                 kvm_set_tsc_khz(vcpu, user_tsc_khz);
2907
2908                 r = 0;
2909                 goto out;
2910         }
2911         case KVM_GET_TSC_KHZ: {
2912                 r = vcpu->arch.virtual_tsc_khz;
2913                 goto out;
2914         }
2915         case KVM_KVMCLOCK_CTRL: {
2916                 r = kvm_set_guest_paused(vcpu);
2917                 goto out;
2918         }
2919         default:
2920                 r = -EINVAL;
2921         }
2922 out:
2923         kfree(u.buffer);
2924         return r;
2925 }
2926
2927 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2928 {
2929         return VM_FAULT_SIGBUS;
2930 }
2931
2932 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2933 {
2934         int ret;
2935
2936         if (addr > (unsigned int)(-3 * PAGE_SIZE))
2937                 return -1;
2938         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2939         return ret;
2940 }
2941
2942 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2943                                               u64 ident_addr)
2944 {
2945         kvm->arch.ept_identity_map_addr = ident_addr;
2946         return 0;
2947 }
2948
2949 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2950                                           u32 kvm_nr_mmu_pages)
2951 {
2952         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2953                 return -EINVAL;
2954
2955         mutex_lock(&kvm->slots_lock);
2956         spin_lock(&kvm->mmu_lock);
2957
2958         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2959         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2960
2961         spin_unlock(&kvm->mmu_lock);
2962         mutex_unlock(&kvm->slots_lock);
2963         return 0;
2964 }
2965
2966 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2967 {
2968         return kvm->arch.n_max_mmu_pages;
2969 }
2970
2971 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2972 {
2973         int r;
2974
2975         r = 0;
2976         switch (chip->chip_id) {
2977         case KVM_IRQCHIP_PIC_MASTER:
2978                 memcpy(&chip->chip.pic,
2979                         &pic_irqchip(kvm)->pics[0],
2980                         sizeof(struct kvm_pic_state));
2981                 break;
2982         case KVM_IRQCHIP_PIC_SLAVE:
2983                 memcpy(&chip->chip.pic,
2984                         &pic_irqchip(kvm)->pics[1],
2985                         sizeof(struct kvm_pic_state));
2986                 break;
2987         case KVM_IRQCHIP_IOAPIC:
2988                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
2989                 break;
2990         default:
2991                 r = -EINVAL;
2992                 break;
2993         }
2994         return r;
2995 }
2996
2997 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2998 {
2999         int r;
3000
3001         r = 0;
3002         switch (chip->chip_id) {
3003         case KVM_IRQCHIP_PIC_MASTER:
3004                 spin_lock(&pic_irqchip(kvm)->lock);
3005                 memcpy(&pic_irqchip(kvm)->pics[0],
3006                         &chip->chip.pic,
3007                         sizeof(struct kvm_pic_state));
3008                 spin_unlock(&pic_irqchip(kvm)->lock);
3009                 break;
3010         case KVM_IRQCHIP_PIC_SLAVE:
3011                 spin_lock(&pic_irqchip(kvm)->lock);
3012                 memcpy(&pic_irqchip(kvm)->pics[1],
3013                         &chip->chip.pic,
3014                         sizeof(struct kvm_pic_state));
3015                 spin_unlock(&pic_irqchip(kvm)->lock);
3016                 break;
3017         case KVM_IRQCHIP_IOAPIC:
3018                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3019                 break;
3020         default:
3021                 r = -EINVAL;
3022                 break;
3023         }
3024         kvm_pic_update_irq(pic_irqchip(kvm));
3025         return r;
3026 }
3027
3028 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3029 {
3030         int r = 0;
3031
3032         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3033         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3034         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3035         return r;
3036 }
3037
3038 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3039 {
3040         int r = 0;
3041
3042         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3043         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3044         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3045         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3046         return r;
3047 }
3048
3049 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3050 {
3051         int r = 0;
3052
3053         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3054         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3055                 sizeof(ps->channels));
3056         ps->flags = kvm->arch.vpit->pit_state.flags;
3057         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3058         memset(&ps->reserved, 0, sizeof(ps->reserved));
3059         return r;
3060 }
3061
3062 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3063 {
3064         int r = 0, start = 0;
3065         u32 prev_legacy, cur_legacy;
3066         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3067         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3068         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3069         if (!prev_legacy && cur_legacy)
3070                 start = 1;
3071         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3072                sizeof(kvm->arch.vpit->pit_state.channels));
3073         kvm->arch.vpit->pit_state.flags = ps->flags;
3074         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3075         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3076         return r;
3077 }
3078
3079 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3080                                  struct kvm_reinject_control *control)
3081 {
3082         if (!kvm->arch.vpit)
3083                 return -ENXIO;
3084         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3085         kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3086         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3087         return 0;
3088 }
3089
3090 /**
3091  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3092  * @kvm: kvm instance
3093  * @log: slot id and address to which we copy the log
3094  *
3095  * We need to keep it in mind that VCPU threads can write to the bitmap
3096  * concurrently.  So, to avoid losing data, we keep the following order for
3097  * each bit:
3098  *
3099  *   1. Take a snapshot of the bit and clear it if needed.
3100  *   2. Write protect the corresponding page.
3101  *   3. Flush TLB's if needed.
3102  *   4. Copy the snapshot to the userspace.
3103  *
3104  * Between 2 and 3, the guest may write to the page using the remaining TLB
3105  * entry.  This is not a problem because the page will be reported dirty at
3106  * step 4 using the snapshot taken before and step 3 ensures that successive
3107  * writes will be logged for the next call.
3108  */
3109 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3110 {
3111         int r;
3112         struct kvm_memory_slot *memslot;
3113         unsigned long n, i;
3114         unsigned long *dirty_bitmap;
3115         unsigned long *dirty_bitmap_buffer;
3116         bool is_dirty = false;
3117
3118         mutex_lock(&kvm->slots_lock);
3119
3120         r = -EINVAL;
3121         if (log->slot >= KVM_MEMORY_SLOTS)
3122                 goto out;
3123
3124         memslot = id_to_memslot(kvm->memslots, log->slot);
3125
3126         dirty_bitmap = memslot->dirty_bitmap;
3127         r = -ENOENT;
3128         if (!dirty_bitmap)
3129                 goto out;
3130
3131         n = kvm_dirty_bitmap_bytes(memslot);
3132
3133         dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3134         memset(dirty_bitmap_buffer, 0, n);
3135
3136         spin_lock(&kvm->mmu_lock);
3137
3138         for (i = 0; i < n / sizeof(long); i++) {
3139                 unsigned long mask;
3140                 gfn_t offset;
3141
3142                 if (!dirty_bitmap[i])
3143                         continue;
3144
3145                 is_dirty = true;
3146
3147                 mask = xchg(&dirty_bitmap[i], 0);
3148                 dirty_bitmap_buffer[i] = mask;
3149
3150                 offset = i * BITS_PER_LONG;
3151                 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3152         }
3153         if (is_dirty)
3154                 kvm_flush_remote_tlbs(kvm);
3155
3156         spin_unlock(&kvm->mmu_lock);
3157
3158         r = -EFAULT;
3159         if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3160                 goto out;
3161
3162         r = 0;
3163 out:
3164         mutex_unlock(&kvm->slots_lock);
3165         return r;
3166 }
3167
3168 long kvm_arch_vm_ioctl(struct file *filp,
3169                        unsigned int ioctl, unsigned long arg)
3170 {
3171         struct kvm *kvm = filp->private_data;
3172         void __user *argp = (void __user *)arg;
3173         int r = -ENOTTY;
3174         /*
3175          * This union makes it completely explicit to gcc-3.x
3176          * that these two variables' stack usage should be
3177          * combined, not added together.
3178          */
3179         union {
3180                 struct kvm_pit_state ps;
3181                 struct kvm_pit_state2 ps2;
3182                 struct kvm_pit_config pit_config;
3183         } u;
3184
3185         switch (ioctl) {
3186         case KVM_SET_TSS_ADDR:
3187                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3188                 if (r < 0)
3189                         goto out;
3190                 break;
3191         case KVM_SET_IDENTITY_MAP_ADDR: {
3192                 u64 ident_addr;
3193
3194                 r = -EFAULT;
3195                 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3196                         goto out;
3197                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3198                 if (r < 0)
3199                         goto out;
3200                 break;
3201         }
3202         case KVM_SET_NR_MMU_PAGES:
3203                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3204                 if (r)
3205                         goto out;
3206                 break;
3207         case KVM_GET_NR_MMU_PAGES:
3208                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3209                 break;
3210         case KVM_CREATE_IRQCHIP: {
3211                 struct kvm_pic *vpic;
3212
3213                 mutex_lock(&kvm->lock);
3214                 r = -EEXIST;
3215                 if (kvm->arch.vpic)
3216                         goto create_irqchip_unlock;
3217                 r = -EINVAL;
3218                 if (atomic_read(&kvm->online_vcpus))
3219                         goto create_irqchip_unlock;
3220                 r = -ENOMEM;
3221                 vpic = kvm_create_pic(kvm);
3222                 if (vpic) {
3223                         r = kvm_ioapic_init(kvm);
3224                         if (r) {
3225                                 mutex_lock(&kvm->slots_lock);
3226                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3227                                                           &vpic->dev_master);
3228                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3229                                                           &vpic->dev_slave);
3230                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3231                                                           &vpic->dev_eclr);
3232                                 mutex_unlock(&kvm->slots_lock);
3233                                 kfree(vpic);
3234                                 goto create_irqchip_unlock;
3235                         }
3236                 } else
3237                         goto create_irqchip_unlock;
3238                 smp_wmb();
3239                 kvm->arch.vpic = vpic;
3240                 smp_wmb();
3241                 r = kvm_setup_default_irq_routing(kvm);
3242                 if (r) {
3243                         mutex_lock(&kvm->slots_lock);
3244                         mutex_lock(&kvm->irq_lock);
3245                         kvm_ioapic_destroy(kvm);
3246                         kvm_destroy_pic(kvm);
3247                         mutex_unlock(&kvm->irq_lock);
3248                         mutex_unlock(&kvm->slots_lock);
3249                 }
3250         create_irqchip_unlock:
3251                 mutex_unlock(&kvm->lock);
3252                 break;
3253         }
3254         case KVM_CREATE_PIT:
3255                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3256                 goto create_pit;
3257         case KVM_CREATE_PIT2:
3258                 r = -EFAULT;
3259                 if (copy_from_user(&u.pit_config, argp,
3260                                    sizeof(struct kvm_pit_config)))
3261                         goto out;
3262         create_pit:
3263                 mutex_lock(&kvm->slots_lock);
3264                 r = -EEXIST;
3265                 if (kvm->arch.vpit)
3266                         goto create_pit_unlock;
3267                 r = -ENOMEM;
3268                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3269                 if (kvm->arch.vpit)
3270                         r = 0;
3271         create_pit_unlock:
3272                 mutex_unlock(&kvm->slots_lock);
3273                 break;
3274         case KVM_IRQ_LINE_STATUS:
3275         case KVM_IRQ_LINE: {
3276                 struct kvm_irq_level irq_event;
3277
3278                 r = -EFAULT;
3279                 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3280                         goto out;
3281                 r = -ENXIO;
3282                 if (irqchip_in_kernel(kvm)) {
3283                         __s32 status;
3284                         status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3285                                         irq_event.irq, irq_event.level);
3286                         if (ioctl == KVM_IRQ_LINE_STATUS) {
3287                                 r = -EFAULT;
3288                                 irq_event.status = status;
3289                                 if (copy_to_user(argp, &irq_event,
3290                                                         sizeof irq_event))
3291                                         goto out;
3292                         }
3293                         r = 0;
3294                 }
3295                 break;
3296         }
3297         case KVM_GET_IRQCHIP: {
3298                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3299                 struct kvm_irqchip *chip;
3300
3301                 chip = memdup_user(argp, sizeof(*chip));
3302                 if (IS_ERR(chip)) {
3303                         r = PTR_ERR(chip);
3304                         goto out;
3305                 }
3306
3307                 r = -ENXIO;
3308                 if (!irqchip_in_kernel(kvm))
3309                         goto get_irqchip_out;
3310                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3311                 if (r)
3312                         goto get_irqchip_out;
3313                 r = -EFAULT;
3314                 if (copy_to_user(argp, chip, sizeof *chip))
3315                         goto get_irqchip_out;
3316                 r = 0;
3317         get_irqchip_out:
3318                 kfree(chip);
3319                 if (r)
3320                         goto out;
3321                 break;
3322         }
3323         case KVM_SET_IRQCHIP: {
3324                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3325                 struct kvm_irqchip *chip;
3326
3327                 chip = memdup_user(argp, sizeof(*chip));
3328                 if (IS_ERR(chip)) {
3329                         r = PTR_ERR(chip);
3330                         goto out;
3331                 }
3332
3333                 r = -ENXIO;
3334                 if (!irqchip_in_kernel(kvm))
3335                         goto set_irqchip_out;
3336                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3337                 if (r)
3338                         goto set_irqchip_out;
3339                 r = 0;
3340         set_irqchip_out:
3341                 kfree(chip);
3342                 if (r)
3343                         goto out;
3344                 break;
3345         }
3346         case KVM_GET_PIT: {
3347                 r = -EFAULT;
3348                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3349                         goto out;
3350                 r = -ENXIO;
3351                 if (!kvm->arch.vpit)
3352                         goto out;
3353                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3354                 if (r)
3355                         goto out;
3356                 r = -EFAULT;
3357                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3358                         goto out;
3359                 r = 0;
3360                 break;
3361         }
3362         case KVM_SET_PIT: {
3363                 r = -EFAULT;
3364                 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3365                         goto out;
3366                 r = -ENXIO;
3367                 if (!kvm->arch.vpit)
3368                         goto out;
3369                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3370                 if (r)
3371                         goto out;
3372                 r = 0;
3373                 break;
3374         }
3375         case KVM_GET_PIT2: {
3376                 r = -ENXIO;
3377                 if (!kvm->arch.vpit)
3378                         goto out;
3379                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3380                 if (r)
3381                         goto out;
3382                 r = -EFAULT;
3383                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3384                         goto out;
3385                 r = 0;
3386                 break;
3387         }
3388         case KVM_SET_PIT2: {
3389                 r = -EFAULT;
3390                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3391                         goto out;
3392                 r = -ENXIO;
3393                 if (!kvm->arch.vpit)
3394                         goto out;
3395                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3396                 if (r)
3397                         goto out;
3398                 r = 0;
3399                 break;
3400         }
3401         case KVM_REINJECT_CONTROL: {
3402                 struct kvm_reinject_control control;
3403                 r =  -EFAULT;
3404                 if (copy_from_user(&control, argp, sizeof(control)))
3405                         goto out;
3406                 r = kvm_vm_ioctl_reinject(kvm, &control);
3407                 if (r)
3408                         goto out;
3409                 r = 0;
3410                 break;
3411         }
3412         case KVM_XEN_HVM_CONFIG: {
3413                 r = -EFAULT;
3414                 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3415                                    sizeof(struct kvm_xen_hvm_config)))
3416                         goto out;
3417                 r = -EINVAL;
3418                 if (kvm->arch.xen_hvm_config.flags)
3419                         goto out;
3420                 r = 0;
3421                 break;
3422         }
3423         case KVM_SET_CLOCK: {
3424                 struct kvm_clock_data user_ns;
3425                 u64 now_ns;
3426                 s64 delta;
3427
3428                 r = -EFAULT;
3429                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3430                         goto out;
3431
3432                 r = -EINVAL;
3433                 if (user_ns.flags)
3434                         goto out;
3435
3436                 r = 0;
3437                 local_irq_disable();
3438                 now_ns = get_kernel_ns();
3439                 delta = user_ns.clock - now_ns;
3440                 local_irq_enable();
3441                 kvm->arch.kvmclock_offset = delta;
3442                 break;
3443         }
3444         case KVM_GET_CLOCK: {
3445                 struct kvm_clock_data user_ns;
3446                 u64 now_ns;
3447
3448                 local_irq_disable();
3449                 now_ns = get_kernel_ns();
3450                 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3451                 local_irq_enable();
3452                 user_ns.flags = 0;
3453                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3454
3455                 r = -EFAULT;
3456                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3457                         goto out;
3458                 r = 0;
3459                 break;
3460         }
3461
3462         default:
3463                 ;
3464         }
3465 out:
3466         return r;
3467 }
3468
3469 static void kvm_init_msr_list(void)
3470 {
3471         u32 dummy[2];
3472         unsigned i, j;
3473
3474         /* skip the first msrs in the list. KVM-specific */
3475         for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3476                 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3477                         continue;
3478                 if (j < i)
3479                         msrs_to_save[j] = msrs_to_save[i];
3480                 j++;
3481         }
3482         num_msrs_to_save = j;
3483 }
3484
3485 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3486                            const void *v)
3487 {
3488         int handled = 0;
3489         int n;
3490
3491         do {
3492                 n = min(len, 8);
3493                 if (!(vcpu->arch.apic &&
3494                       !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3495                     && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3496                         break;
3497                 handled += n;
3498                 addr += n;
3499                 len -= n;
3500                 v += n;
3501         } while (len);
3502
3503         return handled;
3504 }
3505
3506 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3507 {
3508         int handled = 0;
3509         int n;
3510
3511         do {
3512                 n = min(len, 8);
3513                 if (!(vcpu->arch.apic &&
3514                       !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3515                     && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3516                         break;
3517                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3518                 handled += n;
3519                 addr += n;
3520                 len -= n;
3521                 v += n;
3522         } while (len);
3523
3524         return handled;
3525 }
3526
3527 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3528                         struct kvm_segment *var, int seg)
3529 {
3530         kvm_x86_ops->set_segment(vcpu, var, seg);
3531 }
3532
3533 void kvm_get_segment(struct kvm_vcpu *vcpu,
3534                      struct kvm_segment *var, int seg)
3535 {
3536         kvm_x86_ops->get_segment(vcpu, var, seg);
3537 }
3538
3539 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3540 {
3541         gpa_t t_gpa;
3542         struct x86_exception exception;
3543
3544         BUG_ON(!mmu_is_nested(vcpu));
3545
3546         /* NPT walks are always user-walks */
3547         access |= PFERR_USER_MASK;
3548         t_gpa  = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3549
3550         return t_gpa;
3551 }
3552
3553 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3554                               struct x86_exception *exception)
3555 {
3556         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3557         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3558 }
3559
3560  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3561                                 struct x86_exception *exception)
3562 {
3563         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3564         access |= PFERR_FETCH_MASK;
3565         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3566 }
3567
3568 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3569                                struct x86_exception *exception)
3570 {
3571         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3572         access |= PFERR_WRITE_MASK;
3573         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3574 }
3575
3576 /* uses this to access any guest's mapped memory without checking CPL */
3577 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3578                                 struct x86_exception *exception)
3579 {
3580         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3581 }
3582
3583 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3584                                       struct kvm_vcpu *vcpu, u32 access,
3585                                       struct x86_exception *exception)
3586 {
3587         void *data = val;
3588         int r = X86EMUL_CONTINUE;
3589
3590         while (bytes) {
3591                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3592                                                             exception);
3593                 unsigned offset = addr & (PAGE_SIZE-1);
3594                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3595                 int ret;
3596
3597                 if (gpa == UNMAPPED_GVA)
3598                         return X86EMUL_PROPAGATE_FAULT;
3599                 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3600                 if (ret < 0) {
3601                         r = X86EMUL_IO_NEEDED;
3602                         goto out;
3603                 }
3604
3605                 bytes -= toread;
3606                 data += toread;
3607                 addr += toread;
3608         }
3609 out:
3610         return r;
3611 }
3612
3613 /* used for instruction fetching */
3614 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3615                                 gva_t addr, void *val, unsigned int bytes,
3616                                 struct x86_exception *exception)
3617 {
3618         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3619         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3620
3621         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3622                                           access | PFERR_FETCH_MASK,
3623                                           exception);
3624 }
3625
3626 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3627                                gva_t addr, void *val, unsigned int bytes,
3628                                struct x86_exception *exception)
3629 {
3630         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3631         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3632
3633         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3634                                           exception);
3635 }
3636 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3637
3638 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3639                                       gva_t addr, void *val, unsigned int bytes,
3640                                       struct x86_exception *exception)
3641 {
3642         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3643         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3644 }
3645
3646 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3647                                        gva_t addr, void *val,
3648                                        unsigned int bytes,
3649                                        struct x86_exception *exception)
3650 {
3651         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3652         void *data = val;
3653         int r = X86EMUL_CONTINUE;
3654
3655         while (bytes) {
3656                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3657                                                              PFERR_WRITE_MASK,
3658                                                              exception);
3659                 unsigned offset = addr & (PAGE_SIZE-1);
3660                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3661                 int ret;
3662
3663                 if (gpa == UNMAPPED_GVA)
3664                         return X86EMUL_PROPAGATE_FAULT;
3665                 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3666                 if (ret < 0) {
3667                         r = X86EMUL_IO_NEEDED;
3668                         goto out;
3669                 }
3670
3671                 bytes -= towrite;
3672                 data += towrite;
3673                 addr += towrite;
3674         }
3675 out:
3676         return r;
3677 }
3678 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3679
3680 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3681                                 gpa_t *gpa, struct x86_exception *exception,
3682                                 bool write)
3683 {
3684         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3685
3686         if (vcpu_match_mmio_gva(vcpu, gva) &&
3687                   check_write_user_access(vcpu, write, access,
3688                   vcpu->arch.access)) {
3689                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3690                                         (gva & (PAGE_SIZE - 1));
3691                 trace_vcpu_match_mmio(gva, *gpa, write, false);
3692                 return 1;
3693         }
3694
3695         if (write)
3696                 access |= PFERR_WRITE_MASK;
3697
3698         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3699
3700         if (*gpa == UNMAPPED_GVA)
3701                 return -1;
3702
3703         /* For APIC access vmexit */
3704         if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3705                 return 1;
3706
3707         if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3708                 trace_vcpu_match_mmio(gva, *gpa, write, true);
3709                 return 1;
3710         }
3711
3712         return 0;
3713 }
3714
3715 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3716                         const void *val, int bytes)
3717 {
3718         int ret;
3719
3720         ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3721         if (ret < 0)
3722                 return 0;
3723         kvm_mmu_pte_write(vcpu, gpa, val, bytes);
3724         return 1;
3725 }
3726
3727 struct read_write_emulator_ops {
3728         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3729                                   int bytes);
3730         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3731                                   void *val, int bytes);
3732         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3733                                int bytes, void *val);
3734         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3735                                     void *val, int bytes);
3736         bool write;
3737 };
3738
3739 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3740 {
3741         if (vcpu->mmio_read_completed) {
3742                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3743                                vcpu->mmio_fragments[0].gpa, *(u64 *)val);
3744                 vcpu->mmio_read_completed = 0;
3745                 return 1;
3746         }
3747
3748         return 0;
3749 }
3750
3751 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3752                         void *val, int bytes)
3753 {
3754         return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3755 }
3756
3757 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3758                          void *val, int bytes)
3759 {
3760         return emulator_write_phys(vcpu, gpa, val, bytes);
3761 }
3762
3763 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3764 {
3765         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3766         return vcpu_mmio_write(vcpu, gpa, bytes, val);
3767 }
3768
3769 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3770                           void *val, int bytes)
3771 {
3772         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3773         return X86EMUL_IO_NEEDED;
3774 }
3775
3776 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3777                            void *val, int bytes)
3778 {
3779         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3780
3781         memcpy(vcpu->run->mmio.data, frag->data, frag->len);
3782         return X86EMUL_CONTINUE;
3783 }
3784
3785 static struct read_write_emulator_ops read_emultor = {
3786         .read_write_prepare = read_prepare,
3787         .read_write_emulate = read_emulate,
3788         .read_write_mmio = vcpu_mmio_read,
3789         .read_write_exit_mmio = read_exit_mmio,
3790 };
3791
3792 static struct read_write_emulator_ops write_emultor = {
3793         .read_write_emulate = write_emulate,
3794         .read_write_mmio = write_mmio,
3795         .read_write_exit_mmio = write_exit_mmio,
3796         .write = true,
3797 };
3798
3799 static int emulator_read_write_onepage(unsigned long addr, void *val,
3800                                        unsigned int bytes,
3801                                        struct x86_exception *exception,
3802                                        struct kvm_vcpu *vcpu,
3803                                        struct read_write_emulator_ops *ops)
3804 {
3805         gpa_t gpa;
3806         int handled, ret;
3807         bool write = ops->write;
3808         struct kvm_mmio_fragment *frag;
3809
3810         ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
3811
3812         if (ret < 0)
3813                 return X86EMUL_PROPAGATE_FAULT;
3814
3815         /* For APIC access vmexit */
3816         if (ret)
3817                 goto mmio;
3818
3819         if (ops->read_write_emulate(vcpu, gpa, val, bytes))
3820                 return X86EMUL_CONTINUE;
3821
3822 mmio:
3823         /*
3824          * Is this MMIO handled locally?
3825          */
3826         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
3827         if (handled == bytes)
3828                 return X86EMUL_CONTINUE;
3829
3830         gpa += handled;
3831         bytes -= handled;
3832         val += handled;
3833
3834         while (bytes) {
3835                 unsigned now = min(bytes, 8U);
3836
3837                 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3838                 frag->gpa = gpa;
3839                 frag->data = val;
3840                 frag->len = now;
3841
3842                 gpa += now;
3843                 val += now;
3844                 bytes -= now;
3845         }
3846         return X86EMUL_CONTINUE;
3847 }
3848
3849 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3850                         void *val, unsigned int bytes,
3851                         struct x86_exception *exception,
3852                         struct read_write_emulator_ops *ops)
3853 {
3854         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3855         gpa_t gpa;
3856         int rc;
3857
3858         if (ops->read_write_prepare &&
3859                   ops->read_write_prepare(vcpu, val, bytes))
3860                 return X86EMUL_CONTINUE;
3861
3862         vcpu->mmio_nr_fragments = 0;
3863
3864         /* Crossing a page boundary? */
3865         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3866                 int now;
3867
3868                 now = -addr & ~PAGE_MASK;
3869                 rc = emulator_read_write_onepage(addr, val, now, exception,
3870                                                  vcpu, ops);
3871
3872                 if (rc != X86EMUL_CONTINUE)
3873                         return rc;
3874                 addr += now;
3875                 val += now;
3876                 bytes -= now;
3877         }
3878
3879         rc = emulator_read_write_onepage(addr, val, bytes, exception,
3880                                          vcpu, ops);
3881         if (rc != X86EMUL_CONTINUE)
3882                 return rc;
3883
3884         if (!vcpu->mmio_nr_fragments)
3885                 return rc;
3886
3887         gpa = vcpu->mmio_fragments[0].gpa;
3888
3889         vcpu->mmio_needed = 1;
3890         vcpu->mmio_cur_fragment = 0;
3891
3892         vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3893         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3894         vcpu->run->exit_reason = KVM_EXIT_MMIO;
3895         vcpu->run->mmio.phys_addr = gpa;
3896
3897         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
3898 }
3899
3900 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3901                                   unsigned long addr,
3902                                   void *val,
3903                                   unsigned int bytes,
3904                                   struct x86_exception *exception)
3905 {
3906         return emulator_read_write(ctxt, addr, val, bytes,
3907                                    exception, &read_emultor);
3908 }
3909
3910 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3911                             unsigned long addr,
3912                             const void *val,
3913                             unsigned int bytes,
3914                             struct x86_exception *exception)
3915 {
3916         return emulator_read_write(ctxt, addr, (void *)val, bytes,
3917                                    exception, &write_emultor);
3918 }
3919
3920 #define CMPXCHG_TYPE(t, ptr, old, new) \
3921         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3922
3923 #ifdef CONFIG_X86_64
3924 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3925 #else
3926 #  define CMPXCHG64(ptr, old, new) \
3927         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3928 #endif
3929
3930 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3931                                      unsigned long addr,
3932                                      const void *old,
3933                                      const void *new,
3934                                      unsigned int bytes,
3935                                      struct x86_exception *exception)
3936 {
3937         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3938         gpa_t gpa;
3939         struct page *page;
3940         char *kaddr;
3941         bool exchanged;
3942
3943         /* guests cmpxchg8b have to be emulated atomically */
3944         if (bytes > 8 || (bytes & (bytes - 1)))
3945                 goto emul_write;
3946
3947         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3948
3949         if (gpa == UNMAPPED_GVA ||
3950             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3951                 goto emul_write;
3952
3953         if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3954                 goto emul_write;
3955
3956         page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3957         if (is_error_page(page)) {
3958                 kvm_release_page_clean(page);
3959                 goto emul_write;
3960         }
3961
3962         kaddr = kmap_atomic(page);
3963         kaddr += offset_in_page(gpa);
3964         switch (bytes) {
3965         case 1:
3966                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3967                 break;
3968         case 2:
3969                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3970                 break;
3971         case 4:
3972                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3973                 break;
3974         case 8:
3975                 exchanged = CMPXCHG64(kaddr, old, new);
3976                 break;
3977         default:
3978                 BUG();
3979         }
3980         kunmap_atomic(kaddr);
3981         kvm_release_page_dirty(page);
3982
3983         if (!exchanged)
3984                 return X86EMUL_CMPXCHG_FAILED;
3985
3986         kvm_mmu_pte_write(vcpu, gpa, new, bytes);
3987
3988         return X86EMUL_CONTINUE;
3989
3990 emul_write:
3991         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3992
3993         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
3994 }
3995
3996 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3997 {
3998         /* TODO: String I/O for in kernel device */
3999         int r;
4000
4001         if (vcpu->arch.pio.in)
4002                 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4003                                     vcpu->arch.pio.size, pd);
4004         else
4005                 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4006                                      vcpu->arch.pio.port, vcpu->arch.pio.size,
4007                                      pd);
4008         return r;
4009 }
4010
4011 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4012                                unsigned short port, void *val,
4013                                unsigned int count, bool in)
4014 {
4015         trace_kvm_pio(!in, port, size, count);
4016
4017         vcpu->arch.pio.port = port;
4018         vcpu->arch.pio.in = in;
4019         vcpu->arch.pio.count  = count;
4020         vcpu->arch.pio.size = size;
4021
4022         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4023                 vcpu->arch.pio.count = 0;
4024                 return 1;
4025         }
4026
4027         vcpu->run->exit_reason = KVM_EXIT_IO;
4028         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4029         vcpu->run->io.size = size;
4030         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4031         vcpu->run->io.count = count;
4032         vcpu->run->io.port = port;
4033
4034         return 0;
4035 }
4036
4037 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4038                                     int size, unsigned short port, void *val,
4039                                     unsigned int count)
4040 {
4041         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4042         int ret;
4043
4044         if (vcpu->arch.pio.count)
4045                 goto data_avail;
4046
4047         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4048         if (ret) {
4049 data_avail:
4050                 memcpy(val, vcpu->arch.pio_data, size * count);
4051                 vcpu->arch.pio.count = 0;
4052                 return 1;
4053         }
4054
4055         return 0;
4056 }
4057
4058 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4059                                      int size, unsigned short port,
4060                                      const void *val, unsigned int count)
4061 {
4062         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4063
4064         memcpy(vcpu->arch.pio_data, val, size * count);
4065         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4066 }
4067
4068 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4069 {
4070         return kvm_x86_ops->get_segment_base(vcpu, seg);
4071 }
4072
4073 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4074 {
4075         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4076 }
4077
4078 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4079 {
4080         if (!need_emulate_wbinvd(vcpu))
4081                 return X86EMUL_CONTINUE;
4082
4083         if (kvm_x86_ops->has_wbinvd_exit()) {
4084                 int cpu = get_cpu();
4085
4086                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4087                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4088                                 wbinvd_ipi, NULL, 1);
4089                 put_cpu();
4090                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4091         } else
4092                 wbinvd();
4093         return X86EMUL_CONTINUE;
4094 }
4095 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4096
4097 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4098 {
4099         kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4100 }
4101
4102 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4103 {
4104         return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4105 }
4106
4107 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4108 {
4109
4110         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4111 }
4112
4113 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4114 {
4115         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4116 }
4117
4118 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4119 {
4120         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4121         unsigned long value;
4122
4123         switch (cr) {
4124         case 0:
4125                 value = kvm_read_cr0(vcpu);
4126                 break;
4127         case 2:
4128                 value = vcpu->arch.cr2;
4129                 break;
4130         case 3:
4131                 value = kvm_read_cr3(vcpu);
4132                 break;
4133         case 4:
4134                 value = kvm_read_cr4(vcpu);
4135                 break;
4136         case 8:
4137                 value = kvm_get_cr8(vcpu);
4138                 break;
4139         default:
4140                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4141                 return 0;
4142         }
4143
4144         return value;
4145 }
4146
4147 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4148 {
4149         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4150         int res = 0;
4151
4152         switch (cr) {
4153         case 0:
4154                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4155                 break;
4156         case 2:
4157                 vcpu->arch.cr2 = val;
4158                 break;
4159         case 3:
4160                 res = kvm_set_cr3(vcpu, val);
4161                 break;
4162         case 4:
4163                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4164                 break;
4165         case 8:
4166                 res = kvm_set_cr8(vcpu, val);
4167                 break;
4168         default:
4169                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4170                 res = -1;
4171         }
4172
4173         return res;
4174 }
4175
4176 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4177 {
4178         kvm_set_rflags(emul_to_vcpu(ctxt), val);
4179 }
4180
4181 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4182 {
4183         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4184 }
4185
4186 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4187 {
4188         kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4189 }
4190
4191 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4192 {
4193         kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4194 }
4195
4196 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4197 {
4198         kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4199 }
4200
4201 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4202 {
4203         kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4204 }
4205
4206 static unsigned long emulator_get_cached_segment_base(
4207         struct x86_emulate_ctxt *ctxt, int seg)
4208 {
4209         return get_segment_base(emul_to_vcpu(ctxt), seg);
4210 }
4211
4212 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4213                                  struct desc_struct *desc, u32 *base3,
4214                                  int seg)
4215 {
4216         struct kvm_segment var;
4217
4218         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4219         *selector = var.selector;
4220
4221         if (var.unusable)
4222                 return false;
4223
4224         if (var.g)
4225                 var.limit >>= 12;
4226         set_desc_limit(desc, var.limit);
4227         set_desc_base(desc, (unsigned long)var.base);
4228 #ifdef CONFIG_X86_64
4229         if (base3)
4230                 *base3 = var.base >> 32;
4231 #endif
4232         desc->type = var.type;
4233         desc->s = var.s;
4234         desc->dpl = var.dpl;
4235         desc->p = var.present;
4236         desc->avl = var.avl;
4237         desc->l = var.l;
4238         desc->d = var.db;
4239         desc->g = var.g;
4240
4241         return true;
4242 }
4243
4244 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4245                                  struct desc_struct *desc, u32 base3,
4246                                  int seg)
4247 {
4248         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4249         struct kvm_segment var;
4250
4251         var.selector = selector;
4252         var.base = get_desc_base(desc);
4253 #ifdef CONFIG_X86_64
4254         var.base |= ((u64)base3) << 32;
4255 #endif
4256         var.limit = get_desc_limit(desc);
4257         if (desc->g)
4258                 var.limit = (var.limit << 12) | 0xfff;
4259         var.type = desc->type;
4260         var.present = desc->p;
4261         var.dpl = desc->dpl;
4262         var.db = desc->d;
4263         var.s = desc->s;
4264         var.l = desc->l;
4265         var.g = desc->g;
4266         var.avl = desc->avl;
4267         var.present = desc->p;
4268         var.unusable = !var.present;
4269         var.padding = 0;
4270
4271         kvm_set_segment(vcpu, &var, seg);
4272         return;
4273 }
4274
4275 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4276                             u32 msr_index, u64 *pdata)
4277 {
4278         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4279 }
4280
4281 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4282                             u32 msr_index, u64 data)
4283 {
4284         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4285 }
4286
4287 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4288                              u32 pmc, u64 *pdata)
4289 {
4290         return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4291 }
4292
4293 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4294 {
4295         emul_to_vcpu(ctxt)->arch.halt_request = 1;
4296 }
4297
4298 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4299 {
4300         preempt_disable();
4301         kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4302         /*
4303          * CR0.TS may reference the host fpu state, not the guest fpu state,
4304          * so it may be clear at this point.
4305          */
4306         clts();
4307 }
4308
4309 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4310 {
4311         preempt_enable();
4312 }
4313
4314 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4315                               struct x86_instruction_info *info,
4316                               enum x86_intercept_stage stage)
4317 {
4318         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4319 }
4320
4321 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4322                                u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4323 {
4324         kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4325 }
4326
4327 static struct x86_emulate_ops emulate_ops = {
4328         .read_std            = kvm_read_guest_virt_system,
4329         .write_std           = kvm_write_guest_virt_system,
4330         .fetch               = kvm_fetch_guest_virt,
4331         .read_emulated       = emulator_read_emulated,
4332         .write_emulated      = emulator_write_emulated,
4333         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
4334         .invlpg              = emulator_invlpg,
4335         .pio_in_emulated     = emulator_pio_in_emulated,
4336         .pio_out_emulated    = emulator_pio_out_emulated,
4337         .get_segment         = emulator_get_segment,
4338         .set_segment         = emulator_set_segment,
4339         .get_cached_segment_base = emulator_get_cached_segment_base,
4340         .get_gdt             = emulator_get_gdt,
4341         .get_idt             = emulator_get_idt,
4342         .set_gdt             = emulator_set_gdt,
4343         .set_idt             = emulator_set_idt,
4344         .get_cr              = emulator_get_cr,
4345         .set_cr              = emulator_set_cr,
4346         .set_rflags          = emulator_set_rflags,
4347         .cpl                 = emulator_get_cpl,
4348         .get_dr              = emulator_get_dr,
4349         .set_dr              = emulator_set_dr,
4350         .set_msr             = emulator_set_msr,
4351         .get_msr             = emulator_get_msr,
4352         .read_pmc            = emulator_read_pmc,
4353         .halt                = emulator_halt,
4354         .wbinvd              = emulator_wbinvd,
4355         .fix_hypercall       = emulator_fix_hypercall,
4356         .get_fpu             = emulator_get_fpu,
4357         .put_fpu             = emulator_put_fpu,
4358         .intercept           = emulator_intercept,
4359         .get_cpuid           = emulator_get_cpuid,
4360 };
4361
4362 static void cache_all_regs(struct kvm_vcpu *vcpu)
4363 {
4364         kvm_register_read(vcpu, VCPU_REGS_RAX);
4365         kvm_register_read(vcpu, VCPU_REGS_RSP);
4366         kvm_register_read(vcpu, VCPU_REGS_RIP);
4367         vcpu->arch.regs_dirty = ~0;
4368 }
4369
4370 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4371 {
4372         u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4373         /*
4374          * an sti; sti; sequence only disable interrupts for the first
4375          * instruction. So, if the last instruction, be it emulated or
4376          * not, left the system with the INT_STI flag enabled, it
4377          * means that the last instruction is an sti. We should not
4378          * leave the flag on in this case. The same goes for mov ss
4379          */
4380         if (!(int_shadow & mask))
4381                 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4382 }
4383
4384 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4385 {
4386         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4387         if (ctxt->exception.vector == PF_VECTOR)
4388                 kvm_propagate_fault(vcpu, &ctxt->exception);
4389         else if (ctxt->exception.error_code_valid)
4390                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4391                                       ctxt->exception.error_code);
4392         else
4393                 kvm_queue_exception(vcpu, ctxt->exception.vector);
4394 }
4395
4396 static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
4397                               const unsigned long *regs)
4398 {
4399         memset(&ctxt->twobyte, 0,
4400                (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4401         memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
4402
4403         ctxt->fetch.start = 0;
4404         ctxt->fetch.end = 0;
4405         ctxt->io_read.pos = 0;
4406         ctxt->io_read.end = 0;
4407         ctxt->mem_read.pos = 0;
4408         ctxt->mem_read.end = 0;
4409 }
4410
4411 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4412 {
4413         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4414         int cs_db, cs_l;
4415
4416         /*
4417          * TODO: fix emulate.c to use guest_read/write_register
4418          * instead of direct ->regs accesses, can save hundred cycles
4419          * on Intel for instructions that don't read/change RSP, for
4420          * for example.
4421          */
4422         cache_all_regs(vcpu);
4423
4424         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4425
4426         ctxt->eflags = kvm_get_rflags(vcpu);
4427         ctxt->eip = kvm_rip_read(vcpu);
4428         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
4429                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
4430                      cs_l                               ? X86EMUL_MODE_PROT64 :
4431                      cs_db                              ? X86EMUL_MODE_PROT32 :
4432                                                           X86EMUL_MODE_PROT16;
4433         ctxt->guest_mode = is_guest_mode(vcpu);
4434
4435         init_decode_cache(ctxt, vcpu->arch.regs);
4436         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4437 }
4438
4439 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4440 {
4441         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4442         int ret;
4443
4444         init_emulate_ctxt(vcpu);
4445
4446         ctxt->op_bytes = 2;
4447         ctxt->ad_bytes = 2;
4448         ctxt->_eip = ctxt->eip + inc_eip;
4449         ret = emulate_int_real(ctxt, irq);
4450
4451         if (ret != X86EMUL_CONTINUE)
4452                 return EMULATE_FAIL;
4453
4454         ctxt->eip = ctxt->_eip;
4455         memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4456         kvm_rip_write(vcpu, ctxt->eip);
4457         kvm_set_rflags(vcpu, ctxt->eflags);
4458
4459         if (irq == NMI_VECTOR)
4460                 vcpu->arch.nmi_pending = 0;
4461         else
4462                 vcpu->arch.interrupt.pending = false;
4463
4464         return EMULATE_DONE;
4465 }
4466 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4467
4468 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4469 {
4470         int r = EMULATE_DONE;
4471
4472         ++vcpu->stat.insn_emulation_fail;
4473         trace_kvm_emulate_insn_failed(vcpu);
4474         if (!is_guest_mode(vcpu)) {
4475                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4476                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4477                 vcpu->run->internal.ndata = 0;
4478                 r = EMULATE_FAIL;
4479         }
4480         kvm_queue_exception(vcpu, UD_VECTOR);
4481
4482         return r;
4483 }
4484
4485 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4486 {
4487         gpa_t gpa;
4488
4489         if (tdp_enabled)
4490                 return false;
4491
4492         /*
4493          * if emulation was due to access to shadowed page table
4494          * and it failed try to unshadow page and re-enter the
4495          * guest to let CPU execute the instruction.
4496          */
4497         if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4498                 return true;
4499
4500         gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4501
4502         if (gpa == UNMAPPED_GVA)
4503                 return true; /* let cpu generate fault */
4504
4505         if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4506                 return true;
4507
4508         return false;
4509 }
4510
4511 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4512                               unsigned long cr2,  int emulation_type)
4513 {
4514         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4515         unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4516
4517         last_retry_eip = vcpu->arch.last_retry_eip;
4518         last_retry_addr = vcpu->arch.last_retry_addr;
4519
4520         /*
4521          * If the emulation is caused by #PF and it is non-page_table
4522          * writing instruction, it means the VM-EXIT is caused by shadow
4523          * page protected, we can zap the shadow page and retry this
4524          * instruction directly.
4525          *
4526          * Note: if the guest uses a non-page-table modifying instruction
4527          * on the PDE that points to the instruction, then we will unmap
4528          * the instruction and go to an infinite loop. So, we cache the
4529          * last retried eip and the last fault address, if we meet the eip
4530          * and the address again, we can break out of the potential infinite
4531          * loop.
4532          */
4533         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4534
4535         if (!(emulation_type & EMULTYPE_RETRY))
4536                 return false;
4537
4538         if (x86_page_table_writing_insn(ctxt))
4539                 return false;
4540
4541         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4542                 return false;
4543
4544         vcpu->arch.last_retry_eip = ctxt->eip;
4545         vcpu->arch.last_retry_addr = cr2;
4546
4547         if (!vcpu->arch.mmu.direct_map)
4548                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4549
4550         kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4551
4552         return true;
4553 }
4554
4555 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4556                             unsigned long cr2,
4557                             int emulation_type,
4558                             void *insn,
4559                             int insn_len)
4560 {
4561         int r;
4562         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4563         bool writeback = true;
4564
4565         kvm_clear_exception_queue(vcpu);
4566
4567         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4568                 init_emulate_ctxt(vcpu);
4569                 ctxt->interruptibility = 0;
4570                 ctxt->have_exception = false;
4571                 ctxt->perm_ok = false;
4572
4573                 ctxt->only_vendor_specific_insn
4574                         = emulation_type & EMULTYPE_TRAP_UD;
4575
4576                 r = x86_decode_insn(ctxt, insn, insn_len);
4577
4578                 trace_kvm_emulate_insn_start(vcpu);
4579                 ++vcpu->stat.insn_emulation;
4580                 if (r != EMULATION_OK)  {
4581                         if (emulation_type & EMULTYPE_TRAP_UD)
4582                                 return EMULATE_FAIL;
4583                         if (reexecute_instruction(vcpu, cr2))
4584                                 return EMULATE_DONE;
4585                         if (emulation_type & EMULTYPE_SKIP)
4586                                 return EMULATE_FAIL;
4587                         return handle_emulation_failure(vcpu);
4588                 }
4589         }
4590
4591         if (emulation_type & EMULTYPE_SKIP) {
4592                 kvm_rip_write(vcpu, ctxt->_eip);
4593                 return EMULATE_DONE;
4594         }
4595
4596         if (retry_instruction(ctxt, cr2, emulation_type))
4597                 return EMULATE_DONE;
4598
4599         /* this is needed for vmware backdoor interface to work since it
4600            changes registers values  during IO operation */
4601         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4602                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4603                 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
4604         }
4605
4606 restart:
4607         r = x86_emulate_insn(ctxt);
4608
4609         if (r == EMULATION_INTERCEPTED)
4610                 return EMULATE_DONE;
4611
4612         if (r == EMULATION_FAILED) {
4613                 if (reexecute_instruction(vcpu, cr2))
4614                         return EMULATE_DONE;
4615
4616                 return handle_emulation_failure(vcpu);
4617         }
4618
4619         if (ctxt->have_exception) {
4620                 inject_emulated_exception(vcpu);
4621                 r = EMULATE_DONE;
4622         } else if (vcpu->arch.pio.count) {
4623                 if (!vcpu->arch.pio.in)
4624                         vcpu->arch.pio.count = 0;
4625                 else
4626                         writeback = false;
4627                 r = EMULATE_DO_MMIO;
4628         } else if (vcpu->mmio_needed) {
4629                 if (!vcpu->mmio_is_write)
4630                         writeback = false;
4631                 r = EMULATE_DO_MMIO;
4632         } else if (r == EMULATION_RESTART)
4633                 goto restart;
4634         else
4635                 r = EMULATE_DONE;
4636
4637         if (writeback) {
4638                 toggle_interruptibility(vcpu, ctxt->interruptibility);
4639                 kvm_set_rflags(vcpu, ctxt->eflags);
4640                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4641                 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4642                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4643                 kvm_rip_write(vcpu, ctxt->eip);
4644         } else
4645                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4646
4647         return r;
4648 }
4649 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4650
4651 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4652 {
4653         unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4654         int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4655                                             size, port, &val, 1);
4656         /* do not return to emulator after return from userspace */
4657         vcpu->arch.pio.count = 0;
4658         return ret;
4659 }
4660 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4661
4662 static void tsc_bad(void *info)
4663 {
4664         __this_cpu_write(cpu_tsc_khz, 0);
4665 }
4666
4667 static void tsc_khz_changed(void *data)
4668 {
4669         struct cpufreq_freqs *freq = data;
4670         unsigned long khz = 0;
4671
4672         if (data)
4673                 khz = freq->new;
4674         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4675                 khz = cpufreq_quick_get(raw_smp_processor_id());
4676         if (!khz)
4677                 khz = tsc_khz;
4678         __this_cpu_write(cpu_tsc_khz, khz);
4679 }
4680
4681 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4682                                      void *data)
4683 {
4684         struct cpufreq_freqs *freq = data;
4685         struct kvm *kvm;
4686         struct kvm_vcpu *vcpu;
4687         int i, send_ipi = 0;
4688
4689         /*
4690          * We allow guests to temporarily run on slowing clocks,
4691          * provided we notify them after, or to run on accelerating
4692          * clocks, provided we notify them before.  Thus time never
4693          * goes backwards.
4694          *
4695          * However, we have a problem.  We can't atomically update
4696          * the frequency of a given CPU from this function; it is
4697          * merely a notifier, which can be called from any CPU.
4698          * Changing the TSC frequency at arbitrary points in time
4699          * requires a recomputation of local variables related to
4700          * the TSC for each VCPU.  We must flag these local variables
4701          * to be updated and be sure the update takes place with the
4702          * new frequency before any guests proceed.
4703          *
4704          * Unfortunately, the combination of hotplug CPU and frequency
4705          * change creates an intractable locking scenario; the order
4706          * of when these callouts happen is undefined with respect to
4707          * CPU hotplug, and they can race with each other.  As such,
4708          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4709          * undefined; you can actually have a CPU frequency change take
4710          * place in between the computation of X and the setting of the
4711          * variable.  To protect against this problem, all updates of
4712          * the per_cpu tsc_khz variable are done in an interrupt
4713          * protected IPI, and all callers wishing to update the value
4714          * must wait for a synchronous IPI to complete (which is trivial
4715          * if the caller is on the CPU already).  This establishes the
4716          * necessary total order on variable updates.
4717          *
4718          * Note that because a guest time update may take place
4719          * anytime after the setting of the VCPU's request bit, the
4720          * correct TSC value must be set before the request.  However,
4721          * to ensure the update actually makes it to any guest which
4722          * starts running in hardware virtualization between the set
4723          * and the acquisition of the spinlock, we must also ping the
4724          * CPU after setting the request bit.
4725          *
4726          */
4727
4728         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4729                 return 0;
4730         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4731                 return 0;
4732
4733         smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4734
4735         raw_spin_lock(&kvm_lock);
4736         list_for_each_entry(kvm, &vm_list, vm_list) {
4737                 kvm_for_each_vcpu(i, vcpu, kvm) {
4738                         if (vcpu->cpu != freq->cpu)
4739                                 continue;
4740                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4741                         if (vcpu->cpu != smp_processor_id())
4742                                 send_ipi = 1;
4743                 }
4744         }
4745         raw_spin_unlock(&kvm_lock);
4746
4747         if (freq->old < freq->new && send_ipi) {
4748                 /*
4749                  * We upscale the frequency.  Must make the guest
4750                  * doesn't see old kvmclock values while running with
4751                  * the new frequency, otherwise we risk the guest sees
4752                  * time go backwards.
4753                  *
4754                  * In case we update the frequency for another cpu
4755                  * (which might be in guest context) send an interrupt
4756                  * to kick the cpu out of guest context.  Next time
4757                  * guest context is entered kvmclock will be updated,
4758                  * so the guest will not see stale values.
4759                  */
4760                 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4761         }
4762         return 0;
4763 }
4764
4765 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4766         .notifier_call  = kvmclock_cpufreq_notifier
4767 };
4768
4769 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4770                                         unsigned long action, void *hcpu)
4771 {
4772         unsigned int cpu = (unsigned long)hcpu;
4773
4774         switch (action) {
4775                 case CPU_ONLINE:
4776                 case CPU_DOWN_FAILED:
4777                         smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4778                         break;
4779                 case CPU_DOWN_PREPARE:
4780                         smp_call_function_single(cpu, tsc_bad, NULL, 1);
4781                         break;
4782         }
4783         return NOTIFY_OK;
4784 }
4785
4786 static struct notifier_block kvmclock_cpu_notifier_block = {
4787         .notifier_call  = kvmclock_cpu_notifier,
4788         .priority = -INT_MAX
4789 };
4790
4791 static void kvm_timer_init(void)
4792 {
4793         int cpu;
4794
4795         max_tsc_khz = tsc_khz;
4796         register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4797         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4798 #ifdef CONFIG_CPU_FREQ
4799                 struct cpufreq_policy policy;
4800                 memset(&policy, 0, sizeof(policy));
4801                 cpu = get_cpu();
4802                 cpufreq_get_policy(&policy, cpu);
4803                 if (policy.cpuinfo.max_freq)
4804                         max_tsc_khz = policy.cpuinfo.max_freq;
4805                 put_cpu();
4806 #endif
4807                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4808                                           CPUFREQ_TRANSITION_NOTIFIER);
4809         }
4810         pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
4811         for_each_online_cpu(cpu)
4812                 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4813 }
4814
4815 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4816
4817 int kvm_is_in_guest(void)
4818 {
4819         return __this_cpu_read(current_vcpu) != NULL;
4820 }
4821
4822 static int kvm_is_user_mode(void)
4823 {
4824         int user_mode = 3;
4825
4826         if (__this_cpu_read(current_vcpu))
4827                 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
4828
4829         return user_mode != 0;
4830 }
4831
4832 static unsigned long kvm_get_guest_ip(void)
4833 {
4834         unsigned long ip = 0;
4835
4836         if (__this_cpu_read(current_vcpu))
4837                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
4838
4839         return ip;
4840 }
4841
4842 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4843         .is_in_guest            = kvm_is_in_guest,
4844         .is_user_mode           = kvm_is_user_mode,
4845         .get_guest_ip           = kvm_get_guest_ip,
4846 };
4847
4848 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4849 {
4850         __this_cpu_write(current_vcpu, vcpu);
4851 }
4852 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4853
4854 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4855 {
4856         __this_cpu_write(current_vcpu, NULL);
4857 }
4858 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4859
4860 static void kvm_set_mmio_spte_mask(void)
4861 {
4862         u64 mask;
4863         int maxphyaddr = boot_cpu_data.x86_phys_bits;
4864
4865         /*
4866          * Set the reserved bits and the present bit of an paging-structure
4867          * entry to generate page fault with PFER.RSV = 1.
4868          */
4869         mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4870         mask |= 1ull;
4871
4872 #ifdef CONFIG_X86_64
4873         /*
4874          * If reserved bit is not supported, clear the present bit to disable
4875          * mmio page fault.
4876          */
4877         if (maxphyaddr == 52)
4878                 mask &= ~1ull;
4879 #endif
4880
4881         kvm_mmu_set_mmio_spte_mask(mask);
4882 }
4883
4884 int kvm_arch_init(void *opaque)
4885 {
4886         int r;
4887         struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4888
4889         if (kvm_x86_ops) {
4890                 printk(KERN_ERR "kvm: already loaded the other module\n");
4891                 r = -EEXIST;
4892                 goto out;
4893         }
4894
4895         if (!ops->cpu_has_kvm_support()) {
4896                 printk(KERN_ERR "kvm: no hardware support\n");
4897                 r = -EOPNOTSUPP;
4898                 goto out;
4899         }
4900         if (ops->disabled_by_bios()) {
4901                 printk(KERN_ERR "kvm: disabled by bios\n");
4902                 r = -EOPNOTSUPP;
4903                 goto out;
4904         }
4905
4906         r = kvm_mmu_module_init();
4907         if (r)
4908                 goto out;
4909
4910         kvm_set_mmio_spte_mask();
4911         kvm_init_msr_list();
4912
4913         kvm_x86_ops = ops;
4914         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4915                         PT_DIRTY_MASK, PT64_NX_MASK, 0);
4916
4917         kvm_timer_init();
4918
4919         perf_register_guest_info_callbacks(&kvm_guest_cbs);
4920
4921         if (cpu_has_xsave)
4922                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4923
4924         return 0;
4925
4926 out:
4927         return r;
4928 }
4929
4930 void kvm_arch_exit(void)
4931 {
4932         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4933
4934         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4935                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4936                                             CPUFREQ_TRANSITION_NOTIFIER);
4937         unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4938         kvm_x86_ops = NULL;
4939         kvm_mmu_module_exit();
4940 }
4941
4942 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4943 {
4944         ++vcpu->stat.halt_exits;
4945         if (irqchip_in_kernel(vcpu->kvm)) {
4946                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4947                 return 1;
4948         } else {
4949                 vcpu->run->exit_reason = KVM_EXIT_HLT;
4950                 return 0;
4951         }
4952 }
4953 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4954
4955 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4956 {
4957         u64 param, ingpa, outgpa, ret;
4958         uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4959         bool fast, longmode;
4960         int cs_db, cs_l;
4961
4962         /*
4963          * hypercall generates UD from non zero cpl and real mode
4964          * per HYPER-V spec
4965          */
4966         if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4967                 kvm_queue_exception(vcpu, UD_VECTOR);
4968                 return 0;
4969         }
4970
4971         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4972         longmode = is_long_mode(vcpu) && cs_l == 1;
4973
4974         if (!longmode) {
4975                 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4976                         (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4977                 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4978                         (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4979                 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4980                         (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4981         }
4982 #ifdef CONFIG_X86_64
4983         else {
4984                 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4985                 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4986                 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4987         }
4988 #endif
4989
4990         code = param & 0xffff;
4991         fast = (param >> 16) & 0x1;
4992         rep_cnt = (param >> 32) & 0xfff;
4993         rep_idx = (param >> 48) & 0xfff;
4994
4995         trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4996
4997         switch (code) {
4998         case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4999                 kvm_vcpu_on_spin(vcpu);
5000                 break;
5001         default:
5002                 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5003                 break;
5004         }
5005
5006         ret = res | (((u64)rep_done & 0xfff) << 32);
5007         if (longmode) {
5008                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5009         } else {
5010                 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5011                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5012         }
5013
5014         return 1;
5015 }
5016
5017 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5018 {
5019         unsigned long nr, a0, a1, a2, a3, ret;
5020         int r = 1;
5021
5022         if (kvm_hv_hypercall_enabled(vcpu->kvm))
5023                 return kvm_hv_hypercall(vcpu);
5024
5025         nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5026         a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5027         a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5028         a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5029         a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5030
5031         trace_kvm_hypercall(nr, a0, a1, a2, a3);
5032
5033         if (!is_long_mode(vcpu)) {
5034                 nr &= 0xFFFFFFFF;
5035                 a0 &= 0xFFFFFFFF;
5036                 a1 &= 0xFFFFFFFF;
5037                 a2 &= 0xFFFFFFFF;
5038                 a3 &= 0xFFFFFFFF;
5039         }
5040
5041         if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5042                 ret = -KVM_EPERM;
5043                 goto out;
5044         }
5045
5046         switch (nr) {
5047         case KVM_HC_VAPIC_POLL_IRQ:
5048                 ret = 0;
5049                 break;
5050         default:
5051                 ret = -KVM_ENOSYS;
5052                 break;
5053         }
5054 out:
5055         kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5056         ++vcpu->stat.hypercalls;
5057         return r;
5058 }
5059 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5060
5061 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5062 {
5063         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5064         char instruction[3];
5065         unsigned long rip = kvm_rip_read(vcpu);
5066
5067         /*
5068          * Blow out the MMU to ensure that no other VCPU has an active mapping
5069          * to ensure that the updated hypercall appears atomically across all
5070          * VCPUs.
5071          */
5072         kvm_mmu_zap_all(vcpu->kvm);
5073
5074         kvm_x86_ops->patch_hypercall(vcpu, instruction);
5075
5076         return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5077 }
5078
5079 /*
5080  * Check if userspace requested an interrupt window, and that the
5081  * interrupt window is open.
5082  *
5083  * No need to exit to userspace if we already have an interrupt queued.
5084  */
5085 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5086 {
5087         return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5088                 vcpu->run->request_interrupt_window &&
5089                 kvm_arch_interrupt_allowed(vcpu));
5090 }
5091
5092 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5093 {
5094         struct kvm_run *kvm_run = vcpu->run;
5095
5096         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5097         kvm_run->cr8 = kvm_get_cr8(vcpu);
5098         kvm_run->apic_base = kvm_get_apic_base(vcpu);
5099         if (irqchip_in_kernel(vcpu->kvm))
5100                 kvm_run->ready_for_interrupt_injection = 1;
5101         else
5102                 kvm_run->ready_for_interrupt_injection =
5103                         kvm_arch_interrupt_allowed(vcpu) &&
5104                         !kvm_cpu_has_interrupt(vcpu) &&
5105                         !kvm_event_needs_reinjection(vcpu);
5106 }
5107
5108 static void vapic_enter(struct kvm_vcpu *vcpu)
5109 {
5110         struct kvm_lapic *apic = vcpu->arch.apic;
5111         struct page *page;
5112
5113         if (!apic || !apic->vapic_addr)
5114                 return;
5115
5116         page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5117
5118         vcpu->arch.apic->vapic_page = page;
5119 }
5120
5121 static void vapic_exit(struct kvm_vcpu *vcpu)
5122 {
5123         struct kvm_lapic *apic = vcpu->arch.apic;
5124         int idx;
5125
5126         if (!apic || !apic->vapic_addr)
5127                 return;
5128
5129         idx = srcu_read_lock(&vcpu->kvm->srcu);
5130         kvm_release_page_dirty(apic->vapic_page);
5131         mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5132         srcu_read_unlock(&vcpu->kvm->srcu, idx);
5133 }
5134
5135 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5136 {
5137         int max_irr, tpr;
5138
5139         if (!kvm_x86_ops->update_cr8_intercept)
5140                 return;
5141
5142         if (!vcpu->arch.apic)
5143                 return;
5144
5145         if (!vcpu->arch.apic->vapic_addr)
5146                 max_irr = kvm_lapic_find_highest_irr(vcpu);
5147         else
5148                 max_irr = -1;
5149
5150         if (max_irr != -1)
5151                 max_irr >>= 4;
5152
5153         tpr = kvm_lapic_get_cr8(vcpu);
5154
5155         kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5156 }
5157
5158 static void inject_pending_event(struct kvm_vcpu *vcpu)
5159 {
5160         /* try to reinject previous events if any */
5161         if (vcpu->arch.exception.pending) {
5162                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5163                                         vcpu->arch.exception.has_error_code,
5164                                         vcpu->arch.exception.error_code);
5165                 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5166                                           vcpu->arch.exception.has_error_code,
5167                                           vcpu->arch.exception.error_code,
5168                                           vcpu->arch.exception.reinject);
5169                 return;
5170         }
5171
5172         if (vcpu->arch.nmi_injected) {
5173                 kvm_x86_ops->set_nmi(vcpu);
5174                 return;
5175         }
5176
5177         if (vcpu->arch.interrupt.pending) {
5178                 kvm_x86_ops->set_irq(vcpu);
5179                 return;
5180         }
5181
5182         /* try to inject new event if pending */
5183         if (vcpu->arch.nmi_pending) {
5184                 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5185                         --vcpu->arch.nmi_pending;
5186                         vcpu->arch.nmi_injected = true;
5187                         kvm_x86_ops->set_nmi(vcpu);
5188                 }
5189         } else if (kvm_cpu_has_interrupt(vcpu)) {
5190                 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5191                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5192                                             false);
5193                         kvm_x86_ops->set_irq(vcpu);
5194                 }
5195         }
5196 }
5197
5198 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5199 {
5200         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5201                         !vcpu->guest_xcr0_loaded) {
5202                 /* kvm_set_xcr() also depends on this */
5203                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5204                 vcpu->guest_xcr0_loaded = 1;
5205         }
5206 }
5207
5208 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5209 {
5210         if (vcpu->guest_xcr0_loaded) {
5211                 if (vcpu->arch.xcr0 != host_xcr0)
5212                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5213                 vcpu->guest_xcr0_loaded = 0;
5214         }
5215 }
5216
5217 static void process_nmi(struct kvm_vcpu *vcpu)
5218 {
5219         unsigned limit = 2;
5220
5221         /*
5222          * x86 is limited to one NMI running, and one NMI pending after it.
5223          * If an NMI is already in progress, limit further NMIs to just one.
5224          * Otherwise, allow two (and we'll inject the first one immediately).
5225          */
5226         if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5227                 limit = 1;
5228
5229         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5230         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5231         kvm_make_request(KVM_REQ_EVENT, vcpu);
5232 }
5233
5234 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5235 {
5236         int r;
5237         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5238                 vcpu->run->request_interrupt_window;
5239         bool req_immediate_exit = 0;
5240
5241         if (vcpu->requests) {
5242                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5243                         kvm_mmu_unload(vcpu);
5244                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5245                         __kvm_migrate_timers(vcpu);
5246                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5247                         r = kvm_guest_time_update(vcpu);
5248                         if (unlikely(r))
5249                                 goto out;
5250                 }
5251                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5252                         kvm_mmu_sync_roots(vcpu);
5253                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5254                         kvm_x86_ops->tlb_flush(vcpu);
5255                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5256                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5257                         r = 0;
5258                         goto out;
5259                 }
5260                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5261                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5262                         r = 0;
5263                         goto out;
5264                 }
5265                 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5266                         vcpu->fpu_active = 0;
5267                         kvm_x86_ops->fpu_deactivate(vcpu);
5268                 }
5269                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5270                         /* Page is swapped out. Do synthetic halt */
5271                         vcpu->arch.apf.halted = true;
5272                         r = 1;
5273                         goto out;
5274                 }
5275                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5276                         record_steal_time(vcpu);
5277                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5278                         process_nmi(vcpu);
5279                 req_immediate_exit =
5280                         kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5281                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5282                         kvm_handle_pmu_event(vcpu);
5283                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5284                         kvm_deliver_pmi(vcpu);
5285         }
5286
5287         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5288                 inject_pending_event(vcpu);
5289
5290                 /* enable NMI/IRQ window open exits if needed */
5291                 if (vcpu->arch.nmi_pending)
5292                         kvm_x86_ops->enable_nmi_window(vcpu);
5293                 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5294                         kvm_x86_ops->enable_irq_window(vcpu);
5295
5296                 if (kvm_lapic_enabled(vcpu)) {
5297                         update_cr8_intercept(vcpu);
5298                         kvm_lapic_sync_to_vapic(vcpu);
5299                 }
5300         }
5301
5302         r = kvm_mmu_reload(vcpu);
5303         if (unlikely(r)) {
5304                 goto cancel_injection;
5305         }
5306
5307         preempt_disable();
5308
5309         kvm_x86_ops->prepare_guest_switch(vcpu);
5310         if (vcpu->fpu_active)
5311                 kvm_load_guest_fpu(vcpu);
5312         kvm_load_guest_xcr0(vcpu);
5313
5314         vcpu->mode = IN_GUEST_MODE;
5315
5316         /* We should set ->mode before check ->requests,
5317          * see the comment in make_all_cpus_request.
5318          */
5319         smp_mb();
5320
5321         local_irq_disable();
5322
5323         if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5324             || need_resched() || signal_pending(current)) {
5325                 vcpu->mode = OUTSIDE_GUEST_MODE;
5326                 smp_wmb();
5327                 local_irq_enable();
5328                 preempt_enable();
5329                 r = 1;
5330                 goto cancel_injection;
5331         }
5332
5333         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5334
5335         if (req_immediate_exit)
5336                 smp_send_reschedule(vcpu->cpu);
5337
5338         kvm_guest_enter();
5339
5340         if (unlikely(vcpu->arch.switch_db_regs)) {
5341                 set_debugreg(0, 7);
5342                 set_debugreg(vcpu->arch.eff_db[0], 0);
5343                 set_debugreg(vcpu->arch.eff_db[1], 1);
5344                 set_debugreg(vcpu->arch.eff_db[2], 2);
5345                 set_debugreg(vcpu->arch.eff_db[3], 3);
5346         }
5347
5348         trace_kvm_entry(vcpu->vcpu_id);
5349         kvm_x86_ops->run(vcpu);
5350
5351         /*
5352          * If the guest has used debug registers, at least dr7
5353          * will be disabled while returning to the host.
5354          * If we don't have active breakpoints in the host, we don't
5355          * care about the messed up debug address registers. But if
5356          * we have some of them active, restore the old state.
5357          */
5358         if (hw_breakpoint_active())
5359                 hw_breakpoint_restore();
5360
5361         vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
5362
5363         vcpu->mode = OUTSIDE_GUEST_MODE;
5364         smp_wmb();
5365         local_irq_enable();
5366
5367         ++vcpu->stat.exits;
5368
5369         /*
5370          * We must have an instruction between local_irq_enable() and
5371          * kvm_guest_exit(), so the timer interrupt isn't delayed by
5372          * the interrupt shadow.  The stat.exits increment will do nicely.
5373          * But we need to prevent reordering, hence this barrier():
5374          */
5375         barrier();
5376
5377         kvm_guest_exit();
5378
5379         preempt_enable();
5380
5381         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5382
5383         /*
5384          * Profile KVM exit RIPs:
5385          */
5386         if (unlikely(prof_on == KVM_PROFILING)) {
5387                 unsigned long rip = kvm_rip_read(vcpu);
5388                 profile_hit(KVM_PROFILING, (void *)rip);
5389         }
5390
5391         if (unlikely(vcpu->arch.tsc_always_catchup))
5392                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5393
5394         if (vcpu->arch.apic_attention)
5395                 kvm_lapic_sync_from_vapic(vcpu);
5396
5397         r = kvm_x86_ops->handle_exit(vcpu);
5398         return r;
5399
5400 cancel_injection:
5401         kvm_x86_ops->cancel_injection(vcpu);
5402         if (unlikely(vcpu->arch.apic_attention))
5403                 kvm_lapic_sync_from_vapic(vcpu);
5404 out:
5405         return r;
5406 }
5407
5408
5409 static int __vcpu_run(struct kvm_vcpu *vcpu)
5410 {
5411         int r;
5412         struct kvm *kvm = vcpu->kvm;
5413
5414         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5415                 pr_debug("vcpu %d received sipi with vector # %x\n",
5416                          vcpu->vcpu_id, vcpu->arch.sipi_vector);
5417                 kvm_lapic_reset(vcpu);
5418                 r = kvm_arch_vcpu_reset(vcpu);
5419                 if (r)
5420                         return r;
5421                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5422         }
5423
5424         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5425         vapic_enter(vcpu);
5426
5427         r = 1;
5428         while (r > 0) {
5429                 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5430                     !vcpu->arch.apf.halted)
5431                         r = vcpu_enter_guest(vcpu);
5432                 else {
5433                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5434                         kvm_vcpu_block(vcpu);
5435                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5436                         if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5437                         {
5438                                 switch(vcpu->arch.mp_state) {
5439                                 case KVM_MP_STATE_HALTED:
5440                                         vcpu->arch.mp_state =
5441                                                 KVM_MP_STATE_RUNNABLE;
5442                                 case KVM_MP_STATE_RUNNABLE:
5443                                         vcpu->arch.apf.halted = false;
5444                                         break;
5445                                 case KVM_MP_STATE_SIPI_RECEIVED:
5446                                 default:
5447                                         r = -EINTR;
5448                                         break;
5449                                 }
5450                         }
5451                 }
5452
5453                 if (r <= 0)
5454                         break;
5455
5456                 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5457                 if (kvm_cpu_has_pending_timer(vcpu))
5458                         kvm_inject_pending_timer_irqs(vcpu);
5459
5460                 if (dm_request_for_irq_injection(vcpu)) {
5461                         r = -EINTR;
5462                         vcpu->run->exit_reason = KVM_EXIT_INTR;
5463                         ++vcpu->stat.request_irq_exits;
5464                 }
5465
5466                 kvm_check_async_pf_completion(vcpu);
5467
5468                 if (signal_pending(current)) {
5469                         r = -EINTR;
5470                         vcpu->run->exit_reason = KVM_EXIT_INTR;
5471                         ++vcpu->stat.signal_exits;
5472                 }
5473                 if (need_resched()) {
5474                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5475                         kvm_resched(vcpu);
5476                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5477                 }
5478         }
5479
5480         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5481
5482         vapic_exit(vcpu);
5483
5484         return r;
5485 }
5486
5487 /*
5488  * Implements the following, as a state machine:
5489  *
5490  * read:
5491  *   for each fragment
5492  *     write gpa, len
5493  *     exit
5494  *     copy data
5495  *   execute insn
5496  *
5497  * write:
5498  *   for each fragment
5499  *      write gpa, len
5500  *      copy data
5501  *      exit
5502  */
5503 static int complete_mmio(struct kvm_vcpu *vcpu)
5504 {
5505         struct kvm_run *run = vcpu->run;
5506         struct kvm_mmio_fragment *frag;
5507         int r;
5508
5509         if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5510                 return 1;
5511
5512         if (vcpu->mmio_needed) {
5513                 /* Complete previous fragment */
5514                 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5515                 if (!vcpu->mmio_is_write)
5516                         memcpy(frag->data, run->mmio.data, frag->len);
5517                 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5518                         vcpu->mmio_needed = 0;
5519                         if (vcpu->mmio_is_write)
5520                                 return 1;
5521                         vcpu->mmio_read_completed = 1;
5522                         goto done;
5523                 }
5524                 /* Initiate next fragment */
5525                 ++frag;
5526                 run->exit_reason = KVM_EXIT_MMIO;
5527                 run->mmio.phys_addr = frag->gpa;
5528                 if (vcpu->mmio_is_write)
5529                         memcpy(run->mmio.data, frag->data, frag->len);
5530                 run->mmio.len = frag->len;
5531                 run->mmio.is_write = vcpu->mmio_is_write;
5532                 return 0;
5533
5534         }
5535 done:
5536         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5537         r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5538         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5539         if (r != EMULATE_DONE)
5540                 return 0;
5541         return 1;
5542 }
5543
5544 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5545 {
5546         int r;
5547         sigset_t sigsaved;
5548
5549         if (!tsk_used_math(current) && init_fpu(current))
5550                 return -ENOMEM;
5551
5552         if (vcpu->sigset_active)
5553                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5554
5555         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5556                 kvm_vcpu_block(vcpu);
5557                 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5558                 r = -EAGAIN;
5559                 goto out;
5560         }
5561
5562         /* re-sync apic's tpr */
5563         if (!irqchip_in_kernel(vcpu->kvm)) {
5564                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5565                         r = -EINVAL;
5566                         goto out;
5567                 }
5568         }
5569
5570         r = complete_mmio(vcpu);
5571         if (r <= 0)
5572                 goto out;
5573
5574         r = __vcpu_run(vcpu);
5575
5576 out:
5577         post_kvm_run_save(vcpu);
5578         if (vcpu->sigset_active)
5579                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5580
5581         return r;
5582 }
5583
5584 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5585 {
5586         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5587                 /*
5588                  * We are here if userspace calls get_regs() in the middle of
5589                  * instruction emulation. Registers state needs to be copied
5590                  * back from emulation context to vcpu. Userspace shouldn't do
5591                  * that usually, but some bad designed PV devices (vmware
5592                  * backdoor interface) need this to work
5593                  */
5594                 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5595                 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5596                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5597         }
5598         regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5599         regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5600         regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5601         regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5602         regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5603         regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5604         regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5605         regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5606 #ifdef CONFIG_X86_64
5607         regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5608         regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5609         regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5610         regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5611         regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5612         regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5613         regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5614         regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5615 #endif
5616
5617         regs->rip = kvm_rip_read(vcpu);
5618         regs->rflags = kvm_get_rflags(vcpu);
5619
5620         return 0;
5621 }
5622
5623 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5624 {
5625         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5626         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5627
5628         kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5629         kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5630         kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5631         kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5632         kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5633         kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5634         kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5635         kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5636 #ifdef CONFIG_X86_64
5637         kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5638         kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5639         kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5640         kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5641         kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5642         kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5643         kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5644         kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5645 #endif
5646
5647         kvm_rip_write(vcpu, regs->rip);
5648         kvm_set_rflags(vcpu, regs->rflags);
5649
5650         vcpu->arch.exception.pending = false;
5651
5652         kvm_make_request(KVM_REQ_EVENT, vcpu);
5653
5654         return 0;
5655 }
5656
5657 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5658 {
5659         struct kvm_segment cs;
5660
5661         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5662         *db = cs.db;
5663         *l = cs.l;
5664 }
5665 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5666
5667 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5668                                   struct kvm_sregs *sregs)
5669 {
5670         struct desc_ptr dt;
5671
5672         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5673         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5674         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5675         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5676         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5677         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5678
5679         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5680         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5681
5682         kvm_x86_ops->get_idt(vcpu, &dt);
5683         sregs->idt.limit = dt.size;
5684         sregs->idt.base = dt.address;
5685         kvm_x86_ops->get_gdt(vcpu, &dt);
5686         sregs->gdt.limit = dt.size;
5687         sregs->gdt.base = dt.address;
5688
5689         sregs->cr0 = kvm_read_cr0(vcpu);
5690         sregs->cr2 = vcpu->arch.cr2;
5691         sregs->cr3 = kvm_read_cr3(vcpu);
5692         sregs->cr4 = kvm_read_cr4(vcpu);
5693         sregs->cr8 = kvm_get_cr8(vcpu);
5694         sregs->efer = vcpu->arch.efer;
5695         sregs->apic_base = kvm_get_apic_base(vcpu);
5696
5697         memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5698
5699         if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5700                 set_bit(vcpu->arch.interrupt.nr,
5701                         (unsigned long *)sregs->interrupt_bitmap);
5702
5703         return 0;
5704 }
5705
5706 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5707                                     struct kvm_mp_state *mp_state)
5708 {
5709         mp_state->mp_state = vcpu->arch.mp_state;
5710         return 0;
5711 }
5712
5713 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5714                                     struct kvm_mp_state *mp_state)
5715 {
5716         vcpu->arch.mp_state = mp_state->mp_state;
5717         kvm_make_request(KVM_REQ_EVENT, vcpu);
5718         return 0;
5719 }
5720
5721 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5722                     int reason, bool has_error_code, u32 error_code)
5723 {
5724         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5725         int ret;
5726
5727         init_emulate_ctxt(vcpu);
5728
5729         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
5730                                    has_error_code, error_code);
5731
5732         if (ret)
5733                 return EMULATE_FAIL;
5734
5735         memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5736         kvm_rip_write(vcpu, ctxt->eip);
5737         kvm_set_rflags(vcpu, ctxt->eflags);
5738         kvm_make_request(KVM_REQ_EVENT, vcpu);
5739         return EMULATE_DONE;
5740 }
5741 EXPORT_SYMBOL_GPL(kvm_task_switch);
5742
5743 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5744                                   struct kvm_sregs *sregs)
5745 {
5746         int mmu_reset_needed = 0;
5747         int pending_vec, max_bits, idx;
5748         struct desc_ptr dt;
5749
5750         dt.size = sregs->idt.limit;
5751         dt.address = sregs->idt.base;
5752         kvm_x86_ops->set_idt(vcpu, &dt);
5753         dt.size = sregs->gdt.limit;
5754         dt.address = sregs->gdt.base;
5755         kvm_x86_ops->set_gdt(vcpu, &dt);
5756
5757         vcpu->arch.cr2 = sregs->cr2;
5758         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
5759         vcpu->arch.cr3 = sregs->cr3;
5760         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5761
5762         kvm_set_cr8(vcpu, sregs->cr8);
5763
5764         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5765         kvm_x86_ops->set_efer(vcpu, sregs->efer);
5766         kvm_set_apic_base(vcpu, sregs->apic_base);
5767
5768         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5769         kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5770         vcpu->arch.cr0 = sregs->cr0;
5771
5772         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5773         kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5774         if (sregs->cr4 & X86_CR4_OSXSAVE)
5775                 kvm_update_cpuid(vcpu);
5776
5777         idx = srcu_read_lock(&vcpu->kvm->srcu);
5778         if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5779                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
5780                 mmu_reset_needed = 1;
5781         }
5782         srcu_read_unlock(&vcpu->kvm->srcu, idx);
5783
5784         if (mmu_reset_needed)
5785                 kvm_mmu_reset_context(vcpu);
5786
5787         max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5788         pending_vec = find_first_bit(
5789                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5790         if (pending_vec < max_bits) {
5791                 kvm_queue_interrupt(vcpu, pending_vec, false);
5792                 pr_debug("Set back pending irq %d\n", pending_vec);
5793         }
5794
5795         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5796         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5797         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5798         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5799         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5800         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5801
5802         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5803         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5804
5805         update_cr8_intercept(vcpu);
5806
5807         /* Older userspace won't unhalt the vcpu on reset. */
5808         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5809             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5810             !is_protmode(vcpu))
5811                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5812
5813         kvm_make_request(KVM_REQ_EVENT, vcpu);
5814
5815         return 0;
5816 }
5817
5818 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5819                                         struct kvm_guest_debug *dbg)
5820 {
5821         unsigned long rflags;
5822         int i, r;
5823
5824         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5825                 r = -EBUSY;
5826                 if (vcpu->arch.exception.pending)
5827                         goto out;
5828                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5829                         kvm_queue_exception(vcpu, DB_VECTOR);
5830                 else
5831                         kvm_queue_exception(vcpu, BP_VECTOR);
5832         }
5833
5834         /*
5835          * Read rflags as long as potentially injected trace flags are still
5836          * filtered out.
5837          */
5838         rflags = kvm_get_rflags(vcpu);
5839
5840         vcpu->guest_debug = dbg->control;
5841         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5842                 vcpu->guest_debug = 0;
5843
5844         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5845                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5846                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5847                 vcpu->arch.switch_db_regs =
5848                         (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5849         } else {
5850                 for (i = 0; i < KVM_NR_DB_REGS; i++)
5851                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5852                 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5853         }
5854
5855         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5856                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5857                         get_segment_base(vcpu, VCPU_SREG_CS);
5858
5859         /*
5860          * Trigger an rflags update that will inject or remove the trace
5861          * flags.
5862          */
5863         kvm_set_rflags(vcpu, rflags);
5864
5865         kvm_x86_ops->set_guest_debug(vcpu, dbg);
5866
5867         r = 0;
5868
5869 out:
5870
5871         return r;
5872 }
5873
5874 /*
5875  * Translate a guest virtual address to a guest physical address.
5876  */
5877 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5878                                     struct kvm_translation *tr)
5879 {
5880         unsigned long vaddr = tr->linear_address;
5881         gpa_t gpa;
5882         int idx;
5883
5884         idx = srcu_read_lock(&vcpu->kvm->srcu);
5885         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5886         srcu_read_unlock(&vcpu->kvm->srcu, idx);
5887         tr->physical_address = gpa;
5888         tr->valid = gpa != UNMAPPED_GVA;
5889         tr->writeable = 1;
5890         tr->usermode = 0;
5891
5892         return 0;
5893 }
5894
5895 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5896 {
5897         struct i387_fxsave_struct *fxsave =
5898                         &vcpu->arch.guest_fpu.state->fxsave;
5899
5900         memcpy(fpu->fpr, fxsave->st_space, 128);
5901         fpu->fcw = fxsave->cwd;
5902         fpu->fsw = fxsave->swd;
5903         fpu->ftwx = fxsave->twd;
5904         fpu->last_opcode = fxsave->fop;
5905         fpu->last_ip = fxsave->rip;
5906         fpu->last_dp = fxsave->rdp;
5907         memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5908
5909         return 0;
5910 }
5911
5912 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5913 {
5914         struct i387_fxsave_struct *fxsave =
5915                         &vcpu->arch.guest_fpu.state->fxsave;
5916
5917         memcpy(fxsave->st_space, fpu->fpr, 128);
5918         fxsave->cwd = fpu->fcw;
5919         fxsave->swd = fpu->fsw;
5920         fxsave->twd = fpu->ftwx;
5921         fxsave->fop = fpu->last_opcode;
5922         fxsave->rip = fpu->last_ip;
5923         fxsave->rdp = fpu->last_dp;
5924         memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5925
5926         return 0;
5927 }
5928
5929 int fx_init(struct kvm_vcpu *vcpu)
5930 {
5931         int err;
5932
5933         err = fpu_alloc(&vcpu->arch.guest_fpu);
5934         if (err)
5935                 return err;
5936
5937         fpu_finit(&vcpu->arch.guest_fpu);
5938
5939         /*
5940          * Ensure guest xcr0 is valid for loading
5941          */
5942         vcpu->arch.xcr0 = XSTATE_FP;
5943
5944         vcpu->arch.cr0 |= X86_CR0_ET;
5945
5946         return 0;
5947 }
5948 EXPORT_SYMBOL_GPL(fx_init);
5949
5950 static void fx_free(struct kvm_vcpu *vcpu)
5951 {
5952         fpu_free(&vcpu->arch.guest_fpu);
5953 }
5954
5955 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5956 {
5957         if (vcpu->guest_fpu_loaded)
5958                 return;
5959
5960         /*
5961          * Restore all possible states in the guest,
5962          * and assume host would use all available bits.
5963          * Guest xcr0 would be loaded later.
5964          */
5965         kvm_put_guest_xcr0(vcpu);
5966         vcpu->guest_fpu_loaded = 1;
5967         unlazy_fpu(current);
5968         fpu_restore_checking(&vcpu->arch.guest_fpu);
5969         trace_kvm_fpu(1);
5970 }
5971
5972 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5973 {
5974         kvm_put_guest_xcr0(vcpu);
5975
5976         if (!vcpu->guest_fpu_loaded)
5977                 return;
5978
5979         vcpu->guest_fpu_loaded = 0;
5980         fpu_save_init(&vcpu->arch.guest_fpu);
5981         ++vcpu->stat.fpu_reload;
5982         kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5983         trace_kvm_fpu(0);
5984 }
5985
5986 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5987 {
5988         kvmclock_reset(vcpu);
5989
5990         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5991         fx_free(vcpu);
5992         kvm_x86_ops->vcpu_free(vcpu);
5993 }
5994
5995 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5996                                                 unsigned int id)
5997 {
5998         if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5999                 printk_once(KERN_WARNING
6000                 "kvm: SMP vm created on host with unstable TSC; "
6001                 "guest TSC will not be reliable\n");
6002         return kvm_x86_ops->vcpu_create(kvm, id);
6003 }
6004
6005 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6006 {
6007         int r;
6008
6009         vcpu->arch.mtrr_state.have_fixed = 1;
6010         vcpu_load(vcpu);
6011         r = kvm_arch_vcpu_reset(vcpu);
6012         if (r == 0)
6013                 r = kvm_mmu_setup(vcpu);
6014         vcpu_put(vcpu);
6015
6016         return r;
6017 }
6018
6019 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6020 {
6021         vcpu->arch.apf.msr_val = 0;
6022
6023         vcpu_load(vcpu);
6024         kvm_mmu_unload(vcpu);
6025         vcpu_put(vcpu);
6026
6027         fx_free(vcpu);
6028         kvm_x86_ops->vcpu_free(vcpu);
6029 }
6030
6031 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6032 {
6033         atomic_set(&vcpu->arch.nmi_queued, 0);
6034         vcpu->arch.nmi_pending = 0;
6035         vcpu->arch.nmi_injected = false;
6036
6037         vcpu->arch.switch_db_regs = 0;
6038         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6039         vcpu->arch.dr6 = DR6_FIXED_1;
6040         vcpu->arch.dr7 = DR7_FIXED_1;
6041
6042         kvm_make_request(KVM_REQ_EVENT, vcpu);
6043         vcpu->arch.apf.msr_val = 0;
6044         vcpu->arch.st.msr_val = 0;
6045
6046         kvmclock_reset(vcpu);
6047
6048         kvm_clear_async_pf_completion_queue(vcpu);
6049         kvm_async_pf_hash_reset(vcpu);
6050         vcpu->arch.apf.halted = false;
6051
6052         kvm_pmu_reset(vcpu);
6053
6054         return kvm_x86_ops->vcpu_reset(vcpu);
6055 }
6056
6057 int kvm_arch_hardware_enable(void *garbage)
6058 {
6059         struct kvm *kvm;
6060         struct kvm_vcpu *vcpu;
6061         int i;
6062         int ret;
6063         u64 local_tsc;
6064         u64 max_tsc = 0;
6065         bool stable, backwards_tsc = false;
6066
6067         kvm_shared_msr_cpu_online();
6068         ret = kvm_x86_ops->hardware_enable(garbage);
6069         if (ret != 0)
6070                 return ret;
6071
6072         local_tsc = native_read_tsc();
6073         stable = !check_tsc_unstable();
6074         list_for_each_entry(kvm, &vm_list, vm_list) {
6075                 kvm_for_each_vcpu(i, vcpu, kvm) {
6076                         if (!stable && vcpu->cpu == smp_processor_id())
6077                                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6078                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6079                                 backwards_tsc = true;
6080                                 if (vcpu->arch.last_host_tsc > max_tsc)
6081                                         max_tsc = vcpu->arch.last_host_tsc;
6082                         }
6083                 }
6084         }
6085
6086         /*
6087          * Sometimes, even reliable TSCs go backwards.  This happens on
6088          * platforms that reset TSC during suspend or hibernate actions, but
6089          * maintain synchronization.  We must compensate.  Fortunately, we can
6090          * detect that condition here, which happens early in CPU bringup,
6091          * before any KVM threads can be running.  Unfortunately, we can't
6092          * bring the TSCs fully up to date with real time, as we aren't yet far
6093          * enough into CPU bringup that we know how much real time has actually
6094          * elapsed; our helper function, get_kernel_ns() will be using boot
6095          * variables that haven't been updated yet.
6096          *
6097          * So we simply find the maximum observed TSC above, then record the
6098          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
6099          * the adjustment will be applied.  Note that we accumulate
6100          * adjustments, in case multiple suspend cycles happen before some VCPU
6101          * gets a chance to run again.  In the event that no KVM threads get a
6102          * chance to run, we will miss the entire elapsed period, as we'll have
6103          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6104          * loose cycle time.  This isn't too big a deal, since the loss will be
6105          * uniform across all VCPUs (not to mention the scenario is extremely
6106          * unlikely). It is possible that a second hibernate recovery happens
6107          * much faster than a first, causing the observed TSC here to be
6108          * smaller; this would require additional padding adjustment, which is
6109          * why we set last_host_tsc to the local tsc observed here.
6110          *
6111          * N.B. - this code below runs only on platforms with reliable TSC,
6112          * as that is the only way backwards_tsc is set above.  Also note
6113          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6114          * have the same delta_cyc adjustment applied if backwards_tsc
6115          * is detected.  Note further, this adjustment is only done once,
6116          * as we reset last_host_tsc on all VCPUs to stop this from being
6117          * called multiple times (one for each physical CPU bringup).
6118          *
6119          * Platforms with unreliable TSCs don't have to deal with this, they
6120          * will be compensated by the logic in vcpu_load, which sets the TSC to
6121          * catchup mode.  This will catchup all VCPUs to real time, but cannot
6122          * guarantee that they stay in perfect synchronization.
6123          */
6124         if (backwards_tsc) {
6125                 u64 delta_cyc = max_tsc - local_tsc;
6126                 list_for_each_entry(kvm, &vm_list, vm_list) {
6127                         kvm_for_each_vcpu(i, vcpu, kvm) {
6128                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6129                                 vcpu->arch.last_host_tsc = local_tsc;
6130                         }
6131
6132                         /*
6133                          * We have to disable TSC offset matching.. if you were
6134                          * booting a VM while issuing an S4 host suspend....
6135                          * you may have some problem.  Solving this issue is
6136                          * left as an exercise to the reader.
6137                          */
6138                         kvm->arch.last_tsc_nsec = 0;
6139                         kvm->arch.last_tsc_write = 0;
6140                 }
6141
6142         }
6143         return 0;
6144 }
6145
6146 void kvm_arch_hardware_disable(void *garbage)
6147 {
6148         kvm_x86_ops->hardware_disable(garbage);
6149         drop_user_return_notifiers(garbage);
6150 }
6151
6152 int kvm_arch_hardware_setup(void)
6153 {
6154         return kvm_x86_ops->hardware_setup();
6155 }
6156
6157 void kvm_arch_hardware_unsetup(void)
6158 {
6159         kvm_x86_ops->hardware_unsetup();
6160 }
6161
6162 void kvm_arch_check_processor_compat(void *rtn)
6163 {
6164         kvm_x86_ops->check_processor_compatibility(rtn);
6165 }
6166
6167 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6168 {
6169         return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6170 }
6171
6172 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6173 {
6174         struct page *page;
6175         struct kvm *kvm;
6176         int r;
6177
6178         BUG_ON(vcpu->kvm == NULL);
6179         kvm = vcpu->kvm;
6180
6181         vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6182         if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6183                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6184         else
6185                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6186
6187         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6188         if (!page) {
6189                 r = -ENOMEM;
6190                 goto fail;
6191         }
6192         vcpu->arch.pio_data = page_address(page);
6193
6194         kvm_set_tsc_khz(vcpu, max_tsc_khz);
6195
6196         r = kvm_mmu_create(vcpu);
6197         if (r < 0)
6198                 goto fail_free_pio_data;
6199
6200         if (irqchip_in_kernel(kvm)) {
6201                 r = kvm_create_lapic(vcpu);
6202                 if (r < 0)
6203                         goto fail_mmu_destroy;
6204         }
6205
6206         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6207                                        GFP_KERNEL);
6208         if (!vcpu->arch.mce_banks) {
6209                 r = -ENOMEM;
6210                 goto fail_free_lapic;
6211         }
6212         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6213
6214         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6215                 goto fail_free_mce_banks;
6216
6217         kvm_async_pf_hash_reset(vcpu);
6218         kvm_pmu_init(vcpu);
6219
6220         return 0;
6221 fail_free_mce_banks:
6222         kfree(vcpu->arch.mce_banks);
6223 fail_free_lapic:
6224         kvm_free_lapic(vcpu);
6225 fail_mmu_destroy:
6226         kvm_mmu_destroy(vcpu);
6227 fail_free_pio_data:
6228         free_page((unsigned long)vcpu->arch.pio_data);
6229 fail:
6230         return r;
6231 }
6232
6233 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6234 {
6235         int idx;
6236
6237         kvm_pmu_destroy(vcpu);
6238         kfree(vcpu->arch.mce_banks);
6239         kvm_free_lapic(vcpu);
6240         idx = srcu_read_lock(&vcpu->kvm->srcu);
6241         kvm_mmu_destroy(vcpu);
6242         srcu_read_unlock(&vcpu->kvm->srcu, idx);
6243         free_page((unsigned long)vcpu->arch.pio_data);
6244 }
6245
6246 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6247 {
6248         if (type)
6249                 return -EINVAL;
6250
6251         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6252         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6253
6254         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6255         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6256
6257         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6258
6259         return 0;
6260 }
6261