x86, apicv: add virtual interrupt delivery support
[linux-3.10.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9  *
10  * Authors:
11  *   Avi Kivity   <avi@qumranet.com>
12  *   Yaniv Kamay  <yaniv@qumranet.com>
13  *
14  * This work is licensed under the terms of the GNU GPL, version 2.  See
15  * the COPYING file in the top-level directory.
16  *
17  */
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "cpuid.h"
22
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
35 #include "x86.h"
36
37 #include <asm/io.h>
38 #include <asm/desc.h>
39 #include <asm/vmx.h>
40 #include <asm/virtext.h>
41 #include <asm/mce.h>
42 #include <asm/i387.h>
43 #include <asm/xcr.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
46
47 #include "trace.h"
48
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
52
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
55
56 static const struct x86_cpu_id vmx_cpu_id[] = {
57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
58         {}
59 };
60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
62 static bool __read_mostly enable_vpid = 1;
63 module_param_named(vpid, enable_vpid, bool, 0444);
64
65 static bool __read_mostly flexpriority_enabled = 1;
66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
67
68 static bool __read_mostly enable_ept = 1;
69 module_param_named(ept, enable_ept, bool, S_IRUGO);
70
71 static bool __read_mostly enable_unrestricted_guest = 1;
72 module_param_named(unrestricted_guest,
73                         enable_unrestricted_guest, bool, S_IRUGO);
74
75 static bool __read_mostly enable_ept_ad_bits = 1;
76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
78 static bool __read_mostly emulate_invalid_guest_state = true;
79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
80
81 static bool __read_mostly vmm_exclusive = 1;
82 module_param(vmm_exclusive, bool, S_IRUGO);
83
84 static bool __read_mostly fasteoi = 1;
85 module_param(fasteoi, bool, S_IRUGO);
86
87 static bool __read_mostly enable_apicv_reg_vid = 1;
88 module_param(enable_apicv_reg_vid, bool, S_IRUGO);
89
90 /*
91  * If nested=1, nested virtualization is supported, i.e., guests may use
92  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
93  * use VMX instructions.
94  */
95 static bool __read_mostly nested = 0;
96 module_param(nested, bool, S_IRUGO);
97
98 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
99         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
100 #define KVM_GUEST_CR0_MASK                                              \
101         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
102 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
103         (X86_CR0_WP | X86_CR0_NE)
104 #define KVM_VM_CR0_ALWAYS_ON                                            \
105         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
106 #define KVM_CR4_GUEST_OWNED_BITS                                      \
107         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
108          | X86_CR4_OSXMMEXCPT)
109
110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
115 /*
116  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
117  * ple_gap:    upper bound on the amount of time between two successive
118  *             executions of PAUSE in a loop. Also indicate if ple enabled.
119  *             According to test, this time is usually smaller than 128 cycles.
120  * ple_window: upper bound on the amount of time a guest is allowed to execute
121  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
122  *             less than 2^12 cycles
123  * Time is measured based on a counter that runs at the same rate as the TSC,
124  * refer SDM volume 3b section 21.6.13 & 22.1.3.
125  */
126 #define KVM_VMX_DEFAULT_PLE_GAP    128
127 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
128 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
129 module_param(ple_gap, int, S_IRUGO);
130
131 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
132 module_param(ple_window, int, S_IRUGO);
133
134 extern const ulong vmx_return;
135
136 #define NR_AUTOLOAD_MSRS 8
137 #define VMCS02_POOL_SIZE 1
138
139 struct vmcs {
140         u32 revision_id;
141         u32 abort;
142         char data[0];
143 };
144
145 /*
146  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
147  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
148  * loaded on this CPU (so we can clear them if the CPU goes down).
149  */
150 struct loaded_vmcs {
151         struct vmcs *vmcs;
152         int cpu;
153         int launched;
154         struct list_head loaded_vmcss_on_cpu_link;
155 };
156
157 struct shared_msr_entry {
158         unsigned index;
159         u64 data;
160         u64 mask;
161 };
162
163 /*
164  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
165  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
166  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
167  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
168  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
169  * More than one of these structures may exist, if L1 runs multiple L2 guests.
170  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
171  * underlying hardware which will be used to run L2.
172  * This structure is packed to ensure that its layout is identical across
173  * machines (necessary for live migration).
174  * If there are changes in this struct, VMCS12_REVISION must be changed.
175  */
176 typedef u64 natural_width;
177 struct __packed vmcs12 {
178         /* According to the Intel spec, a VMCS region must start with the
179          * following two fields. Then follow implementation-specific data.
180          */
181         u32 revision_id;
182         u32 abort;
183
184         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
185         u32 padding[7]; /* room for future expansion */
186
187         u64 io_bitmap_a;
188         u64 io_bitmap_b;
189         u64 msr_bitmap;
190         u64 vm_exit_msr_store_addr;
191         u64 vm_exit_msr_load_addr;
192         u64 vm_entry_msr_load_addr;
193         u64 tsc_offset;
194         u64 virtual_apic_page_addr;
195         u64 apic_access_addr;
196         u64 ept_pointer;
197         u64 guest_physical_address;
198         u64 vmcs_link_pointer;
199         u64 guest_ia32_debugctl;
200         u64 guest_ia32_pat;
201         u64 guest_ia32_efer;
202         u64 guest_ia32_perf_global_ctrl;
203         u64 guest_pdptr0;
204         u64 guest_pdptr1;
205         u64 guest_pdptr2;
206         u64 guest_pdptr3;
207         u64 host_ia32_pat;
208         u64 host_ia32_efer;
209         u64 host_ia32_perf_global_ctrl;
210         u64 padding64[8]; /* room for future expansion */
211         /*
212          * To allow migration of L1 (complete with its L2 guests) between
213          * machines of different natural widths (32 or 64 bit), we cannot have
214          * unsigned long fields with no explict size. We use u64 (aliased
215          * natural_width) instead. Luckily, x86 is little-endian.
216          */
217         natural_width cr0_guest_host_mask;
218         natural_width cr4_guest_host_mask;
219         natural_width cr0_read_shadow;
220         natural_width cr4_read_shadow;
221         natural_width cr3_target_value0;
222         natural_width cr3_target_value1;
223         natural_width cr3_target_value2;
224         natural_width cr3_target_value3;
225         natural_width exit_qualification;
226         natural_width guest_linear_address;
227         natural_width guest_cr0;
228         natural_width guest_cr3;
229         natural_width guest_cr4;
230         natural_width guest_es_base;
231         natural_width guest_cs_base;
232         natural_width guest_ss_base;
233         natural_width guest_ds_base;
234         natural_width guest_fs_base;
235         natural_width guest_gs_base;
236         natural_width guest_ldtr_base;
237         natural_width guest_tr_base;
238         natural_width guest_gdtr_base;
239         natural_width guest_idtr_base;
240         natural_width guest_dr7;
241         natural_width guest_rsp;
242         natural_width guest_rip;
243         natural_width guest_rflags;
244         natural_width guest_pending_dbg_exceptions;
245         natural_width guest_sysenter_esp;
246         natural_width guest_sysenter_eip;
247         natural_width host_cr0;
248         natural_width host_cr3;
249         natural_width host_cr4;
250         natural_width host_fs_base;
251         natural_width host_gs_base;
252         natural_width host_tr_base;
253         natural_width host_gdtr_base;
254         natural_width host_idtr_base;
255         natural_width host_ia32_sysenter_esp;
256         natural_width host_ia32_sysenter_eip;
257         natural_width host_rsp;
258         natural_width host_rip;
259         natural_width paddingl[8]; /* room for future expansion */
260         u32 pin_based_vm_exec_control;
261         u32 cpu_based_vm_exec_control;
262         u32 exception_bitmap;
263         u32 page_fault_error_code_mask;
264         u32 page_fault_error_code_match;
265         u32 cr3_target_count;
266         u32 vm_exit_controls;
267         u32 vm_exit_msr_store_count;
268         u32 vm_exit_msr_load_count;
269         u32 vm_entry_controls;
270         u32 vm_entry_msr_load_count;
271         u32 vm_entry_intr_info_field;
272         u32 vm_entry_exception_error_code;
273         u32 vm_entry_instruction_len;
274         u32 tpr_threshold;
275         u32 secondary_vm_exec_control;
276         u32 vm_instruction_error;
277         u32 vm_exit_reason;
278         u32 vm_exit_intr_info;
279         u32 vm_exit_intr_error_code;
280         u32 idt_vectoring_info_field;
281         u32 idt_vectoring_error_code;
282         u32 vm_exit_instruction_len;
283         u32 vmx_instruction_info;
284         u32 guest_es_limit;
285         u32 guest_cs_limit;
286         u32 guest_ss_limit;
287         u32 guest_ds_limit;
288         u32 guest_fs_limit;
289         u32 guest_gs_limit;
290         u32 guest_ldtr_limit;
291         u32 guest_tr_limit;
292         u32 guest_gdtr_limit;
293         u32 guest_idtr_limit;
294         u32 guest_es_ar_bytes;
295         u32 guest_cs_ar_bytes;
296         u32 guest_ss_ar_bytes;
297         u32 guest_ds_ar_bytes;
298         u32 guest_fs_ar_bytes;
299         u32 guest_gs_ar_bytes;
300         u32 guest_ldtr_ar_bytes;
301         u32 guest_tr_ar_bytes;
302         u32 guest_interruptibility_info;
303         u32 guest_activity_state;
304         u32 guest_sysenter_cs;
305         u32 host_ia32_sysenter_cs;
306         u32 padding32[8]; /* room for future expansion */
307         u16 virtual_processor_id;
308         u16 guest_es_selector;
309         u16 guest_cs_selector;
310         u16 guest_ss_selector;
311         u16 guest_ds_selector;
312         u16 guest_fs_selector;
313         u16 guest_gs_selector;
314         u16 guest_ldtr_selector;
315         u16 guest_tr_selector;
316         u16 host_es_selector;
317         u16 host_cs_selector;
318         u16 host_ss_selector;
319         u16 host_ds_selector;
320         u16 host_fs_selector;
321         u16 host_gs_selector;
322         u16 host_tr_selector;
323 };
324
325 /*
326  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
327  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
328  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
329  */
330 #define VMCS12_REVISION 0x11e57ed0
331
332 /*
333  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
334  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
335  * current implementation, 4K are reserved to avoid future complications.
336  */
337 #define VMCS12_SIZE 0x1000
338
339 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
340 struct vmcs02_list {
341         struct list_head list;
342         gpa_t vmptr;
343         struct loaded_vmcs vmcs02;
344 };
345
346 /*
347  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
348  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
349  */
350 struct nested_vmx {
351         /* Has the level1 guest done vmxon? */
352         bool vmxon;
353
354         /* The guest-physical address of the current VMCS L1 keeps for L2 */
355         gpa_t current_vmptr;
356         /* The host-usable pointer to the above */
357         struct page *current_vmcs12_page;
358         struct vmcs12 *current_vmcs12;
359
360         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
361         struct list_head vmcs02_pool;
362         int vmcs02_num;
363         u64 vmcs01_tsc_offset;
364         /* L2 must run next, and mustn't decide to exit to L1. */
365         bool nested_run_pending;
366         /*
367          * Guest pages referred to in vmcs02 with host-physical pointers, so
368          * we must keep them pinned while L2 runs.
369          */
370         struct page *apic_access_page;
371 };
372
373 struct vcpu_vmx {
374         struct kvm_vcpu       vcpu;
375         unsigned long         host_rsp;
376         u8                    fail;
377         u8                    cpl;
378         bool                  nmi_known_unmasked;
379         u32                   exit_intr_info;
380         u32                   idt_vectoring_info;
381         ulong                 rflags;
382         struct shared_msr_entry *guest_msrs;
383         int                   nmsrs;
384         int                   save_nmsrs;
385 #ifdef CONFIG_X86_64
386         u64                   msr_host_kernel_gs_base;
387         u64                   msr_guest_kernel_gs_base;
388 #endif
389         /*
390          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
391          * non-nested (L1) guest, it always points to vmcs01. For a nested
392          * guest (L2), it points to a different VMCS.
393          */
394         struct loaded_vmcs    vmcs01;
395         struct loaded_vmcs   *loaded_vmcs;
396         bool                  __launched; /* temporary, used in vmx_vcpu_run */
397         struct msr_autoload {
398                 unsigned nr;
399                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
400                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
401         } msr_autoload;
402         struct {
403                 int           loaded;
404                 u16           fs_sel, gs_sel, ldt_sel;
405 #ifdef CONFIG_X86_64
406                 u16           ds_sel, es_sel;
407 #endif
408                 int           gs_ldt_reload_needed;
409                 int           fs_reload_needed;
410         } host_state;
411         struct {
412                 int vm86_active;
413                 ulong save_rflags;
414                 struct kvm_segment segs[8];
415         } rmode;
416         struct {
417                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
418                 struct kvm_save_segment {
419                         u16 selector;
420                         unsigned long base;
421                         u32 limit;
422                         u32 ar;
423                 } seg[8];
424         } segment_cache;
425         int vpid;
426         bool emulation_required;
427
428         /* Support for vnmi-less CPUs */
429         int soft_vnmi_blocked;
430         ktime_t entry_time;
431         s64 vnmi_blocked_time;
432         u32 exit_reason;
433
434         bool rdtscp_enabled;
435
436         /* Support for a guest hypervisor (nested VMX) */
437         struct nested_vmx nested;
438 };
439
440 enum segment_cache_field {
441         SEG_FIELD_SEL = 0,
442         SEG_FIELD_BASE = 1,
443         SEG_FIELD_LIMIT = 2,
444         SEG_FIELD_AR = 3,
445
446         SEG_FIELD_NR = 4
447 };
448
449 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
450 {
451         return container_of(vcpu, struct vcpu_vmx, vcpu);
452 }
453
454 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
455 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
456 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
457                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
458
459 static const unsigned short vmcs_field_to_offset_table[] = {
460         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
461         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
462         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
463         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
464         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
465         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
466         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
467         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
468         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
469         FIELD(HOST_ES_SELECTOR, host_es_selector),
470         FIELD(HOST_CS_SELECTOR, host_cs_selector),
471         FIELD(HOST_SS_SELECTOR, host_ss_selector),
472         FIELD(HOST_DS_SELECTOR, host_ds_selector),
473         FIELD(HOST_FS_SELECTOR, host_fs_selector),
474         FIELD(HOST_GS_SELECTOR, host_gs_selector),
475         FIELD(HOST_TR_SELECTOR, host_tr_selector),
476         FIELD64(IO_BITMAP_A, io_bitmap_a),
477         FIELD64(IO_BITMAP_B, io_bitmap_b),
478         FIELD64(MSR_BITMAP, msr_bitmap),
479         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
480         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
481         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
482         FIELD64(TSC_OFFSET, tsc_offset),
483         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
484         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
485         FIELD64(EPT_POINTER, ept_pointer),
486         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
487         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
488         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
489         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
490         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
491         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
492         FIELD64(GUEST_PDPTR0, guest_pdptr0),
493         FIELD64(GUEST_PDPTR1, guest_pdptr1),
494         FIELD64(GUEST_PDPTR2, guest_pdptr2),
495         FIELD64(GUEST_PDPTR3, guest_pdptr3),
496         FIELD64(HOST_IA32_PAT, host_ia32_pat),
497         FIELD64(HOST_IA32_EFER, host_ia32_efer),
498         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
499         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
500         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
501         FIELD(EXCEPTION_BITMAP, exception_bitmap),
502         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
503         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
504         FIELD(CR3_TARGET_COUNT, cr3_target_count),
505         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
506         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
507         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
508         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
509         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
510         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
511         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
512         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
513         FIELD(TPR_THRESHOLD, tpr_threshold),
514         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
515         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
516         FIELD(VM_EXIT_REASON, vm_exit_reason),
517         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
518         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
519         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
520         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
521         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
522         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
523         FIELD(GUEST_ES_LIMIT, guest_es_limit),
524         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
525         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
526         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
527         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
528         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
529         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
530         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
531         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
532         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
533         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
534         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
535         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
536         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
537         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
538         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
539         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
540         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
541         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
542         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
543         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
544         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
545         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
546         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
547         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
548         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
549         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
550         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
551         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
552         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
553         FIELD(EXIT_QUALIFICATION, exit_qualification),
554         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
555         FIELD(GUEST_CR0, guest_cr0),
556         FIELD(GUEST_CR3, guest_cr3),
557         FIELD(GUEST_CR4, guest_cr4),
558         FIELD(GUEST_ES_BASE, guest_es_base),
559         FIELD(GUEST_CS_BASE, guest_cs_base),
560         FIELD(GUEST_SS_BASE, guest_ss_base),
561         FIELD(GUEST_DS_BASE, guest_ds_base),
562         FIELD(GUEST_FS_BASE, guest_fs_base),
563         FIELD(GUEST_GS_BASE, guest_gs_base),
564         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
565         FIELD(GUEST_TR_BASE, guest_tr_base),
566         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
567         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
568         FIELD(GUEST_DR7, guest_dr7),
569         FIELD(GUEST_RSP, guest_rsp),
570         FIELD(GUEST_RIP, guest_rip),
571         FIELD(GUEST_RFLAGS, guest_rflags),
572         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
573         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
574         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
575         FIELD(HOST_CR0, host_cr0),
576         FIELD(HOST_CR3, host_cr3),
577         FIELD(HOST_CR4, host_cr4),
578         FIELD(HOST_FS_BASE, host_fs_base),
579         FIELD(HOST_GS_BASE, host_gs_base),
580         FIELD(HOST_TR_BASE, host_tr_base),
581         FIELD(HOST_GDTR_BASE, host_gdtr_base),
582         FIELD(HOST_IDTR_BASE, host_idtr_base),
583         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
584         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
585         FIELD(HOST_RSP, host_rsp),
586         FIELD(HOST_RIP, host_rip),
587 };
588 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
589
590 static inline short vmcs_field_to_offset(unsigned long field)
591 {
592         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
593                 return -1;
594         return vmcs_field_to_offset_table[field];
595 }
596
597 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
598 {
599         return to_vmx(vcpu)->nested.current_vmcs12;
600 }
601
602 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
603 {
604         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
605         if (is_error_page(page))
606                 return NULL;
607
608         return page;
609 }
610
611 static void nested_release_page(struct page *page)
612 {
613         kvm_release_page_dirty(page);
614 }
615
616 static void nested_release_page_clean(struct page *page)
617 {
618         kvm_release_page_clean(page);
619 }
620
621 static u64 construct_eptp(unsigned long root_hpa);
622 static void kvm_cpu_vmxon(u64 addr);
623 static void kvm_cpu_vmxoff(void);
624 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
625 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
626 static void vmx_set_segment(struct kvm_vcpu *vcpu,
627                             struct kvm_segment *var, int seg);
628 static void vmx_get_segment(struct kvm_vcpu *vcpu,
629                             struct kvm_segment *var, int seg);
630 static bool guest_state_valid(struct kvm_vcpu *vcpu);
631 static u32 vmx_segment_access_rights(struct kvm_segment *var);
632
633 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
634 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
635 /*
636  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
637  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
638  */
639 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
640 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
641
642 static unsigned long *vmx_io_bitmap_a;
643 static unsigned long *vmx_io_bitmap_b;
644 static unsigned long *vmx_msr_bitmap_legacy;
645 static unsigned long *vmx_msr_bitmap_longmode;
646 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
647 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
648
649 static bool cpu_has_load_ia32_efer;
650 static bool cpu_has_load_perf_global_ctrl;
651
652 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
653 static DEFINE_SPINLOCK(vmx_vpid_lock);
654
655 static struct vmcs_config {
656         int size;
657         int order;
658         u32 revision_id;
659         u32 pin_based_exec_ctrl;
660         u32 cpu_based_exec_ctrl;
661         u32 cpu_based_2nd_exec_ctrl;
662         u32 vmexit_ctrl;
663         u32 vmentry_ctrl;
664 } vmcs_config;
665
666 static struct vmx_capability {
667         u32 ept;
668         u32 vpid;
669 } vmx_capability;
670
671 #define VMX_SEGMENT_FIELD(seg)                                  \
672         [VCPU_SREG_##seg] = {                                   \
673                 .selector = GUEST_##seg##_SELECTOR,             \
674                 .base = GUEST_##seg##_BASE,                     \
675                 .limit = GUEST_##seg##_LIMIT,                   \
676                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
677         }
678
679 static const struct kvm_vmx_segment_field {
680         unsigned selector;
681         unsigned base;
682         unsigned limit;
683         unsigned ar_bytes;
684 } kvm_vmx_segment_fields[] = {
685         VMX_SEGMENT_FIELD(CS),
686         VMX_SEGMENT_FIELD(DS),
687         VMX_SEGMENT_FIELD(ES),
688         VMX_SEGMENT_FIELD(FS),
689         VMX_SEGMENT_FIELD(GS),
690         VMX_SEGMENT_FIELD(SS),
691         VMX_SEGMENT_FIELD(TR),
692         VMX_SEGMENT_FIELD(LDTR),
693 };
694
695 static u64 host_efer;
696
697 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
698
699 /*
700  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
701  * away by decrementing the array size.
702  */
703 static const u32 vmx_msr_index[] = {
704 #ifdef CONFIG_X86_64
705         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
706 #endif
707         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
708 };
709 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
710
711 static inline bool is_page_fault(u32 intr_info)
712 {
713         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
714                              INTR_INFO_VALID_MASK)) ==
715                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
716 }
717
718 static inline bool is_no_device(u32 intr_info)
719 {
720         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
721                              INTR_INFO_VALID_MASK)) ==
722                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
723 }
724
725 static inline bool is_invalid_opcode(u32 intr_info)
726 {
727         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
728                              INTR_INFO_VALID_MASK)) ==
729                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
730 }
731
732 static inline bool is_external_interrupt(u32 intr_info)
733 {
734         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
735                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
736 }
737
738 static inline bool is_machine_check(u32 intr_info)
739 {
740         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
741                              INTR_INFO_VALID_MASK)) ==
742                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
743 }
744
745 static inline bool cpu_has_vmx_msr_bitmap(void)
746 {
747         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
748 }
749
750 static inline bool cpu_has_vmx_tpr_shadow(void)
751 {
752         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
753 }
754
755 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
756 {
757         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
758 }
759
760 static inline bool cpu_has_secondary_exec_ctrls(void)
761 {
762         return vmcs_config.cpu_based_exec_ctrl &
763                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
764 }
765
766 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
767 {
768         return vmcs_config.cpu_based_2nd_exec_ctrl &
769                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
770 }
771
772 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
773 {
774         return vmcs_config.cpu_based_2nd_exec_ctrl &
775                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
776 }
777
778 static inline bool cpu_has_vmx_apic_register_virt(void)
779 {
780         return vmcs_config.cpu_based_2nd_exec_ctrl &
781                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
782 }
783
784 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
785 {
786         return vmcs_config.cpu_based_2nd_exec_ctrl &
787                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
788 }
789
790 static inline bool cpu_has_vmx_flexpriority(void)
791 {
792         return cpu_has_vmx_tpr_shadow() &&
793                 cpu_has_vmx_virtualize_apic_accesses();
794 }
795
796 static inline bool cpu_has_vmx_ept_execute_only(void)
797 {
798         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
799 }
800
801 static inline bool cpu_has_vmx_eptp_uncacheable(void)
802 {
803         return vmx_capability.ept & VMX_EPTP_UC_BIT;
804 }
805
806 static inline bool cpu_has_vmx_eptp_writeback(void)
807 {
808         return vmx_capability.ept & VMX_EPTP_WB_BIT;
809 }
810
811 static inline bool cpu_has_vmx_ept_2m_page(void)
812 {
813         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
814 }
815
816 static inline bool cpu_has_vmx_ept_1g_page(void)
817 {
818         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
819 }
820
821 static inline bool cpu_has_vmx_ept_4levels(void)
822 {
823         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
824 }
825
826 static inline bool cpu_has_vmx_ept_ad_bits(void)
827 {
828         return vmx_capability.ept & VMX_EPT_AD_BIT;
829 }
830
831 static inline bool cpu_has_vmx_invept_context(void)
832 {
833         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
834 }
835
836 static inline bool cpu_has_vmx_invept_global(void)
837 {
838         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
839 }
840
841 static inline bool cpu_has_vmx_invvpid_single(void)
842 {
843         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
844 }
845
846 static inline bool cpu_has_vmx_invvpid_global(void)
847 {
848         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
849 }
850
851 static inline bool cpu_has_vmx_ept(void)
852 {
853         return vmcs_config.cpu_based_2nd_exec_ctrl &
854                 SECONDARY_EXEC_ENABLE_EPT;
855 }
856
857 static inline bool cpu_has_vmx_unrestricted_guest(void)
858 {
859         return vmcs_config.cpu_based_2nd_exec_ctrl &
860                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
861 }
862
863 static inline bool cpu_has_vmx_ple(void)
864 {
865         return vmcs_config.cpu_based_2nd_exec_ctrl &
866                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
867 }
868
869 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
870 {
871         return flexpriority_enabled && irqchip_in_kernel(kvm);
872 }
873
874 static inline bool cpu_has_vmx_vpid(void)
875 {
876         return vmcs_config.cpu_based_2nd_exec_ctrl &
877                 SECONDARY_EXEC_ENABLE_VPID;
878 }
879
880 static inline bool cpu_has_vmx_rdtscp(void)
881 {
882         return vmcs_config.cpu_based_2nd_exec_ctrl &
883                 SECONDARY_EXEC_RDTSCP;
884 }
885
886 static inline bool cpu_has_vmx_invpcid(void)
887 {
888         return vmcs_config.cpu_based_2nd_exec_ctrl &
889                 SECONDARY_EXEC_ENABLE_INVPCID;
890 }
891
892 static inline bool cpu_has_virtual_nmis(void)
893 {
894         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
895 }
896
897 static inline bool cpu_has_vmx_wbinvd_exit(void)
898 {
899         return vmcs_config.cpu_based_2nd_exec_ctrl &
900                 SECONDARY_EXEC_WBINVD_EXITING;
901 }
902
903 static inline bool report_flexpriority(void)
904 {
905         return flexpriority_enabled;
906 }
907
908 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
909 {
910         return vmcs12->cpu_based_vm_exec_control & bit;
911 }
912
913 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
914 {
915         return (vmcs12->cpu_based_vm_exec_control &
916                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
917                 (vmcs12->secondary_vm_exec_control & bit);
918 }
919
920 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
921         struct kvm_vcpu *vcpu)
922 {
923         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
924 }
925
926 static inline bool is_exception(u32 intr_info)
927 {
928         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
929                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
930 }
931
932 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
933 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
934                         struct vmcs12 *vmcs12,
935                         u32 reason, unsigned long qualification);
936
937 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
938 {
939         int i;
940
941         for (i = 0; i < vmx->nmsrs; ++i)
942                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
943                         return i;
944         return -1;
945 }
946
947 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
948 {
949     struct {
950         u64 vpid : 16;
951         u64 rsvd : 48;
952         u64 gva;
953     } operand = { vpid, 0, gva };
954
955     asm volatile (__ex(ASM_VMX_INVVPID)
956                   /* CF==1 or ZF==1 --> rc = -1 */
957                   "; ja 1f ; ud2 ; 1:"
958                   : : "a"(&operand), "c"(ext) : "cc", "memory");
959 }
960
961 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
962 {
963         struct {
964                 u64 eptp, gpa;
965         } operand = {eptp, gpa};
966
967         asm volatile (__ex(ASM_VMX_INVEPT)
968                         /* CF==1 or ZF==1 --> rc = -1 */
969                         "; ja 1f ; ud2 ; 1:\n"
970                         : : "a" (&operand), "c" (ext) : "cc", "memory");
971 }
972
973 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
974 {
975         int i;
976
977         i = __find_msr_index(vmx, msr);
978         if (i >= 0)
979                 return &vmx->guest_msrs[i];
980         return NULL;
981 }
982
983 static void vmcs_clear(struct vmcs *vmcs)
984 {
985         u64 phys_addr = __pa(vmcs);
986         u8 error;
987
988         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
989                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
990                       : "cc", "memory");
991         if (error)
992                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
993                        vmcs, phys_addr);
994 }
995
996 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
997 {
998         vmcs_clear(loaded_vmcs->vmcs);
999         loaded_vmcs->cpu = -1;
1000         loaded_vmcs->launched = 0;
1001 }
1002
1003 static void vmcs_load(struct vmcs *vmcs)
1004 {
1005         u64 phys_addr = __pa(vmcs);
1006         u8 error;
1007
1008         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1009                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1010                         : "cc", "memory");
1011         if (error)
1012                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1013                        vmcs, phys_addr);
1014 }
1015
1016 #ifdef CONFIG_KEXEC
1017 /*
1018  * This bitmap is used to indicate whether the vmclear
1019  * operation is enabled on all cpus. All disabled by
1020  * default.
1021  */
1022 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1023
1024 static inline void crash_enable_local_vmclear(int cpu)
1025 {
1026         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1027 }
1028
1029 static inline void crash_disable_local_vmclear(int cpu)
1030 {
1031         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1032 }
1033
1034 static inline int crash_local_vmclear_enabled(int cpu)
1035 {
1036         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1037 }
1038
1039 static void crash_vmclear_local_loaded_vmcss(void)
1040 {
1041         int cpu = raw_smp_processor_id();
1042         struct loaded_vmcs *v;
1043
1044         if (!crash_local_vmclear_enabled(cpu))
1045                 return;
1046
1047         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1048                             loaded_vmcss_on_cpu_link)
1049                 vmcs_clear(v->vmcs);
1050 }
1051 #else
1052 static inline void crash_enable_local_vmclear(int cpu) { }
1053 static inline void crash_disable_local_vmclear(int cpu) { }
1054 #endif /* CONFIG_KEXEC */
1055
1056 static void __loaded_vmcs_clear(void *arg)
1057 {
1058         struct loaded_vmcs *loaded_vmcs = arg;
1059         int cpu = raw_smp_processor_id();
1060
1061         if (loaded_vmcs->cpu != cpu)
1062                 return; /* vcpu migration can race with cpu offline */
1063         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1064                 per_cpu(current_vmcs, cpu) = NULL;
1065         crash_disable_local_vmclear(cpu);
1066         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1067
1068         /*
1069          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1070          * is before setting loaded_vmcs->vcpu to -1 which is done in
1071          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1072          * then adds the vmcs into percpu list before it is deleted.
1073          */
1074         smp_wmb();
1075
1076         loaded_vmcs_init(loaded_vmcs);
1077         crash_enable_local_vmclear(cpu);
1078 }
1079
1080 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1081 {
1082         int cpu = loaded_vmcs->cpu;
1083
1084         if (cpu != -1)
1085                 smp_call_function_single(cpu,
1086                          __loaded_vmcs_clear, loaded_vmcs, 1);
1087 }
1088
1089 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1090 {
1091         if (vmx->vpid == 0)
1092                 return;
1093
1094         if (cpu_has_vmx_invvpid_single())
1095                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1096 }
1097
1098 static inline void vpid_sync_vcpu_global(void)
1099 {
1100         if (cpu_has_vmx_invvpid_global())
1101                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1102 }
1103
1104 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1105 {
1106         if (cpu_has_vmx_invvpid_single())
1107                 vpid_sync_vcpu_single(vmx);
1108         else
1109                 vpid_sync_vcpu_global();
1110 }
1111
1112 static inline void ept_sync_global(void)
1113 {
1114         if (cpu_has_vmx_invept_global())
1115                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1116 }
1117
1118 static inline void ept_sync_context(u64 eptp)
1119 {
1120         if (enable_ept) {
1121                 if (cpu_has_vmx_invept_context())
1122                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1123                 else
1124                         ept_sync_global();
1125         }
1126 }
1127
1128 static __always_inline unsigned long vmcs_readl(unsigned long field)
1129 {
1130         unsigned long value;
1131
1132         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1133                       : "=a"(value) : "d"(field) : "cc");
1134         return value;
1135 }
1136
1137 static __always_inline u16 vmcs_read16(unsigned long field)
1138 {
1139         return vmcs_readl(field);
1140 }
1141
1142 static __always_inline u32 vmcs_read32(unsigned long field)
1143 {
1144         return vmcs_readl(field);
1145 }
1146
1147 static __always_inline u64 vmcs_read64(unsigned long field)
1148 {
1149 #ifdef CONFIG_X86_64
1150         return vmcs_readl(field);
1151 #else
1152         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1153 #endif
1154 }
1155
1156 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1157 {
1158         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1159                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1160         dump_stack();
1161 }
1162
1163 static void vmcs_writel(unsigned long field, unsigned long value)
1164 {
1165         u8 error;
1166
1167         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1168                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1169         if (unlikely(error))
1170                 vmwrite_error(field, value);
1171 }
1172
1173 static void vmcs_write16(unsigned long field, u16 value)
1174 {
1175         vmcs_writel(field, value);
1176 }
1177
1178 static void vmcs_write32(unsigned long field, u32 value)
1179 {
1180         vmcs_writel(field, value);
1181 }
1182
1183 static void vmcs_write64(unsigned long field, u64 value)
1184 {
1185         vmcs_writel(field, value);
1186 #ifndef CONFIG_X86_64
1187         asm volatile ("");
1188         vmcs_writel(field+1, value >> 32);
1189 #endif
1190 }
1191
1192 static void vmcs_clear_bits(unsigned long field, u32 mask)
1193 {
1194         vmcs_writel(field, vmcs_readl(field) & ~mask);
1195 }
1196
1197 static void vmcs_set_bits(unsigned long field, u32 mask)
1198 {
1199         vmcs_writel(field, vmcs_readl(field) | mask);
1200 }
1201
1202 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1203 {
1204         vmx->segment_cache.bitmask = 0;
1205 }
1206
1207 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1208                                        unsigned field)
1209 {
1210         bool ret;
1211         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1212
1213         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1214                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1215                 vmx->segment_cache.bitmask = 0;
1216         }
1217         ret = vmx->segment_cache.bitmask & mask;
1218         vmx->segment_cache.bitmask |= mask;
1219         return ret;
1220 }
1221
1222 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1223 {
1224         u16 *p = &vmx->segment_cache.seg[seg].selector;
1225
1226         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1227                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1228         return *p;
1229 }
1230
1231 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1232 {
1233         ulong *p = &vmx->segment_cache.seg[seg].base;
1234
1235         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1236                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1237         return *p;
1238 }
1239
1240 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1241 {
1242         u32 *p = &vmx->segment_cache.seg[seg].limit;
1243
1244         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1245                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1246         return *p;
1247 }
1248
1249 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1250 {
1251         u32 *p = &vmx->segment_cache.seg[seg].ar;
1252
1253         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1254                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1255         return *p;
1256 }
1257
1258 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1259 {
1260         u32 eb;
1261
1262         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1263              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1264         if ((vcpu->guest_debug &
1265              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1266             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1267                 eb |= 1u << BP_VECTOR;
1268         if (to_vmx(vcpu)->rmode.vm86_active)
1269                 eb = ~0;
1270         if (enable_ept)
1271                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1272         if (vcpu->fpu_active)
1273                 eb &= ~(1u << NM_VECTOR);
1274
1275         /* When we are running a nested L2 guest and L1 specified for it a
1276          * certain exception bitmap, we must trap the same exceptions and pass
1277          * them to L1. When running L2, we will only handle the exceptions
1278          * specified above if L1 did not want them.
1279          */
1280         if (is_guest_mode(vcpu))
1281                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1282
1283         vmcs_write32(EXCEPTION_BITMAP, eb);
1284 }
1285
1286 static void clear_atomic_switch_msr_special(unsigned long entry,
1287                 unsigned long exit)
1288 {
1289         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1290         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1291 }
1292
1293 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1294 {
1295         unsigned i;
1296         struct msr_autoload *m = &vmx->msr_autoload;
1297
1298         switch (msr) {
1299         case MSR_EFER:
1300                 if (cpu_has_load_ia32_efer) {
1301                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1302                                         VM_EXIT_LOAD_IA32_EFER);
1303                         return;
1304                 }
1305                 break;
1306         case MSR_CORE_PERF_GLOBAL_CTRL:
1307                 if (cpu_has_load_perf_global_ctrl) {
1308                         clear_atomic_switch_msr_special(
1309                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1310                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1311                         return;
1312                 }
1313                 break;
1314         }
1315
1316         for (i = 0; i < m->nr; ++i)
1317                 if (m->guest[i].index == msr)
1318                         break;
1319
1320         if (i == m->nr)
1321                 return;
1322         --m->nr;
1323         m->guest[i] = m->guest[m->nr];
1324         m->host[i] = m->host[m->nr];
1325         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1326         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1327 }
1328
1329 static void add_atomic_switch_msr_special(unsigned long entry,
1330                 unsigned long exit, unsigned long guest_val_vmcs,
1331                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1332 {
1333         vmcs_write64(guest_val_vmcs, guest_val);
1334         vmcs_write64(host_val_vmcs, host_val);
1335         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1336         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1337 }
1338
1339 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1340                                   u64 guest_val, u64 host_val)
1341 {
1342         unsigned i;
1343         struct msr_autoload *m = &vmx->msr_autoload;
1344
1345         switch (msr) {
1346         case MSR_EFER:
1347                 if (cpu_has_load_ia32_efer) {
1348                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1349                                         VM_EXIT_LOAD_IA32_EFER,
1350                                         GUEST_IA32_EFER,
1351                                         HOST_IA32_EFER,
1352                                         guest_val, host_val);
1353                         return;
1354                 }
1355                 break;
1356         case MSR_CORE_PERF_GLOBAL_CTRL:
1357                 if (cpu_has_load_perf_global_ctrl) {
1358                         add_atomic_switch_msr_special(
1359                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1360                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1361                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1362                                         HOST_IA32_PERF_GLOBAL_CTRL,
1363                                         guest_val, host_val);
1364                         return;
1365                 }
1366                 break;
1367         }
1368
1369         for (i = 0; i < m->nr; ++i)
1370                 if (m->guest[i].index == msr)
1371                         break;
1372
1373         if (i == NR_AUTOLOAD_MSRS) {
1374                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1375                                 "Can't add msr %x\n", msr);
1376                 return;
1377         } else if (i == m->nr) {
1378                 ++m->nr;
1379                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1380                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1381         }
1382
1383         m->guest[i].index = msr;
1384         m->guest[i].value = guest_val;
1385         m->host[i].index = msr;
1386         m->host[i].value = host_val;
1387 }
1388
1389 static void reload_tss(void)
1390 {
1391         /*
1392          * VT restores TR but not its size.  Useless.
1393          */
1394         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1395         struct desc_struct *descs;
1396
1397         descs = (void *)gdt->address;
1398         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1399         load_TR_desc();
1400 }
1401
1402 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1403 {
1404         u64 guest_efer;
1405         u64 ignore_bits;
1406
1407         guest_efer = vmx->vcpu.arch.efer;
1408
1409         /*
1410          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1411          * outside long mode
1412          */
1413         ignore_bits = EFER_NX | EFER_SCE;
1414 #ifdef CONFIG_X86_64
1415         ignore_bits |= EFER_LMA | EFER_LME;
1416         /* SCE is meaningful only in long mode on Intel */
1417         if (guest_efer & EFER_LMA)
1418                 ignore_bits &= ~(u64)EFER_SCE;
1419 #endif
1420         guest_efer &= ~ignore_bits;
1421         guest_efer |= host_efer & ignore_bits;
1422         vmx->guest_msrs[efer_offset].data = guest_efer;
1423         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1424
1425         clear_atomic_switch_msr(vmx, MSR_EFER);
1426         /* On ept, can't emulate nx, and must switch nx atomically */
1427         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1428                 guest_efer = vmx->vcpu.arch.efer;
1429                 if (!(guest_efer & EFER_LMA))
1430                         guest_efer &= ~EFER_LME;
1431                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1432                 return false;
1433         }
1434
1435         return true;
1436 }
1437
1438 static unsigned long segment_base(u16 selector)
1439 {
1440         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1441         struct desc_struct *d;
1442         unsigned long table_base;
1443         unsigned long v;
1444
1445         if (!(selector & ~3))
1446                 return 0;
1447
1448         table_base = gdt->address;
1449
1450         if (selector & 4) {           /* from ldt */
1451                 u16 ldt_selector = kvm_read_ldt();
1452
1453                 if (!(ldt_selector & ~3))
1454                         return 0;
1455
1456                 table_base = segment_base(ldt_selector);
1457         }
1458         d = (struct desc_struct *)(table_base + (selector & ~7));
1459         v = get_desc_base(d);
1460 #ifdef CONFIG_X86_64
1461        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1462                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1463 #endif
1464         return v;
1465 }
1466
1467 static inline unsigned long kvm_read_tr_base(void)
1468 {
1469         u16 tr;
1470         asm("str %0" : "=g"(tr));
1471         return segment_base(tr);
1472 }
1473
1474 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1475 {
1476         struct vcpu_vmx *vmx = to_vmx(vcpu);
1477         int i;
1478
1479         if (vmx->host_state.loaded)
1480                 return;
1481
1482         vmx->host_state.loaded = 1;
1483         /*
1484          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1485          * allow segment selectors with cpl > 0 or ti == 1.
1486          */
1487         vmx->host_state.ldt_sel = kvm_read_ldt();
1488         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1489         savesegment(fs, vmx->host_state.fs_sel);
1490         if (!(vmx->host_state.fs_sel & 7)) {
1491                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1492                 vmx->host_state.fs_reload_needed = 0;
1493         } else {
1494                 vmcs_write16(HOST_FS_SELECTOR, 0);
1495                 vmx->host_state.fs_reload_needed = 1;
1496         }
1497         savesegment(gs, vmx->host_state.gs_sel);
1498         if (!(vmx->host_state.gs_sel & 7))
1499                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1500         else {
1501                 vmcs_write16(HOST_GS_SELECTOR, 0);
1502                 vmx->host_state.gs_ldt_reload_needed = 1;
1503         }
1504
1505 #ifdef CONFIG_X86_64
1506         savesegment(ds, vmx->host_state.ds_sel);
1507         savesegment(es, vmx->host_state.es_sel);
1508 #endif
1509
1510 #ifdef CONFIG_X86_64
1511         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1512         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1513 #else
1514         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1515         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1516 #endif
1517
1518 #ifdef CONFIG_X86_64
1519         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1520         if (is_long_mode(&vmx->vcpu))
1521                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1522 #endif
1523         for (i = 0; i < vmx->save_nmsrs; ++i)
1524                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1525                                    vmx->guest_msrs[i].data,
1526                                    vmx->guest_msrs[i].mask);
1527 }
1528
1529 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1530 {
1531         if (!vmx->host_state.loaded)
1532                 return;
1533
1534         ++vmx->vcpu.stat.host_state_reload;
1535         vmx->host_state.loaded = 0;
1536 #ifdef CONFIG_X86_64
1537         if (is_long_mode(&vmx->vcpu))
1538                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1539 #endif
1540         if (vmx->host_state.gs_ldt_reload_needed) {
1541                 kvm_load_ldt(vmx->host_state.ldt_sel);
1542 #ifdef CONFIG_X86_64
1543                 load_gs_index(vmx->host_state.gs_sel);
1544 #else
1545                 loadsegment(gs, vmx->host_state.gs_sel);
1546 #endif
1547         }
1548         if (vmx->host_state.fs_reload_needed)
1549                 loadsegment(fs, vmx->host_state.fs_sel);
1550 #ifdef CONFIG_X86_64
1551         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1552                 loadsegment(ds, vmx->host_state.ds_sel);
1553                 loadsegment(es, vmx->host_state.es_sel);
1554         }
1555 #endif
1556         reload_tss();
1557 #ifdef CONFIG_X86_64
1558         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1559 #endif
1560         /*
1561          * If the FPU is not active (through the host task or
1562          * the guest vcpu), then restore the cr0.TS bit.
1563          */
1564         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1565                 stts();
1566         load_gdt(&__get_cpu_var(host_gdt));
1567 }
1568
1569 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1570 {
1571         preempt_disable();
1572         __vmx_load_host_state(vmx);
1573         preempt_enable();
1574 }
1575
1576 /*
1577  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1578  * vcpu mutex is already taken.
1579  */
1580 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1581 {
1582         struct vcpu_vmx *vmx = to_vmx(vcpu);
1583         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1584
1585         if (!vmm_exclusive)
1586                 kvm_cpu_vmxon(phys_addr);
1587         else if (vmx->loaded_vmcs->cpu != cpu)
1588                 loaded_vmcs_clear(vmx->loaded_vmcs);
1589
1590         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1591                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1592                 vmcs_load(vmx->loaded_vmcs->vmcs);
1593         }
1594
1595         if (vmx->loaded_vmcs->cpu != cpu) {
1596                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1597                 unsigned long sysenter_esp;
1598
1599                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1600                 local_irq_disable();
1601                 crash_disable_local_vmclear(cpu);
1602
1603                 /*
1604                  * Read loaded_vmcs->cpu should be before fetching
1605                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1606                  * See the comments in __loaded_vmcs_clear().
1607                  */
1608                 smp_rmb();
1609
1610                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1611                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1612                 crash_enable_local_vmclear(cpu);
1613                 local_irq_enable();
1614
1615                 /*
1616                  * Linux uses per-cpu TSS and GDT, so set these when switching
1617                  * processors.
1618                  */
1619                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1620                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1621
1622                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1623                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1624                 vmx->loaded_vmcs->cpu = cpu;
1625         }
1626 }
1627
1628 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1629 {
1630         __vmx_load_host_state(to_vmx(vcpu));
1631         if (!vmm_exclusive) {
1632                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1633                 vcpu->cpu = -1;
1634                 kvm_cpu_vmxoff();
1635         }
1636 }
1637
1638 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1639 {
1640         ulong cr0;
1641
1642         if (vcpu->fpu_active)
1643                 return;
1644         vcpu->fpu_active = 1;
1645         cr0 = vmcs_readl(GUEST_CR0);
1646         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1647         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1648         vmcs_writel(GUEST_CR0, cr0);
1649         update_exception_bitmap(vcpu);
1650         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1651         if (is_guest_mode(vcpu))
1652                 vcpu->arch.cr0_guest_owned_bits &=
1653                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1654         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1655 }
1656
1657 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1658
1659 /*
1660  * Return the cr0 value that a nested guest would read. This is a combination
1661  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1662  * its hypervisor (cr0_read_shadow).
1663  */
1664 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1665 {
1666         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1667                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1668 }
1669 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1670 {
1671         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1672                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1673 }
1674
1675 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1676 {
1677         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1678          * set this *before* calling this function.
1679          */
1680         vmx_decache_cr0_guest_bits(vcpu);
1681         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1682         update_exception_bitmap(vcpu);
1683         vcpu->arch.cr0_guest_owned_bits = 0;
1684         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1685         if (is_guest_mode(vcpu)) {
1686                 /*
1687                  * L1's specified read shadow might not contain the TS bit,
1688                  * so now that we turned on shadowing of this bit, we need to
1689                  * set this bit of the shadow. Like in nested_vmx_run we need
1690                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1691                  * up-to-date here because we just decached cr0.TS (and we'll
1692                  * only update vmcs12->guest_cr0 on nested exit).
1693                  */
1694                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1695                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1696                         (vcpu->arch.cr0 & X86_CR0_TS);
1697                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1698         } else
1699                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1700 }
1701
1702 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1703 {
1704         unsigned long rflags, save_rflags;
1705
1706         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1707                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1708                 rflags = vmcs_readl(GUEST_RFLAGS);
1709                 if (to_vmx(vcpu)->rmode.vm86_active) {
1710                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1711                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1712                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1713                 }
1714                 to_vmx(vcpu)->rflags = rflags;
1715         }
1716         return to_vmx(vcpu)->rflags;
1717 }
1718
1719 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1720 {
1721         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1722         to_vmx(vcpu)->rflags = rflags;
1723         if (to_vmx(vcpu)->rmode.vm86_active) {
1724                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1725                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1726         }
1727         vmcs_writel(GUEST_RFLAGS, rflags);
1728 }
1729
1730 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1731 {
1732         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1733         int ret = 0;
1734
1735         if (interruptibility & GUEST_INTR_STATE_STI)
1736                 ret |= KVM_X86_SHADOW_INT_STI;
1737         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1738                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1739
1740         return ret & mask;
1741 }
1742
1743 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1744 {
1745         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1746         u32 interruptibility = interruptibility_old;
1747
1748         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1749
1750         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1751                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1752         else if (mask & KVM_X86_SHADOW_INT_STI)
1753                 interruptibility |= GUEST_INTR_STATE_STI;
1754
1755         if ((interruptibility != interruptibility_old))
1756                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1757 }
1758
1759 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1760 {
1761         unsigned long rip;
1762
1763         rip = kvm_rip_read(vcpu);
1764         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1765         kvm_rip_write(vcpu, rip);
1766
1767         /* skipping an emulated instruction also counts */
1768         vmx_set_interrupt_shadow(vcpu, 0);
1769 }
1770
1771 /*
1772  * KVM wants to inject page-faults which it got to the guest. This function
1773  * checks whether in a nested guest, we need to inject them to L1 or L2.
1774  * This function assumes it is called with the exit reason in vmcs02 being
1775  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1776  * is running).
1777  */
1778 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1779 {
1780         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1781
1782         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1783         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1784                 return 0;
1785
1786         nested_vmx_vmexit(vcpu);
1787         return 1;
1788 }
1789
1790 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1791                                 bool has_error_code, u32 error_code,
1792                                 bool reinject)
1793 {
1794         struct vcpu_vmx *vmx = to_vmx(vcpu);
1795         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1796
1797         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1798                 nested_pf_handled(vcpu))
1799                 return;
1800
1801         if (has_error_code) {
1802                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1803                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1804         }
1805
1806         if (vmx->rmode.vm86_active) {
1807                 int inc_eip = 0;
1808                 if (kvm_exception_is_soft(nr))
1809                         inc_eip = vcpu->arch.event_exit_inst_len;
1810                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1811                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1812                 return;
1813         }
1814
1815         if (kvm_exception_is_soft(nr)) {
1816                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1817                              vmx->vcpu.arch.event_exit_inst_len);
1818                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1819         } else
1820                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1821
1822         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1823 }
1824
1825 static bool vmx_rdtscp_supported(void)
1826 {
1827         return cpu_has_vmx_rdtscp();
1828 }
1829
1830 static bool vmx_invpcid_supported(void)
1831 {
1832         return cpu_has_vmx_invpcid() && enable_ept;
1833 }
1834
1835 /*
1836  * Swap MSR entry in host/guest MSR entry array.
1837  */
1838 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1839 {
1840         struct shared_msr_entry tmp;
1841
1842         tmp = vmx->guest_msrs[to];
1843         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1844         vmx->guest_msrs[from] = tmp;
1845 }
1846
1847 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1848 {
1849         unsigned long *msr_bitmap;
1850
1851         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1852                 if (is_long_mode(vcpu))
1853                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1854                 else
1855                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1856         } else {
1857                 if (is_long_mode(vcpu))
1858                         msr_bitmap = vmx_msr_bitmap_longmode;
1859                 else
1860                         msr_bitmap = vmx_msr_bitmap_legacy;
1861         }
1862
1863         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1864 }
1865
1866 /*
1867  * Set up the vmcs to automatically save and restore system
1868  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1869  * mode, as fiddling with msrs is very expensive.
1870  */
1871 static void setup_msrs(struct vcpu_vmx *vmx)
1872 {
1873         int save_nmsrs, index;
1874
1875         save_nmsrs = 0;
1876 #ifdef CONFIG_X86_64
1877         if (is_long_mode(&vmx->vcpu)) {
1878                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1879                 if (index >= 0)
1880                         move_msr_up(vmx, index, save_nmsrs++);
1881                 index = __find_msr_index(vmx, MSR_LSTAR);
1882                 if (index >= 0)
1883                         move_msr_up(vmx, index, save_nmsrs++);
1884                 index = __find_msr_index(vmx, MSR_CSTAR);
1885                 if (index >= 0)
1886                         move_msr_up(vmx, index, save_nmsrs++);
1887                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1888                 if (index >= 0 && vmx->rdtscp_enabled)
1889                         move_msr_up(vmx, index, save_nmsrs++);
1890                 /*
1891                  * MSR_STAR is only needed on long mode guests, and only
1892                  * if efer.sce is enabled.
1893                  */
1894                 index = __find_msr_index(vmx, MSR_STAR);
1895                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1896                         move_msr_up(vmx, index, save_nmsrs++);
1897         }
1898 #endif
1899         index = __find_msr_index(vmx, MSR_EFER);
1900         if (index >= 0 && update_transition_efer(vmx, index))
1901                 move_msr_up(vmx, index, save_nmsrs++);
1902
1903         vmx->save_nmsrs = save_nmsrs;
1904
1905         if (cpu_has_vmx_msr_bitmap())
1906                 vmx_set_msr_bitmap(&vmx->vcpu);
1907 }
1908
1909 /*
1910  * reads and returns guest's timestamp counter "register"
1911  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1912  */
1913 static u64 guest_read_tsc(void)
1914 {
1915         u64 host_tsc, tsc_offset;
1916
1917         rdtscll(host_tsc);
1918         tsc_offset = vmcs_read64(TSC_OFFSET);
1919         return host_tsc + tsc_offset;
1920 }
1921
1922 /*
1923  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1924  * counter, even if a nested guest (L2) is currently running.
1925  */
1926 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1927 {
1928         u64 tsc_offset;
1929
1930         tsc_offset = is_guest_mode(vcpu) ?
1931                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1932                 vmcs_read64(TSC_OFFSET);
1933         return host_tsc + tsc_offset;
1934 }
1935
1936 /*
1937  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1938  * software catchup for faster rates on slower CPUs.
1939  */
1940 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1941 {
1942         if (!scale)
1943                 return;
1944
1945         if (user_tsc_khz > tsc_khz) {
1946                 vcpu->arch.tsc_catchup = 1;
1947                 vcpu->arch.tsc_always_catchup = 1;
1948         } else
1949                 WARN(1, "user requested TSC rate below hardware speed\n");
1950 }
1951
1952 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1953 {
1954         return vmcs_read64(TSC_OFFSET);
1955 }
1956
1957 /*
1958  * writes 'offset' into guest's timestamp counter offset register
1959  */
1960 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1961 {
1962         if (is_guest_mode(vcpu)) {
1963                 /*
1964                  * We're here if L1 chose not to trap WRMSR to TSC. According
1965                  * to the spec, this should set L1's TSC; The offset that L1
1966                  * set for L2 remains unchanged, and still needs to be added
1967                  * to the newly set TSC to get L2's TSC.
1968                  */
1969                 struct vmcs12 *vmcs12;
1970                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1971                 /* recalculate vmcs02.TSC_OFFSET: */
1972                 vmcs12 = get_vmcs12(vcpu);
1973                 vmcs_write64(TSC_OFFSET, offset +
1974                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1975                          vmcs12->tsc_offset : 0));
1976         } else {
1977                 vmcs_write64(TSC_OFFSET, offset);
1978         }
1979 }
1980
1981 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1982 {
1983         u64 offset = vmcs_read64(TSC_OFFSET);
1984         vmcs_write64(TSC_OFFSET, offset + adjustment);
1985         if (is_guest_mode(vcpu)) {
1986                 /* Even when running L2, the adjustment needs to apply to L1 */
1987                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1988         }
1989 }
1990
1991 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1992 {
1993         return target_tsc - native_read_tsc();
1994 }
1995
1996 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1997 {
1998         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1999         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2000 }
2001
2002 /*
2003  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2004  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2005  * all guests if the "nested" module option is off, and can also be disabled
2006  * for a single guest by disabling its VMX cpuid bit.
2007  */
2008 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2009 {
2010         return nested && guest_cpuid_has_vmx(vcpu);
2011 }
2012
2013 /*
2014  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2015  * returned for the various VMX controls MSRs when nested VMX is enabled.
2016  * The same values should also be used to verify that vmcs12 control fields are
2017  * valid during nested entry from L1 to L2.
2018  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2019  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2020  * bit in the high half is on if the corresponding bit in the control field
2021  * may be on. See also vmx_control_verify().
2022  * TODO: allow these variables to be modified (downgraded) by module options
2023  * or other means.
2024  */
2025 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2026 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2027 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2028 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2029 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2030 static __init void nested_vmx_setup_ctls_msrs(void)
2031 {
2032         /*
2033          * Note that as a general rule, the high half of the MSRs (bits in
2034          * the control fields which may be 1) should be initialized by the
2035          * intersection of the underlying hardware's MSR (i.e., features which
2036          * can be supported) and the list of features we want to expose -
2037          * because they are known to be properly supported in our code.
2038          * Also, usually, the low half of the MSRs (bits which must be 1) can
2039          * be set to 0, meaning that L1 may turn off any of these bits. The
2040          * reason is that if one of these bits is necessary, it will appear
2041          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2042          * fields of vmcs01 and vmcs02, will turn these bits off - and
2043          * nested_vmx_exit_handled() will not pass related exits to L1.
2044          * These rules have exceptions below.
2045          */
2046
2047         /* pin-based controls */
2048         /*
2049          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2050          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2051          */
2052         nested_vmx_pinbased_ctls_low = 0x16 ;
2053         nested_vmx_pinbased_ctls_high = 0x16 |
2054                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
2055                 PIN_BASED_VIRTUAL_NMIS;
2056
2057         /* exit controls */
2058         nested_vmx_exit_ctls_low = 0;
2059         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2060 #ifdef CONFIG_X86_64
2061         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2062 #else
2063         nested_vmx_exit_ctls_high = 0;
2064 #endif
2065
2066         /* entry controls */
2067         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2068                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2069         nested_vmx_entry_ctls_low = 0;
2070         nested_vmx_entry_ctls_high &=
2071                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2072
2073         /* cpu-based controls */
2074         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2075                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2076         nested_vmx_procbased_ctls_low = 0;
2077         nested_vmx_procbased_ctls_high &=
2078                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2079                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2080                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2081                 CPU_BASED_CR3_STORE_EXITING |
2082 #ifdef CONFIG_X86_64
2083                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2084 #endif
2085                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2086                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2087                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2088                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2089         /*
2090          * We can allow some features even when not supported by the
2091          * hardware. For example, L1 can specify an MSR bitmap - and we
2092          * can use it to avoid exits to L1 - even when L0 runs L2
2093          * without MSR bitmaps.
2094          */
2095         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2096
2097         /* secondary cpu-based controls */
2098         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2099                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2100         nested_vmx_secondary_ctls_low = 0;
2101         nested_vmx_secondary_ctls_high &=
2102                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2103 }
2104
2105 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2106 {
2107         /*
2108          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2109          */
2110         return ((control & high) | low) == control;
2111 }
2112
2113 static inline u64 vmx_control_msr(u32 low, u32 high)
2114 {
2115         return low | ((u64)high << 32);
2116 }
2117
2118 /*
2119  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2120  * also let it use VMX-specific MSRs.
2121  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2122  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2123  * like all other MSRs).
2124  */
2125 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2126 {
2127         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2128                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2129                 /*
2130                  * According to the spec, processors which do not support VMX
2131                  * should throw a #GP(0) when VMX capability MSRs are read.
2132                  */
2133                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2134                 return 1;
2135         }
2136
2137         switch (msr_index) {
2138         case MSR_IA32_FEATURE_CONTROL:
2139                 *pdata = 0;
2140                 break;
2141         case MSR_IA32_VMX_BASIC:
2142                 /*
2143                  * This MSR reports some information about VMX support. We
2144                  * should return information about the VMX we emulate for the
2145                  * guest, and the VMCS structure we give it - not about the
2146                  * VMX support of the underlying hardware.
2147                  */
2148                 *pdata = VMCS12_REVISION |
2149                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2150                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2151                 break;
2152         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2153         case MSR_IA32_VMX_PINBASED_CTLS:
2154                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2155                                         nested_vmx_pinbased_ctls_high);
2156                 break;
2157         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2158         case MSR_IA32_VMX_PROCBASED_CTLS:
2159                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2160                                         nested_vmx_procbased_ctls_high);
2161                 break;
2162         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2163         case MSR_IA32_VMX_EXIT_CTLS:
2164                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2165                                         nested_vmx_exit_ctls_high);
2166                 break;
2167         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2168         case MSR_IA32_VMX_ENTRY_CTLS:
2169                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2170                                         nested_vmx_entry_ctls_high);
2171                 break;
2172         case MSR_IA32_VMX_MISC:
2173                 *pdata = 0;
2174                 break;
2175         /*
2176          * These MSRs specify bits which the guest must keep fixed (on or off)
2177          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2178          * We picked the standard core2 setting.
2179          */
2180 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2181 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2182         case MSR_IA32_VMX_CR0_FIXED0:
2183                 *pdata = VMXON_CR0_ALWAYSON;
2184                 break;
2185         case MSR_IA32_VMX_CR0_FIXED1:
2186                 *pdata = -1ULL;
2187                 break;
2188         case MSR_IA32_VMX_CR4_FIXED0:
2189                 *pdata = VMXON_CR4_ALWAYSON;
2190                 break;
2191         case MSR_IA32_VMX_CR4_FIXED1:
2192                 *pdata = -1ULL;
2193                 break;
2194         case MSR_IA32_VMX_VMCS_ENUM:
2195                 *pdata = 0x1f;
2196                 break;
2197         case MSR_IA32_VMX_PROCBASED_CTLS2:
2198                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2199                                         nested_vmx_secondary_ctls_high);
2200                 break;
2201         case MSR_IA32_VMX_EPT_VPID_CAP:
2202                 /* Currently, no nested ept or nested vpid */
2203                 *pdata = 0;
2204                 break;
2205         default:
2206                 return 0;
2207         }
2208
2209         return 1;
2210 }
2211
2212 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2213 {
2214         if (!nested_vmx_allowed(vcpu))
2215                 return 0;
2216
2217         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2218                 /* TODO: the right thing. */
2219                 return 1;
2220         /*
2221          * No need to treat VMX capability MSRs specially: If we don't handle
2222          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2223          */
2224         return 0;
2225 }
2226
2227 /*
2228  * Reads an msr value (of 'msr_index') into 'pdata'.
2229  * Returns 0 on success, non-0 otherwise.
2230  * Assumes vcpu_load() was already called.
2231  */
2232 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2233 {
2234         u64 data;
2235         struct shared_msr_entry *msr;
2236
2237         if (!pdata) {
2238                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2239                 return -EINVAL;
2240         }
2241
2242         switch (msr_index) {
2243 #ifdef CONFIG_X86_64
2244         case MSR_FS_BASE:
2245                 data = vmcs_readl(GUEST_FS_BASE);
2246                 break;
2247         case MSR_GS_BASE:
2248                 data = vmcs_readl(GUEST_GS_BASE);
2249                 break;
2250         case MSR_KERNEL_GS_BASE:
2251                 vmx_load_host_state(to_vmx(vcpu));
2252                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2253                 break;
2254 #endif
2255         case MSR_EFER:
2256                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2257         case MSR_IA32_TSC:
2258                 data = guest_read_tsc();
2259                 break;
2260         case MSR_IA32_SYSENTER_CS:
2261                 data = vmcs_read32(GUEST_SYSENTER_CS);
2262                 break;
2263         case MSR_IA32_SYSENTER_EIP:
2264                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2265                 break;
2266         case MSR_IA32_SYSENTER_ESP:
2267                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2268                 break;
2269         case MSR_TSC_AUX:
2270                 if (!to_vmx(vcpu)->rdtscp_enabled)
2271                         return 1;
2272                 /* Otherwise falls through */
2273         default:
2274                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2275                         return 0;
2276                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2277                 if (msr) {
2278                         data = msr->data;
2279                         break;
2280                 }
2281                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2282         }
2283
2284         *pdata = data;
2285         return 0;
2286 }
2287
2288 /*
2289  * Writes msr value into into the appropriate "register".
2290  * Returns 0 on success, non-0 otherwise.
2291  * Assumes vcpu_load() was already called.
2292  */
2293 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2294 {
2295         struct vcpu_vmx *vmx = to_vmx(vcpu);
2296         struct shared_msr_entry *msr;
2297         int ret = 0;
2298         u32 msr_index = msr_info->index;
2299         u64 data = msr_info->data;
2300
2301         switch (msr_index) {
2302         case MSR_EFER:
2303                 ret = kvm_set_msr_common(vcpu, msr_info);
2304                 break;
2305 #ifdef CONFIG_X86_64
2306         case MSR_FS_BASE:
2307                 vmx_segment_cache_clear(vmx);
2308                 vmcs_writel(GUEST_FS_BASE, data);
2309                 break;
2310         case MSR_GS_BASE:
2311                 vmx_segment_cache_clear(vmx);
2312                 vmcs_writel(GUEST_GS_BASE, data);
2313                 break;
2314         case MSR_KERNEL_GS_BASE:
2315                 vmx_load_host_state(vmx);
2316                 vmx->msr_guest_kernel_gs_base = data;
2317                 break;
2318 #endif
2319         case MSR_IA32_SYSENTER_CS:
2320                 vmcs_write32(GUEST_SYSENTER_CS, data);
2321                 break;
2322         case MSR_IA32_SYSENTER_EIP:
2323                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2324                 break;
2325         case MSR_IA32_SYSENTER_ESP:
2326                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2327                 break;
2328         case MSR_IA32_TSC:
2329                 kvm_write_tsc(vcpu, msr_info);
2330                 break;
2331         case MSR_IA32_CR_PAT:
2332                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2333                         vmcs_write64(GUEST_IA32_PAT, data);
2334                         vcpu->arch.pat = data;
2335                         break;
2336                 }
2337                 ret = kvm_set_msr_common(vcpu, msr_info);
2338                 break;
2339         case MSR_IA32_TSC_ADJUST:
2340                 ret = kvm_set_msr_common(vcpu, msr_info);
2341                 break;
2342         case MSR_TSC_AUX:
2343                 if (!vmx->rdtscp_enabled)
2344                         return 1;
2345                 /* Check reserved bit, higher 32 bits should be zero */
2346                 if ((data >> 32) != 0)
2347                         return 1;
2348                 /* Otherwise falls through */
2349         default:
2350                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2351                         break;
2352                 msr = find_msr_entry(vmx, msr_index);
2353                 if (msr) {
2354                         msr->data = data;
2355                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2356                                 preempt_disable();
2357                                 kvm_set_shared_msr(msr->index, msr->data,
2358                                                    msr->mask);
2359                                 preempt_enable();
2360                         }
2361                         break;
2362                 }
2363                 ret = kvm_set_msr_common(vcpu, msr_info);
2364         }
2365
2366         return ret;
2367 }
2368
2369 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2370 {
2371         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2372         switch (reg) {
2373         case VCPU_REGS_RSP:
2374                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2375                 break;
2376         case VCPU_REGS_RIP:
2377                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2378                 break;
2379         case VCPU_EXREG_PDPTR:
2380                 if (enable_ept)
2381                         ept_save_pdptrs(vcpu);
2382                 break;
2383         default:
2384                 break;
2385         }
2386 }
2387
2388 static __init int cpu_has_kvm_support(void)
2389 {
2390         return cpu_has_vmx();
2391 }
2392
2393 static __init int vmx_disabled_by_bios(void)
2394 {
2395         u64 msr;
2396
2397         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2398         if (msr & FEATURE_CONTROL_LOCKED) {
2399                 /* launched w/ TXT and VMX disabled */
2400                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2401                         && tboot_enabled())
2402                         return 1;
2403                 /* launched w/o TXT and VMX only enabled w/ TXT */
2404                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2405                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2406                         && !tboot_enabled()) {
2407                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2408                                 "activate TXT before enabling KVM\n");
2409                         return 1;
2410                 }
2411                 /* launched w/o TXT and VMX disabled */
2412                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2413                         && !tboot_enabled())
2414                         return 1;
2415         }
2416
2417         return 0;
2418 }
2419
2420 static void kvm_cpu_vmxon(u64 addr)
2421 {
2422         asm volatile (ASM_VMX_VMXON_RAX
2423                         : : "a"(&addr), "m"(addr)
2424                         : "memory", "cc");
2425 }
2426
2427 static int hardware_enable(void *garbage)
2428 {
2429         int cpu = raw_smp_processor_id();
2430         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2431         u64 old, test_bits;
2432
2433         if (read_cr4() & X86_CR4_VMXE)
2434                 return -EBUSY;
2435
2436         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2437
2438         /*
2439          * Now we can enable the vmclear operation in kdump
2440          * since the loaded_vmcss_on_cpu list on this cpu
2441          * has been initialized.
2442          *
2443          * Though the cpu is not in VMX operation now, there
2444          * is no problem to enable the vmclear operation
2445          * for the loaded_vmcss_on_cpu list is empty!
2446          */
2447         crash_enable_local_vmclear(cpu);
2448
2449         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2450
2451         test_bits = FEATURE_CONTROL_LOCKED;
2452         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2453         if (tboot_enabled())
2454                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2455
2456         if ((old & test_bits) != test_bits) {
2457                 /* enable and lock */
2458                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2459         }
2460         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2461
2462         if (vmm_exclusive) {
2463                 kvm_cpu_vmxon(phys_addr);
2464                 ept_sync_global();
2465         }
2466
2467         store_gdt(&__get_cpu_var(host_gdt));
2468
2469         return 0;
2470 }
2471
2472 static void vmclear_local_loaded_vmcss(void)
2473 {
2474         int cpu = raw_smp_processor_id();
2475         struct loaded_vmcs *v, *n;
2476
2477         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2478                                  loaded_vmcss_on_cpu_link)
2479                 __loaded_vmcs_clear(v);
2480 }
2481
2482
2483 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2484  * tricks.
2485  */
2486 static void kvm_cpu_vmxoff(void)
2487 {
2488         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2489 }
2490
2491 static void hardware_disable(void *garbage)
2492 {
2493         if (vmm_exclusive) {
2494                 vmclear_local_loaded_vmcss();
2495                 kvm_cpu_vmxoff();
2496         }
2497         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2498 }
2499
2500 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2501                                       u32 msr, u32 *result)
2502 {
2503         u32 vmx_msr_low, vmx_msr_high;
2504         u32 ctl = ctl_min | ctl_opt;
2505
2506         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2507
2508         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2509         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2510
2511         /* Ensure minimum (required) set of control bits are supported. */
2512         if (ctl_min & ~ctl)
2513                 return -EIO;
2514
2515         *result = ctl;
2516         return 0;
2517 }
2518
2519 static __init bool allow_1_setting(u32 msr, u32 ctl)
2520 {
2521         u32 vmx_msr_low, vmx_msr_high;
2522
2523         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2524         return vmx_msr_high & ctl;
2525 }
2526
2527 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2528 {
2529         u32 vmx_msr_low, vmx_msr_high;
2530         u32 min, opt, min2, opt2;
2531         u32 _pin_based_exec_control = 0;
2532         u32 _cpu_based_exec_control = 0;
2533         u32 _cpu_based_2nd_exec_control = 0;
2534         u32 _vmexit_control = 0;
2535         u32 _vmentry_control = 0;
2536
2537         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2538         opt = PIN_BASED_VIRTUAL_NMIS;
2539         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2540                                 &_pin_based_exec_control) < 0)
2541                 return -EIO;
2542
2543         min = CPU_BASED_HLT_EXITING |
2544 #ifdef CONFIG_X86_64
2545               CPU_BASED_CR8_LOAD_EXITING |
2546               CPU_BASED_CR8_STORE_EXITING |
2547 #endif
2548               CPU_BASED_CR3_LOAD_EXITING |
2549               CPU_BASED_CR3_STORE_EXITING |
2550               CPU_BASED_USE_IO_BITMAPS |
2551               CPU_BASED_MOV_DR_EXITING |
2552               CPU_BASED_USE_TSC_OFFSETING |
2553               CPU_BASED_MWAIT_EXITING |
2554               CPU_BASED_MONITOR_EXITING |
2555               CPU_BASED_INVLPG_EXITING |
2556               CPU_BASED_RDPMC_EXITING;
2557
2558         opt = CPU_BASED_TPR_SHADOW |
2559               CPU_BASED_USE_MSR_BITMAPS |
2560               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2561         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2562                                 &_cpu_based_exec_control) < 0)
2563                 return -EIO;
2564 #ifdef CONFIG_X86_64
2565         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2566                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2567                                            ~CPU_BASED_CR8_STORE_EXITING;
2568 #endif
2569         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2570                 min2 = 0;
2571                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2572                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2573                         SECONDARY_EXEC_WBINVD_EXITING |
2574                         SECONDARY_EXEC_ENABLE_VPID |
2575                         SECONDARY_EXEC_ENABLE_EPT |
2576                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2577                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2578                         SECONDARY_EXEC_RDTSCP |
2579                         SECONDARY_EXEC_ENABLE_INVPCID |
2580                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2581                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
2582                 if (adjust_vmx_controls(min2, opt2,
2583                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2584                                         &_cpu_based_2nd_exec_control) < 0)
2585                         return -EIO;
2586         }
2587 #ifndef CONFIG_X86_64
2588         if (!(_cpu_based_2nd_exec_control &
2589                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2590                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2591 #endif
2592
2593         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2594                 _cpu_based_2nd_exec_control &= ~(
2595                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2596                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2597                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2598
2599         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2600                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2601                    enabled */
2602                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2603                                              CPU_BASED_CR3_STORE_EXITING |
2604                                              CPU_BASED_INVLPG_EXITING);
2605                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2606                       vmx_capability.ept, vmx_capability.vpid);
2607         }
2608
2609         min = 0;
2610 #ifdef CONFIG_X86_64
2611         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2612 #endif
2613         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2614         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2615                                 &_vmexit_control) < 0)
2616                 return -EIO;
2617
2618         min = 0;
2619         opt = VM_ENTRY_LOAD_IA32_PAT;
2620         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2621                                 &_vmentry_control) < 0)
2622                 return -EIO;
2623
2624         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2625
2626         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2627         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2628                 return -EIO;
2629
2630 #ifdef CONFIG_X86_64
2631         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2632         if (vmx_msr_high & (1u<<16))
2633                 return -EIO;
2634 #endif
2635
2636         /* Require Write-Back (WB) memory type for VMCS accesses. */
2637         if (((vmx_msr_high >> 18) & 15) != 6)
2638                 return -EIO;
2639
2640         vmcs_conf->size = vmx_msr_high & 0x1fff;
2641         vmcs_conf->order = get_order(vmcs_config.size);
2642         vmcs_conf->revision_id = vmx_msr_low;
2643
2644         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2645         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2646         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2647         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2648         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2649
2650         cpu_has_load_ia32_efer =
2651                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2652                                 VM_ENTRY_LOAD_IA32_EFER)
2653                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2654                                    VM_EXIT_LOAD_IA32_EFER);
2655
2656         cpu_has_load_perf_global_ctrl =
2657                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2658                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2659                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2660                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2661
2662         /*
2663          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2664          * but due to arrata below it can't be used. Workaround is to use
2665          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2666          *
2667          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2668          *
2669          * AAK155             (model 26)
2670          * AAP115             (model 30)
2671          * AAT100             (model 37)
2672          * BC86,AAY89,BD102   (model 44)
2673          * BA97               (model 46)
2674          *
2675          */
2676         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2677                 switch (boot_cpu_data.x86_model) {
2678                 case 26:
2679                 case 30:
2680                 case 37:
2681                 case 44:
2682                 case 46:
2683                         cpu_has_load_perf_global_ctrl = false;
2684                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2685                                         "does not work properly. Using workaround\n");
2686                         break;
2687                 default:
2688                         break;
2689                 }
2690         }
2691
2692         return 0;
2693 }
2694
2695 static struct vmcs *alloc_vmcs_cpu(int cpu)
2696 {
2697         int node = cpu_to_node(cpu);
2698         struct page *pages;
2699         struct vmcs *vmcs;
2700
2701         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2702         if (!pages)
2703                 return NULL;
2704         vmcs = page_address(pages);
2705         memset(vmcs, 0, vmcs_config.size);
2706         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2707         return vmcs;
2708 }
2709
2710 static struct vmcs *alloc_vmcs(void)
2711 {
2712         return alloc_vmcs_cpu(raw_smp_processor_id());
2713 }
2714
2715 static void free_vmcs(struct vmcs *vmcs)
2716 {
2717         free_pages((unsigned long)vmcs, vmcs_config.order);
2718 }
2719
2720 /*
2721  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2722  */
2723 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2724 {
2725         if (!loaded_vmcs->vmcs)
2726                 return;
2727         loaded_vmcs_clear(loaded_vmcs);
2728         free_vmcs(loaded_vmcs->vmcs);
2729         loaded_vmcs->vmcs = NULL;
2730 }
2731
2732 static void free_kvm_area(void)
2733 {
2734         int cpu;
2735
2736         for_each_possible_cpu(cpu) {
2737                 free_vmcs(per_cpu(vmxarea, cpu));
2738                 per_cpu(vmxarea, cpu) = NULL;
2739         }
2740 }
2741
2742 static __init int alloc_kvm_area(void)
2743 {
2744         int cpu;
2745
2746         for_each_possible_cpu(cpu) {
2747                 struct vmcs *vmcs;
2748
2749                 vmcs = alloc_vmcs_cpu(cpu);
2750                 if (!vmcs) {
2751                         free_kvm_area();
2752                         return -ENOMEM;
2753                 }
2754
2755                 per_cpu(vmxarea, cpu) = vmcs;
2756         }
2757         return 0;
2758 }
2759
2760 static __init int hardware_setup(void)
2761 {
2762         if (setup_vmcs_config(&vmcs_config) < 0)
2763                 return -EIO;
2764
2765         if (boot_cpu_has(X86_FEATURE_NX))
2766                 kvm_enable_efer_bits(EFER_NX);
2767
2768         if (!cpu_has_vmx_vpid())
2769                 enable_vpid = 0;
2770
2771         if (!cpu_has_vmx_ept() ||
2772             !cpu_has_vmx_ept_4levels()) {
2773                 enable_ept = 0;
2774                 enable_unrestricted_guest = 0;
2775                 enable_ept_ad_bits = 0;
2776         }
2777
2778         if (!cpu_has_vmx_ept_ad_bits())
2779                 enable_ept_ad_bits = 0;
2780
2781         if (!cpu_has_vmx_unrestricted_guest())
2782                 enable_unrestricted_guest = 0;
2783
2784         if (!cpu_has_vmx_flexpriority())
2785                 flexpriority_enabled = 0;
2786
2787         if (!cpu_has_vmx_tpr_shadow())
2788                 kvm_x86_ops->update_cr8_intercept = NULL;
2789
2790         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2791                 kvm_disable_largepages();
2792
2793         if (!cpu_has_vmx_ple())
2794                 ple_gap = 0;
2795
2796         if (!cpu_has_vmx_apic_register_virt() ||
2797                                 !cpu_has_vmx_virtual_intr_delivery())
2798                 enable_apicv_reg_vid = 0;
2799
2800         if (enable_apicv_reg_vid)
2801                 kvm_x86_ops->update_cr8_intercept = NULL;
2802         else
2803                 kvm_x86_ops->hwapic_irr_update = NULL;
2804
2805         if (nested)
2806                 nested_vmx_setup_ctls_msrs();
2807
2808         return alloc_kvm_area();
2809 }
2810
2811 static __exit void hardware_unsetup(void)
2812 {
2813         free_kvm_area();
2814 }
2815
2816 static bool emulation_required(struct kvm_vcpu *vcpu)
2817 {
2818         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2819 }
2820
2821 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2822                 struct kvm_segment *save)
2823 {
2824         if (!emulate_invalid_guest_state) {
2825                 /*
2826                  * CS and SS RPL should be equal during guest entry according
2827                  * to VMX spec, but in reality it is not always so. Since vcpu
2828                  * is in the middle of the transition from real mode to
2829                  * protected mode it is safe to assume that RPL 0 is a good
2830                  * default value.
2831                  */
2832                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2833                         save->selector &= ~SELECTOR_RPL_MASK;
2834                 save->dpl = save->selector & SELECTOR_RPL_MASK;
2835                 save->s = 1;
2836         }
2837         vmx_set_segment(vcpu, save, seg);
2838 }
2839
2840 static void enter_pmode(struct kvm_vcpu *vcpu)
2841 {
2842         unsigned long flags;
2843         struct vcpu_vmx *vmx = to_vmx(vcpu);
2844
2845         /*
2846          * Update real mode segment cache. It may be not up-to-date if sement
2847          * register was written while vcpu was in a guest mode.
2848          */
2849         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2850         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2851         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2852         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2853         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2854         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2855
2856         vmx->rmode.vm86_active = 0;
2857
2858         vmx_segment_cache_clear(vmx);
2859
2860         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2861
2862         flags = vmcs_readl(GUEST_RFLAGS);
2863         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2864         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2865         vmcs_writel(GUEST_RFLAGS, flags);
2866
2867         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2868                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2869
2870         update_exception_bitmap(vcpu);
2871
2872         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2873         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2874         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2875         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2876         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2877         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2878
2879         /* CPL is always 0 when CPU enters protected mode */
2880         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2881         vmx->cpl = 0;
2882 }
2883
2884 static gva_t rmode_tss_base(struct kvm *kvm)
2885 {
2886         if (!kvm->arch.tss_addr) {
2887                 struct kvm_memslots *slots;
2888                 struct kvm_memory_slot *slot;
2889                 gfn_t base_gfn;
2890
2891                 slots = kvm_memslots(kvm);
2892                 slot = id_to_memslot(slots, 0);
2893                 base_gfn = slot->base_gfn + slot->npages - 3;
2894
2895                 return base_gfn << PAGE_SHIFT;
2896         }
2897         return kvm->arch.tss_addr;
2898 }
2899
2900 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2901 {
2902         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2903         struct kvm_segment var = *save;
2904
2905         var.dpl = 0x3;
2906         if (seg == VCPU_SREG_CS)
2907                 var.type = 0x3;
2908
2909         if (!emulate_invalid_guest_state) {
2910                 var.selector = var.base >> 4;
2911                 var.base = var.base & 0xffff0;
2912                 var.limit = 0xffff;
2913                 var.g = 0;
2914                 var.db = 0;
2915                 var.present = 1;
2916                 var.s = 1;
2917                 var.l = 0;
2918                 var.unusable = 0;
2919                 var.type = 0x3;
2920                 var.avl = 0;
2921                 if (save->base & 0xf)
2922                         printk_once(KERN_WARNING "kvm: segment base is not "
2923                                         "paragraph aligned when entering "
2924                                         "protected mode (seg=%d)", seg);
2925         }
2926
2927         vmcs_write16(sf->selector, var.selector);
2928         vmcs_write32(sf->base, var.base);
2929         vmcs_write32(sf->limit, var.limit);
2930         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2931 }
2932
2933 static void enter_rmode(struct kvm_vcpu *vcpu)
2934 {
2935         unsigned long flags;
2936         struct vcpu_vmx *vmx = to_vmx(vcpu);
2937
2938         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2939         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2940         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2941         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2942         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2943         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2944         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2945
2946         vmx->rmode.vm86_active = 1;
2947
2948         /*
2949          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2950          * vcpu. Call it here with phys address pointing 16M below 4G.
2951          */
2952         if (!vcpu->kvm->arch.tss_addr) {
2953                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2954                              "called before entering vcpu\n");
2955                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2956                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2957                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2958         }
2959
2960         vmx_segment_cache_clear(vmx);
2961
2962         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2963         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2964         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2965
2966         flags = vmcs_readl(GUEST_RFLAGS);
2967         vmx->rmode.save_rflags = flags;
2968
2969         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2970
2971         vmcs_writel(GUEST_RFLAGS, flags);
2972         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2973         update_exception_bitmap(vcpu);
2974
2975         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2976         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2977         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2978         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2979         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2980         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2981
2982         kvm_mmu_reset_context(vcpu);
2983 }
2984
2985 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2986 {
2987         struct vcpu_vmx *vmx = to_vmx(vcpu);
2988         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2989
2990         if (!msr)
2991                 return;
2992
2993         /*
2994          * Force kernel_gs_base reloading before EFER changes, as control
2995          * of this msr depends on is_long_mode().
2996          */
2997         vmx_load_host_state(to_vmx(vcpu));
2998         vcpu->arch.efer = efer;
2999         if (efer & EFER_LMA) {
3000                 vmcs_write32(VM_ENTRY_CONTROLS,
3001                              vmcs_read32(VM_ENTRY_CONTROLS) |
3002                              VM_ENTRY_IA32E_MODE);
3003                 msr->data = efer;
3004         } else {
3005                 vmcs_write32(VM_ENTRY_CONTROLS,
3006                              vmcs_read32(VM_ENTRY_CONTROLS) &
3007                              ~VM_ENTRY_IA32E_MODE);
3008
3009                 msr->data = efer & ~EFER_LME;
3010         }
3011         setup_msrs(vmx);
3012 }
3013
3014 #ifdef CONFIG_X86_64
3015
3016 static void enter_lmode(struct kvm_vcpu *vcpu)
3017 {
3018         u32 guest_tr_ar;
3019
3020         vmx_segment_cache_clear(to_vmx(vcpu));
3021
3022         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3023         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3024                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3025                                      __func__);
3026                 vmcs_write32(GUEST_TR_AR_BYTES,
3027                              (guest_tr_ar & ~AR_TYPE_MASK)
3028                              | AR_TYPE_BUSY_64_TSS);
3029         }
3030         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3031 }
3032
3033 static void exit_lmode(struct kvm_vcpu *vcpu)
3034 {
3035         vmcs_write32(VM_ENTRY_CONTROLS,
3036                      vmcs_read32(VM_ENTRY_CONTROLS)
3037                      & ~VM_ENTRY_IA32E_MODE);
3038         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3039 }
3040
3041 #endif
3042
3043 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3044 {
3045         vpid_sync_context(to_vmx(vcpu));
3046         if (enable_ept) {
3047                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3048                         return;
3049                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3050         }
3051 }
3052
3053 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3054 {
3055         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3056
3057         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3058         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3059 }
3060
3061 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3062 {
3063         if (enable_ept && is_paging(vcpu))
3064                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3065         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3066 }
3067
3068 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3069 {
3070         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3071
3072         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3073         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3074 }
3075
3076 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3077 {
3078         if (!test_bit(VCPU_EXREG_PDPTR,
3079                       (unsigned long *)&vcpu->arch.regs_dirty))
3080                 return;
3081
3082         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3083                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3084                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3085                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3086                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3087         }
3088 }
3089
3090 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3091 {
3092         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3093                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3094                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3095                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3096                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3097         }
3098
3099         __set_bit(VCPU_EXREG_PDPTR,
3100                   (unsigned long *)&vcpu->arch.regs_avail);
3101         __set_bit(VCPU_EXREG_PDPTR,
3102                   (unsigned long *)&vcpu->arch.regs_dirty);
3103 }
3104
3105 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3106
3107 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3108                                         unsigned long cr0,
3109                                         struct kvm_vcpu *vcpu)
3110 {
3111         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3112                 vmx_decache_cr3(vcpu);
3113         if (!(cr0 & X86_CR0_PG)) {
3114                 /* From paging/starting to nonpaging */
3115                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3116                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3117                              (CPU_BASED_CR3_LOAD_EXITING |
3118                               CPU_BASED_CR3_STORE_EXITING));
3119                 vcpu->arch.cr0 = cr0;
3120                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3121         } else if (!is_paging(vcpu)) {
3122                 /* From nonpaging to paging */
3123                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3124                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3125                              ~(CPU_BASED_CR3_LOAD_EXITING |
3126                                CPU_BASED_CR3_STORE_EXITING));
3127                 vcpu->arch.cr0 = cr0;
3128                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3129         }
3130
3131         if (!(cr0 & X86_CR0_WP))
3132                 *hw_cr0 &= ~X86_CR0_WP;
3133 }
3134
3135 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3136 {
3137         struct vcpu_vmx *vmx = to_vmx(vcpu);
3138         unsigned long hw_cr0;
3139
3140         if (enable_unrestricted_guest)
3141                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3142                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3143         else {
3144                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
3145
3146                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3147                         enter_pmode(vcpu);
3148
3149                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3150                         enter_rmode(vcpu);
3151         }
3152
3153 #ifdef CONFIG_X86_64
3154         if (vcpu->arch.efer & EFER_LME) {
3155                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3156                         enter_lmode(vcpu);
3157                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3158                         exit_lmode(vcpu);
3159         }
3160 #endif
3161
3162         if (enable_ept)
3163                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3164
3165         if (!vcpu->fpu_active)
3166                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3167
3168         vmcs_writel(CR0_READ_SHADOW, cr0);
3169         vmcs_writel(GUEST_CR0, hw_cr0);
3170         vcpu->arch.cr0 = cr0;
3171
3172         /* depends on vcpu->arch.cr0 to be set to a new value */
3173         vmx->emulation_required = emulation_required(vcpu);
3174 }
3175
3176 static u64 construct_eptp(unsigned long root_hpa)
3177 {
3178         u64 eptp;
3179
3180         /* TODO write the value reading from MSR */
3181         eptp = VMX_EPT_DEFAULT_MT |
3182                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3183         if (enable_ept_ad_bits)
3184                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3185         eptp |= (root_hpa & PAGE_MASK);
3186
3187         return eptp;
3188 }
3189
3190 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3191 {
3192         unsigned long guest_cr3;
3193         u64 eptp;
3194
3195         guest_cr3 = cr3;
3196         if (enable_ept) {
3197                 eptp = construct_eptp(cr3);
3198                 vmcs_write64(EPT_POINTER, eptp);
3199                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3200                         vcpu->kvm->arch.ept_identity_map_addr;
3201                 ept_load_pdptrs(vcpu);
3202         }
3203
3204         vmx_flush_tlb(vcpu);
3205         vmcs_writel(GUEST_CR3, guest_cr3);
3206 }
3207
3208 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3209 {
3210         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3211                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3212
3213         if (cr4 & X86_CR4_VMXE) {
3214                 /*
3215                  * To use VMXON (and later other VMX instructions), a guest
3216                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3217                  * So basically the check on whether to allow nested VMX
3218                  * is here.
3219                  */
3220                 if (!nested_vmx_allowed(vcpu))
3221                         return 1;
3222         } else if (to_vmx(vcpu)->nested.vmxon)
3223                 return 1;
3224
3225         vcpu->arch.cr4 = cr4;
3226         if (enable_ept) {
3227                 if (!is_paging(vcpu)) {
3228                         hw_cr4 &= ~X86_CR4_PAE;
3229                         hw_cr4 |= X86_CR4_PSE;
3230                 } else if (!(cr4 & X86_CR4_PAE)) {
3231                         hw_cr4 &= ~X86_CR4_PAE;
3232                 }
3233         }
3234
3235         vmcs_writel(CR4_READ_SHADOW, cr4);
3236         vmcs_writel(GUEST_CR4, hw_cr4);
3237         return 0;
3238 }
3239
3240 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3241                             struct kvm_segment *var, int seg)
3242 {
3243         struct vcpu_vmx *vmx = to_vmx(vcpu);
3244         u32 ar;
3245
3246         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3247                 *var = vmx->rmode.segs[seg];
3248                 if (seg == VCPU_SREG_TR
3249                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3250                         return;
3251                 var->base = vmx_read_guest_seg_base(vmx, seg);
3252                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3253                 return;
3254         }
3255         var->base = vmx_read_guest_seg_base(vmx, seg);
3256         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3257         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3258         ar = vmx_read_guest_seg_ar(vmx, seg);
3259         var->type = ar & 15;
3260         var->s = (ar >> 4) & 1;
3261         var->dpl = (ar >> 5) & 3;
3262         var->present = (ar >> 7) & 1;
3263         var->avl = (ar >> 12) & 1;
3264         var->l = (ar >> 13) & 1;
3265         var->db = (ar >> 14) & 1;
3266         var->g = (ar >> 15) & 1;
3267         var->unusable = (ar >> 16) & 1;
3268 }
3269
3270 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3271 {
3272         struct kvm_segment s;
3273
3274         if (to_vmx(vcpu)->rmode.vm86_active) {
3275                 vmx_get_segment(vcpu, &s, seg);
3276                 return s.base;
3277         }
3278         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3279 }
3280
3281 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3282 {
3283         struct vcpu_vmx *vmx = to_vmx(vcpu);
3284
3285         if (!is_protmode(vcpu))
3286                 return 0;
3287
3288         if (!is_long_mode(vcpu)
3289             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3290                 return 3;
3291
3292         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3293                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3294                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3295         }
3296
3297         return vmx->cpl;
3298 }
3299
3300
3301 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3302 {
3303         u32 ar;
3304
3305         if (var->unusable || !var->present)
3306                 ar = 1 << 16;
3307         else {
3308                 ar = var->type & 15;
3309                 ar |= (var->s & 1) << 4;
3310                 ar |= (var->dpl & 3) << 5;
3311                 ar |= (var->present & 1) << 7;
3312                 ar |= (var->avl & 1) << 12;
3313                 ar |= (var->l & 1) << 13;
3314                 ar |= (var->db & 1) << 14;
3315                 ar |= (var->g & 1) << 15;
3316         }
3317
3318         return ar;
3319 }
3320
3321 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3322                             struct kvm_segment *var, int seg)
3323 {
3324         struct vcpu_vmx *vmx = to_vmx(vcpu);
3325         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3326
3327         vmx_segment_cache_clear(vmx);
3328         if (seg == VCPU_SREG_CS)
3329                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3330
3331         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3332                 vmx->rmode.segs[seg] = *var;
3333                 if (seg == VCPU_SREG_TR)
3334                         vmcs_write16(sf->selector, var->selector);
3335                 else if (var->s)
3336                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3337                 goto out;
3338         }
3339
3340         vmcs_writel(sf->base, var->base);
3341         vmcs_write32(sf->limit, var->limit);
3342         vmcs_write16(sf->selector, var->selector);
3343
3344         /*
3345          *   Fix the "Accessed" bit in AR field of segment registers for older
3346          * qemu binaries.
3347          *   IA32 arch specifies that at the time of processor reset the
3348          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3349          * is setting it to 0 in the userland code. This causes invalid guest
3350          * state vmexit when "unrestricted guest" mode is turned on.
3351          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3352          * tree. Newer qemu binaries with that qemu fix would not need this
3353          * kvm hack.
3354          */
3355         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3356                 var->type |= 0x1; /* Accessed */
3357
3358         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3359
3360 out:
3361         vmx->emulation_required |= emulation_required(vcpu);
3362 }
3363
3364 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3365 {
3366         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3367
3368         *db = (ar >> 14) & 1;
3369         *l = (ar >> 13) & 1;
3370 }
3371
3372 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3373 {
3374         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3375         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3376 }
3377
3378 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3379 {
3380         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3381         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3382 }
3383
3384 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3385 {
3386         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3387         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3388 }
3389
3390 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3391 {
3392         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3393         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3394 }
3395
3396 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3397 {
3398         struct kvm_segment var;
3399         u32 ar;
3400
3401         vmx_get_segment(vcpu, &var, seg);
3402         var.dpl = 0x3;
3403         if (seg == VCPU_SREG_CS)
3404                 var.type = 0x3;
3405         ar = vmx_segment_access_rights(&var);
3406
3407         if (var.base != (var.selector << 4))
3408                 return false;
3409         if (var.limit != 0xffff)
3410                 return false;
3411         if (ar != 0xf3)
3412                 return false;
3413
3414         return true;
3415 }
3416
3417 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3418 {
3419         struct kvm_segment cs;
3420         unsigned int cs_rpl;
3421
3422         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3423         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3424
3425         if (cs.unusable)
3426                 return false;
3427         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3428                 return false;
3429         if (!cs.s)
3430                 return false;
3431         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3432                 if (cs.dpl > cs_rpl)
3433                         return false;
3434         } else {
3435                 if (cs.dpl != cs_rpl)
3436                         return false;
3437         }
3438         if (!cs.present)
3439                 return false;
3440
3441         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3442         return true;
3443 }
3444
3445 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3446 {
3447         struct kvm_segment ss;
3448         unsigned int ss_rpl;
3449
3450         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3451         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3452
3453         if (ss.unusable)
3454                 return true;
3455         if (ss.type != 3 && ss.type != 7)
3456                 return false;
3457         if (!ss.s)
3458                 return false;
3459         if (ss.dpl != ss_rpl) /* DPL != RPL */
3460                 return false;
3461         if (!ss.present)
3462                 return false;
3463
3464         return true;
3465 }
3466
3467 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3468 {
3469         struct kvm_segment var;
3470         unsigned int rpl;
3471
3472         vmx_get_segment(vcpu, &var, seg);
3473         rpl = var.selector & SELECTOR_RPL_MASK;
3474
3475         if (var.unusable)
3476                 return true;
3477         if (!var.s)
3478                 return false;
3479         if (!var.present)
3480                 return false;
3481         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3482                 if (var.dpl < rpl) /* DPL < RPL */
3483                         return false;
3484         }
3485
3486         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3487          * rights flags
3488          */
3489         return true;
3490 }
3491
3492 static bool tr_valid(struct kvm_vcpu *vcpu)
3493 {
3494         struct kvm_segment tr;
3495
3496         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3497
3498         if (tr.unusable)
3499                 return false;
3500         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3501                 return false;
3502         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3503                 return false;
3504         if (!tr.present)
3505                 return false;
3506
3507         return true;
3508 }
3509
3510 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3511 {
3512         struct kvm_segment ldtr;
3513
3514         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3515
3516         if (ldtr.unusable)
3517                 return true;
3518         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3519                 return false;
3520         if (ldtr.type != 2)
3521                 return false;
3522         if (!ldtr.present)
3523                 return false;
3524
3525         return true;
3526 }
3527
3528 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3529 {
3530         struct kvm_segment cs, ss;
3531
3532         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3533         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3534
3535         return ((cs.selector & SELECTOR_RPL_MASK) ==
3536                  (ss.selector & SELECTOR_RPL_MASK));
3537 }
3538
3539 /*
3540  * Check if guest state is valid. Returns true if valid, false if
3541  * not.
3542  * We assume that registers are always usable
3543  */
3544 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3545 {
3546         if (enable_unrestricted_guest)
3547                 return true;
3548
3549         /* real mode guest state checks */
3550         if (!is_protmode(vcpu)) {
3551                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3552                         return false;
3553                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3554                         return false;
3555                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3556                         return false;
3557                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3558                         return false;
3559                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3560                         return false;
3561                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3562                         return false;
3563         } else {
3564         /* protected mode guest state checks */
3565                 if (!cs_ss_rpl_check(vcpu))
3566                         return false;
3567                 if (!code_segment_valid(vcpu))
3568                         return false;
3569                 if (!stack_segment_valid(vcpu))
3570                         return false;
3571                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3572                         return false;
3573                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3574                         return false;
3575                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3576                         return false;
3577                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3578                         return false;
3579                 if (!tr_valid(vcpu))
3580                         return false;
3581                 if (!ldtr_valid(vcpu))
3582                         return false;
3583         }
3584         /* TODO:
3585          * - Add checks on RIP
3586          * - Add checks on RFLAGS
3587          */
3588
3589         return true;
3590 }
3591
3592 static int init_rmode_tss(struct kvm *kvm)
3593 {
3594         gfn_t fn;
3595         u16 data = 0;
3596         int r, idx, ret = 0;
3597
3598         idx = srcu_read_lock(&kvm->srcu);
3599         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3600         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3601         if (r < 0)
3602                 goto out;
3603         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3604         r = kvm_write_guest_page(kvm, fn++, &data,
3605                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3606         if (r < 0)
3607                 goto out;
3608         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3609         if (r < 0)
3610                 goto out;
3611         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3612         if (r < 0)
3613                 goto out;
3614         data = ~0;
3615         r = kvm_write_guest_page(kvm, fn, &data,
3616                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3617                                  sizeof(u8));
3618         if (r < 0)
3619                 goto out;
3620
3621         ret = 1;
3622 out:
3623         srcu_read_unlock(&kvm->srcu, idx);
3624         return ret;
3625 }
3626
3627 static int init_rmode_identity_map(struct kvm *kvm)
3628 {
3629         int i, idx, r, ret;
3630         pfn_t identity_map_pfn;
3631         u32 tmp;
3632
3633         if (!enable_ept)
3634                 return 1;
3635         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3636                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3637                         "haven't been allocated!\n");
3638                 return 0;
3639         }
3640         if (likely(kvm->arch.ept_identity_pagetable_done))
3641                 return 1;
3642         ret = 0;
3643         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3644         idx = srcu_read_lock(&kvm->srcu);
3645         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3646         if (r < 0)
3647                 goto out;
3648         /* Set up identity-mapping pagetable for EPT in real mode */
3649         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3650                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3651                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3652                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3653                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3654                 if (r < 0)
3655                         goto out;
3656         }
3657         kvm->arch.ept_identity_pagetable_done = true;
3658         ret = 1;
3659 out:
3660         srcu_read_unlock(&kvm->srcu, idx);
3661         return ret;
3662 }
3663
3664 static void seg_setup(int seg)
3665 {
3666         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3667         unsigned int ar;
3668
3669         vmcs_write16(sf->selector, 0);
3670         vmcs_writel(sf->base, 0);
3671         vmcs_write32(sf->limit, 0xffff);
3672         ar = 0x93;
3673         if (seg == VCPU_SREG_CS)
3674                 ar |= 0x08; /* code segment */
3675
3676         vmcs_write32(sf->ar_bytes, ar);
3677 }
3678
3679 static int alloc_apic_access_page(struct kvm *kvm)
3680 {
3681         struct page *page;
3682         struct kvm_userspace_memory_region kvm_userspace_mem;
3683         int r = 0;
3684
3685         mutex_lock(&kvm->slots_lock);
3686         if (kvm->arch.apic_access_page)
3687                 goto out;
3688         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3689         kvm_userspace_mem.flags = 0;
3690         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3691         kvm_userspace_mem.memory_size = PAGE_SIZE;
3692         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
3693         if (r)
3694                 goto out;
3695
3696         page = gfn_to_page(kvm, 0xfee00);
3697         if (is_error_page(page)) {
3698                 r = -EFAULT;
3699                 goto out;
3700         }
3701
3702         kvm->arch.apic_access_page = page;
3703 out:
3704         mutex_unlock(&kvm->slots_lock);
3705         return r;
3706 }
3707
3708 static int alloc_identity_pagetable(struct kvm *kvm)
3709 {
3710         struct page *page;
3711         struct kvm_userspace_memory_region kvm_userspace_mem;
3712         int r = 0;
3713
3714         mutex_lock(&kvm->slots_lock);
3715         if (kvm->arch.ept_identity_pagetable)
3716                 goto out;
3717         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3718         kvm_userspace_mem.flags = 0;
3719         kvm_userspace_mem.guest_phys_addr =
3720                 kvm->arch.ept_identity_map_addr;
3721         kvm_userspace_mem.memory_size = PAGE_SIZE;
3722         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
3723         if (r)
3724                 goto out;
3725
3726         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3727         if (is_error_page(page)) {
3728                 r = -EFAULT;
3729                 goto out;
3730         }
3731
3732         kvm->arch.ept_identity_pagetable = page;
3733 out:
3734         mutex_unlock(&kvm->slots_lock);
3735         return r;
3736 }
3737
3738 static void allocate_vpid(struct vcpu_vmx *vmx)
3739 {
3740         int vpid;
3741
3742         vmx->vpid = 0;
3743         if (!enable_vpid)
3744                 return;
3745         spin_lock(&vmx_vpid_lock);
3746         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3747         if (vpid < VMX_NR_VPIDS) {
3748                 vmx->vpid = vpid;
3749                 __set_bit(vpid, vmx_vpid_bitmap);
3750         }
3751         spin_unlock(&vmx_vpid_lock);
3752 }
3753
3754 static void free_vpid(struct vcpu_vmx *vmx)
3755 {
3756         if (!enable_vpid)
3757                 return;
3758         spin_lock(&vmx_vpid_lock);
3759         if (vmx->vpid != 0)
3760                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3761         spin_unlock(&vmx_vpid_lock);
3762 }
3763
3764 #define MSR_TYPE_R      1
3765 #define MSR_TYPE_W      2
3766 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3767                                                 u32 msr, int type)
3768 {
3769         int f = sizeof(unsigned long);
3770
3771         if (!cpu_has_vmx_msr_bitmap())
3772                 return;
3773
3774         /*
3775          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3776          * have the write-low and read-high bitmap offsets the wrong way round.
3777          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3778          */
3779         if (msr <= 0x1fff) {
3780                 if (type & MSR_TYPE_R)
3781                         /* read-low */
3782                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3783
3784                 if (type & MSR_TYPE_W)
3785                         /* write-low */
3786                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3787
3788         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3789                 msr &= 0x1fff;
3790                 if (type & MSR_TYPE_R)
3791                         /* read-high */
3792                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3793
3794                 if (type & MSR_TYPE_W)
3795                         /* write-high */
3796                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3797
3798         }
3799 }
3800
3801 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3802                                                 u32 msr, int type)
3803 {
3804         int f = sizeof(unsigned long);
3805
3806         if (!cpu_has_vmx_msr_bitmap())
3807                 return;
3808
3809         /*
3810          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3811          * have the write-low and read-high bitmap offsets the wrong way round.
3812          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3813          */
3814         if (msr <= 0x1fff) {
3815                 if (type & MSR_TYPE_R)
3816                         /* read-low */
3817                         __set_bit(msr, msr_bitmap + 0x000 / f);
3818
3819                 if (type & MSR_TYPE_W)
3820                         /* write-low */
3821                         __set_bit(msr, msr_bitmap + 0x800 / f);
3822
3823         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3824                 msr &= 0x1fff;
3825                 if (type & MSR_TYPE_R)
3826                         /* read-high */
3827                         __set_bit(msr, msr_bitmap + 0x400 / f);
3828
3829                 if (type & MSR_TYPE_W)
3830                         /* write-high */
3831                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3832
3833         }
3834 }
3835
3836 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3837 {
3838         if (!longmode_only)
3839                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3840                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3841         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3842                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3843 }
3844
3845 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3846 {
3847         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3848                         msr, MSR_TYPE_R);
3849         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3850                         msr, MSR_TYPE_R);
3851 }
3852
3853 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3854 {
3855         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3856                         msr, MSR_TYPE_R);
3857         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3858                         msr, MSR_TYPE_R);
3859 }
3860
3861 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
3862 {
3863         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3864                         msr, MSR_TYPE_W);
3865         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3866                         msr, MSR_TYPE_W);
3867 }
3868
3869 /*
3870  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3871  * will not change in the lifetime of the guest.
3872  * Note that host-state that does change is set elsewhere. E.g., host-state
3873  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3874  */
3875 static void vmx_set_constant_host_state(void)
3876 {
3877         u32 low32, high32;
3878         unsigned long tmpl;
3879         struct desc_ptr dt;
3880
3881         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
3882         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3883         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3884
3885         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3886 #ifdef CONFIG_X86_64
3887         /*
3888          * Load null selectors, so we can avoid reloading them in
3889          * __vmx_load_host_state(), in case userspace uses the null selectors
3890          * too (the expected case).
3891          */
3892         vmcs_write16(HOST_DS_SELECTOR, 0);
3893         vmcs_write16(HOST_ES_SELECTOR, 0);
3894 #else
3895         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3896         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3897 #endif
3898         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3899         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3900
3901         native_store_idt(&dt);
3902         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3903
3904         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
3905
3906         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3907         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3908         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3909         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3910
3911         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3912                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3913                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3914         }
3915 }
3916
3917 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3918 {
3919         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3920         if (enable_ept)
3921                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3922         if (is_guest_mode(&vmx->vcpu))
3923                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3924                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3925         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3926 }
3927
3928 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3929 {
3930         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3931         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3932                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3933 #ifdef CONFIG_X86_64
3934                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3935                                 CPU_BASED_CR8_LOAD_EXITING;
3936 #endif
3937         }
3938         if (!enable_ept)
3939                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3940                                 CPU_BASED_CR3_LOAD_EXITING  |
3941                                 CPU_BASED_INVLPG_EXITING;
3942         return exec_control;
3943 }
3944
3945 static int vmx_vm_has_apicv(struct kvm *kvm)
3946 {
3947         return enable_apicv_reg_vid && irqchip_in_kernel(kvm);
3948 }
3949
3950 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3951 {
3952         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3953         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3954                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3955         if (vmx->vpid == 0)
3956                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3957         if (!enable_ept) {
3958                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3959                 enable_unrestricted_guest = 0;
3960                 /* Enable INVPCID for non-ept guests may cause performance regression. */
3961                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3962         }
3963         if (!enable_unrestricted_guest)
3964                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3965         if (!ple_gap)
3966                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3967         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
3968                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3969                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3970         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
3971         return exec_control;
3972 }
3973
3974 static void ept_set_mmio_spte_mask(void)
3975 {
3976         /*
3977          * EPT Misconfigurations can be generated if the value of bits 2:0
3978          * of an EPT paging-structure entry is 110b (write/execute).
3979          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3980          * spte.
3981          */
3982         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3983 }
3984
3985 /*
3986  * Sets up the vmcs for emulated real mode.
3987  */
3988 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3989 {
3990 #ifdef CONFIG_X86_64
3991         unsigned long a;
3992 #endif
3993         int i;
3994
3995         /* I/O */
3996         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3997         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3998
3999         if (cpu_has_vmx_msr_bitmap())
4000                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4001
4002         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4003
4004         /* Control */
4005         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
4006                 vmcs_config.pin_based_exec_ctrl);
4007
4008         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4009
4010         if (cpu_has_secondary_exec_ctrls()) {
4011                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4012                                 vmx_secondary_exec_control(vmx));
4013         }
4014
4015         if (enable_apicv_reg_vid) {
4016                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4017                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4018                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4019                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4020
4021                 vmcs_write16(GUEST_INTR_STATUS, 0);
4022         }
4023
4024         if (ple_gap) {
4025                 vmcs_write32(PLE_GAP, ple_gap);
4026                 vmcs_write32(PLE_WINDOW, ple_window);
4027         }
4028
4029         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4030         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4031         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4032
4033         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4034         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4035         vmx_set_constant_host_state();
4036 #ifdef CONFIG_X86_64
4037         rdmsrl(MSR_FS_BASE, a);
4038         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4039         rdmsrl(MSR_GS_BASE, a);
4040         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4041 #else
4042         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4043         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4044 #endif
4045
4046         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4047         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4048         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4049         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4050         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4051
4052         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4053                 u32 msr_low, msr_high;
4054                 u64 host_pat;
4055                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4056                 host_pat = msr_low | ((u64) msr_high << 32);
4057                 /* Write the default value follow host pat */
4058                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4059                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4060                 vmx->vcpu.arch.pat = host_pat;
4061         }
4062
4063         for (i = 0; i < NR_VMX_MSR; ++i) {
4064                 u32 index = vmx_msr_index[i];
4065                 u32 data_low, data_high;
4066                 int j = vmx->nmsrs;
4067
4068                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4069                         continue;
4070                 if (wrmsr_safe(index, data_low, data_high) < 0)
4071                         continue;
4072                 vmx->guest_msrs[j].index = i;
4073                 vmx->guest_msrs[j].data = 0;
4074                 vmx->guest_msrs[j].mask = -1ull;
4075                 ++vmx->nmsrs;
4076         }
4077
4078         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4079
4080         /* 22.2.1, 20.8.1 */
4081         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4082
4083         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4084         set_cr4_guest_host_mask(vmx);
4085
4086         return 0;
4087 }
4088
4089 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4090 {
4091         struct vcpu_vmx *vmx = to_vmx(vcpu);
4092         u64 msr;
4093         int ret;
4094
4095         vmx->rmode.vm86_active = 0;
4096
4097         vmx->soft_vnmi_blocked = 0;
4098
4099         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4100         kvm_set_cr8(&vmx->vcpu, 0);
4101         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4102         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4103                 msr |= MSR_IA32_APICBASE_BSP;
4104         kvm_set_apic_base(&vmx->vcpu, msr);
4105
4106         vmx_segment_cache_clear(vmx);
4107
4108         seg_setup(VCPU_SREG_CS);
4109         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4110                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4111         else {
4112                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
4113                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
4114         }
4115
4116         seg_setup(VCPU_SREG_DS);
4117         seg_setup(VCPU_SREG_ES);
4118         seg_setup(VCPU_SREG_FS);
4119         seg_setup(VCPU_SREG_GS);
4120         seg_setup(VCPU_SREG_SS);
4121
4122         vmcs_write16(GUEST_TR_SELECTOR, 0);
4123         vmcs_writel(GUEST_TR_BASE, 0);
4124         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4125         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4126
4127         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4128         vmcs_writel(GUEST_LDTR_BASE, 0);
4129         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4130         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4131
4132         vmcs_write32(GUEST_SYSENTER_CS, 0);
4133         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4134         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4135
4136         vmcs_writel(GUEST_RFLAGS, 0x02);
4137         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4138                 kvm_rip_write(vcpu, 0xfff0);
4139         else
4140                 kvm_rip_write(vcpu, 0);
4141
4142         vmcs_writel(GUEST_GDTR_BASE, 0);
4143         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4144
4145         vmcs_writel(GUEST_IDTR_BASE, 0);
4146         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4147
4148         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4149         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4150         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4151
4152         /* Special registers */
4153         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4154
4155         setup_msrs(vmx);
4156
4157         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4158
4159         if (cpu_has_vmx_tpr_shadow()) {
4160                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4161                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4162                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4163                                      __pa(vmx->vcpu.arch.apic->regs));
4164                 vmcs_write32(TPR_THRESHOLD, 0);
4165         }
4166
4167         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4168                 vmcs_write64(APIC_ACCESS_ADDR,
4169                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4170
4171         if (vmx->vpid != 0)
4172                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4173
4174         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4175         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4176         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4177         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4178         vmx_set_cr4(&vmx->vcpu, 0);
4179         vmx_set_efer(&vmx->vcpu, 0);
4180         vmx_fpu_activate(&vmx->vcpu);
4181         update_exception_bitmap(&vmx->vcpu);
4182
4183         vpid_sync_context(vmx);
4184
4185         ret = 0;
4186
4187         return ret;
4188 }
4189
4190 /*
4191  * In nested virtualization, check if L1 asked to exit on external interrupts.
4192  * For most existing hypervisors, this will always return true.
4193  */
4194 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4195 {
4196         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4197                 PIN_BASED_EXT_INTR_MASK;
4198 }
4199
4200 static void enable_irq_window(struct kvm_vcpu *vcpu)
4201 {
4202         u32 cpu_based_vm_exec_control;
4203         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4204                 /*
4205                  * We get here if vmx_interrupt_allowed() said we can't
4206                  * inject to L1 now because L2 must run. Ask L2 to exit
4207                  * right after entry, so we can inject to L1 more promptly.
4208                  */
4209                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4210                 return;
4211         }
4212
4213         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4214         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4215         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4216 }
4217
4218 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4219 {
4220         u32 cpu_based_vm_exec_control;
4221
4222         if (!cpu_has_virtual_nmis()) {
4223                 enable_irq_window(vcpu);
4224                 return;
4225         }
4226
4227         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4228                 enable_irq_window(vcpu);
4229                 return;
4230         }
4231         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4232         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4233         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4234 }
4235
4236 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4237 {
4238         struct vcpu_vmx *vmx = to_vmx(vcpu);
4239         uint32_t intr;
4240         int irq = vcpu->arch.interrupt.nr;
4241
4242         trace_kvm_inj_virq(irq);
4243
4244         ++vcpu->stat.irq_injections;
4245         if (vmx->rmode.vm86_active) {
4246                 int inc_eip = 0;
4247                 if (vcpu->arch.interrupt.soft)
4248                         inc_eip = vcpu->arch.event_exit_inst_len;
4249                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4250                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4251                 return;
4252         }
4253         intr = irq | INTR_INFO_VALID_MASK;
4254         if (vcpu->arch.interrupt.soft) {
4255                 intr |= INTR_TYPE_SOFT_INTR;
4256                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4257                              vmx->vcpu.arch.event_exit_inst_len);
4258         } else
4259                 intr |= INTR_TYPE_EXT_INTR;
4260         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4261 }
4262
4263 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4264 {
4265         struct vcpu_vmx *vmx = to_vmx(vcpu);
4266
4267         if (is_guest_mode(vcpu))
4268                 return;
4269
4270         if (!cpu_has_virtual_nmis()) {
4271                 /*
4272                  * Tracking the NMI-blocked state in software is built upon
4273                  * finding the next open IRQ window. This, in turn, depends on
4274                  * well-behaving guests: They have to keep IRQs disabled at
4275                  * least as long as the NMI handler runs. Otherwise we may
4276                  * cause NMI nesting, maybe breaking the guest. But as this is
4277                  * highly unlikely, we can live with the residual risk.
4278                  */
4279                 vmx->soft_vnmi_blocked = 1;
4280                 vmx->vnmi_blocked_time = 0;
4281         }
4282
4283         ++vcpu->stat.nmi_injections;
4284         vmx->nmi_known_unmasked = false;
4285         if (vmx->rmode.vm86_active) {
4286                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4287                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4288                 return;
4289         }
4290         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4291                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4292 }
4293
4294 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4295 {
4296         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4297                 return 0;
4298
4299         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4300                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4301                    | GUEST_INTR_STATE_NMI));
4302 }
4303
4304 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4305 {
4306         if (!cpu_has_virtual_nmis())
4307                 return to_vmx(vcpu)->soft_vnmi_blocked;
4308         if (to_vmx(vcpu)->nmi_known_unmasked)
4309                 return false;
4310         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4311 }
4312
4313 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4314 {
4315         struct vcpu_vmx *vmx = to_vmx(vcpu);
4316
4317         if (!cpu_has_virtual_nmis()) {
4318                 if (vmx->soft_vnmi_blocked != masked) {
4319                         vmx->soft_vnmi_blocked = masked;
4320                         vmx->vnmi_blocked_time = 0;
4321                 }
4322         } else {
4323                 vmx->nmi_known_unmasked = !masked;
4324                 if (masked)
4325                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4326                                       GUEST_INTR_STATE_NMI);
4327                 else
4328                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4329                                         GUEST_INTR_STATE_NMI);
4330         }
4331 }
4332
4333 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4334 {
4335         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4336                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4337                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4338                     (vmcs12->idt_vectoring_info_field &
4339                      VECTORING_INFO_VALID_MASK))
4340                         return 0;
4341                 nested_vmx_vmexit(vcpu);
4342                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4343                 vmcs12->vm_exit_intr_info = 0;
4344                 /* fall through to normal code, but now in L1, not L2 */
4345         }
4346
4347         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4348                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4349                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4350 }
4351
4352 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4353 {
4354         int ret;
4355         struct kvm_userspace_memory_region tss_mem = {
4356                 .slot = TSS_PRIVATE_MEMSLOT,
4357                 .guest_phys_addr = addr,
4358                 .memory_size = PAGE_SIZE * 3,
4359                 .flags = 0,
4360         };
4361
4362         ret = kvm_set_memory_region(kvm, &tss_mem, false);
4363         if (ret)
4364                 return ret;
4365         kvm->arch.tss_addr = addr;
4366         if (!init_rmode_tss(kvm))
4367                 return  -ENOMEM;
4368
4369         return 0;
4370 }
4371
4372 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4373 {
4374         switch (vec) {
4375         case BP_VECTOR:
4376                 /*
4377                  * Update instruction length as we may reinject the exception
4378                  * from user space while in guest debugging mode.
4379                  */
4380                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4381                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4382                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4383                         return false;
4384                 /* fall through */
4385         case DB_VECTOR:
4386                 if (vcpu->guest_debug &
4387                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4388                         return false;
4389                 /* fall through */
4390         case DE_VECTOR:
4391         case OF_VECTOR:
4392         case BR_VECTOR:
4393         case UD_VECTOR:
4394         case DF_VECTOR:
4395         case SS_VECTOR:
4396         case GP_VECTOR:
4397         case MF_VECTOR:
4398                 return true;
4399         break;
4400         }
4401         return false;
4402 }
4403
4404 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4405                                   int vec, u32 err_code)
4406 {
4407         /*
4408          * Instruction with address size override prefix opcode 0x67
4409          * Cause the #SS fault with 0 error code in VM86 mode.
4410          */
4411         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4412                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4413                         if (vcpu->arch.halt_request) {
4414                                 vcpu->arch.halt_request = 0;
4415                                 return kvm_emulate_halt(vcpu);
4416                         }
4417                         return 1;
4418                 }
4419                 return 0;
4420         }
4421
4422         /*
4423          * Forward all other exceptions that are valid in real mode.
4424          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4425          *        the required debugging infrastructure rework.
4426          */
4427         kvm_queue_exception(vcpu, vec);
4428         return 1;
4429 }
4430
4431 /*
4432  * Trigger machine check on the host. We assume all the MSRs are already set up
4433  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4434  * We pass a fake environment to the machine check handler because we want
4435  * the guest to be always treated like user space, no matter what context
4436  * it used internally.
4437  */
4438 static void kvm_machine_check(void)
4439 {
4440 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4441         struct pt_regs regs = {
4442                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4443                 .flags = X86_EFLAGS_IF,
4444         };
4445
4446         do_machine_check(&regs, 0);
4447 #endif
4448 }
4449
4450 static int handle_machine_check(struct kvm_vcpu *vcpu)
4451 {
4452         /* already handled by vcpu_run */
4453         return 1;
4454 }
4455
4456 static int handle_exception(struct kvm_vcpu *vcpu)
4457 {
4458         struct vcpu_vmx *vmx = to_vmx(vcpu);
4459         struct kvm_run *kvm_run = vcpu->run;
4460         u32 intr_info, ex_no, error_code;
4461         unsigned long cr2, rip, dr6;
4462         u32 vect_info;
4463         enum emulation_result er;
4464
4465         vect_info = vmx->idt_vectoring_info;
4466         intr_info = vmx->exit_intr_info;
4467
4468         if (is_machine_check(intr_info))
4469                 return handle_machine_check(vcpu);
4470
4471         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4472                 return 1;  /* already handled by vmx_vcpu_run() */
4473
4474         if (is_no_device(intr_info)) {
4475                 vmx_fpu_activate(vcpu);
4476                 return 1;
4477         }
4478
4479         if (is_invalid_opcode(intr_info)) {
4480                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4481                 if (er != EMULATE_DONE)
4482                         kvm_queue_exception(vcpu, UD_VECTOR);
4483                 return 1;
4484         }
4485
4486         error_code = 0;
4487         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4488                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4489
4490         /*
4491          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4492          * MMIO, it is better to report an internal error.
4493          * See the comments in vmx_handle_exit.
4494          */
4495         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4496             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4497                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4498                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4499                 vcpu->run->internal.ndata = 2;
4500                 vcpu->run->internal.data[0] = vect_info;
4501                 vcpu->run->internal.data[1] = intr_info;
4502                 return 0;
4503         }
4504
4505         if (is_page_fault(intr_info)) {
4506                 /* EPT won't cause page fault directly */
4507                 BUG_ON(enable_ept);
4508                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4509                 trace_kvm_page_fault(cr2, error_code);
4510
4511                 if (kvm_event_needs_reinjection(vcpu))
4512                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4513                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4514         }
4515
4516         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4517
4518         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4519                 return handle_rmode_exception(vcpu, ex_no, error_code);
4520
4521         switch (ex_no) {
4522         case DB_VECTOR:
4523                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4524                 if (!(vcpu->guest_debug &
4525                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4526                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4527                         kvm_queue_exception(vcpu, DB_VECTOR);
4528                         return 1;
4529                 }
4530                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4531                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4532                 /* fall through */
4533         case BP_VECTOR:
4534                 /*
4535                  * Update instruction length as we may reinject #BP from
4536                  * user space while in guest debugging mode. Reading it for
4537                  * #DB as well causes no harm, it is not used in that case.
4538                  */
4539                 vmx->vcpu.arch.event_exit_inst_len =
4540                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4541                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4542                 rip = kvm_rip_read(vcpu);
4543                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4544                 kvm_run->debug.arch.exception = ex_no;
4545                 break;
4546         default:
4547                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4548                 kvm_run->ex.exception = ex_no;
4549                 kvm_run->ex.error_code = error_code;
4550                 break;
4551         }
4552         return 0;
4553 }
4554
4555 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4556 {
4557         ++vcpu->stat.irq_exits;
4558         return 1;
4559 }
4560
4561 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4562 {
4563         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4564         return 0;
4565 }
4566
4567 static int handle_io(struct kvm_vcpu *vcpu)
4568 {
4569         unsigned long exit_qualification;
4570         int size, in, string;
4571         unsigned port;
4572
4573         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4574         string = (exit_qualification & 16) != 0;
4575         in = (exit_qualification & 8) != 0;
4576
4577         ++vcpu->stat.io_exits;
4578
4579         if (string || in)
4580                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4581
4582         port = exit_qualification >> 16;
4583         size = (exit_qualification & 7) + 1;
4584         skip_emulated_instruction(vcpu);
4585
4586         return kvm_fast_pio_out(vcpu, size, port);
4587 }
4588
4589 static void
4590 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4591 {
4592         /*
4593          * Patch in the VMCALL instruction:
4594          */
4595         hypercall[0] = 0x0f;
4596         hypercall[1] = 0x01;
4597         hypercall[2] = 0xc1;
4598 }
4599
4600 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4601 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4602 {
4603         if (to_vmx(vcpu)->nested.vmxon &&
4604             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4605                 return 1;
4606
4607         if (is_guest_mode(vcpu)) {
4608                 /*
4609                  * We get here when L2 changed cr0 in a way that did not change
4610                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4611                  * but did change L0 shadowed bits. This can currently happen
4612                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4613                  * loading) while pretending to allow the guest to change it.
4614                  */
4615                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4616                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4617                         return 1;
4618                 vmcs_writel(CR0_READ_SHADOW, val);
4619                 return 0;
4620         } else
4621                 return kvm_set_cr0(vcpu, val);
4622 }
4623
4624 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4625 {
4626         if (is_guest_mode(vcpu)) {
4627                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4628                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4629                         return 1;
4630                 vmcs_writel(CR4_READ_SHADOW, val);
4631                 return 0;
4632         } else
4633                 return kvm_set_cr4(vcpu, val);
4634 }
4635
4636 /* called to set cr0 as approriate for clts instruction exit. */
4637 static void handle_clts(struct kvm_vcpu *vcpu)
4638 {
4639         if (is_guest_mode(vcpu)) {
4640                 /*
4641                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4642                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4643                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4644                  */
4645                 vmcs_writel(CR0_READ_SHADOW,
4646                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4647                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4648         } else
4649                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4650 }
4651
4652 static int handle_cr(struct kvm_vcpu *vcpu)
4653 {
4654         unsigned long exit_qualification, val;
4655         int cr;
4656         int reg;
4657         int err;
4658
4659         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4660         cr = exit_qualification & 15;
4661         reg = (exit_qualification >> 8) & 15;
4662         switch ((exit_qualification >> 4) & 3) {
4663         case 0: /* mov to cr */
4664                 val = kvm_register_read(vcpu, reg);
4665                 trace_kvm_cr_write(cr, val);
4666                 switch (cr) {
4667                 case 0:
4668                         err = handle_set_cr0(vcpu, val);
4669                         kvm_complete_insn_gp(vcpu, err);
4670                         return 1;
4671                 case 3:
4672                         err = kvm_set_cr3(vcpu, val);
4673                         kvm_complete_insn_gp(vcpu, err);
4674                         return 1;
4675                 case 4:
4676                         err = handle_set_cr4(vcpu, val);
4677                         kvm_complete_insn_gp(vcpu, err);
4678                         return 1;
4679                 case 8: {
4680                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4681                                 u8 cr8 = kvm_register_read(vcpu, reg);
4682                                 err = kvm_set_cr8(vcpu, cr8);
4683                                 kvm_complete_insn_gp(vcpu, err);
4684                                 if (irqchip_in_kernel(vcpu->kvm))
4685                                         return 1;
4686                                 if (cr8_prev <= cr8)
4687                                         return 1;
4688                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4689                                 return 0;
4690                         }
4691                 }
4692                 break;
4693         case 2: /* clts */
4694                 handle_clts(vcpu);
4695                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4696                 skip_emulated_instruction(vcpu);
4697                 vmx_fpu_activate(vcpu);
4698                 return 1;
4699         case 1: /*mov from cr*/
4700                 switch (cr) {
4701                 case 3:
4702                         val = kvm_read_cr3(vcpu);
4703                         kvm_register_write(vcpu, reg, val);
4704                         trace_kvm_cr_read(cr, val);
4705                         skip_emulated_instruction(vcpu);
4706                         return 1;
4707                 case 8:
4708                         val = kvm_get_cr8(vcpu);
4709                         kvm_register_write(vcpu, reg, val);
4710                         trace_kvm_cr_read(cr, val);
4711                         skip_emulated_instruction(vcpu);
4712                         return 1;
4713                 }
4714                 break;
4715         case 3: /* lmsw */
4716                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4717                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4718                 kvm_lmsw(vcpu, val);
4719
4720                 skip_emulated_instruction(vcpu);
4721                 return 1;
4722         default:
4723                 break;
4724         }
4725         vcpu->run->exit_reason = 0;
4726         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4727                (int)(exit_qualification >> 4) & 3, cr);
4728         return 0;
4729 }
4730
4731 static int handle_dr(struct kvm_vcpu *vcpu)
4732 {
4733         unsigned long exit_qualification;
4734         int dr, reg;
4735
4736         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4737         if (!kvm_require_cpl(vcpu, 0))
4738                 return 1;
4739         dr = vmcs_readl(GUEST_DR7);
4740         if (dr & DR7_GD) {
4741                 /*
4742                  * As the vm-exit takes precedence over the debug trap, we
4743                  * need to emulate the latter, either for the host or the
4744                  * guest debugging itself.
4745                  */
4746                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4747                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4748                         vcpu->run->debug.arch.dr7 = dr;
4749                         vcpu->run->debug.arch.pc =
4750                                 vmcs_readl(GUEST_CS_BASE) +
4751                                 vmcs_readl(GUEST_RIP);
4752                         vcpu->run->debug.arch.exception = DB_VECTOR;
4753                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4754                         return 0;
4755                 } else {
4756                         vcpu->arch.dr7 &= ~DR7_GD;
4757                         vcpu->arch.dr6 |= DR6_BD;
4758                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4759                         kvm_queue_exception(vcpu, DB_VECTOR);
4760                         return 1;
4761                 }
4762         }
4763
4764         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4765         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4766         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4767         if (exit_qualification & TYPE_MOV_FROM_DR) {
4768                 unsigned long val;
4769                 if (!kvm_get_dr(vcpu, dr, &val))
4770                         kvm_register_write(vcpu, reg, val);
4771         } else
4772                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4773         skip_emulated_instruction(vcpu);
4774         return 1;
4775 }
4776
4777 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4778 {
4779         vmcs_writel(GUEST_DR7, val);
4780 }
4781
4782 static int handle_cpuid(struct kvm_vcpu *vcpu)
4783 {
4784         kvm_emulate_cpuid(vcpu);
4785         return 1;
4786 }
4787
4788 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4789 {
4790         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4791         u64 data;
4792
4793         if (vmx_get_msr(vcpu, ecx, &data)) {
4794                 trace_kvm_msr_read_ex(ecx);
4795                 kvm_inject_gp(vcpu, 0);
4796                 return 1;
4797         }
4798
4799         trace_kvm_msr_read(ecx, data);
4800
4801         /* FIXME: handling of bits 32:63 of rax, rdx */
4802         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4803         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4804         skip_emulated_instruction(vcpu);
4805         return 1;
4806 }
4807
4808 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4809 {
4810         struct msr_data msr;
4811         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4812         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4813                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4814
4815         msr.data = data;
4816         msr.index = ecx;
4817         msr.host_initiated = false;
4818         if (vmx_set_msr(vcpu, &msr) != 0) {
4819                 trace_kvm_msr_write_ex(ecx, data);
4820                 kvm_inject_gp(vcpu, 0);
4821                 return 1;
4822         }
4823
4824         trace_kvm_msr_write(ecx, data);
4825         skip_emulated_instruction(vcpu);
4826         return 1;
4827 }
4828
4829 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4830 {
4831         kvm_make_request(KVM_REQ_EVENT, vcpu);
4832         return 1;
4833 }
4834
4835 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4836 {
4837         u32 cpu_based_vm_exec_control;
4838
4839         /* clear pending irq */
4840         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4841         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4842         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4843
4844         kvm_make_request(KVM_REQ_EVENT, vcpu);
4845
4846         ++vcpu->stat.irq_window_exits;
4847
4848         /*
4849          * If the user space waits to inject interrupts, exit as soon as
4850          * possible
4851          */
4852         if (!irqchip_in_kernel(vcpu->kvm) &&
4853             vcpu->run->request_interrupt_window &&
4854             !kvm_cpu_has_interrupt(vcpu)) {
4855                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4856                 return 0;
4857         }
4858         return 1;
4859 }
4860
4861 static int handle_halt(struct kvm_vcpu *vcpu)
4862 {
4863         skip_emulated_instruction(vcpu);
4864         return kvm_emulate_halt(vcpu);
4865 }
4866
4867 static int handle_vmcall(struct kvm_vcpu *vcpu)
4868 {
4869         skip_emulated_instruction(vcpu);
4870         kvm_emulate_hypercall(vcpu);
4871         return 1;
4872 }
4873
4874 static int handle_invd(struct kvm_vcpu *vcpu)
4875 {
4876         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4877 }
4878
4879 static int handle_invlpg(struct kvm_vcpu *vcpu)
4880 {
4881         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4882
4883         kvm_mmu_invlpg(vcpu, exit_qualification);
4884         skip_emulated_instruction(vcpu);
4885         return 1;
4886 }
4887
4888 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4889 {
4890         int err;
4891
4892         err = kvm_rdpmc(vcpu);
4893         kvm_complete_insn_gp(vcpu, err);
4894
4895         return 1;
4896 }
4897
4898 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4899 {
4900         skip_emulated_instruction(vcpu);
4901         kvm_emulate_wbinvd(vcpu);
4902         return 1;
4903 }
4904
4905 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4906 {
4907         u64 new_bv = kvm_read_edx_eax(vcpu);
4908         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4909
4910         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4911                 skip_emulated_instruction(vcpu);
4912         return 1;
4913 }
4914
4915 static int handle_apic_access(struct kvm_vcpu *vcpu)
4916 {
4917         if (likely(fasteoi)) {
4918                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4919                 int access_type, offset;
4920
4921                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4922                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4923                 /*
4924                  * Sane guest uses MOV to write EOI, with written value
4925                  * not cared. So make a short-circuit here by avoiding
4926                  * heavy instruction emulation.
4927                  */
4928                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4929                     (offset == APIC_EOI)) {
4930                         kvm_lapic_set_eoi(vcpu);
4931                         skip_emulated_instruction(vcpu);
4932                         return 1;
4933                 }
4934         }
4935         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4936 }
4937
4938 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4939 {
4940         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4941         int vector = exit_qualification & 0xff;
4942
4943         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4944         kvm_apic_set_eoi_accelerated(vcpu, vector);
4945         return 1;
4946 }
4947
4948 static int handle_apic_write(struct kvm_vcpu *vcpu)
4949 {
4950         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4951         u32 offset = exit_qualification & 0xfff;
4952
4953         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4954         kvm_apic_write_nodecode(vcpu, offset);
4955         return 1;
4956 }
4957
4958 static int handle_task_switch(struct kvm_vcpu *vcpu)
4959 {
4960         struct vcpu_vmx *vmx = to_vmx(vcpu);
4961         unsigned long exit_qualification;
4962         bool has_error_code = false;
4963         u32 error_code = 0;
4964         u16 tss_selector;
4965         int reason, type, idt_v, idt_index;
4966
4967         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4968         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4969         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4970
4971         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4972
4973         reason = (u32)exit_qualification >> 30;
4974         if (reason == TASK_SWITCH_GATE && idt_v) {
4975                 switch (type) {
4976                 case INTR_TYPE_NMI_INTR:
4977                         vcpu->arch.nmi_injected = false;
4978                         vmx_set_nmi_mask(vcpu, true);
4979                         break;
4980                 case INTR_TYPE_EXT_INTR:
4981                 case INTR_TYPE_SOFT_INTR:
4982                         kvm_clear_interrupt_queue(vcpu);
4983                         break;
4984                 case INTR_TYPE_HARD_EXCEPTION:
4985                         if (vmx->idt_vectoring_info &
4986                             VECTORING_INFO_DELIVER_CODE_MASK) {
4987                                 has_error_code = true;
4988                                 error_code =
4989                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4990                         }
4991                         /* fall through */
4992                 case INTR_TYPE_SOFT_EXCEPTION:
4993                         kvm_clear_exception_queue(vcpu);
4994                         break;
4995                 default:
4996                         break;
4997                 }
4998         }
4999         tss_selector = exit_qualification;
5000
5001         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5002                        type != INTR_TYPE_EXT_INTR &&
5003                        type != INTR_TYPE_NMI_INTR))
5004                 skip_emulated_instruction(vcpu);
5005
5006         if (kvm_task_switch(vcpu, tss_selector,
5007                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5008                             has_error_code, error_code) == EMULATE_FAIL) {
5009                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5010                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5011                 vcpu->run->internal.ndata = 0;
5012                 return 0;
5013         }
5014
5015         /* clear all local breakpoint enable flags */
5016         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5017
5018         /*
5019          * TODO: What about debug traps on tss switch?
5020          *       Are we supposed to inject them and update dr6?
5021          */
5022
5023         return 1;
5024 }
5025
5026 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5027 {
5028         unsigned long exit_qualification;
5029         gpa_t gpa;
5030         u32 error_code;
5031         int gla_validity;
5032
5033         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5034
5035         gla_validity = (exit_qualification >> 7) & 0x3;
5036         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5037                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5038                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5039                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5040                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5041                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5042                         (long unsigned int)exit_qualification);
5043                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5044                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5045                 return 0;
5046         }
5047
5048         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5049         trace_kvm_page_fault(gpa, exit_qualification);
5050
5051         /* It is a write fault? */
5052         error_code = exit_qualification & (1U << 1);
5053         /* ept page table is present? */
5054         error_code |= (exit_qualification >> 3) & 0x1;
5055
5056         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5057 }
5058
5059 static u64 ept_rsvd_mask(u64 spte, int level)
5060 {
5061         int i;
5062         u64 mask = 0;
5063
5064         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5065                 mask |= (1ULL << i);
5066
5067         if (level > 2)
5068                 /* bits 7:3 reserved */
5069                 mask |= 0xf8;
5070         else if (level == 2) {
5071                 if (spte & (1ULL << 7))
5072                         /* 2MB ref, bits 20:12 reserved */
5073                         mask |= 0x1ff000;
5074                 else
5075                         /* bits 6:3 reserved */
5076                         mask |= 0x78;
5077         }
5078
5079         return mask;
5080 }
5081
5082 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5083                                        int level)
5084 {
5085         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5086
5087         /* 010b (write-only) */
5088         WARN_ON((spte & 0x7) == 0x2);
5089
5090         /* 110b (write/execute) */
5091         WARN_ON((spte & 0x7) == 0x6);
5092
5093         /* 100b (execute-only) and value not supported by logical processor */
5094         if (!cpu_has_vmx_ept_execute_only())
5095                 WARN_ON((spte & 0x7) == 0x4);
5096
5097         /* not 000b */
5098         if ((spte & 0x7)) {
5099                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5100
5101                 if (rsvd_bits != 0) {
5102                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5103                                          __func__, rsvd_bits);
5104                         WARN_ON(1);
5105                 }
5106
5107                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5108                         u64 ept_mem_type = (spte & 0x38) >> 3;
5109
5110                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5111                             ept_mem_type == 7) {
5112                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5113                                                 __func__, ept_mem_type);
5114                                 WARN_ON(1);
5115                         }
5116                 }
5117         }
5118 }
5119
5120 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5121 {
5122         u64 sptes[4];
5123         int nr_sptes, i, ret;
5124         gpa_t gpa;
5125
5126         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5127
5128         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5129         if (likely(ret == 1))
5130                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5131                                               EMULATE_DONE;
5132         if (unlikely(!ret))
5133                 return 1;
5134
5135         /* It is the real ept misconfig */
5136         printk(KERN_ERR "EPT: Misconfiguration.\n");
5137         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5138
5139         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5140
5141         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5142                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5143
5144         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5145         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5146
5147         return 0;
5148 }
5149
5150 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5151 {
5152         u32 cpu_based_vm_exec_control;
5153
5154         /* clear pending NMI */
5155         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5156         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5157         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5158         ++vcpu->stat.nmi_window_exits;
5159         kvm_make_request(KVM_REQ_EVENT, vcpu);
5160
5161         return 1;
5162 }
5163
5164 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5165 {
5166         struct vcpu_vmx *vmx = to_vmx(vcpu);
5167         enum emulation_result err = EMULATE_DONE;
5168         int ret = 1;
5169         u32 cpu_exec_ctrl;
5170         bool intr_window_requested;
5171         unsigned count = 130;
5172
5173         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5174         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5175
5176         while (!guest_state_valid(vcpu) && count-- != 0) {
5177                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5178                         return handle_interrupt_window(&vmx->vcpu);
5179
5180                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5181                         return 1;
5182
5183                 err = emulate_instruction(vcpu, 0);
5184
5185                 if (err == EMULATE_DO_MMIO) {
5186                         ret = 0;
5187                         goto out;
5188                 }
5189
5190                 if (err != EMULATE_DONE) {
5191                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5192                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5193                         vcpu->run->internal.ndata = 0;
5194                         return 0;
5195                 }
5196
5197                 if (signal_pending(current))
5198                         goto out;
5199                 if (need_resched())
5200                         schedule();
5201         }
5202
5203         vmx->emulation_required = emulation_required(vcpu);
5204 out:
5205         return ret;
5206 }
5207
5208 /*
5209  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5210  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5211  */
5212 static int handle_pause(struct kvm_vcpu *vcpu)
5213 {
5214         skip_emulated_instruction(vcpu);
5215         kvm_vcpu_on_spin(vcpu);
5216
5217         return 1;
5218 }
5219
5220 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5221 {
5222         kvm_queue_exception(vcpu, UD_VECTOR);
5223         return 1;
5224 }
5225
5226 /*
5227  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5228  * We could reuse a single VMCS for all the L2 guests, but we also want the
5229  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5230  * allows keeping them loaded on the processor, and in the future will allow
5231  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5232  * every entry if they never change.
5233  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5234  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5235  *
5236  * The following functions allocate and free a vmcs02 in this pool.
5237  */
5238
5239 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5240 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5241 {
5242         struct vmcs02_list *item;
5243         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5244                 if (item->vmptr == vmx->nested.current_vmptr) {
5245                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5246                         return &item->vmcs02;
5247                 }
5248
5249         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5250                 /* Recycle the least recently used VMCS. */
5251                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5252                         struct vmcs02_list, list);
5253                 item->vmptr = vmx->nested.current_vmptr;
5254                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5255                 return &item->vmcs02;
5256         }
5257
5258         /* Create a new VMCS */
5259         item = (struct vmcs02_list *)
5260                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5261         if (!item)
5262                 return NULL;
5263         item->vmcs02.vmcs = alloc_vmcs();
5264         if (!item->vmcs02.vmcs) {
5265                 kfree(item);
5266                 return NULL;
5267         }
5268         loaded_vmcs_init(&item->vmcs02);
5269         item->vmptr = vmx->nested.current_vmptr;
5270         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5271         vmx->nested.vmcs02_num++;
5272         return &item->vmcs02;
5273 }
5274
5275 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5276 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5277 {
5278         struct vmcs02_list *item;
5279         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5280                 if (item->vmptr == vmptr) {
5281                         free_loaded_vmcs(&item->vmcs02);
5282                         list_del(&item->list);
5283                         kfree(item);
5284                         vmx->nested.vmcs02_num--;
5285                         return;
5286                 }
5287 }
5288
5289 /*
5290  * Free all VMCSs saved for this vcpu, except the one pointed by
5291  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5292  * currently used, if running L2), and vmcs01 when running L2.
5293  */
5294 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5295 {
5296         struct vmcs02_list *item, *n;
5297         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5298                 if (vmx->loaded_vmcs != &item->vmcs02)
5299                         free_loaded_vmcs(&item->vmcs02);
5300                 list_del(&item->list);
5301                 kfree(item);
5302         }
5303         vmx->nested.vmcs02_num = 0;
5304
5305         if (vmx->loaded_vmcs != &vmx->vmcs01)
5306                 free_loaded_vmcs(&vmx->vmcs01);
5307 }
5308
5309 /*
5310  * Emulate the VMXON instruction.
5311  * Currently, we just remember that VMX is active, and do not save or even
5312  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5313  * do not currently need to store anything in that guest-allocated memory
5314  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5315  * argument is different from the VMXON pointer (which the spec says they do).
5316  */
5317 static int handle_vmon(struct kvm_vcpu *vcpu)
5318 {
5319         struct kvm_segment cs;
5320         struct vcpu_vmx *vmx = to_vmx(vcpu);
5321
5322         /* The Intel VMX Instruction Reference lists a bunch of bits that
5323          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5324          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5325          * Otherwise, we should fail with #UD. We test these now:
5326          */
5327         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5328             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5329             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5330                 kvm_queue_exception(vcpu, UD_VECTOR);
5331                 return 1;
5332         }
5333
5334         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5335         if (is_long_mode(vcpu) && !cs.l) {
5336                 kvm_queue_exception(vcpu, UD_VECTOR);
5337                 return 1;
5338         }
5339
5340         if (vmx_get_cpl(vcpu)) {
5341                 kvm_inject_gp(vcpu, 0);
5342                 return 1;
5343         }
5344
5345         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5346         vmx->nested.vmcs02_num = 0;
5347
5348         vmx->nested.vmxon = true;
5349
5350         skip_emulated_instruction(vcpu);
5351         return 1;
5352 }
5353
5354 /*
5355  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5356  * for running VMX instructions (except VMXON, whose prerequisites are
5357  * slightly different). It also specifies what exception to inject otherwise.
5358  */
5359 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5360 {
5361         struct kvm_segment cs;
5362         struct vcpu_vmx *vmx = to_vmx(vcpu);
5363
5364         if (!vmx->nested.vmxon) {
5365                 kvm_queue_exception(vcpu, UD_VECTOR);
5366                 return 0;
5367         }
5368
5369         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5370         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5371             (is_long_mode(vcpu) && !cs.l)) {
5372                 kvm_queue_exception(vcpu, UD_VECTOR);
5373                 return 0;
5374         }
5375
5376         if (vmx_get_cpl(vcpu)) {
5377                 kvm_inject_gp(vcpu, 0);
5378                 return 0;
5379         }
5380
5381         return 1;
5382 }
5383
5384 /*
5385  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5386  * just stops using VMX.
5387  */
5388 static void free_nested(struct vcpu_vmx *vmx)
5389 {
5390         if (!vmx->nested.vmxon)
5391                 return;
5392         vmx->nested.vmxon = false;
5393         if (vmx->nested.current_vmptr != -1ull) {
5394                 kunmap(vmx->nested.current_vmcs12_page);
5395                 nested_release_page(vmx->nested.current_vmcs12_page);
5396                 vmx->nested.current_vmptr = -1ull;
5397                 vmx->nested.current_vmcs12 = NULL;
5398         }
5399         /* Unpin physical memory we referred to in current vmcs02 */
5400         if (vmx->nested.apic_access_page) {
5401                 nested_release_page(vmx->nested.apic_access_page);
5402                 vmx->nested.apic_access_page = 0;
5403         }
5404
5405         nested_free_all_saved_vmcss(vmx);
5406 }
5407
5408 /* Emulate the VMXOFF instruction */
5409 static int handle_vmoff(struct kvm_vcpu *vcpu)
5410 {
5411         if (!nested_vmx_check_permission(vcpu))
5412                 return 1;
5413         free_nested(to_vmx(vcpu));
5414         skip_emulated_instruction(vcpu);
5415         return 1;
5416 }
5417
5418 /*
5419  * Decode the memory-address operand of a vmx instruction, as recorded on an
5420  * exit caused by such an instruction (run by a guest hypervisor).
5421  * On success, returns 0. When the operand is invalid, returns 1 and throws
5422  * #UD or #GP.
5423  */
5424 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5425                                  unsigned long exit_qualification,
5426                                  u32 vmx_instruction_info, gva_t *ret)
5427 {
5428         /*
5429          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5430          * Execution", on an exit, vmx_instruction_info holds most of the
5431          * addressing components of the operand. Only the displacement part
5432          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5433          * For how an actual address is calculated from all these components,
5434          * refer to Vol. 1, "Operand Addressing".
5435          */
5436         int  scaling = vmx_instruction_info & 3;
5437         int  addr_size = (vmx_instruction_info >> 7) & 7;
5438         bool is_reg = vmx_instruction_info & (1u << 10);
5439         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5440         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5441         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5442         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5443         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5444
5445         if (is_reg) {
5446                 kvm_queue_exception(vcpu, UD_VECTOR);
5447                 return 1;
5448         }
5449
5450         /* Addr = segment_base + offset */
5451         /* offset = base + [index * scale] + displacement */
5452         *ret = vmx_get_segment_base(vcpu, seg_reg);
5453         if (base_is_valid)
5454                 *ret += kvm_register_read(vcpu, base_reg);
5455         if (index_is_valid)
5456                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5457         *ret += exit_qualification; /* holds the displacement */
5458
5459         if (addr_size == 1) /* 32 bit */
5460                 *ret &= 0xffffffff;
5461
5462         /*
5463          * TODO: throw #GP (and return 1) in various cases that the VM*
5464          * instructions require it - e.g., offset beyond segment limit,
5465          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5466          * address, and so on. Currently these are not checked.
5467          */
5468         return 0;
5469 }
5470
5471 /*
5472  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5473  * set the success or error code of an emulated VMX instruction, as specified
5474  * by Vol 2B, VMX Instruction Reference, "Conventions".
5475  */
5476 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5477 {
5478         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5479                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5480                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5481 }
5482
5483 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5484 {
5485         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5486                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5487                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5488                         | X86_EFLAGS_CF);
5489 }
5490
5491 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5492                                         u32 vm_instruction_error)
5493 {
5494         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5495                 /*
5496                  * failValid writes the error number to the current VMCS, which
5497                  * can't be done there isn't a current VMCS.
5498                  */
5499                 nested_vmx_failInvalid(vcpu);
5500                 return;
5501         }
5502         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5503                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5504                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5505                         | X86_EFLAGS_ZF);
5506         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5507 }
5508
5509 /* Emulate the VMCLEAR instruction */
5510 static int handle_vmclear(struct kvm_vcpu *vcpu)
5511 {
5512         struct vcpu_vmx *vmx = to_vmx(vcpu);
5513         gva_t gva;
5514         gpa_t vmptr;
5515         struct vmcs12 *vmcs12;
5516         struct page *page;
5517         struct x86_exception e;
5518
5519         if (!nested_vmx_check_permission(vcpu))
5520                 return 1;
5521
5522         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5523                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5524                 return 1;
5525
5526         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5527                                 sizeof(vmptr), &e)) {
5528                 kvm_inject_page_fault(vcpu, &e);
5529                 return 1;
5530         }
5531
5532         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5533                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5534                 skip_emulated_instruction(vcpu);
5535                 return 1;
5536         }
5537
5538         if (vmptr == vmx->nested.current_vmptr) {
5539                 kunmap(vmx->nested.current_vmcs12_page);
5540                 nested_release_page(vmx->nested.current_vmcs12_page);
5541                 vmx->nested.current_vmptr = -1ull;
5542                 vmx->nested.current_vmcs12 = NULL;
5543         }
5544
5545         page = nested_get_page(vcpu, vmptr);
5546         if (page == NULL) {
5547                 /*
5548                  * For accurate processor emulation, VMCLEAR beyond available
5549                  * physical memory should do nothing at all. However, it is
5550                  * possible that a nested vmx bug, not a guest hypervisor bug,
5551                  * resulted in this case, so let's shut down before doing any
5552                  * more damage:
5553                  */
5554                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5555                 return 1;
5556         }
5557         vmcs12 = kmap(page);
5558         vmcs12->launch_state = 0;
5559         kunmap(page);
5560         nested_release_page(page);
5561
5562         nested_free_vmcs02(vmx, vmptr);
5563
5564         skip_emulated_instruction(vcpu);
5565         nested_vmx_succeed(vcpu);
5566         return 1;
5567 }
5568
5569 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5570
5571 /* Emulate the VMLAUNCH instruction */
5572 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5573 {
5574         return nested_vmx_run(vcpu, true);
5575 }
5576
5577 /* Emulate the VMRESUME instruction */
5578 static int handle_vmresume(struct kvm_vcpu *vcpu)
5579 {
5580
5581         return nested_vmx_run(vcpu, false);
5582 }
5583
5584 enum vmcs_field_type {
5585         VMCS_FIELD_TYPE_U16 = 0,
5586         VMCS_FIELD_TYPE_U64 = 1,
5587         VMCS_FIELD_TYPE_U32 = 2,
5588         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5589 };
5590
5591 static inline int vmcs_field_type(unsigned long field)
5592 {
5593         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5594                 return VMCS_FIELD_TYPE_U32;
5595         return (field >> 13) & 0x3 ;
5596 }
5597
5598 static inline int vmcs_field_readonly(unsigned long field)
5599 {
5600         return (((field >> 10) & 0x3) == 1);
5601 }
5602
5603 /*
5604  * Read a vmcs12 field. Since these can have varying lengths and we return
5605  * one type, we chose the biggest type (u64) and zero-extend the return value
5606  * to that size. Note that the caller, handle_vmread, might need to use only
5607  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5608  * 64-bit fields are to be returned).
5609  */
5610 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5611                                         unsigned long field, u64 *ret)
5612 {
5613         short offset = vmcs_field_to_offset(field);
5614         char *p;
5615
5616         if (offset < 0)
5617                 return 0;
5618
5619         p = ((char *)(get_vmcs12(vcpu))) + offset;
5620
5621         switch (vmcs_field_type(field)) {
5622         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5623                 *ret = *((natural_width *)p);
5624                 return 1;
5625         case VMCS_FIELD_TYPE_U16:
5626                 *ret = *((u16 *)p);
5627                 return 1;
5628         case VMCS_FIELD_TYPE_U32:
5629                 *ret = *((u32 *)p);
5630                 return 1;
5631         case VMCS_FIELD_TYPE_U64:
5632                 *ret = *((u64 *)p);
5633                 return 1;
5634         default:
5635                 return 0; /* can never happen. */
5636         }
5637 }
5638
5639 /*
5640  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5641  * used before) all generate the same failure when it is missing.
5642  */
5643 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5644 {
5645         struct vcpu_vmx *vmx = to_vmx(vcpu);
5646         if (vmx->nested.current_vmptr == -1ull) {
5647                 nested_vmx_failInvalid(vcpu);
5648                 skip_emulated_instruction(vcpu);
5649                 return 0;
5650         }
5651         return 1;
5652 }
5653
5654 static int handle_vmread(struct kvm_vcpu *vcpu)
5655 {
5656         unsigned long field;
5657         u64 field_value;
5658         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5659         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5660         gva_t gva = 0;
5661
5662         if (!nested_vmx_check_permission(vcpu) ||
5663             !nested_vmx_check_vmcs12(vcpu))
5664                 return 1;
5665
5666         /* Decode instruction info and find the field to read */
5667         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5668         /* Read the field, zero-extended to a u64 field_value */
5669         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5670                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5671                 skip_emulated_instruction(vcpu);
5672                 return 1;
5673         }
5674         /*
5675          * Now copy part of this value to register or memory, as requested.
5676          * Note that the number of bits actually copied is 32 or 64 depending
5677          * on the guest's mode (32 or 64 bit), not on the given field's length.
5678          */
5679         if (vmx_instruction_info & (1u << 10)) {
5680                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5681                         field_value);
5682         } else {
5683                 if (get_vmx_mem_address(vcpu, exit_qualification,
5684                                 vmx_instruction_info, &gva))
5685                         return 1;
5686                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5687                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5688                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5689         }
5690
5691         nested_vmx_succeed(vcpu);
5692         skip_emulated_instruction(vcpu);
5693         return 1;
5694 }
5695
5696
5697 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5698 {
5699         unsigned long field;
5700         gva_t gva;
5701         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5702         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5703         char *p;
5704         short offset;
5705         /* The value to write might be 32 or 64 bits, depending on L1's long
5706          * mode, and eventually we need to write that into a field of several
5707          * possible lengths. The code below first zero-extends the value to 64
5708          * bit (field_value), and then copies only the approriate number of
5709          * bits into the vmcs12 field.
5710          */
5711         u64 field_value = 0;
5712         struct x86_exception e;
5713
5714         if (!nested_vmx_check_permission(vcpu) ||
5715             !nested_vmx_check_vmcs12(vcpu))
5716                 return 1;
5717
5718         if (vmx_instruction_info & (1u << 10))
5719                 field_value = kvm_register_read(vcpu,
5720                         (((vmx_instruction_info) >> 3) & 0xf));
5721         else {
5722                 if (get_vmx_mem_address(vcpu, exit_qualification,
5723                                 vmx_instruction_info, &gva))
5724                         return 1;
5725                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5726                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5727                         kvm_inject_page_fault(vcpu, &e);
5728                         return 1;
5729                 }
5730         }
5731
5732
5733         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5734         if (vmcs_field_readonly(field)) {
5735                 nested_vmx_failValid(vcpu,
5736                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5737                 skip_emulated_instruction(vcpu);
5738                 return 1;
5739         }
5740
5741         offset = vmcs_field_to_offset(field);
5742         if (offset < 0) {
5743                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5744                 skip_emulated_instruction(vcpu);
5745                 return 1;
5746         }
5747         p = ((char *) get_vmcs12(vcpu)) + offset;
5748
5749         switch (vmcs_field_type(field)) {
5750         case VMCS_FIELD_TYPE_U16:
5751                 *(u16 *)p = field_value;
5752                 break;
5753         case VMCS_FIELD_TYPE_U32:
5754                 *(u32 *)p = field_value;
5755                 break;
5756         case VMCS_FIELD_TYPE_U64:
5757                 *(u64 *)p = field_value;
5758                 break;
5759         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5760                 *(natural_width *)p = field_value;
5761                 break;
5762         default:
5763                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5764                 skip_emulated_instruction(vcpu);
5765                 return 1;
5766         }
5767
5768         nested_vmx_succeed(vcpu);
5769         skip_emulated_instruction(vcpu);
5770         return 1;
5771 }
5772
5773 /* Emulate the VMPTRLD instruction */
5774 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5775 {
5776         struct vcpu_vmx *vmx = to_vmx(vcpu);
5777         gva_t gva;
5778         gpa_t vmptr;
5779         struct x86_exception e;
5780
5781         if (!nested_vmx_check_permission(vcpu))
5782                 return 1;
5783
5784         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5785                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5786                 return 1;
5787
5788         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5789                                 sizeof(vmptr), &e)) {
5790                 kvm_inject_page_fault(vcpu, &e);
5791                 return 1;
5792         }
5793
5794         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5795                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5796                 skip_emulated_instruction(vcpu);
5797                 return 1;
5798         }
5799
5800         if (vmx->nested.current_vmptr != vmptr) {
5801                 struct vmcs12 *new_vmcs12;
5802                 struct page *page;
5803                 page = nested_get_page(vcpu, vmptr);
5804                 if (page == NULL) {
5805                         nested_vmx_failInvalid(vcpu);
5806                         skip_emulated_instruction(vcpu);
5807                         return 1;
5808                 }
5809                 new_vmcs12 = kmap(page);
5810                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5811                         kunmap(page);
5812                         nested_release_page_clean(page);
5813                         nested_vmx_failValid(vcpu,
5814                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5815                         skip_emulated_instruction(vcpu);
5816                         return 1;
5817                 }
5818                 if (vmx->nested.current_vmptr != -1ull) {
5819                         kunmap(vmx->nested.current_vmcs12_page);
5820                         nested_release_page(vmx->nested.current_vmcs12_page);
5821                 }
5822
5823                 vmx->nested.current_vmptr = vmptr;
5824                 vmx->nested.current_vmcs12 = new_vmcs12;
5825                 vmx->nested.current_vmcs12_page = page;
5826         }
5827
5828         nested_vmx_succeed(vcpu);
5829         skip_emulated_instruction(vcpu);
5830         return 1;
5831 }
5832
5833 /* Emulate the VMPTRST instruction */
5834 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5835 {
5836         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5837         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5838         gva_t vmcs_gva;
5839         struct x86_exception e;
5840
5841         if (!nested_vmx_check_permission(vcpu))
5842                 return 1;
5843
5844         if (get_vmx_mem_address(vcpu, exit_qualification,
5845                         vmx_instruction_info, &vmcs_gva))
5846                 return 1;
5847         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5848         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5849                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5850                                  sizeof(u64), &e)) {
5851                 kvm_inject_page_fault(vcpu, &e);
5852                 return 1;
5853         }
5854         nested_vmx_succeed(vcpu);
5855         skip_emulated_instruction(vcpu);
5856         return 1;
5857 }
5858
5859 /*
5860  * The exit handlers return 1 if the exit was handled fully and guest execution
5861  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5862  * to be done to userspace and return 0.
5863  */
5864 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5865         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5866         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5867         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5868         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5869         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5870         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5871         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5872         [EXIT_REASON_CPUID]                   = handle_cpuid,
5873         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5874         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5875         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5876         [EXIT_REASON_HLT]                     = handle_halt,
5877         [EXIT_REASON_INVD]                    = handle_invd,
5878         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5879         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5880         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5881         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5882         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5883         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5884         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5885         [EXIT_REASON_VMREAD]                  = handle_vmread,
5886         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5887         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5888         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5889         [EXIT_REASON_VMON]                    = handle_vmon,
5890         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5891         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5892         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5893         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5894         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5895         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5896         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5897         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5898         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5899         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5900         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5901         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5902         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5903 };
5904
5905 static const int kvm_vmx_max_exit_handlers =
5906         ARRAY_SIZE(kvm_vmx_exit_handlers);
5907
5908 /*
5909  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5910  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5911  * disinterest in the current event (read or write a specific MSR) by using an
5912  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5913  */
5914 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5915         struct vmcs12 *vmcs12, u32 exit_reason)
5916 {
5917         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5918         gpa_t bitmap;
5919
5920         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5921                 return 1;
5922
5923         /*
5924          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5925          * for the four combinations of read/write and low/high MSR numbers.
5926          * First we need to figure out which of the four to use:
5927          */
5928         bitmap = vmcs12->msr_bitmap;
5929         if (exit_reason == EXIT_REASON_MSR_WRITE)
5930                 bitmap += 2048;
5931         if (msr_index >= 0xc0000000) {
5932                 msr_index -= 0xc0000000;
5933                 bitmap += 1024;
5934         }
5935
5936         /* Then read the msr_index'th bit from this bitmap: */
5937         if (msr_index < 1024*8) {
5938                 unsigned char b;
5939                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5940                 return 1 & (b >> (msr_index & 7));
5941         } else
5942                 return 1; /* let L1 handle the wrong parameter */
5943 }
5944
5945 /*
5946  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5947  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5948  * intercept (via guest_host_mask etc.) the current event.
5949  */
5950 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5951         struct vmcs12 *vmcs12)
5952 {
5953         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5954         int cr = exit_qualification & 15;
5955         int reg = (exit_qualification >> 8) & 15;
5956         unsigned long val = kvm_register_read(vcpu, reg);
5957
5958         switch ((exit_qualification >> 4) & 3) {
5959         case 0: /* mov to cr */
5960                 switch (cr) {
5961                 case 0:
5962                         if (vmcs12->cr0_guest_host_mask &
5963                             (val ^ vmcs12->cr0_read_shadow))
5964                                 return 1;
5965                         break;
5966                 case 3:
5967                         if ((vmcs12->cr3_target_count >= 1 &&
5968                                         vmcs12->cr3_target_value0 == val) ||
5969                                 (vmcs12->cr3_target_count >= 2 &&
5970                                         vmcs12->cr3_target_value1 == val) ||
5971                                 (vmcs12->cr3_target_count >= 3 &&
5972                                         vmcs12->cr3_target_value2 == val) ||
5973                                 (vmcs12->cr3_target_count >= 4 &&
5974                                         vmcs12->cr3_target_value3 == val))
5975                                 return 0;
5976                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5977                                 return 1;
5978                         break;
5979                 case 4:
5980                         if (vmcs12->cr4_guest_host_mask &
5981                             (vmcs12->cr4_read_shadow ^ val))
5982                                 return 1;
5983                         break;
5984                 case 8:
5985                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5986                                 return 1;
5987                         break;
5988                 }
5989                 break;
5990         case 2: /* clts */
5991                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5992                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5993                         return 1;
5994                 break;
5995         case 1: /* mov from cr */
5996                 switch (cr) {
5997                 case 3:
5998                         if (vmcs12->cpu_based_vm_exec_control &
5999                             CPU_BASED_CR3_STORE_EXITING)
6000                                 return 1;
6001                         break;
6002                 case 8:
6003                         if (vmcs12->cpu_based_vm_exec_control &
6004                             CPU_BASED_CR8_STORE_EXITING)
6005                                 return 1;
6006                         break;
6007                 }
6008                 break;
6009         case 3: /* lmsw */
6010                 /*
6011                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6012                  * cr0. Other attempted changes are ignored, with no exit.
6013                  */
6014                 if (vmcs12->cr0_guest_host_mask & 0xe &
6015                     (val ^ vmcs12->cr0_read_shadow))
6016                         return 1;
6017                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6018                     !(vmcs12->cr0_read_shadow & 0x1) &&
6019                     (val & 0x1))
6020                         return 1;
6021                 break;
6022         }
6023         return 0;
6024 }
6025
6026 /*
6027  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6028  * should handle it ourselves in L0 (and then continue L2). Only call this
6029  * when in is_guest_mode (L2).
6030  */
6031 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6032 {
6033         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
6034         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6035         struct vcpu_vmx *vmx = to_vmx(vcpu);
6036         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6037
6038         if (vmx->nested.nested_run_pending)
6039                 return 0;
6040
6041         if (unlikely(vmx->fail)) {
6042                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6043                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6044                 return 1;
6045         }
6046
6047         switch (exit_reason) {
6048         case EXIT_REASON_EXCEPTION_NMI:
6049                 if (!is_exception(intr_info))
6050                         return 0;
6051                 else if (is_page_fault(intr_info))
6052                         return enable_ept;
6053                 return vmcs12->exception_bitmap &
6054                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6055         case EXIT_REASON_EXTERNAL_INTERRUPT:
6056                 return 0;
6057         case EXIT_REASON_TRIPLE_FAULT:
6058                 return 1;
6059         case EXIT_REASON_PENDING_INTERRUPT:
6060         case EXIT_REASON_NMI_WINDOW:
6061                 /*
6062                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
6063                  * (aka Interrupt Window Exiting) only when L1 turned it on,
6064                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
6065                  * Same for NMI Window Exiting.
6066                  */
6067                 return 1;
6068         case EXIT_REASON_TASK_SWITCH:
6069                 return 1;
6070         case EXIT_REASON_CPUID:
6071                 return 1;
6072         case EXIT_REASON_HLT:
6073                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6074         case EXIT_REASON_INVD:
6075                 return 1;
6076         case EXIT_REASON_INVLPG:
6077                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6078         case EXIT_REASON_RDPMC:
6079                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6080         case EXIT_REASON_RDTSC:
6081                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6082         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6083         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6084         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6085         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6086         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6087                 /*
6088                  * VMX instructions trap unconditionally. This allows L1 to
6089                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6090                  */
6091                 return 1;
6092         case EXIT_REASON_CR_ACCESS:
6093                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6094         case EXIT_REASON_DR_ACCESS:
6095                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6096         case EXIT_REASON_IO_INSTRUCTION:
6097                 /* TODO: support IO bitmaps */
6098                 return 1;
6099         case EXIT_REASON_MSR_READ:
6100         case EXIT_REASON_MSR_WRITE:
6101                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6102         case EXIT_REASON_INVALID_STATE:
6103                 return 1;
6104         case EXIT_REASON_MWAIT_INSTRUCTION:
6105                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6106         case EXIT_REASON_MONITOR_INSTRUCTION:
6107                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6108         case EXIT_REASON_PAUSE_INSTRUCTION:
6109                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6110                         nested_cpu_has2(vmcs12,
6111                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6112         case EXIT_REASON_MCE_DURING_VMENTRY:
6113                 return 0;
6114         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6115                 return 1;
6116         case EXIT_REASON_APIC_ACCESS:
6117                 return nested_cpu_has2(vmcs12,
6118                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6119         case EXIT_REASON_EPT_VIOLATION:
6120         case EXIT_REASON_EPT_MISCONFIG:
6121                 return 0;
6122         case EXIT_REASON_WBINVD:
6123                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6124         case EXIT_REASON_XSETBV:
6125                 return 1;
6126         default:
6127                 return 1;
6128         }
6129 }
6130
6131 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6132 {
6133         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6134         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6135 }
6136
6137 /*
6138  * The guest has exited.  See if we can fix it or if we need userspace
6139  * assistance.
6140  */
6141 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6142 {
6143         struct vcpu_vmx *vmx = to_vmx(vcpu);
6144         u32 exit_reason = vmx->exit_reason;
6145         u32 vectoring_info = vmx->idt_vectoring_info;
6146
6147         /* If guest state is invalid, start emulating */
6148         if (vmx->emulation_required)
6149                 return handle_invalid_guest_state(vcpu);
6150
6151         /*
6152          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6153          * we did not inject a still-pending event to L1 now because of
6154          * nested_run_pending, we need to re-enable this bit.
6155          */
6156         if (vmx->nested.nested_run_pending)
6157                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6158
6159         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6160             exit_reason == EXIT_REASON_VMRESUME))
6161                 vmx->nested.nested_run_pending = 1;
6162         else
6163                 vmx->nested.nested_run_pending = 0;
6164
6165         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6166                 nested_vmx_vmexit(vcpu);
6167                 return 1;
6168         }
6169
6170         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6171                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6172                 vcpu->run->fail_entry.hardware_entry_failure_reason
6173                         = exit_reason;
6174                 return 0;
6175         }
6176
6177         if (unlikely(vmx->fail)) {
6178                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6179                 vcpu->run->fail_entry.hardware_entry_failure_reason
6180                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6181                 return 0;
6182         }
6183
6184         /*
6185          * Note:
6186          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6187          * delivery event since it indicates guest is accessing MMIO.
6188          * The vm-exit can be triggered again after return to guest that
6189          * will cause infinite loop.
6190          */
6191         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6192                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6193                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6194                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6195                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6196                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6197                 vcpu->run->internal.ndata = 2;
6198                 vcpu->run->internal.data[0] = vectoring_info;
6199                 vcpu->run->internal.data[1] = exit_reason;
6200                 return 0;
6201         }
6202
6203         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6204             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6205                                         get_vmcs12(vcpu), vcpu)))) {
6206                 if (vmx_interrupt_allowed(vcpu)) {
6207                         vmx->soft_vnmi_blocked = 0;
6208                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6209                            vcpu->arch.nmi_pending) {
6210                         /*
6211                          * This CPU don't support us in finding the end of an
6212                          * NMI-blocked window if the guest runs with IRQs
6213                          * disabled. So we pull the trigger after 1 s of
6214                          * futile waiting, but inform the user about this.
6215                          */
6216                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6217                                "state on VCPU %d after 1 s timeout\n",
6218                                __func__, vcpu->vcpu_id);
6219                         vmx->soft_vnmi_blocked = 0;
6220                 }
6221         }
6222
6223         if (exit_reason < kvm_vmx_max_exit_handlers
6224             && kvm_vmx_exit_handlers[exit_reason])
6225                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6226         else {
6227                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6228                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6229         }
6230         return 0;
6231 }
6232
6233 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6234 {
6235         if (irr == -1 || tpr < irr) {
6236                 vmcs_write32(TPR_THRESHOLD, 0);
6237                 return;
6238         }
6239
6240         vmcs_write32(TPR_THRESHOLD, irr);
6241 }
6242
6243 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6244 {
6245         u32 sec_exec_control;
6246
6247         /*
6248          * There is not point to enable virtualize x2apic without enable
6249          * apicv
6250          */
6251         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6252                                 !vmx_vm_has_apicv(vcpu->kvm))
6253                 return;
6254
6255         if (!vm_need_tpr_shadow(vcpu->kvm))
6256                 return;
6257
6258         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6259
6260         if (set) {
6261                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6262                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6263         } else {
6264                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6265                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6266         }
6267         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6268
6269         vmx_set_msr_bitmap(vcpu);
6270 }
6271
6272 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6273 {
6274         u16 status;
6275         u8 old;
6276
6277         if (!vmx_vm_has_apicv(kvm))
6278                 return;
6279
6280         if (isr == -1)
6281                 isr = 0;
6282
6283         status = vmcs_read16(GUEST_INTR_STATUS);
6284         old = status >> 8;
6285         if (isr != old) {
6286                 status &= 0xff;
6287                 status |= isr << 8;
6288                 vmcs_write16(GUEST_INTR_STATUS, status);
6289         }
6290 }
6291
6292 static void vmx_set_rvi(int vector)
6293 {
6294         u16 status;
6295         u8 old;
6296
6297         status = vmcs_read16(GUEST_INTR_STATUS);
6298         old = (u8)status & 0xff;
6299         if ((u8)vector != old) {
6300                 status &= ~0xff;
6301                 status |= (u8)vector;
6302                 vmcs_write16(GUEST_INTR_STATUS, status);
6303         }
6304 }
6305
6306 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6307 {
6308         if (max_irr == -1)
6309                 return;
6310
6311         vmx_set_rvi(max_irr);
6312 }
6313
6314 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6315 {
6316         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6317         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6318         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6319         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6320 }
6321
6322 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6323 {
6324         u32 exit_intr_info;
6325
6326         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6327               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6328                 return;
6329
6330         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6331         exit_intr_info = vmx->exit_intr_info;
6332
6333         /* Handle machine checks before interrupts are enabled */
6334         if (is_machine_check(exit_intr_info))
6335                 kvm_machine_check();
6336
6337         /* We need to handle NMIs before interrupts are enabled */
6338         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6339             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6340                 kvm_before_handle_nmi(&vmx->vcpu);
6341                 asm("int $2");
6342                 kvm_after_handle_nmi(&vmx->vcpu);
6343         }
6344 }
6345
6346 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6347 {
6348         u32 exit_intr_info;
6349         bool unblock_nmi;
6350         u8 vector;
6351         bool idtv_info_valid;
6352
6353         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6354
6355         if (cpu_has_virtual_nmis()) {
6356                 if (vmx->nmi_known_unmasked)
6357                         return;
6358                 /*
6359                  * Can't use vmx->exit_intr_info since we're not sure what
6360                  * the exit reason is.
6361                  */
6362                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6363                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6364                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6365                 /*
6366                  * SDM 3: 27.7.1.2 (September 2008)
6367                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6368                  * a guest IRET fault.
6369                  * SDM 3: 23.2.2 (September 2008)
6370                  * Bit 12 is undefined in any of the following cases:
6371                  *  If the VM exit sets the valid bit in the IDT-vectoring
6372                  *   information field.
6373                  *  If the VM exit is due to a double fault.