KVM: introduce KVM_PFN_ERR_HWPOISON
[linux-3.10.git] / arch / x86 / kvm / mmu.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * MMU support
8  *
9  * Copyright (C) 2006 Qumranet, Inc.
10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11  *
12  * Authors:
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Avi Kivity   <avi@qumranet.com>
15  *
16  * This work is licensed under the terms of the GNU GPL, version 2.  See
17  * the COPYING file in the top-level directory.
18  *
19  */
20
21 #include "irq.h"
22 #include "mmu.h"
23 #include "x86.h"
24 #include "kvm_cache_regs.h"
25
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
29 #include <linux/mm.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
38
39 #include <asm/page.h>
40 #include <asm/cmpxchg.h>
41 #include <asm/io.h>
42 #include <asm/vmx.h>
43
44 /*
45  * When setting this variable to true it enables Two-Dimensional-Paging
46  * where the hardware walks 2 page tables:
47  * 1. the guest-virtual to guest-physical
48  * 2. while doing 1. it walks guest-physical to host-physical
49  * If the hardware supports that we don't need to do shadow paging.
50  */
51 bool tdp_enabled = false;
52
53 enum {
54         AUDIT_PRE_PAGE_FAULT,
55         AUDIT_POST_PAGE_FAULT,
56         AUDIT_PRE_PTE_WRITE,
57         AUDIT_POST_PTE_WRITE,
58         AUDIT_PRE_SYNC,
59         AUDIT_POST_SYNC
60 };
61
62 #undef MMU_DEBUG
63
64 #ifdef MMU_DEBUG
65
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
68
69 #else
70
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
73
74 #endif
75
76 #ifdef MMU_DEBUG
77 static bool dbg = 0;
78 module_param(dbg, bool, 0644);
79 #endif
80
81 #ifndef MMU_DEBUG
82 #define ASSERT(x) do { } while (0)
83 #else
84 #define ASSERT(x)                                                       \
85         if (!(x)) {                                                     \
86                 printk(KERN_WARNING "assertion failed %s:%d: %s\n",     \
87                        __FILE__, __LINE__, #x);                         \
88         }
89 #endif
90
91 #define PTE_PREFETCH_NUM                8
92
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
95
96 #define PT64_LEVEL_BITS 9
97
98 #define PT64_LEVEL_SHIFT(level) \
99                 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
100
101 #define PT64_INDEX(address, level)\
102         (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
103
104
105 #define PT32_LEVEL_BITS 10
106
107 #define PT32_LEVEL_SHIFT(level) \
108                 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
109
110 #define PT32_LVL_OFFSET_MASK(level) \
111         (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112                                                 * PT32_LEVEL_BITS))) - 1))
113
114 #define PT32_INDEX(address, level)\
115         (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
116
117
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123                                                 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125         (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126                                                 * PT64_LEVEL_BITS))) - 1))
127
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133                                             * PT32_LEVEL_BITS))) - 1))
134
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
136                         | PT64_NX_MASK)
137
138 #define ACC_EXEC_MASK    1
139 #define ACC_WRITE_MASK   PT_WRITABLE_MASK
140 #define ACC_USER_MASK    PT_USER_MASK
141 #define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
142
143 #include <trace/events/kvm.h>
144
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
147
148 #define SPTE_HOST_WRITEABLE     (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE      (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
150
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
152
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
155
156 struct pte_list_desc {
157         u64 *sptes[PTE_LIST_EXT];
158         struct pte_list_desc *more;
159 };
160
161 struct kvm_shadow_walk_iterator {
162         u64 addr;
163         hpa_t shadow_addr;
164         u64 *sptep;
165         int level;
166         unsigned index;
167 };
168
169 #define for_each_shadow_entry(_vcpu, _addr, _walker)    \
170         for (shadow_walk_init(&(_walker), _vcpu, _addr);        \
171              shadow_walk_okay(&(_walker));                      \
172              shadow_walk_next(&(_walker)))
173
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte)     \
175         for (shadow_walk_init(&(_walker), _vcpu, _addr);                \
176              shadow_walk_okay(&(_walker)) &&                            \
177                 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; });  \
178              __shadow_walk_next(&(_walker), spte))
179
180 static struct kmem_cache *pte_list_desc_cache;
181 static struct kmem_cache *mmu_page_header_cache;
182 static struct percpu_counter kvm_total_used_mmu_pages;
183
184 static u64 __read_mostly shadow_nx_mask;
185 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask;
187 static u64 __read_mostly shadow_accessed_mask;
188 static u64 __read_mostly shadow_dirty_mask;
189 static u64 __read_mostly shadow_mmio_mask;
190
191 static void mmu_spte_set(u64 *sptep, u64 spte);
192 static void mmu_free_roots(struct kvm_vcpu *vcpu);
193
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
195 {
196         shadow_mmio_mask = mmio_mask;
197 }
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
199
200 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
201 {
202         access &= ACC_WRITE_MASK | ACC_USER_MASK;
203
204         trace_mark_mmio_spte(sptep, gfn, access);
205         mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
206 }
207
208 static bool is_mmio_spte(u64 spte)
209 {
210         return (spte & shadow_mmio_mask) == shadow_mmio_mask;
211 }
212
213 static gfn_t get_mmio_spte_gfn(u64 spte)
214 {
215         return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
216 }
217
218 static unsigned get_mmio_spte_access(u64 spte)
219 {
220         return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
221 }
222
223 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
224 {
225         if (unlikely(is_noslot_pfn(pfn))) {
226                 mark_mmio_spte(sptep, gfn, access);
227                 return true;
228         }
229
230         return false;
231 }
232
233 static inline u64 rsvd_bits(int s, int e)
234 {
235         return ((1ULL << (e - s + 1)) - 1) << s;
236 }
237
238 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
239                 u64 dirty_mask, u64 nx_mask, u64 x_mask)
240 {
241         shadow_user_mask = user_mask;
242         shadow_accessed_mask = accessed_mask;
243         shadow_dirty_mask = dirty_mask;
244         shadow_nx_mask = nx_mask;
245         shadow_x_mask = x_mask;
246 }
247 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
248
249 static int is_cpuid_PSE36(void)
250 {
251         return 1;
252 }
253
254 static int is_nx(struct kvm_vcpu *vcpu)
255 {
256         return vcpu->arch.efer & EFER_NX;
257 }
258
259 static int is_shadow_present_pte(u64 pte)
260 {
261         return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
262 }
263
264 static int is_large_pte(u64 pte)
265 {
266         return pte & PT_PAGE_SIZE_MASK;
267 }
268
269 static int is_dirty_gpte(unsigned long pte)
270 {
271         return pte & PT_DIRTY_MASK;
272 }
273
274 static int is_rmap_spte(u64 pte)
275 {
276         return is_shadow_present_pte(pte);
277 }
278
279 static int is_last_spte(u64 pte, int level)
280 {
281         if (level == PT_PAGE_TABLE_LEVEL)
282                 return 1;
283         if (is_large_pte(pte))
284                 return 1;
285         return 0;
286 }
287
288 static pfn_t spte_to_pfn(u64 pte)
289 {
290         return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
291 }
292
293 static gfn_t pse36_gfn_delta(u32 gpte)
294 {
295         int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
296
297         return (gpte & PT32_DIR_PSE36_MASK) << shift;
298 }
299
300 #ifdef CONFIG_X86_64
301 static void __set_spte(u64 *sptep, u64 spte)
302 {
303         *sptep = spte;
304 }
305
306 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
307 {
308         *sptep = spte;
309 }
310
311 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
312 {
313         return xchg(sptep, spte);
314 }
315
316 static u64 __get_spte_lockless(u64 *sptep)
317 {
318         return ACCESS_ONCE(*sptep);
319 }
320
321 static bool __check_direct_spte_mmio_pf(u64 spte)
322 {
323         /* It is valid if the spte is zapped. */
324         return spte == 0ull;
325 }
326 #else
327 union split_spte {
328         struct {
329                 u32 spte_low;
330                 u32 spte_high;
331         };
332         u64 spte;
333 };
334
335 static void count_spte_clear(u64 *sptep, u64 spte)
336 {
337         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
338
339         if (is_shadow_present_pte(spte))
340                 return;
341
342         /* Ensure the spte is completely set before we increase the count */
343         smp_wmb();
344         sp->clear_spte_count++;
345 }
346
347 static void __set_spte(u64 *sptep, u64 spte)
348 {
349         union split_spte *ssptep, sspte;
350
351         ssptep = (union split_spte *)sptep;
352         sspte = (union split_spte)spte;
353
354         ssptep->spte_high = sspte.spte_high;
355
356         /*
357          * If we map the spte from nonpresent to present, We should store
358          * the high bits firstly, then set present bit, so cpu can not
359          * fetch this spte while we are setting the spte.
360          */
361         smp_wmb();
362
363         ssptep->spte_low = sspte.spte_low;
364 }
365
366 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
367 {
368         union split_spte *ssptep, sspte;
369
370         ssptep = (union split_spte *)sptep;
371         sspte = (union split_spte)spte;
372
373         ssptep->spte_low = sspte.spte_low;
374
375         /*
376          * If we map the spte from present to nonpresent, we should clear
377          * present bit firstly to avoid vcpu fetch the old high bits.
378          */
379         smp_wmb();
380
381         ssptep->spte_high = sspte.spte_high;
382         count_spte_clear(sptep, spte);
383 }
384
385 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
386 {
387         union split_spte *ssptep, sspte, orig;
388
389         ssptep = (union split_spte *)sptep;
390         sspte = (union split_spte)spte;
391
392         /* xchg acts as a barrier before the setting of the high bits */
393         orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
394         orig.spte_high = ssptep->spte_high;
395         ssptep->spte_high = sspte.spte_high;
396         count_spte_clear(sptep, spte);
397
398         return orig.spte;
399 }
400
401 /*
402  * The idea using the light way get the spte on x86_32 guest is from
403  * gup_get_pte(arch/x86/mm/gup.c).
404  * The difference is we can not catch the spte tlb flush if we leave
405  * guest mode, so we emulate it by increase clear_spte_count when spte
406  * is cleared.
407  */
408 static u64 __get_spte_lockless(u64 *sptep)
409 {
410         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
411         union split_spte spte, *orig = (union split_spte *)sptep;
412         int count;
413
414 retry:
415         count = sp->clear_spte_count;
416         smp_rmb();
417
418         spte.spte_low = orig->spte_low;
419         smp_rmb();
420
421         spte.spte_high = orig->spte_high;
422         smp_rmb();
423
424         if (unlikely(spte.spte_low != orig->spte_low ||
425               count != sp->clear_spte_count))
426                 goto retry;
427
428         return spte.spte;
429 }
430
431 static bool __check_direct_spte_mmio_pf(u64 spte)
432 {
433         union split_spte sspte = (union split_spte)spte;
434         u32 high_mmio_mask = shadow_mmio_mask >> 32;
435
436         /* It is valid if the spte is zapped. */
437         if (spte == 0ull)
438                 return true;
439
440         /* It is valid if the spte is being zapped. */
441         if (sspte.spte_low == 0ull &&
442             (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
443                 return true;
444
445         return false;
446 }
447 #endif
448
449 static bool spte_is_locklessly_modifiable(u64 spte)
450 {
451         return !(~spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE));
452 }
453
454 static bool spte_has_volatile_bits(u64 spte)
455 {
456         /*
457          * Always atomicly update spte if it can be updated
458          * out of mmu-lock, it can ensure dirty bit is not lost,
459          * also, it can help us to get a stable is_writable_pte()
460          * to ensure tlb flush is not missed.
461          */
462         if (spte_is_locklessly_modifiable(spte))
463                 return true;
464
465         if (!shadow_accessed_mask)
466                 return false;
467
468         if (!is_shadow_present_pte(spte))
469                 return false;
470
471         if ((spte & shadow_accessed_mask) &&
472               (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
473                 return false;
474
475         return true;
476 }
477
478 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
479 {
480         return (old_spte & bit_mask) && !(new_spte & bit_mask);
481 }
482
483 /* Rules for using mmu_spte_set:
484  * Set the sptep from nonpresent to present.
485  * Note: the sptep being assigned *must* be either not present
486  * or in a state where the hardware will not attempt to update
487  * the spte.
488  */
489 static void mmu_spte_set(u64 *sptep, u64 new_spte)
490 {
491         WARN_ON(is_shadow_present_pte(*sptep));
492         __set_spte(sptep, new_spte);
493 }
494
495 /* Rules for using mmu_spte_update:
496  * Update the state bits, it means the mapped pfn is not changged.
497  *
498  * Whenever we overwrite a writable spte with a read-only one we
499  * should flush remote TLBs. Otherwise rmap_write_protect
500  * will find a read-only spte, even though the writable spte
501  * might be cached on a CPU's TLB, the return value indicates this
502  * case.
503  */
504 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
505 {
506         u64 old_spte = *sptep;
507         bool ret = false;
508
509         WARN_ON(!is_rmap_spte(new_spte));
510
511         if (!is_shadow_present_pte(old_spte)) {
512                 mmu_spte_set(sptep, new_spte);
513                 return ret;
514         }
515
516         if (!spte_has_volatile_bits(old_spte))
517                 __update_clear_spte_fast(sptep, new_spte);
518         else
519                 old_spte = __update_clear_spte_slow(sptep, new_spte);
520
521         /*
522          * For the spte updated out of mmu-lock is safe, since
523          * we always atomicly update it, see the comments in
524          * spte_has_volatile_bits().
525          */
526         if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
527                 ret = true;
528
529         if (!shadow_accessed_mask)
530                 return ret;
531
532         if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
533                 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
534         if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
535                 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
536
537         return ret;
538 }
539
540 /*
541  * Rules for using mmu_spte_clear_track_bits:
542  * It sets the sptep from present to nonpresent, and track the
543  * state bits, it is used to clear the last level sptep.
544  */
545 static int mmu_spte_clear_track_bits(u64 *sptep)
546 {
547         pfn_t pfn;
548         u64 old_spte = *sptep;
549
550         if (!spte_has_volatile_bits(old_spte))
551                 __update_clear_spte_fast(sptep, 0ull);
552         else
553                 old_spte = __update_clear_spte_slow(sptep, 0ull);
554
555         if (!is_rmap_spte(old_spte))
556                 return 0;
557
558         pfn = spte_to_pfn(old_spte);
559
560         /*
561          * KVM does not hold the refcount of the page used by
562          * kvm mmu, before reclaiming the page, we should
563          * unmap it from mmu first.
564          */
565         WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
566
567         if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
568                 kvm_set_pfn_accessed(pfn);
569         if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
570                 kvm_set_pfn_dirty(pfn);
571         return 1;
572 }
573
574 /*
575  * Rules for using mmu_spte_clear_no_track:
576  * Directly clear spte without caring the state bits of sptep,
577  * it is used to set the upper level spte.
578  */
579 static void mmu_spte_clear_no_track(u64 *sptep)
580 {
581         __update_clear_spte_fast(sptep, 0ull);
582 }
583
584 static u64 mmu_spte_get_lockless(u64 *sptep)
585 {
586         return __get_spte_lockless(sptep);
587 }
588
589 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
590 {
591         /*
592          * Prevent page table teardown by making any free-er wait during
593          * kvm_flush_remote_tlbs() IPI to all active vcpus.
594          */
595         local_irq_disable();
596         vcpu->mode = READING_SHADOW_PAGE_TABLES;
597         /*
598          * Make sure a following spte read is not reordered ahead of the write
599          * to vcpu->mode.
600          */
601         smp_mb();
602 }
603
604 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
605 {
606         /*
607          * Make sure the write to vcpu->mode is not reordered in front of
608          * reads to sptes.  If it does, kvm_commit_zap_page() can see us
609          * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
610          */
611         smp_mb();
612         vcpu->mode = OUTSIDE_GUEST_MODE;
613         local_irq_enable();
614 }
615
616 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
617                                   struct kmem_cache *base_cache, int min)
618 {
619         void *obj;
620
621         if (cache->nobjs >= min)
622                 return 0;
623         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
624                 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
625                 if (!obj)
626                         return -ENOMEM;
627                 cache->objects[cache->nobjs++] = obj;
628         }
629         return 0;
630 }
631
632 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
633 {
634         return cache->nobjs;
635 }
636
637 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
638                                   struct kmem_cache *cache)
639 {
640         while (mc->nobjs)
641                 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
642 }
643
644 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
645                                        int min)
646 {
647         void *page;
648
649         if (cache->nobjs >= min)
650                 return 0;
651         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
652                 page = (void *)__get_free_page(GFP_KERNEL);
653                 if (!page)
654                         return -ENOMEM;
655                 cache->objects[cache->nobjs++] = page;
656         }
657         return 0;
658 }
659
660 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
661 {
662         while (mc->nobjs)
663                 free_page((unsigned long)mc->objects[--mc->nobjs]);
664 }
665
666 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
667 {
668         int r;
669
670         r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
671                                    pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
672         if (r)
673                 goto out;
674         r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
675         if (r)
676                 goto out;
677         r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
678                                    mmu_page_header_cache, 4);
679 out:
680         return r;
681 }
682
683 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
684 {
685         mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
686                                 pte_list_desc_cache);
687         mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
688         mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
689                                 mmu_page_header_cache);
690 }
691
692 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
693 {
694         void *p;
695
696         BUG_ON(!mc->nobjs);
697         p = mc->objects[--mc->nobjs];
698         return p;
699 }
700
701 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
702 {
703         return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
704 }
705
706 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
707 {
708         kmem_cache_free(pte_list_desc_cache, pte_list_desc);
709 }
710
711 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
712 {
713         if (!sp->role.direct)
714                 return sp->gfns[index];
715
716         return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
717 }
718
719 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
720 {
721         if (sp->role.direct)
722                 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
723         else
724                 sp->gfns[index] = gfn;
725 }
726
727 /*
728  * Return the pointer to the large page information for a given gfn,
729  * handling slots that are not large page aligned.
730  */
731 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
732                                               struct kvm_memory_slot *slot,
733                                               int level)
734 {
735         unsigned long idx;
736
737         idx = gfn_to_index(gfn, slot->base_gfn, level);
738         return &slot->arch.lpage_info[level - 2][idx];
739 }
740
741 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
742 {
743         struct kvm_memory_slot *slot;
744         struct kvm_lpage_info *linfo;
745         int i;
746
747         slot = gfn_to_memslot(kvm, gfn);
748         for (i = PT_DIRECTORY_LEVEL;
749              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
750                 linfo = lpage_info_slot(gfn, slot, i);
751                 linfo->write_count += 1;
752         }
753         kvm->arch.indirect_shadow_pages++;
754 }
755
756 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
757 {
758         struct kvm_memory_slot *slot;
759         struct kvm_lpage_info *linfo;
760         int i;
761
762         slot = gfn_to_memslot(kvm, gfn);
763         for (i = PT_DIRECTORY_LEVEL;
764              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
765                 linfo = lpage_info_slot(gfn, slot, i);
766                 linfo->write_count -= 1;
767                 WARN_ON(linfo->write_count < 0);
768         }
769         kvm->arch.indirect_shadow_pages--;
770 }
771
772 static int has_wrprotected_page(struct kvm *kvm,
773                                 gfn_t gfn,
774                                 int level)
775 {
776         struct kvm_memory_slot *slot;
777         struct kvm_lpage_info *linfo;
778
779         slot = gfn_to_memslot(kvm, gfn);
780         if (slot) {
781                 linfo = lpage_info_slot(gfn, slot, level);
782                 return linfo->write_count;
783         }
784
785         return 1;
786 }
787
788 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
789 {
790         unsigned long page_size;
791         int i, ret = 0;
792
793         page_size = kvm_host_page_size(kvm, gfn);
794
795         for (i = PT_PAGE_TABLE_LEVEL;
796              i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
797                 if (page_size >= KVM_HPAGE_SIZE(i))
798                         ret = i;
799                 else
800                         break;
801         }
802
803         return ret;
804 }
805
806 static struct kvm_memory_slot *
807 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
808                             bool no_dirty_log)
809 {
810         struct kvm_memory_slot *slot;
811
812         slot = gfn_to_memslot(vcpu->kvm, gfn);
813         if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
814               (no_dirty_log && slot->dirty_bitmap))
815                 slot = NULL;
816
817         return slot;
818 }
819
820 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
821 {
822         return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
823 }
824
825 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
826 {
827         int host_level, level, max_level;
828
829         host_level = host_mapping_level(vcpu->kvm, large_gfn);
830
831         if (host_level == PT_PAGE_TABLE_LEVEL)
832                 return host_level;
833
834         max_level = kvm_x86_ops->get_lpage_level() < host_level ?
835                 kvm_x86_ops->get_lpage_level() : host_level;
836
837         for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
838                 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
839                         break;
840
841         return level - 1;
842 }
843
844 /*
845  * Pte mapping structures:
846  *
847  * If pte_list bit zero is zero, then pte_list point to the spte.
848  *
849  * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
850  * pte_list_desc containing more mappings.
851  *
852  * Returns the number of pte entries before the spte was added or zero if
853  * the spte was not added.
854  *
855  */
856 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
857                         unsigned long *pte_list)
858 {
859         struct pte_list_desc *desc;
860         int i, count = 0;
861
862         if (!*pte_list) {
863                 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
864                 *pte_list = (unsigned long)spte;
865         } else if (!(*pte_list & 1)) {
866                 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
867                 desc = mmu_alloc_pte_list_desc(vcpu);
868                 desc->sptes[0] = (u64 *)*pte_list;
869                 desc->sptes[1] = spte;
870                 *pte_list = (unsigned long)desc | 1;
871                 ++count;
872         } else {
873                 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
874                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
875                 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
876                         desc = desc->more;
877                         count += PTE_LIST_EXT;
878                 }
879                 if (desc->sptes[PTE_LIST_EXT-1]) {
880                         desc->more = mmu_alloc_pte_list_desc(vcpu);
881                         desc = desc->more;
882                 }
883                 for (i = 0; desc->sptes[i]; ++i)
884                         ++count;
885                 desc->sptes[i] = spte;
886         }
887         return count;
888 }
889
890 static void
891 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
892                            int i, struct pte_list_desc *prev_desc)
893 {
894         int j;
895
896         for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
897                 ;
898         desc->sptes[i] = desc->sptes[j];
899         desc->sptes[j] = NULL;
900         if (j != 0)
901                 return;
902         if (!prev_desc && !desc->more)
903                 *pte_list = (unsigned long)desc->sptes[0];
904         else
905                 if (prev_desc)
906                         prev_desc->more = desc->more;
907                 else
908                         *pte_list = (unsigned long)desc->more | 1;
909         mmu_free_pte_list_desc(desc);
910 }
911
912 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
913 {
914         struct pte_list_desc *desc;
915         struct pte_list_desc *prev_desc;
916         int i;
917
918         if (!*pte_list) {
919                 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
920                 BUG();
921         } else if (!(*pte_list & 1)) {
922                 rmap_printk("pte_list_remove:  %p 1->0\n", spte);
923                 if ((u64 *)*pte_list != spte) {
924                         printk(KERN_ERR "pte_list_remove:  %p 1->BUG\n", spte);
925                         BUG();
926                 }
927                 *pte_list = 0;
928         } else {
929                 rmap_printk("pte_list_remove:  %p many->many\n", spte);
930                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
931                 prev_desc = NULL;
932                 while (desc) {
933                         for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
934                                 if (desc->sptes[i] == spte) {
935                                         pte_list_desc_remove_entry(pte_list,
936                                                                desc, i,
937                                                                prev_desc);
938                                         return;
939                                 }
940                         prev_desc = desc;
941                         desc = desc->more;
942                 }
943                 pr_err("pte_list_remove: %p many->many\n", spte);
944                 BUG();
945         }
946 }
947
948 typedef void (*pte_list_walk_fn) (u64 *spte);
949 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
950 {
951         struct pte_list_desc *desc;
952         int i;
953
954         if (!*pte_list)
955                 return;
956
957         if (!(*pte_list & 1))
958                 return fn((u64 *)*pte_list);
959
960         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
961         while (desc) {
962                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
963                         fn(desc->sptes[i]);
964                 desc = desc->more;
965         }
966 }
967
968 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
969                                     struct kvm_memory_slot *slot)
970 {
971         unsigned long idx;
972
973         idx = gfn_to_index(gfn, slot->base_gfn, level);
974         return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
975 }
976
977 /*
978  * Take gfn and return the reverse mapping to it.
979  */
980 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
981 {
982         struct kvm_memory_slot *slot;
983
984         slot = gfn_to_memslot(kvm, gfn);
985         return __gfn_to_rmap(gfn, level, slot);
986 }
987
988 static bool rmap_can_add(struct kvm_vcpu *vcpu)
989 {
990         struct kvm_mmu_memory_cache *cache;
991
992         cache = &vcpu->arch.mmu_pte_list_desc_cache;
993         return mmu_memory_cache_free_objects(cache);
994 }
995
996 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
997 {
998         struct kvm_mmu_page *sp;
999         unsigned long *rmapp;
1000
1001         sp = page_header(__pa(spte));
1002         kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1003         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1004         return pte_list_add(vcpu, spte, rmapp);
1005 }
1006
1007 static void rmap_remove(struct kvm *kvm, u64 *spte)
1008 {
1009         struct kvm_mmu_page *sp;
1010         gfn_t gfn;
1011         unsigned long *rmapp;
1012
1013         sp = page_header(__pa(spte));
1014         gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1015         rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1016         pte_list_remove(spte, rmapp);
1017 }
1018
1019 /*
1020  * Used by the following functions to iterate through the sptes linked by a
1021  * rmap.  All fields are private and not assumed to be used outside.
1022  */
1023 struct rmap_iterator {
1024         /* private fields */
1025         struct pte_list_desc *desc;     /* holds the sptep if not NULL */
1026         int pos;                        /* index of the sptep */
1027 };
1028
1029 /*
1030  * Iteration must be started by this function.  This should also be used after
1031  * removing/dropping sptes from the rmap link because in such cases the
1032  * information in the itererator may not be valid.
1033  *
1034  * Returns sptep if found, NULL otherwise.
1035  */
1036 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1037 {
1038         if (!rmap)
1039                 return NULL;
1040
1041         if (!(rmap & 1)) {
1042                 iter->desc = NULL;
1043                 return (u64 *)rmap;
1044         }
1045
1046         iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1047         iter->pos = 0;
1048         return iter->desc->sptes[iter->pos];
1049 }
1050
1051 /*
1052  * Must be used with a valid iterator: e.g. after rmap_get_first().
1053  *
1054  * Returns sptep if found, NULL otherwise.
1055  */
1056 static u64 *rmap_get_next(struct rmap_iterator *iter)
1057 {
1058         if (iter->desc) {
1059                 if (iter->pos < PTE_LIST_EXT - 1) {
1060                         u64 *sptep;
1061
1062                         ++iter->pos;
1063                         sptep = iter->desc->sptes[iter->pos];
1064                         if (sptep)
1065                                 return sptep;
1066                 }
1067
1068                 iter->desc = iter->desc->more;
1069
1070                 if (iter->desc) {
1071                         iter->pos = 0;
1072                         /* desc->sptes[0] cannot be NULL */
1073                         return iter->desc->sptes[iter->pos];
1074                 }
1075         }
1076
1077         return NULL;
1078 }
1079
1080 static void drop_spte(struct kvm *kvm, u64 *sptep)
1081 {
1082         if (mmu_spte_clear_track_bits(sptep))
1083                 rmap_remove(kvm, sptep);
1084 }
1085
1086
1087 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1088 {
1089         if (is_large_pte(*sptep)) {
1090                 WARN_ON(page_header(__pa(sptep))->role.level ==
1091                         PT_PAGE_TABLE_LEVEL);
1092                 drop_spte(kvm, sptep);
1093                 --kvm->stat.lpages;
1094                 return true;
1095         }
1096
1097         return false;
1098 }
1099
1100 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1101 {
1102         if (__drop_large_spte(vcpu->kvm, sptep))
1103                 kvm_flush_remote_tlbs(vcpu->kvm);
1104 }
1105
1106 /*
1107  * Write-protect on the specified @sptep, @pt_protect indicates whether
1108  * spte writ-protection is caused by protecting shadow page table.
1109  * @flush indicates whether tlb need be flushed.
1110  *
1111  * Note: write protection is difference between drity logging and spte
1112  * protection:
1113  * - for dirty logging, the spte can be set to writable at anytime if
1114  *   its dirty bitmap is properly set.
1115  * - for spte protection, the spte can be writable only after unsync-ing
1116  *   shadow page.
1117  *
1118  * Return true if the spte is dropped.
1119  */
1120 static bool
1121 spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect)
1122 {
1123         u64 spte = *sptep;
1124
1125         if (!is_writable_pte(spte) &&
1126               !(pt_protect && spte_is_locklessly_modifiable(spte)))
1127                 return false;
1128
1129         rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1130
1131         if (__drop_large_spte(kvm, sptep)) {
1132                 *flush |= true;
1133                 return true;
1134         }
1135
1136         if (pt_protect)
1137                 spte &= ~SPTE_MMU_WRITEABLE;
1138         spte = spte & ~PT_WRITABLE_MASK;
1139
1140         *flush |= mmu_spte_update(sptep, spte);
1141         return false;
1142 }
1143
1144 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1145                                  int level, bool pt_protect)
1146 {
1147         u64 *sptep;
1148         struct rmap_iterator iter;
1149         bool flush = false;
1150
1151         for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1152                 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1153                 if (spte_write_protect(kvm, sptep, &flush, pt_protect)) {
1154                         sptep = rmap_get_first(*rmapp, &iter);
1155                         continue;
1156                 }
1157
1158                 sptep = rmap_get_next(&iter);
1159         }
1160
1161         return flush;
1162 }
1163
1164 /**
1165  * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1166  * @kvm: kvm instance
1167  * @slot: slot to protect
1168  * @gfn_offset: start of the BITS_PER_LONG pages we care about
1169  * @mask: indicates which pages we should protect
1170  *
1171  * Used when we do not need to care about huge page mappings: e.g. during dirty
1172  * logging we do not have any such mappings.
1173  */
1174 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1175                                      struct kvm_memory_slot *slot,
1176                                      gfn_t gfn_offset, unsigned long mask)
1177 {
1178         unsigned long *rmapp;
1179
1180         while (mask) {
1181                 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1182                                       PT_PAGE_TABLE_LEVEL, slot);
1183                 __rmap_write_protect(kvm, rmapp, PT_PAGE_TABLE_LEVEL, false);
1184
1185                 /* clear the first set bit */
1186                 mask &= mask - 1;
1187         }
1188 }
1189
1190 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1191 {
1192         struct kvm_memory_slot *slot;
1193         unsigned long *rmapp;
1194         int i;
1195         bool write_protected = false;
1196
1197         slot = gfn_to_memslot(kvm, gfn);
1198
1199         for (i = PT_PAGE_TABLE_LEVEL;
1200              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1201                 rmapp = __gfn_to_rmap(gfn, i, slot);
1202                 write_protected |= __rmap_write_protect(kvm, rmapp, i, true);
1203         }
1204
1205         return write_protected;
1206 }
1207
1208 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1209                            struct kvm_memory_slot *slot, unsigned long data)
1210 {
1211         u64 *sptep;
1212         struct rmap_iterator iter;
1213         int need_tlb_flush = 0;
1214
1215         while ((sptep = rmap_get_first(*rmapp, &iter))) {
1216                 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1217                 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1218
1219                 drop_spte(kvm, sptep);
1220                 need_tlb_flush = 1;
1221         }
1222
1223         return need_tlb_flush;
1224 }
1225
1226 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1227                              struct kvm_memory_slot *slot, unsigned long data)
1228 {
1229         u64 *sptep;
1230         struct rmap_iterator iter;
1231         int need_flush = 0;
1232         u64 new_spte;
1233         pte_t *ptep = (pte_t *)data;
1234         pfn_t new_pfn;
1235
1236         WARN_ON(pte_huge(*ptep));
1237         new_pfn = pte_pfn(*ptep);
1238
1239         for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1240                 BUG_ON(!is_shadow_present_pte(*sptep));
1241                 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1242
1243                 need_flush = 1;
1244
1245                 if (pte_write(*ptep)) {
1246                         drop_spte(kvm, sptep);
1247                         sptep = rmap_get_first(*rmapp, &iter);
1248                 } else {
1249                         new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1250                         new_spte |= (u64)new_pfn << PAGE_SHIFT;
1251
1252                         new_spte &= ~PT_WRITABLE_MASK;
1253                         new_spte &= ~SPTE_HOST_WRITEABLE;
1254                         new_spte &= ~shadow_accessed_mask;
1255
1256                         mmu_spte_clear_track_bits(sptep);
1257                         mmu_spte_set(sptep, new_spte);
1258                         sptep = rmap_get_next(&iter);
1259                 }
1260         }
1261
1262         if (need_flush)
1263                 kvm_flush_remote_tlbs(kvm);
1264
1265         return 0;
1266 }
1267
1268 static int kvm_handle_hva_range(struct kvm *kvm,
1269                                 unsigned long start,
1270                                 unsigned long end,
1271                                 unsigned long data,
1272                                 int (*handler)(struct kvm *kvm,
1273                                                unsigned long *rmapp,
1274                                                struct kvm_memory_slot *slot,
1275                                                unsigned long data))
1276 {
1277         int j;
1278         int ret = 0;
1279         struct kvm_memslots *slots;
1280         struct kvm_memory_slot *memslot;
1281
1282         slots = kvm_memslots(kvm);
1283
1284         kvm_for_each_memslot(memslot, slots) {
1285                 unsigned long hva_start, hva_end;
1286                 gfn_t gfn_start, gfn_end;
1287
1288                 hva_start = max(start, memslot->userspace_addr);
1289                 hva_end = min(end, memslot->userspace_addr +
1290                                         (memslot->npages << PAGE_SHIFT));
1291                 if (hva_start >= hva_end)
1292                         continue;
1293                 /*
1294                  * {gfn(page) | page intersects with [hva_start, hva_end)} =
1295                  * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1296                  */
1297                 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1298                 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1299
1300                 for (j = PT_PAGE_TABLE_LEVEL;
1301                      j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1302                         unsigned long idx, idx_end;
1303                         unsigned long *rmapp;
1304
1305                         /*
1306                          * {idx(page_j) | page_j intersects with
1307                          *  [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1308                          */
1309                         idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1310                         idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1311
1312                         rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1313
1314                         for (; idx <= idx_end; ++idx)
1315                                 ret |= handler(kvm, rmapp++, memslot, data);
1316                 }
1317         }
1318
1319         return ret;
1320 }
1321
1322 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1323                           unsigned long data,
1324                           int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1325                                          struct kvm_memory_slot *slot,
1326                                          unsigned long data))
1327 {
1328         return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1329 }
1330
1331 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1332 {
1333         return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1334 }
1335
1336 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1337 {
1338         return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1339 }
1340
1341 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1342 {
1343         kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1344 }
1345
1346 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1347                          struct kvm_memory_slot *slot, unsigned long data)
1348 {
1349         u64 *sptep;
1350         struct rmap_iterator uninitialized_var(iter);
1351         int young = 0;
1352
1353         /*
1354          * In case of absence of EPT Access and Dirty Bits supports,
1355          * emulate the accessed bit for EPT, by checking if this page has
1356          * an EPT mapping, and clearing it if it does. On the next access,
1357          * a new EPT mapping will be established.
1358          * This has some overhead, but not as much as the cost of swapping
1359          * out actively used pages or breaking up actively used hugepages.
1360          */
1361         if (!shadow_accessed_mask) {
1362                 young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
1363                 goto out;
1364         }
1365
1366         for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1367              sptep = rmap_get_next(&iter)) {
1368                 BUG_ON(!is_shadow_present_pte(*sptep));
1369
1370                 if (*sptep & shadow_accessed_mask) {
1371                         young = 1;
1372                         clear_bit((ffs(shadow_accessed_mask) - 1),
1373                                  (unsigned long *)sptep);
1374                 }
1375         }
1376 out:
1377         /* @data has hva passed to kvm_age_hva(). */
1378         trace_kvm_age_page(data, slot, young);
1379         return young;
1380 }
1381
1382 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1383                               struct kvm_memory_slot *slot, unsigned long data)
1384 {
1385         u64 *sptep;
1386         struct rmap_iterator iter;
1387         int young = 0;
1388
1389         /*
1390          * If there's no access bit in the secondary pte set by the
1391          * hardware it's up to gup-fast/gup to set the access bit in
1392          * the primary pte or in the page structure.
1393          */
1394         if (!shadow_accessed_mask)
1395                 goto out;
1396
1397         for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1398              sptep = rmap_get_next(&iter)) {
1399                 BUG_ON(!is_shadow_present_pte(*sptep));
1400
1401                 if (*sptep & shadow_accessed_mask) {
1402                         young = 1;
1403                         break;
1404                 }
1405         }
1406 out:
1407         return young;
1408 }
1409
1410 #define RMAP_RECYCLE_THRESHOLD 1000
1411
1412 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1413 {
1414         unsigned long *rmapp;
1415         struct kvm_mmu_page *sp;
1416
1417         sp = page_header(__pa(spte));
1418
1419         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1420
1421         kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
1422         kvm_flush_remote_tlbs(vcpu->kvm);
1423 }
1424
1425 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1426 {
1427         return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
1428 }
1429
1430 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1431 {
1432         return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1433 }
1434
1435 #ifdef MMU_DEBUG
1436 static int is_empty_shadow_page(u64 *spt)
1437 {
1438         u64 *pos;
1439         u64 *end;
1440
1441         for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1442                 if (is_shadow_present_pte(*pos)) {
1443                         printk(KERN_ERR "%s: %p %llx\n", __func__,
1444                                pos, *pos);
1445                         return 0;
1446                 }
1447         return 1;
1448 }
1449 #endif
1450
1451 /*
1452  * This value is the sum of all of the kvm instances's
1453  * kvm->arch.n_used_mmu_pages values.  We need a global,
1454  * aggregate version in order to make the slab shrinker
1455  * faster
1456  */
1457 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1458 {
1459         kvm->arch.n_used_mmu_pages += nr;
1460         percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1461 }
1462
1463 /*
1464  * Remove the sp from shadow page cache, after call it,
1465  * we can not find this sp from the cache, and the shadow
1466  * page table is still valid.
1467  * It should be under the protection of mmu lock.
1468  */
1469 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1470 {
1471         ASSERT(is_empty_shadow_page(sp->spt));
1472         hlist_del(&sp->hash_link);
1473         if (!sp->role.direct)
1474                 free_page((unsigned long)sp->gfns);
1475 }
1476
1477 /*
1478  * Free the shadow page table and the sp, we can do it
1479  * out of the protection of mmu lock.
1480  */
1481 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1482 {
1483         list_del(&sp->link);
1484         free_page((unsigned long)sp->spt);
1485         kmem_cache_free(mmu_page_header_cache, sp);
1486 }
1487
1488 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1489 {
1490         return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1491 }
1492
1493 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1494                                     struct kvm_mmu_page *sp, u64 *parent_pte)
1495 {
1496         if (!parent_pte)
1497                 return;
1498
1499         pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1500 }
1501
1502 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1503                                        u64 *parent_pte)
1504 {
1505         pte_list_remove(parent_pte, &sp->parent_ptes);
1506 }
1507
1508 static void drop_parent_pte(struct kvm_mmu_page *sp,
1509                             u64 *parent_pte)
1510 {
1511         mmu_page_remove_parent_pte(sp, parent_pte);
1512         mmu_spte_clear_no_track(parent_pte);
1513 }
1514
1515 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1516                                                u64 *parent_pte, int direct)
1517 {
1518         struct kvm_mmu_page *sp;
1519         sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1520         sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1521         if (!direct)
1522                 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1523         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1524         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1525         bitmap_zero(sp->slot_bitmap, KVM_MEM_SLOTS_NUM);
1526         sp->parent_ptes = 0;
1527         mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1528         kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1529         return sp;
1530 }
1531
1532 static void mark_unsync(u64 *spte);
1533 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1534 {
1535         pte_list_walk(&sp->parent_ptes, mark_unsync);
1536 }
1537
1538 static void mark_unsync(u64 *spte)
1539 {
1540         struct kvm_mmu_page *sp;
1541         unsigned int index;
1542
1543         sp = page_header(__pa(spte));
1544         index = spte - sp->spt;
1545         if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1546                 return;
1547         if (sp->unsync_children++)
1548                 return;
1549         kvm_mmu_mark_parents_unsync(sp);
1550 }
1551
1552 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1553                                struct kvm_mmu_page *sp)
1554 {
1555         return 1;
1556 }
1557
1558 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1559 {
1560 }
1561
1562 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1563                                  struct kvm_mmu_page *sp, u64 *spte,
1564                                  const void *pte)
1565 {
1566         WARN_ON(1);
1567 }
1568
1569 #define KVM_PAGE_ARRAY_NR 16
1570
1571 struct kvm_mmu_pages {
1572         struct mmu_page_and_offset {
1573                 struct kvm_mmu_page *sp;
1574                 unsigned int idx;
1575         } page[KVM_PAGE_ARRAY_NR];
1576         unsigned int nr;
1577 };
1578
1579 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1580                          int idx)
1581 {
1582         int i;
1583
1584         if (sp->unsync)
1585                 for (i=0; i < pvec->nr; i++)
1586                         if (pvec->page[i].sp == sp)
1587                                 return 0;
1588
1589         pvec->page[pvec->nr].sp = sp;
1590         pvec->page[pvec->nr].idx = idx;
1591         pvec->nr++;
1592         return (pvec->nr == KVM_PAGE_ARRAY_NR);
1593 }
1594
1595 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1596                            struct kvm_mmu_pages *pvec)
1597 {
1598         int i, ret, nr_unsync_leaf = 0;
1599
1600         for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1601                 struct kvm_mmu_page *child;
1602                 u64 ent = sp->spt[i];
1603
1604                 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1605                         goto clear_child_bitmap;
1606
1607                 child = page_header(ent & PT64_BASE_ADDR_MASK);
1608
1609                 if (child->unsync_children) {
1610                         if (mmu_pages_add(pvec, child, i))
1611                                 return -ENOSPC;
1612
1613                         ret = __mmu_unsync_walk(child, pvec);
1614                         if (!ret)
1615                                 goto clear_child_bitmap;
1616                         else if (ret > 0)
1617                                 nr_unsync_leaf += ret;
1618                         else
1619                                 return ret;
1620                 } else if (child->unsync) {
1621                         nr_unsync_leaf++;
1622                         if (mmu_pages_add(pvec, child, i))
1623                                 return -ENOSPC;
1624                 } else
1625                          goto clear_child_bitmap;
1626
1627                 continue;
1628
1629 clear_child_bitmap:
1630                 __clear_bit(i, sp->unsync_child_bitmap);
1631                 sp->unsync_children--;
1632                 WARN_ON((int)sp->unsync_children < 0);
1633         }
1634
1635
1636         return nr_unsync_leaf;
1637 }
1638
1639 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1640                            struct kvm_mmu_pages *pvec)
1641 {
1642         if (!sp->unsync_children)
1643                 return 0;
1644
1645         mmu_pages_add(pvec, sp, 0);
1646         return __mmu_unsync_walk(sp, pvec);
1647 }
1648
1649 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1650 {
1651         WARN_ON(!sp->unsync);
1652         trace_kvm_mmu_sync_page(sp);
1653         sp->unsync = 0;
1654         --kvm->stat.mmu_unsync;
1655 }
1656
1657 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1658                                     struct list_head *invalid_list);
1659 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1660                                     struct list_head *invalid_list);
1661
1662 #define for_each_gfn_sp(kvm, sp, gfn, pos)                              \
1663   hlist_for_each_entry(sp, pos,                                         \
1664    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1665         if ((sp)->gfn != (gfn)) {} else
1666
1667 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos)               \
1668   hlist_for_each_entry(sp, pos,                                         \
1669    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1670                 if ((sp)->gfn != (gfn) || (sp)->role.direct ||          \
1671                         (sp)->role.invalid) {} else
1672
1673 /* @sp->gfn should be write-protected at the call site */
1674 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1675                            struct list_head *invalid_list, bool clear_unsync)
1676 {
1677         if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1678                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1679                 return 1;
1680         }
1681
1682         if (clear_unsync)
1683                 kvm_unlink_unsync_page(vcpu->kvm, sp);
1684
1685         if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1686                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1687                 return 1;
1688         }
1689
1690         kvm_mmu_flush_tlb(vcpu);
1691         return 0;
1692 }
1693
1694 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1695                                    struct kvm_mmu_page *sp)
1696 {
1697         LIST_HEAD(invalid_list);
1698         int ret;
1699
1700         ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1701         if (ret)
1702                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1703
1704         return ret;
1705 }
1706
1707 #ifdef CONFIG_KVM_MMU_AUDIT
1708 #include "mmu_audit.c"
1709 #else
1710 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1711 static void mmu_audit_disable(void) { }
1712 #endif
1713
1714 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1715                          struct list_head *invalid_list)
1716 {
1717         return __kvm_sync_page(vcpu, sp, invalid_list, true);
1718 }
1719
1720 /* @gfn should be write-protected at the call site */
1721 static void kvm_sync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
1722 {
1723         struct kvm_mmu_page *s;
1724         struct hlist_node *node;
1725         LIST_HEAD(invalid_list);
1726         bool flush = false;
1727
1728         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1729                 if (!s->unsync)
1730                         continue;
1731
1732                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1733                 kvm_unlink_unsync_page(vcpu->kvm, s);
1734                 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1735                         (vcpu->arch.mmu.sync_page(vcpu, s))) {
1736                         kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1737                         continue;
1738                 }
1739                 flush = true;
1740         }
1741
1742         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1743         if (flush)
1744                 kvm_mmu_flush_tlb(vcpu);
1745 }
1746
1747 struct mmu_page_path {
1748         struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1749         unsigned int idx[PT64_ROOT_LEVEL-1];
1750 };
1751
1752 #define for_each_sp(pvec, sp, parents, i)                       \
1753                 for (i = mmu_pages_next(&pvec, &parents, -1),   \
1754                         sp = pvec.page[i].sp;                   \
1755                         i < pvec.nr && ({ sp = pvec.page[i].sp; 1;});   \
1756                         i = mmu_pages_next(&pvec, &parents, i))
1757
1758 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1759                           struct mmu_page_path *parents,
1760                           int i)
1761 {
1762         int n;
1763
1764         for (n = i+1; n < pvec->nr; n++) {
1765                 struct kvm_mmu_page *sp = pvec->page[n].sp;
1766
1767                 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1768                         parents->idx[0] = pvec->page[n].idx;
1769                         return n;
1770                 }
1771
1772                 parents->parent[sp->role.level-2] = sp;
1773                 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1774         }
1775
1776         return n;
1777 }
1778
1779 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1780 {
1781         struct kvm_mmu_page *sp;
1782         unsigned int level = 0;
1783
1784         do {
1785                 unsigned int idx = parents->idx[level];
1786
1787                 sp = parents->parent[level];
1788                 if (!sp)
1789                         return;
1790
1791                 --sp->unsync_children;
1792                 WARN_ON((int)sp->unsync_children < 0);
1793                 __clear_bit(idx, sp->unsync_child_bitmap);
1794                 level++;
1795         } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1796 }
1797
1798 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1799                                struct mmu_page_path *parents,
1800                                struct kvm_mmu_pages *pvec)
1801 {
1802         parents->parent[parent->role.level-1] = NULL;
1803         pvec->nr = 0;
1804 }
1805
1806 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1807                               struct kvm_mmu_page *parent)
1808 {
1809         int i;
1810         struct kvm_mmu_page *sp;
1811         struct mmu_page_path parents;
1812         struct kvm_mmu_pages pages;
1813         LIST_HEAD(invalid_list);
1814
1815         kvm_mmu_pages_init(parent, &parents, &pages);
1816         while (mmu_unsync_walk(parent, &pages)) {
1817                 bool protected = false;
1818
1819                 for_each_sp(pages, sp, parents, i)
1820                         protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1821
1822                 if (protected)
1823                         kvm_flush_remote_tlbs(vcpu->kvm);
1824
1825                 for_each_sp(pages, sp, parents, i) {
1826                         kvm_sync_page(vcpu, sp, &invalid_list);
1827                         mmu_pages_clear_parents(&parents);
1828                 }
1829                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1830                 cond_resched_lock(&vcpu->kvm->mmu_lock);
1831                 kvm_mmu_pages_init(parent, &parents, &pages);
1832         }
1833 }
1834
1835 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1836 {
1837         int i;
1838
1839         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1840                 sp->spt[i] = 0ull;
1841 }
1842
1843 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1844 {
1845         sp->write_flooding_count = 0;
1846 }
1847
1848 static void clear_sp_write_flooding_count(u64 *spte)
1849 {
1850         struct kvm_mmu_page *sp =  page_header(__pa(spte));
1851
1852         __clear_sp_write_flooding_count(sp);
1853 }
1854
1855 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1856                                              gfn_t gfn,
1857                                              gva_t gaddr,
1858                                              unsigned level,
1859                                              int direct,
1860                                              unsigned access,
1861                                              u64 *parent_pte)
1862 {
1863         union kvm_mmu_page_role role;
1864         unsigned quadrant;
1865         struct kvm_mmu_page *sp;
1866         struct hlist_node *node;
1867         bool need_sync = false;
1868
1869         role = vcpu->arch.mmu.base_role;
1870         role.level = level;
1871         role.direct = direct;
1872         if (role.direct)
1873                 role.cr4_pae = 0;
1874         role.access = access;
1875         if (!vcpu->arch.mmu.direct_map
1876             && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1877                 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1878                 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1879                 role.quadrant = quadrant;
1880         }
1881         for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1882                 if (!need_sync && sp->unsync)
1883                         need_sync = true;
1884
1885                 if (sp->role.word != role.word)
1886                         continue;
1887
1888                 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1889                         break;
1890
1891                 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1892                 if (sp->unsync_children) {
1893                         kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1894                         kvm_mmu_mark_parents_unsync(sp);
1895                 } else if (sp->unsync)
1896                         kvm_mmu_mark_parents_unsync(sp);
1897
1898                 __clear_sp_write_flooding_count(sp);
1899                 trace_kvm_mmu_get_page(sp, false);
1900                 return sp;
1901         }
1902         ++vcpu->kvm->stat.mmu_cache_miss;
1903         sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1904         if (!sp)
1905                 return sp;
1906         sp->gfn = gfn;
1907         sp->role = role;
1908         hlist_add_head(&sp->hash_link,
1909                 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1910         if (!direct) {
1911                 if (rmap_write_protect(vcpu->kvm, gfn))
1912                         kvm_flush_remote_tlbs(vcpu->kvm);
1913                 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1914                         kvm_sync_pages(vcpu, gfn);
1915
1916                 account_shadowed(vcpu->kvm, gfn);
1917         }
1918         init_shadow_page_table(sp);
1919         trace_kvm_mmu_get_page(sp, true);
1920         return sp;
1921 }
1922
1923 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1924                              struct kvm_vcpu *vcpu, u64 addr)
1925 {
1926         iterator->addr = addr;
1927         iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1928         iterator->level = vcpu->arch.mmu.shadow_root_level;
1929
1930         if (iterator->level == PT64_ROOT_LEVEL &&
1931             vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1932             !vcpu->arch.mmu.direct_map)
1933                 --iterator->level;
1934
1935         if (iterator->level == PT32E_ROOT_LEVEL) {
1936                 iterator->shadow_addr
1937                         = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1938                 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1939                 --iterator->level;
1940                 if (!iterator->shadow_addr)
1941                         iterator->level = 0;
1942         }
1943 }
1944
1945 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1946 {
1947         if (iterator->level < PT_PAGE_TABLE_LEVEL)
1948                 return false;
1949
1950         iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1951         iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1952         return true;
1953 }
1954
1955 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1956                                u64 spte)
1957 {
1958         if (is_last_spte(spte, iterator->level)) {
1959                 iterator->level = 0;
1960                 return;
1961         }
1962
1963         iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1964         --iterator->level;
1965 }
1966
1967 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1968 {
1969         return __shadow_walk_next(iterator, *iterator->sptep);
1970 }
1971
1972 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1973 {
1974         u64 spte;
1975
1976         spte = __pa(sp->spt)
1977                 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1978                 | PT_WRITABLE_MASK | PT_USER_MASK;
1979         mmu_spte_set(sptep, spte);
1980 }
1981
1982 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1983                                    unsigned direct_access)
1984 {
1985         if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1986                 struct kvm_mmu_page *child;
1987
1988                 /*
1989                  * For the direct sp, if the guest pte's dirty bit
1990                  * changed form clean to dirty, it will corrupt the
1991                  * sp's access: allow writable in the read-only sp,
1992                  * so we should update the spte at this point to get
1993                  * a new sp with the correct access.
1994                  */
1995                 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1996                 if (child->role.access == direct_access)
1997                         return;
1998
1999                 drop_parent_pte(child, sptep);
2000                 kvm_flush_remote_tlbs(vcpu->kvm);
2001         }
2002 }
2003
2004 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2005                              u64 *spte)
2006 {
2007         u64 pte;
2008         struct kvm_mmu_page *child;
2009
2010         pte = *spte;
2011         if (is_shadow_present_pte(pte)) {
2012                 if (is_last_spte(pte, sp->role.level)) {
2013                         drop_spte(kvm, spte);
2014                         if (is_large_pte(pte))
2015                                 --kvm->stat.lpages;
2016                 } else {
2017                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2018                         drop_parent_pte(child, spte);
2019                 }
2020                 return true;
2021         }
2022
2023         if (is_mmio_spte(pte))
2024                 mmu_spte_clear_no_track(spte);
2025
2026         return false;
2027 }
2028
2029 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2030                                          struct kvm_mmu_page *sp)
2031 {
2032         unsigned i;
2033
2034         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2035                 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2036 }
2037
2038 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2039 {
2040         mmu_page_remove_parent_pte(sp, parent_pte);
2041 }
2042
2043 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2044 {
2045         u64 *sptep;
2046         struct rmap_iterator iter;
2047
2048         while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2049                 drop_parent_pte(sp, sptep);
2050 }
2051
2052 static int mmu_zap_unsync_children(struct kvm *kvm,
2053                                    struct kvm_mmu_page *parent,
2054                                    struct list_head *invalid_list)
2055 {
2056         int i, zapped = 0;
2057         struct mmu_page_path parents;
2058         struct kvm_mmu_pages pages;
2059
2060         if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2061                 return 0;
2062
2063         kvm_mmu_pages_init(parent, &parents, &pages);
2064         while (mmu_unsync_walk(parent, &pages)) {
2065                 struct kvm_mmu_page *sp;
2066
2067                 for_each_sp(pages, sp, parents, i) {
2068                         kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2069                         mmu_pages_clear_parents(&parents);
2070                         zapped++;
2071                 }
2072                 kvm_mmu_pages_init(parent, &parents, &pages);
2073         }
2074
2075         return zapped;
2076 }
2077
2078 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2079                                     struct list_head *invalid_list)
2080 {
2081         int ret;
2082
2083         trace_kvm_mmu_prepare_zap_page(sp);
2084         ++kvm->stat.mmu_shadow_zapped;
2085         ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2086         kvm_mmu_page_unlink_children(kvm, sp);
2087         kvm_mmu_unlink_parents(kvm, sp);
2088         if (!sp->role.invalid && !sp->role.direct)
2089                 unaccount_shadowed(kvm, sp->gfn);
2090         if (sp->unsync)
2091                 kvm_unlink_unsync_page(kvm, sp);
2092         if (!sp->root_count) {
2093                 /* Count self */
2094                 ret++;
2095                 list_move(&sp->link, invalid_list);
2096                 kvm_mod_used_mmu_pages(kvm, -1);
2097         } else {
2098                 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2099                 kvm_reload_remote_mmus(kvm);
2100         }
2101
2102         sp->role.invalid = 1;
2103         return ret;
2104 }
2105
2106 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2107                                     struct list_head *invalid_list)
2108 {
2109         struct kvm_mmu_page *sp;
2110
2111         if (list_empty(invalid_list))
2112                 return;
2113
2114         /*
2115          * wmb: make sure everyone sees our modifications to the page tables
2116          * rmb: make sure we see changes to vcpu->mode
2117          */
2118         smp_mb();
2119
2120         /*
2121          * Wait for all vcpus to exit guest mode and/or lockless shadow
2122          * page table walks.
2123          */
2124         kvm_flush_remote_tlbs(kvm);
2125
2126         do {
2127                 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
2128                 WARN_ON(!sp->role.invalid || sp->root_count);
2129                 kvm_mmu_isolate_page(sp);
2130                 kvm_mmu_free_page(sp);
2131         } while (!list_empty(invalid_list));
2132 }
2133
2134 /*
2135  * Changing the number of mmu pages allocated to the vm
2136  * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2137  */
2138 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2139 {
2140         LIST_HEAD(invalid_list);
2141         /*
2142          * If we set the number of mmu pages to be smaller be than the
2143          * number of actived pages , we must to free some mmu pages before we
2144          * change the value
2145          */
2146
2147         if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2148                 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
2149                         !list_empty(&kvm->arch.active_mmu_pages)) {
2150                         struct kvm_mmu_page *page;
2151
2152                         page = container_of(kvm->arch.active_mmu_pages.prev,
2153                                             struct kvm_mmu_page, link);
2154                         kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
2155                 }
2156                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2157                 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2158         }
2159
2160         kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2161 }
2162
2163 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2164 {
2165         struct kvm_mmu_page *sp;
2166         struct hlist_node *node;
2167         LIST_HEAD(invalid_list);
2168         int r;
2169
2170         pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2171         r = 0;
2172         spin_lock(&kvm->mmu_lock);
2173         for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2174                 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2175                          sp->role.word);
2176                 r = 1;
2177                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2178         }
2179         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2180         spin_unlock(&kvm->mmu_lock);
2181
2182         return r;
2183 }
2184 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2185
2186 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
2187 {
2188         int slot = memslot_id(kvm, gfn);
2189         struct kvm_mmu_page *sp = page_header(__pa(pte));
2190
2191         __set_bit(slot, sp->slot_bitmap);
2192 }
2193
2194 /*
2195  * The function is based on mtrr_type_lookup() in
2196  * arch/x86/kernel/cpu/mtrr/generic.c
2197  */
2198 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2199                          u64 start, u64 end)
2200 {
2201         int i;
2202         u64 base, mask;
2203         u8 prev_match, curr_match;
2204         int num_var_ranges = KVM_NR_VAR_MTRR;
2205
2206         if (!mtrr_state->enabled)
2207                 return 0xFF;
2208
2209         /* Make end inclusive end, instead of exclusive */
2210         end--;
2211
2212         /* Look in fixed ranges. Just return the type as per start */
2213         if (mtrr_state->have_fixed && (start < 0x100000)) {
2214                 int idx;
2215
2216                 if (start < 0x80000) {
2217                         idx = 0;
2218                         idx += (start >> 16);
2219                         return mtrr_state->fixed_ranges[idx];
2220                 } else if (start < 0xC0000) {
2221                         idx = 1 * 8;
2222                         idx += ((start - 0x80000) >> 14);
2223                         return mtrr_state->fixed_ranges[idx];
2224                 } else if (start < 0x1000000) {
2225                         idx = 3 * 8;
2226                         idx += ((start - 0xC0000) >> 12);
2227                         return mtrr_state->fixed_ranges[idx];
2228                 }
2229         }
2230
2231         /*
2232          * Look in variable ranges
2233          * Look of multiple ranges matching this address and pick type
2234          * as per MTRR precedence
2235          */
2236         if (!(mtrr_state->enabled & 2))
2237                 return mtrr_state->def_type;
2238
2239         prev_match = 0xFF;
2240         for (i = 0; i < num_var_ranges; ++i) {
2241                 unsigned short start_state, end_state;
2242
2243                 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2244                         continue;
2245
2246                 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2247                        (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2248                 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2249                        (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2250
2251                 start_state = ((start & mask) == (base & mask));
2252                 end_state = ((end & mask) == (base & mask));
2253                 if (start_state != end_state)
2254                         return 0xFE;
2255
2256                 if ((start & mask) != (base & mask))
2257                         continue;
2258
2259                 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2260                 if (prev_match == 0xFF) {
2261                         prev_match = curr_match;
2262                         continue;
2263                 }
2264
2265                 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2266                     curr_match == MTRR_TYPE_UNCACHABLE)
2267                         return MTRR_TYPE_UNCACHABLE;
2268
2269                 if ((prev_match == MTRR_TYPE_WRBACK &&
2270                      curr_match == MTRR_TYPE_WRTHROUGH) ||
2271                     (prev_match == MTRR_TYPE_WRTHROUGH &&
2272                      curr_match == MTRR_TYPE_WRBACK)) {
2273                         prev_match = MTRR_TYPE_WRTHROUGH;
2274                         curr_match = MTRR_TYPE_WRTHROUGH;
2275                 }
2276
2277                 if (prev_match != curr_match)
2278                         return MTRR_TYPE_UNCACHABLE;
2279         }
2280
2281         if (prev_match != 0xFF)
2282                 return prev_match;
2283
2284         return mtrr_state->def_type;
2285 }
2286
2287 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2288 {
2289         u8 mtrr;
2290
2291         mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2292                              (gfn << PAGE_SHIFT) + PAGE_SIZE);
2293         if (mtrr == 0xfe || mtrr == 0xff)
2294                 mtrr = MTRR_TYPE_WRBACK;
2295         return mtrr;
2296 }
2297 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2298
2299 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2300 {
2301         trace_kvm_mmu_unsync_page(sp);
2302         ++vcpu->kvm->stat.mmu_unsync;
2303         sp->unsync = 1;
2304
2305         kvm_mmu_mark_parents_unsync(sp);
2306 }
2307
2308 static void kvm_unsync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
2309 {
2310         struct kvm_mmu_page *s;
2311         struct hlist_node *node;
2312
2313         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2314                 if (s->unsync)
2315                         continue;
2316                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2317                 __kvm_unsync_page(vcpu, s);
2318         }
2319 }
2320
2321 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2322                                   bool can_unsync)
2323 {
2324         struct kvm_mmu_page *s;
2325         struct hlist_node *node;
2326         bool need_unsync = false;
2327
2328         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2329                 if (!can_unsync)
2330                         return 1;
2331
2332                 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2333                         return 1;
2334
2335                 if (!need_unsync && !s->unsync) {
2336                         need_unsync = true;
2337                 }
2338         }
2339         if (need_unsync)
2340                 kvm_unsync_pages(vcpu, gfn);
2341         return 0;
2342 }
2343
2344 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2345                     unsigned pte_access, int user_fault,
2346                     int write_fault, int level,
2347                     gfn_t gfn, pfn_t pfn, bool speculative,
2348                     bool can_unsync, bool host_writable)
2349 {
2350         u64 spte;
2351         int ret = 0;
2352
2353         if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2354                 return 0;
2355
2356         spte = PT_PRESENT_MASK;
2357         if (!speculative)
2358                 spte |= shadow_accessed_mask;
2359
2360         if (pte_access & ACC_EXEC_MASK)
2361                 spte |= shadow_x_mask;
2362         else
2363                 spte |= shadow_nx_mask;
2364
2365         if (pte_access & ACC_USER_MASK)
2366                 spte |= shadow_user_mask;
2367
2368         if (level > PT_PAGE_TABLE_LEVEL)
2369                 spte |= PT_PAGE_SIZE_MASK;
2370         if (tdp_enabled)
2371                 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2372                         kvm_is_mmio_pfn(pfn));
2373
2374         if (host_writable)
2375                 spte |= SPTE_HOST_WRITEABLE;
2376         else
2377                 pte_access &= ~ACC_WRITE_MASK;
2378
2379         spte |= (u64)pfn << PAGE_SHIFT;
2380
2381         if ((pte_access & ACC_WRITE_MASK)
2382             || (!vcpu->arch.mmu.direct_map && write_fault
2383                 && !is_write_protection(vcpu) && !user_fault)) {
2384
2385                 if (level > PT_PAGE_TABLE_LEVEL &&
2386                     has_wrprotected_page(vcpu->kvm, gfn, level)) {
2387                         ret = 1;
2388                         drop_spte(vcpu->kvm, sptep);
2389                         goto done;
2390                 }
2391
2392                 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2393
2394                 if (!vcpu->arch.mmu.direct_map
2395                     && !(pte_access & ACC_WRITE_MASK)) {
2396                         spte &= ~PT_USER_MASK;
2397                         /*
2398                          * If we converted a user page to a kernel page,
2399                          * so that the kernel can write to it when cr0.wp=0,
2400                          * then we should prevent the kernel from executing it
2401                          * if SMEP is enabled.
2402                          */
2403                         if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
2404                                 spte |= PT64_NX_MASK;
2405                 }
2406
2407                 /*
2408                  * Optimization: for pte sync, if spte was writable the hash
2409                  * lookup is unnecessary (and expensive). Write protection
2410                  * is responsibility of mmu_get_page / kvm_sync_page.
2411                  * Same reasoning can be applied to dirty page accounting.
2412                  */
2413                 if (!can_unsync && is_writable_pte(*sptep))
2414                         goto set_pte;
2415
2416                 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2417                         pgprintk("%s: found shadow page for %llx, marking ro\n",
2418                                  __func__, gfn);
2419                         ret = 1;
2420                         pte_access &= ~ACC_WRITE_MASK;
2421                         spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2422                 }
2423         }
2424
2425         if (pte_access & ACC_WRITE_MASK)
2426                 mark_page_dirty(vcpu->kvm, gfn);
2427
2428 set_pte:
2429         if (mmu_spte_update(sptep, spte))
2430                 kvm_flush_remote_tlbs(vcpu->kvm);
2431 done:
2432         return ret;
2433 }
2434
2435 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2436                          unsigned pt_access, unsigned pte_access,
2437                          int user_fault, int write_fault,
2438                          int *emulate, int level, gfn_t gfn,
2439                          pfn_t pfn, bool speculative,
2440                          bool host_writable)
2441 {
2442         int was_rmapped = 0;
2443         int rmap_count;
2444
2445         pgprintk("%s: spte %llx access %x write_fault %d"
2446                  " user_fault %d gfn %llx\n",
2447                  __func__, *sptep, pt_access,
2448                  write_fault, user_fault, gfn);
2449
2450         if (is_rmap_spte(*sptep)) {
2451                 /*
2452                  * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2453                  * the parent of the now unreachable PTE.
2454                  */
2455                 if (level > PT_PAGE_TABLE_LEVEL &&
2456                     !is_large_pte(*sptep)) {
2457                         struct kvm_mmu_page *child;
2458                         u64 pte = *sptep;
2459
2460                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2461                         drop_parent_pte(child, sptep);
2462                         kvm_flush_remote_tlbs(vcpu->kvm);
2463                 } else if (pfn != spte_to_pfn(*sptep)) {
2464                         pgprintk("hfn old %llx new %llx\n",
2465                                  spte_to_pfn(*sptep), pfn);
2466                         drop_spte(vcpu->kvm, sptep);
2467                         kvm_flush_remote_tlbs(vcpu->kvm);
2468                 } else
2469                         was_rmapped = 1;
2470         }
2471
2472         if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2473                       level, gfn, pfn, speculative, true,
2474                       host_writable)) {
2475                 if (write_fault)
2476                         *emulate = 1;
2477                 kvm_mmu_flush_tlb(vcpu);
2478         }
2479
2480         if (unlikely(is_mmio_spte(*sptep) && emulate))
2481                 *emulate = 1;
2482
2483         pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2484         pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2485                  is_large_pte(*sptep)? "2MB" : "4kB",
2486                  *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2487                  *sptep, sptep);
2488         if (!was_rmapped && is_large_pte(*sptep))
2489                 ++vcpu->kvm->stat.lpages;
2490
2491         if (is_shadow_present_pte(*sptep)) {
2492                 page_header_update_slot(vcpu->kvm, sptep, gfn);
2493                 if (!was_rmapped) {
2494                         rmap_count = rmap_add(vcpu, sptep, gfn);
2495                         if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2496                                 rmap_recycle(vcpu, sptep, gfn);
2497                 }
2498         }
2499         kvm_release_pfn_clean(pfn);
2500 }
2501
2502 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2503 {
2504         mmu_free_roots(vcpu);
2505 }
2506
2507 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2508                                      bool no_dirty_log)
2509 {
2510         struct kvm_memory_slot *slot;
2511         unsigned long hva;
2512
2513         slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2514         if (!slot)
2515                 return KVM_PFN_ERR_FAULT;
2516
2517         hva = gfn_to_hva_memslot(slot, gfn);
2518
2519         return hva_to_pfn_atomic(hva);
2520 }
2521
2522 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2523                                     struct kvm_mmu_page *sp,
2524                                     u64 *start, u64 *end)
2525 {
2526         struct page *pages[PTE_PREFETCH_NUM];
2527         unsigned access = sp->role.access;
2528         int i, ret;
2529         gfn_t gfn;
2530
2531         gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2532         if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2533                 return -1;
2534
2535         ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2536         if (ret <= 0)
2537                 return -1;
2538
2539         for (i = 0; i < ret; i++, gfn++, start++)
2540                 mmu_set_spte(vcpu, start, ACC_ALL,
2541                              access, 0, 0, NULL,
2542                              sp->role.level, gfn,
2543                              page_to_pfn(pages[i]), true, true);
2544
2545         return 0;
2546 }
2547
2548 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2549                                   struct kvm_mmu_page *sp, u64 *sptep)
2550 {
2551         u64 *spte, *start = NULL;
2552         int i;
2553
2554         WARN_ON(!sp->role.direct);
2555
2556         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2557         spte = sp->spt + i;
2558
2559         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2560                 if (is_shadow_present_pte(*spte) || spte == sptep) {
2561                         if (!start)
2562                                 continue;
2563                         if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2564                                 break;
2565                         start = NULL;
2566                 } else if (!start)
2567                         start = spte;
2568         }
2569 }
2570
2571 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2572 {
2573         struct kvm_mmu_page *sp;
2574
2575         /*
2576          * Since it's no accessed bit on EPT, it's no way to
2577          * distinguish between actually accessed translations
2578          * and prefetched, so disable pte prefetch if EPT is
2579          * enabled.
2580          */
2581         if (!shadow_accessed_mask)
2582                 return;
2583
2584         sp = page_header(__pa(sptep));
2585         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2586                 return;
2587
2588         __direct_pte_prefetch(vcpu, sp, sptep);
2589 }
2590
2591 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2592                         int map_writable, int level, gfn_t gfn, pfn_t pfn,
2593                         bool prefault)
2594 {
2595         struct kvm_shadow_walk_iterator iterator;
2596         struct kvm_mmu_page *sp;
2597         int emulate = 0;
2598         gfn_t pseudo_gfn;
2599
2600         for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2601                 if (iterator.level == level) {
2602                         unsigned pte_access = ACC_ALL;
2603
2604                         mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2605                                      0, write, &emulate,
2606                                      level, gfn, pfn, prefault, map_writable);
2607                         direct_pte_prefetch(vcpu, iterator.sptep);
2608                         ++vcpu->stat.pf_fixed;
2609                         break;
2610                 }
2611
2612                 if (!is_shadow_present_pte(*iterator.sptep)) {
2613                         u64 base_addr = iterator.addr;
2614
2615                         base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2616                         pseudo_gfn = base_addr >> PAGE_SHIFT;
2617                         sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2618                                               iterator.level - 1,
2619                                               1, ACC_ALL, iterator.sptep);
2620                         if (!sp) {
2621                                 pgprintk("nonpaging_map: ENOMEM\n");
2622                                 kvm_release_pfn_clean(pfn);
2623                                 return -ENOMEM;
2624                         }
2625
2626                         mmu_spte_set(iterator.sptep,
2627                                      __pa(sp->spt)
2628                                      | PT_PRESENT_MASK | PT_WRITABLE_MASK
2629                                      | shadow_user_mask | shadow_x_mask
2630                                      | shadow_accessed_mask);
2631                 }
2632         }
2633         return emulate;
2634 }
2635
2636 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2637 {
2638         siginfo_t info;
2639
2640         info.si_signo   = SIGBUS;
2641         info.si_errno   = 0;
2642         info.si_code    = BUS_MCEERR_AR;
2643         info.si_addr    = (void __user *)address;
2644         info.si_addr_lsb = PAGE_SHIFT;
2645
2646         send_sig_info(SIGBUS, &info, tsk);
2647 }
2648
2649 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2650 {
2651         kvm_release_pfn_clean(pfn);
2652         if (pfn == KVM_PFN_ERR_HWPOISON) {
2653                 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2654                 return 0;
2655         }
2656
2657         return -EFAULT;
2658 }
2659
2660 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2661                                         gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2662 {
2663         pfn_t pfn = *pfnp;
2664         gfn_t gfn = *gfnp;
2665         int level = *levelp;
2666
2667         /*
2668          * Check if it's a transparent hugepage. If this would be an
2669          * hugetlbfs page, level wouldn't be set to
2670          * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2671          * here.
2672          */
2673         if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2674             level == PT_PAGE_TABLE_LEVEL &&
2675             PageTransCompound(pfn_to_page(pfn)) &&
2676             !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2677                 unsigned long mask;
2678                 /*
2679                  * mmu_notifier_retry was successful and we hold the
2680                  * mmu_lock here, so the pmd can't become splitting
2681                  * from under us, and in turn
2682                  * __split_huge_page_refcount() can't run from under
2683                  * us and we can safely transfer the refcount from
2684                  * PG_tail to PG_head as we switch the pfn to tail to
2685                  * head.
2686                  */
2687                 *levelp = level = PT_DIRECTORY_LEVEL;
2688                 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2689                 VM_BUG_ON((gfn & mask) != (pfn & mask));
2690                 if (pfn & mask) {
2691                         gfn &= ~mask;
2692                         *gfnp = gfn;
2693                         kvm_release_pfn_clean(pfn);
2694                         pfn &= ~mask;
2695                         kvm_get_pfn(pfn);
2696                         *pfnp = pfn;
2697                 }
2698         }
2699 }
2700
2701 static bool mmu_invalid_pfn(pfn_t pfn)
2702 {
2703         return unlikely(is_invalid_pfn(pfn));
2704 }
2705
2706 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2707                                 pfn_t pfn, unsigned access, int *ret_val)
2708 {
2709         bool ret = true;
2710
2711         /* The pfn is invalid, report the error! */
2712         if (unlikely(is_invalid_pfn(pfn))) {
2713                 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2714                 goto exit;
2715         }
2716
2717         if (unlikely(is_noslot_pfn(pfn)))
2718                 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2719
2720         ret = false;
2721 exit:
2722         return ret;
2723 }
2724
2725 static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code)
2726 {
2727         /*
2728          * #PF can be fast only if the shadow page table is present and it
2729          * is caused by write-protect, that means we just need change the
2730          * W bit of the spte which can be done out of mmu-lock.
2731          */
2732         if (!(error_code & PFERR_PRESENT_MASK) ||
2733               !(error_code & PFERR_WRITE_MASK))
2734                 return false;
2735
2736         return true;
2737 }
2738
2739 static bool
2740 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
2741 {
2742         struct kvm_mmu_page *sp = page_header(__pa(sptep));
2743         gfn_t gfn;
2744
2745         WARN_ON(!sp->role.direct);
2746
2747         /*
2748          * The gfn of direct spte is stable since it is calculated
2749          * by sp->gfn.
2750          */
2751         gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2752
2753         if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2754                 mark_page_dirty(vcpu->kvm, gfn);
2755
2756         return true;
2757 }
2758
2759 /*
2760  * Return value:
2761  * - true: let the vcpu to access on the same address again.
2762  * - false: let the real page fault path to fix it.
2763  */
2764 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2765                             u32 error_code)
2766 {
2767         struct kvm_shadow_walk_iterator iterator;
2768         bool ret = false;
2769         u64 spte = 0ull;
2770
2771         if (!page_fault_can_be_fast(vcpu, error_code))
2772                 return false;
2773
2774         walk_shadow_page_lockless_begin(vcpu);
2775         for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2776                 if (!is_shadow_present_pte(spte) || iterator.level < level)
2777                         break;
2778
2779         /*
2780          * If the mapping has been changed, let the vcpu fault on the
2781          * same address again.
2782          */
2783         if (!is_rmap_spte(spte)) {
2784                 ret = true;
2785                 goto exit;
2786         }
2787
2788         if (!is_last_spte(spte, level))
2789                 goto exit;
2790
2791         /*
2792          * Check if it is a spurious fault caused by TLB lazily flushed.
2793          *
2794          * Need not check the access of upper level table entries since
2795          * they are always ACC_ALL.
2796          */
2797          if (is_writable_pte(spte)) {
2798                 ret = true;
2799                 goto exit;
2800         }
2801
2802         /*
2803          * Currently, to simplify the code, only the spte write-protected
2804          * by dirty-log can be fast fixed.
2805          */
2806         if (!spte_is_locklessly_modifiable(spte))
2807                 goto exit;
2808
2809         /*
2810          * Currently, fast page fault only works for direct mapping since
2811          * the gfn is not stable for indirect shadow page.
2812          * See Documentation/virtual/kvm/locking.txt to get more detail.
2813          */
2814         ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
2815 exit:
2816         trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2817                               spte, ret);
2818         walk_shadow_page_lockless_end(vcpu);
2819
2820         return ret;
2821 }
2822
2823 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2824                          gva_t gva, pfn_t *pfn, bool write, bool *writable);
2825
2826 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2827                          gfn_t gfn, bool prefault)
2828 {
2829         int r;
2830         int level;
2831         int force_pt_level;
2832         pfn_t pfn;
2833         unsigned long mmu_seq;
2834         bool map_writable, write = error_code & PFERR_WRITE_MASK;
2835
2836         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2837         if (likely(!force_pt_level)) {
2838                 level = mapping_level(vcpu, gfn);
2839                 /*
2840                  * This path builds a PAE pagetable - so we can map
2841                  * 2mb pages at maximum. Therefore check if the level
2842                  * is larger than that.
2843                  */
2844                 if (level > PT_DIRECTORY_LEVEL)
2845                         level = PT_DIRECTORY_LEVEL;
2846
2847                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2848         } else
2849                 level = PT_PAGE_TABLE_LEVEL;
2850
2851         if (fast_page_fault(vcpu, v, level, error_code))
2852                 return 0;
2853
2854         mmu_seq = vcpu->kvm->mmu_notifier_seq;
2855         smp_rmb();
2856
2857         if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2858                 return 0;
2859
2860         if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2861                 return r;
2862
2863         spin_lock(&vcpu->kvm->mmu_lock);
2864         if (mmu_notifier_retry(vcpu, mmu_seq))
2865                 goto out_unlock;
2866         kvm_mmu_free_some_pages(vcpu);
2867         if (likely(!force_pt_level))
2868                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2869         r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2870                          prefault);
2871         spin_unlock(&vcpu->kvm->mmu_lock);
2872
2873
2874         return r;
2875
2876 out_unlock:
2877         spin_unlock(&vcpu->kvm->mmu_lock);
2878         kvm_release_pfn_clean(pfn);
2879         return 0;
2880 }
2881
2882
2883 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2884 {
2885         int i;
2886         struct kvm_mmu_page *sp;
2887         LIST_HEAD(invalid_list);
2888
2889         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2890                 return;
2891         spin_lock(&vcpu->kvm->mmu_lock);
2892         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2893             (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2894              vcpu->arch.mmu.direct_map)) {
2895                 hpa_t root = vcpu->arch.mmu.root_hpa;
2896
2897                 sp = page_header(root);
2898                 --sp->root_count;
2899                 if (!sp->root_count && sp->role.invalid) {
2900                         kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2901                         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2902                 }
2903                 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2904                 spin_unlock(&vcpu->kvm->mmu_lock);
2905                 return;
2906         }
2907         for (i = 0; i < 4; ++i) {
2908                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2909
2910                 if (root) {
2911                         root &= PT64_BASE_ADDR_MASK;
2912                         sp = page_header(root);
2913                         --sp->root_count;
2914                         if (!sp->root_count && sp->role.invalid)
2915                                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2916                                                          &invalid_list);
2917                 }
2918                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2919         }
2920         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2921         spin_unlock(&vcpu->kvm->mmu_lock);
2922         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2923 }
2924
2925 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2926 {
2927         int ret = 0;
2928
2929         if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2930                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2931                 ret = 1;
2932         }
2933
2934         return ret;
2935 }
2936
2937 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2938 {
2939         struct kvm_mmu_page *sp;
2940         unsigned i;
2941
2942         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2943                 spin_lock(&vcpu->kvm->mmu_lock);
2944                 kvm_mmu_free_some_pages(vcpu);
2945                 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2946                                       1, ACC_ALL, NULL);
2947                 ++sp->root_count;
2948                 spin_unlock(&vcpu->kvm->mmu_lock);
2949                 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2950         } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2951                 for (i = 0; i < 4; ++i) {
2952                         hpa_t root = vcpu->arch.mmu.pae_root[i];
2953
2954                         ASSERT(!VALID_PAGE(root));
2955                         spin_lock(&vcpu->kvm->mmu_lock);
2956                         kvm_mmu_free_some_pages(vcpu);
2957                         sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2958                                               i << 30,
2959                                               PT32_ROOT_LEVEL, 1, ACC_ALL,
2960                                               NULL);
2961                         root = __pa(sp->spt);
2962                         ++sp->root_count;
2963                         spin_unlock(&vcpu->kvm->mmu_lock);
2964                         vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2965                 }
2966                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2967         } else
2968                 BUG();
2969
2970         return 0;
2971 }
2972
2973 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2974 {
2975         struct kvm_mmu_page *sp;
2976         u64 pdptr, pm_mask;
2977         gfn_t root_gfn;
2978         int i;
2979
2980         root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2981
2982         if (mmu_check_root(vcpu, root_gfn))
2983                 return 1;
2984
2985         /*
2986          * Do we shadow a long mode page table? If so we need to
2987          * write-protect the guests page table root.
2988          */
2989         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2990                 hpa_t root = vcpu->arch.mmu.root_hpa;
2991
2992                 ASSERT(!VALID_PAGE(root));
2993
2994                 spin_lock(&vcpu->kvm->mmu_lock);
2995                 kvm_mmu_free_some_pages(vcpu);
2996                 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2997                                       0, ACC_ALL, NULL);
2998                 root = __pa(sp->spt);
2999                 ++sp->root_count;
3000                 spin_unlock(&vcpu->kvm->mmu_lock);
3001                 vcpu->arch.mmu.root_hpa = root;
3002                 return 0;
3003         }
3004
3005         /*
3006          * We shadow a 32 bit page table. This may be a legacy 2-level
3007          * or a PAE 3-level page table. In either case we need to be aware that
3008          * the shadow page table may be a PAE or a long mode page table.
3009          */
3010         pm_mask = PT_PRESENT_MASK;
3011         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3012                 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3013
3014         for (i = 0; i < 4; ++i) {
3015                 hpa_t root = vcpu->arch.mmu.pae_root[i];
3016
3017                 ASSERT(!VALID_PAGE(root));
3018                 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3019                         pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3020                         if (!is_present_gpte(pdptr)) {
3021                                 vcpu->arch.mmu.pae_root[i] = 0;
3022                                 continue;
3023                         }
3024                         root_gfn = pdptr >> PAGE_SHIFT;
3025                         if (mmu_check_root(vcpu, root_gfn))
3026                                 return 1;
3027                 }
3028                 spin_lock(&vcpu->kvm->mmu_lock);
3029                 kvm_mmu_free_some_pages(vcpu);
3030                 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3031                                       PT32_ROOT_LEVEL, 0,
3032                                       ACC_ALL, NULL);
3033                 root = __pa(sp->spt);
3034                 ++sp->root_count;
3035                 spin_unlock(&vcpu->kvm->mmu_lock);
3036
3037                 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3038         }
3039         vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3040
3041         /*
3042          * If we shadow a 32 bit page table with a long mode page
3043          * table we enter this path.
3044          */
3045         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3046                 if (vcpu->arch.mmu.lm_root == NULL) {
3047                         /*
3048                          * The additional page necessary for this is only
3049                          * allocated on demand.
3050                          */
3051
3052                         u64 *lm_root;
3053
3054                         lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3055                         if (lm_root == NULL)
3056                                 return 1;
3057
3058                         lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3059
3060                         vcpu->arch.mmu.lm_root = lm_root;
3061                 }
3062
3063                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3064         }
3065
3066         return 0;
3067 }
3068
3069 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3070 {
3071         if (vcpu->arch.mmu.direct_map)
3072                 return mmu_alloc_direct_roots(vcpu);
3073         else
3074                 return mmu_alloc_shadow_roots(vcpu);
3075 }
3076
3077 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3078 {
3079         int i;
3080         struct kvm_mmu_page *sp;
3081
3082         if (vcpu->arch.mmu.direct_map)
3083                 return;
3084
3085         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3086                 return;
3087
3088         vcpu_clear_mmio_info(vcpu, ~0ul);
3089         kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3090         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3091                 hpa_t root = vcpu->arch.mmu.root_hpa;
3092                 sp = page_header(root);
3093                 mmu_sync_children(vcpu, sp);
3094                 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3095                 return;
3096         }
3097         for (i = 0; i < 4; ++i) {
3098                 hpa_t root = vcpu->arch.mmu.pae_root[i];
3099
3100                 if (root && VALID_PAGE(root)) {
3101                         root &= PT64_BASE_ADDR_MASK;
3102                         sp = page_header(root);
3103                         mmu_sync_children(vcpu, sp);
3104                 }
3105         }
3106         kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3107 }
3108
3109 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3110 {
3111         spin_lock(&vcpu->kvm->mmu_lock);
3112         mmu_sync_roots(vcpu);
3113         spin_unlock(&vcpu->kvm->mmu_lock);
3114 }
3115
3116 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3117                                   u32 access, struct x86_exception *exception)
3118 {
3119         if (exception)
3120                 exception->error_code = 0;
3121         return vaddr;
3122 }
3123
3124 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3125                                          u32 access,
3126                                          struct x86_exception *exception)
3127 {
3128         if (exception)
3129                 exception->error_code = 0;
3130         return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3131 }
3132
3133 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3134 {
3135         if (direct)
3136                 return vcpu_match_mmio_gpa(vcpu, addr);
3137
3138         return vcpu_match_mmio_gva(vcpu, addr);
3139 }
3140
3141
3142 /*
3143  * On direct hosts, the last spte is only allows two states
3144  * for mmio page fault:
3145  *   - It is the mmio spte
3146  *   - It is zapped or it is being zapped.
3147  *
3148  * This function completely checks the spte when the last spte
3149  * is not the mmio spte.
3150  */
3151 static bool check_direct_spte_mmio_pf(u64 spte)
3152 {
3153         return __check_direct_spte_mmio_pf(spte);
3154 }
3155
3156 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3157 {
3158         struct kvm_shadow_walk_iterator iterator;
3159         u64 spte = 0ull;
3160
3161         walk_shadow_page_lockless_begin(vcpu);
3162         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3163                 if (!is_shadow_present_pte(spte))
3164                         break;
3165         walk_shadow_page_lockless_end(vcpu);
3166
3167         return spte;
3168 }
3169
3170 /*
3171  * If it is a real mmio page fault, return 1 and emulat the instruction
3172  * directly, return 0 to let CPU fault again on the address, -1 is
3173  * returned if bug is detected.
3174  */
3175 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3176 {
3177         u64 spte;
3178
3179         if (quickly_check_mmio_pf(vcpu, addr, direct))
3180                 return 1;
3181
3182         spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3183
3184         if (is_mmio_spte(spte)) {
3185                 gfn_t gfn = get_mmio_spte_gfn(spte);
3186                 unsigned access = get_mmio_spte_access(spte);
3187
3188                 if (direct)
3189                         addr = 0;
3190
3191                 trace_handle_mmio_page_fault(addr, gfn, access);
3192                 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3193                 return 1;
3194         }
3195
3196         /*
3197          * It's ok if the gva is remapped by other cpus on shadow guest,
3198          * it's a BUG if the gfn is not a mmio page.
3199          */
3200         if (direct && !check_direct_spte_mmio_pf(spte))
3201                 return -1;
3202
3203         /*
3204          * If the page table is zapped by other cpus, let CPU fault again on
3205          * the address.
3206          */
3207         return 0;
3208 }
3209 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3210
3211 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3212                                   u32 error_code, bool direct)
3213 {
3214         int ret;
3215
3216         ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3217         WARN_ON(ret < 0);
3218         return ret;
3219 }
3220
3221 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3222                                 u32 error_code, bool prefault)
3223 {
3224         gfn_t gfn;
3225         int r;
3226
3227         pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3228
3229         if (unlikely(error_code & PFERR_RSVD_MASK))
3230                 return handle_mmio_page_fault(vcpu, gva, error_code, true);
3231
3232         r = mmu_topup_memory_caches(vcpu);
3233         if (r)
3234                 return r;
3235
3236         ASSERT(vcpu);
3237         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3238
3239         gfn = gva >> PAGE_SHIFT;
3240
3241         return nonpaging_map(vcpu, gva & PAGE_MASK,
3242                              error_code, gfn, prefault);
3243 }
3244
3245 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3246 {
3247         struct kvm_arch_async_pf arch;
3248
3249         arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3250         arch.gfn = gfn;
3251         arch.direct_map = vcpu->arch.mmu.direct_map;
3252         arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3253
3254         return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3255 }
3256
3257 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3258 {
3259         if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3260                      kvm_event_needs_reinjection(vcpu)))
3261                 return false;
3262
3263         return kvm_x86_ops->interrupt_allowed(vcpu);
3264 }
3265
3266 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3267                          gva_t gva, pfn_t *pfn, bool write, bool *writable)
3268 {
3269         bool async;
3270
3271         *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3272
3273         if (!async)
3274                 return false; /* *pfn has correct page already */
3275
3276         kvm_release_pfn_clean(*pfn);
3277
3278         if (!prefault && can_do_async_pf(vcpu)) {
3279                 trace_kvm_try_async_get_page(gva, gfn);
3280                 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3281                         trace_kvm_async_pf_doublefault(gva, gfn);
3282                         kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3283                         return true;
3284                 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3285                         return true;
3286         }
3287
3288         *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3289
3290         return false;
3291 }
3292
3293 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3294                           bool prefault)
3295 {
3296         pfn_t pfn;
3297         int r;
3298         int level;
3299         int force_pt_level;
3300         gfn_t gfn = gpa >> PAGE_SHIFT;
3301         unsigned long mmu_seq;
3302         int write = error_code & PFERR_WRITE_MASK;
3303         bool map_writable;
3304
3305         ASSERT(vcpu);
3306         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3307
3308         if (unlikely(error_code & PFERR_RSVD_MASK))
3309                 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3310
3311         r = mmu_topup_memory_caches(vcpu);
3312         if (r)
3313                 return r;
3314
3315         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3316         if (likely(!force_pt_level)) {
3317                 level = mapping_level(vcpu, gfn);
3318                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3319         } else
3320                 level = PT_PAGE_TABLE_LEVEL;
3321
3322         if (fast_page_fault(vcpu, gpa, level, error_code))
3323                 return 0;
3324
3325         mmu_seq = vcpu->kvm->mmu_notifier_seq;
3326         smp_rmb();
3327
3328         if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3329                 return 0;
3330
3331         if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3332                 return r;
3333
3334         spin_lock(&vcpu->kvm->mmu_lock);
3335         if (mmu_notifier_retry(vcpu, mmu_seq))
3336                 goto out_unlock;
3337         kvm_mmu_free_some_pages(vcpu);
3338         if (likely(!force_pt_level))
3339                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3340         r = __direct_map(vcpu, gpa, write, map_writable,
3341                          level, gfn, pfn, prefault);
3342         spin_unlock(&vcpu->kvm->mmu_lock);
3343
3344         return r;
3345
3346 out_unlock:
3347         spin_unlock(&vcpu->kvm->mmu_lock);
3348         kvm_release_pfn_clean(pfn);
3349         return 0;
3350 }
3351
3352 static void nonpaging_free(struct kvm_vcpu *vcpu)
3353 {
3354         mmu_free_roots(vcpu);
3355 }
3356
3357 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3358                                   struct kvm_mmu *context)
3359 {
3360         context->new_cr3 = nonpaging_new_cr3;
3361         context->page_fault = nonpaging_page_fault;
3362         context->gva_to_gpa = nonpaging_gva_to_gpa;
3363         context->free = nonpaging_free;
3364         context->sync_page = nonpaging_sync_page;
3365         context->invlpg = nonpaging_invlpg;
3366         context->update_pte = nonpaging_update_pte;
3367         context->root_level = 0;
3368         context->shadow_root_level = PT32E_ROOT_LEVEL;
3369         context->root_hpa = INVALID_PAGE;
3370         context->direct_map = true;
3371         context->nx = false;
3372         return 0;
3373 }
3374
3375 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3376 {
3377         ++vcpu->stat.tlb_flush;
3378         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3379 }
3380
3381 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3382 {
3383         pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3384         mmu_free_roots(vcpu);
3385 }
3386
3387 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3388 {
3389         return kvm_read_cr3(vcpu);
3390 }
3391
3392 static void inject_page_fault(struct kvm_vcpu *vcpu,
3393                               struct x86_exception *fault)
3394 {
3395         vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3396 }
3397
3398 static void paging_free(struct kvm_vcpu *vcpu)
3399 {
3400         nonpaging_free(vcpu);
3401 }
3402
3403 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3404 {
3405         int bit7;
3406
3407         bit7 = (gpte >> 7) & 1;
3408         return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
3409 }
3410
3411 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3412                            int *nr_present)
3413 {
3414         if (unlikely(is_mmio_spte(*sptep))) {
3415                 if (gfn != get_mmio_spte_gfn(*sptep)) {
3416                         mmu_spte_clear_no_track(sptep);
3417                         return true;
3418                 }
3419
3420                 (*nr_present)++;
3421                 mark_mmio_spte(sptep, gfn, access);
3422                 return true;
3423         }
3424
3425         return false;
3426 }
3427
3428 #define PTTYPE 64
3429 #include "paging_tmpl.h"
3430 #undef PTTYPE
3431
3432 #define PTTYPE 32
3433 #include "paging_tmpl.h"
3434 #undef PTTYPE
3435
3436 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3437                                   struct kvm_mmu *context)
3438 {
3439         int maxphyaddr = cpuid_maxphyaddr(vcpu);
3440         u64 exb_bit_rsvd = 0;
3441
3442         if (!context->nx)
3443                 exb_bit_rsvd = rsvd_bits(63, 63);
3444         switch (context->root_level) {
3445         case PT32_ROOT_LEVEL:
3446                 /* no rsvd bits for 2 level 4K page table entries */
3447                 context->rsvd_bits_mask[0][1] = 0;
3448                 context->rsvd_bits_mask[0][0] = 0;
3449                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3450
3451                 if (!is_pse(vcpu)) {
3452                         context->rsvd_bits_mask[1][1] = 0;
3453                         break;
3454                 }
3455
3456                 if (is_cpuid_PSE36())
3457                         /* 36bits PSE 4MB page */
3458                         context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3459                 else
3460                         /* 32 bits PSE 4MB page */
3461                         context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3462                 break;
3463         case PT32E_ROOT_LEVEL:
3464                 context->rsvd_bits_mask[0][2] =
3465                         rsvd_bits(maxphyaddr, 63) |
3466                         rsvd_bits(7, 8) | rsvd_bits(1, 2);      /* PDPTE */
3467                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3468                         rsvd_bits(maxphyaddr, 62);      /* PDE */
3469                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3470                         rsvd_bits(maxphyaddr, 62);      /* PTE */
3471                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3472                         rsvd_bits(maxphyaddr, 62) |
3473                         rsvd_bits(13, 20);              /* large page */
3474                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3475                 break;
3476         case PT64_ROOT_LEVEL:
3477                 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3478                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3479                 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3480                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3481                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3482                         rsvd_bits(maxphyaddr, 51);
3483                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3484                         rsvd_bits(maxphyaddr, 51);
3485                 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3486                 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3487                         rsvd_bits(maxphyaddr, 51) |
3488                         rsvd_bits(13, 29);
3489                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3490                         rsvd_bits(maxphyaddr, 51) |
3491                         rsvd_bits(13, 20);              /* large page */
3492                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3493                 break;
3494         }
3495 }
3496
3497 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3498                                         struct kvm_mmu *context,
3499                                         int level)
3500 {
3501         context->nx = is_nx(vcpu);
3502         context->root_level = level;
3503
3504         reset_rsvds_bits_mask(vcpu, context);
3505
3506         ASSERT(is_pae(vcpu));
3507         context->new_cr3 = paging_new_cr3;
3508         context->page_fault = paging64_page_fault;
3509         context->gva_to_gpa = paging64_gva_to_gpa;
3510         context->sync_page = paging64_sync_page;
3511         context->invlpg = paging64_invlpg;
3512         context->update_pte = paging64_update_pte;
3513         context->free = paging_free;
3514         context->shadow_root_level = level;
3515         context->root_hpa = INVALID_PAGE;
3516         context->direct_map = false;
3517         return 0;
3518 }
3519
3520 static int paging64_init_context(struct kvm_vcpu *vcpu,
3521                                  struct kvm_mmu *context)
3522 {
3523         return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3524 }
3525
3526 static int paging32_init_context(struct kvm_vcpu *vcpu,
3527                                  struct kvm_mmu *context)
3528 {
3529         context->nx = false;
3530         context->root_level = PT32_ROOT_LEVEL;
3531
3532         reset_rsvds_bits_mask(vcpu, context);
3533
3534         context->new_cr3 = paging_new_cr3;
3535         context->page_fault = paging32_page_fault;
3536         context->gva_to_gpa = paging32_gva_to_gpa;
3537         context->free = paging_free;
3538         context->sync_page = paging32_sync_page;
3539         context->invlpg = paging32_invlpg;
3540         context->update_pte = paging32_update_pte;
3541         context->shadow_root_level = PT32E_ROOT_LEVEL;
3542         context->root_hpa = INVALID_PAGE;
3543         context->direct_map = false;
3544         return 0;
3545 }
3546
3547 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3548                                   struct kvm_mmu *context)
3549 {
3550         return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3551 }
3552
3553 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3554 {
3555         struct kvm_mmu *context = vcpu->arch.walk_mmu;
3556
3557         context->base_role.word = 0;
3558         context->new_cr3 = nonpaging_new_cr3;
3559         context->page_fault = tdp_page_fault;
3560         context->free = nonpaging_free;
3561         context->sync_page = nonpaging_sync_page;
3562         context->invlpg = nonpaging_invlpg;
3563         context->update_pte = nonpaging_update_pte;
3564         context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3565         context->root_hpa = INVALID_PAGE;
3566         context->direct_map = true;
3567         context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3568         context->get_cr3 = get_cr3;
3569         context->get_pdptr = kvm_pdptr_read;
3570         context->inject_page_fault = kvm_inject_page_fault;
3571
3572         if (!is_paging(vcpu)) {
3573                 context->nx = false;
3574                 context->gva_to_gpa = nonpaging_gva_to_gpa;
3575                 context->root_level = 0;
3576         } else if (is_long_mode(vcpu)) {
3577                 context->nx = is_nx(vcpu);
3578                 context->root_level = PT64_ROOT_LEVEL;
3579                 reset_rsvds_bits_mask(vcpu, context);
3580                 context->gva_to_gpa = paging64_gva_to_gpa;
3581         } else if (is_pae(vcpu)) {
3582                 context->nx = is_nx(vcpu);
3583                 context->root_level = PT32E_ROOT_LEVEL;
3584                 reset_rsvds_bits_mask(vcpu, context);
3585                 context->gva_to_gpa = paging64_gva_to_gpa;
3586         } else {
3587                 context->nx = false;
3588                 context->root_level = PT32_ROOT_LEVEL;
3589                 reset_rsvds_bits_mask(vcpu, context);
3590                 context->gva_to_gpa = paging32_gva_to_gpa;
3591         }
3592
3593         return 0;
3594 }
3595
3596 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3597 {
3598         int r;
3599         bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3600         ASSERT(vcpu);
3601         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3602
3603         if (!is_paging(vcpu))
3604                 r = nonpaging_init_context(vcpu, context);
3605         else if (is_long_mode(vcpu))
3606                 r = paging64_init_context(vcpu, context);
3607         else if (is_pae(vcpu))
3608                 r = paging32E_init_context(vcpu, context);
3609         else
3610                 r = paging32_init_context(vcpu, context);
3611
3612         vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3613         vcpu->arch.mmu.base_role.cr0_wp  = is_write_protection(vcpu);
3614         vcpu->arch.mmu.base_role.smep_andnot_wp
3615                 = smep && !is_write_protection(vcpu);
3616
3617         return r;
3618 }
3619 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3620
3621 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3622 {
3623         int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3624
3625         vcpu->arch.walk_mmu->set_cr3           = kvm_x86_ops->set_cr3;
3626         vcpu->arch.walk_mmu->get_cr3           = get_cr3;
3627         vcpu->arch.walk_mmu->get_pdptr         = kvm_pdptr_read;
3628         vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3629
3630         return r;
3631 }
3632
3633 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3634 {
3635         struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3636
3637         g_context->get_cr3           = get_cr3;
3638         g_context->get_pdptr         = kvm_pdptr_read;
3639         g_context->inject_page_fault = kvm_inject_page_fault;
3640
3641         /*
3642          * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3643          * translation of l2_gpa to l1_gpa addresses is done using the
3644          * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3645          * functions between mmu and nested_mmu are swapped.
3646          */
3647         if (!is_paging(vcpu)) {
3648                 g_context->nx = false;
3649                 g_context->root_level = 0;
3650                 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3651         } else if (is_long_mode(vcpu)) {
3652                 g_context->nx = is_nx(vcpu);
3653                 g_context->root_level = PT64_ROOT_LEVEL;
3654                 reset_rsvds_bits_mask(vcpu, g_context);
3655                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3656         } else if (is_pae(vcpu)) {
3657                 g_context->nx = is_nx(vcpu);
3658                 g_context->root_level = PT32E_ROOT_LEVEL;
3659                 reset_rsvds_bits_mask(vcpu, g_context);
3660                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3661         } else {
3662                 g_context->nx = false;
3663                 g_context->root_level = PT32_ROOT_LEVEL;
3664                 reset_rsvds_bits_mask(vcpu, g_context);
3665                 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3666         }
3667
3668         return 0;
3669 }
3670
3671 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3672 {
3673         if (mmu_is_nested(vcpu))
3674                 return init_kvm_nested_mmu(vcpu);
3675         else if (tdp_enabled)
3676                 return init_kvm_tdp_mmu(vcpu);
3677         else
3678                 return init_kvm_softmmu(vcpu);
3679 }
3680
3681 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3682 {
3683         ASSERT(vcpu);
3684         if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3685                 /* mmu.free() should set root_hpa = INVALID_PAGE */
3686                 vcpu->arch.mmu.free(vcpu);
3687 }
3688
3689 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3690 {
3691         destroy_kvm_mmu(vcpu);
3692         return init_kvm_mmu(vcpu);
3693 }
3694 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3695
3696 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3697 {
3698         int r;
3699
3700         r = mmu_topup_memory_caches(vcpu);
3701         if (r)
3702                 goto out;
3703         r = mmu_alloc_roots(vcpu);
3704         spin_lock(&vcpu->kvm->mmu_lock);
3705         mmu_sync_roots(vcpu);
3706         spin_unlock(&vcpu->kvm->mmu_lock);
3707         if (r)
3708                 goto out;
3709         /* set_cr3() should ensure TLB has been flushed */
3710         vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3711 out:
3712         return r;
3713 }
3714 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3715
3716 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3717 {
3718         mmu_free_roots(vcpu);
3719 }
3720 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3721
3722 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3723                                   struct kvm_mmu_page *sp, u64 *spte,
3724                                   const void *new)
3725 {
3726         if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3727                 ++vcpu->kvm->stat.mmu_pde_zapped;
3728                 return;
3729         }
3730
3731         ++vcpu->kvm->stat.mmu_pte_updated;
3732         vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3733 }
3734
3735 static bool need_remote_flush(u64 old, u64 new)
3736 {
3737         if (!is_shadow_present_pte(old))
3738                 return false;
3739         if (!is_shadow_present_pte(new))
3740                 return true;
3741         if ((old ^ new) & PT64_BASE_ADDR_MASK)
3742                 return true;
3743         old ^= PT64_NX_MASK;
3744         new ^= PT64_NX_MASK;
3745         return (old & ~new & PT64_PERM_MASK) != 0;
3746 }
3747
3748 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3749                                     bool remote_flush, bool local_flush)
3750 {
3751         if (zap_page)
3752                 return;
3753
3754         if (remote_flush)
3755                 kvm_flush_remote_tlbs(vcpu->kvm);
3756         else if (local_flush)
3757                 kvm_mmu_flush_tlb(vcpu);
3758 }
3759
3760 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3761                                     const u8 *new, int *bytes)
3762 {
3763         u64 gentry;
3764         int r;
3765
3766         /*
3767          * Assume that the pte write on a page table of the same type
3768          * as the current vcpu paging mode since we update the sptes only
3769          * when they have the same mode.
3770          */
3771         if (is_pae(vcpu) && *bytes == 4) {
3772                 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3773                 *gpa &= ~(gpa_t)7;
3774                 *bytes = 8;
3775                 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, min(*bytes, 8));
3776                 if (r)
3777                         gentry = 0;
3778                 new = (const u8 *)&gentry;
3779         }
3780
3781         switch (*bytes) {
3782         case 4:
3783                 gentry = *(const u32 *)new;
3784                 break;
3785         case 8:
3786                 gentry = *(const u64 *)new;
3787                 break;
3788         default:
3789                 gentry = 0;
3790                 break;
3791         }
3792
3793         return gentry;
3794 }
3795
3796 /*
3797  * If we're seeing too many writes to a page, it may no longer be a page table,
3798  * or we may be forking, in which case it is better to unmap the page.
3799  */
3800 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3801 {
3802         /*
3803          * Skip write-flooding detected for the sp whose level is 1, because
3804          * it can become unsync, then the guest page is not write-protected.
3805          */
3806         if (sp->role.level == PT_PAGE_TABLE_LEVEL)
3807                 return false;
3808
3809         return ++sp->write_flooding_count >= 3;
3810 }
3811
3812 /*
3813  * Misaligned accesses are too much trouble to fix up; also, they usually
3814  * indicate a page is not used as a page table.
3815  */
3816 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3817                                     int bytes)
3818 {
3819         unsigned offset, pte_size, misaligned;
3820
3821         pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3822                  gpa, bytes, sp->role.word);
3823
3824         offset = offset_in_page(gpa);
3825         pte_size = sp->role.cr4_pae ? 8 : 4;
3826
3827         /*
3828          * Sometimes, the OS only writes the last one bytes to update status
3829          * bits, for example, in linux, andb instruction is used in clear_bit().
3830          */
3831         if (!(offset & (pte_size - 1)) && bytes == 1)
3832                 return false;
3833
3834         misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3835         misaligned |= bytes < 4;
3836
3837         return misaligned;
3838 }
3839
3840 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3841 {
3842         unsigned page_offset, quadrant;
3843         u64 *spte;
3844         int level;
3845
3846         page_offset = offset_in_page(gpa);
3847         level = sp->role.level;
3848         *nspte = 1;
3849         if (!sp->role.cr4_pae) {
3850                 page_offset <<= 1;      /* 32->64 */
3851                 /*
3852                  * A 32-bit pde maps 4MB while the shadow pdes map
3853                  * only 2MB.  So we need to double the offset again
3854                  * and zap two pdes instead of one.
3855                  */
3856                 if (level == PT32_ROOT_LEVEL) {
3857                         page_offset &= ~7; /* kill rounding error */
3858                         page_offset <<= 1;
3859                         *nspte = 2;
3860                 }
3861                 quadrant = page_offset >> PAGE_SHIFT;
3862                 page_offset &= ~PAGE_MASK;
3863                 if (quadrant != sp->role.quadrant)
3864                         return NULL;
3865         }
3866
3867         spte = &sp->spt[page_offset / sizeof(*spte)];
3868         return spte;
3869 }
3870
3871 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3872                        const u8 *new, int bytes)
3873 {
3874         gfn_t gfn = gpa >> PAGE_SHIFT;
3875         union kvm_mmu_page_role mask = { .word = 0 };
3876         struct kvm_mmu_page *sp;
3877         struct hlist_node *node;
3878         LIST_HEAD(invalid_list);
3879         u64 entry, gentry, *spte;
3880         int npte;
3881         bool remote_flush, local_flush, zap_page;
3882
3883         /*
3884          * If we don't have indirect shadow pages, it means no page is
3885          * write-protected, so we can exit simply.
3886          */
3887         if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3888                 return;
3889
3890         zap_page = remote_flush = local_flush = false;
3891
3892         pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3893
3894         gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
3895
3896         /*
3897          * No need to care whether allocation memory is successful
3898          * or not since pte prefetch is skiped if it does not have
3899          * enough objects in the cache.
3900          */
3901         mmu_topup_memory_caches(vcpu);
3902
3903         spin_lock(&vcpu->kvm->mmu_lock);
3904         ++vcpu->kvm->stat.mmu_pte_write;
3905         kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3906
3907         mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3908         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3909                 if (detect_write_misaligned(sp, gpa, bytes) ||
3910                       detect_write_flooding(sp)) {
3911                         zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3912                                                      &invalid_list);
3913                         ++vcpu->kvm->stat.mmu_flooded;
3914                         continue;
3915                 }
3916
3917                 spte = get_written_sptes(sp, gpa, &npte);
3918                 if (!spte)
3919                         continue;
3920
3921                 local_flush = true;
3922                 while (npte--) {
3923                         entry = *spte;
3924                         mmu_page_zap_pte(vcpu->kvm, sp, spte);
3925                         if (gentry &&
3926                               !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3927                               & mask.word) && rmap_can_add(vcpu))
3928                                 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3929                         if (!remote_flush && need_remote_flush(entry, *spte))
3930                                 remote_flush = true;
3931                         ++spte;
3932                 }
3933         }
3934         mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3935         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3936         kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3937         spin_unlock(&vcpu->kvm->mmu_lock);
3938 }
3939
3940 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3941 {
3942         gpa_t gpa;
3943         int r;
3944
3945         if (vcpu->arch.mmu.direct_map)
3946                 return 0;
3947
3948         gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3949
3950         r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3951
3952         return r;
3953 }
3954 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3955
3956 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3957 {
3958         LIST_HEAD(invalid_list);
3959
3960         while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3961                !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3962                 struct kvm_mmu_page *sp;
3963
3964                 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3965                                   struct kvm_mmu_page, link);
3966                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3967                 ++vcpu->kvm->stat.mmu_recycled;
3968         }
3969         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3970 }
3971
3972 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
3973 {
3974         if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
3975                 return vcpu_match_mmio_gpa(vcpu, addr);
3976
3977         return vcpu_match_mmio_gva(vcpu, addr);
3978 }
3979
3980 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3981                        void *insn, int insn_len)
3982 {
3983         int r, emulation_type = EMULTYPE_RETRY;
3984         enum emulation_result er;
3985
3986         r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3987         if (r < 0)
3988                 goto out;
3989
3990         if (!r) {
3991                 r = 1;
3992                 goto out;
3993         }
3994
3995         if (is_mmio_page_fault(vcpu, cr2))
3996                 emulation_type = 0;
3997
3998         er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
3999
4000         switch (er) {
4001         case EMULATE_DONE:
4002                 return 1;
4003         case EMULATE_DO_MMIO:
4004                 ++vcpu->stat.mmio_exits;
4005                 /* fall through */
4006         case EMULATE_FAIL:
4007                 return 0;
4008         default:
4009                 BUG();
4010         }
4011 out:
4012         return r;
4013 }
4014 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4015
4016 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4017 {
4018         vcpu->arch.mmu.invlpg(vcpu, gva);
4019         kvm_mmu_flush_tlb(vcpu);
4020         ++vcpu->stat.invlpg;
4021 }
4022 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4023
4024 void kvm_enable_tdp(void)
4025 {
4026         tdp_enabled = true;
4027 }
4028 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4029
4030 void kvm_disable_tdp(void)
4031 {
4032         tdp_enabled = false;
4033 }
4034 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4035
4036 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4037 {
4038         free_page((unsigned long)vcpu->arch.mmu.pae_root);
4039         if (vcpu->arch.mmu.lm_root != NULL)
4040                 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4041 }
4042
4043 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4044 {
4045         struct page *page;
4046         int i;
4047
4048         ASSERT(vcpu);
4049
4050         /*
4051          * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4052          * Therefore we need to allocate shadow page tables in the first
4053          * 4GB of memory, which happens to fit the DMA32 zone.
4054          */
4055         page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4056         if (!page)
4057                 return -ENOMEM;
4058
4059         vcpu->arch.mmu.pae_root = page_address(page);
4060         for (i = 0; i < 4; ++i)
4061                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4062
4063         return 0;
4064 }
4065
4066 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4067 {
4068         ASSERT(vcpu);
4069
4070         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4071         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4072         vcpu->arch.mmu.translate_gpa = translate_gpa;
4073         vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4074
4075         return alloc_mmu_pages(vcpu);
4076 }
4077
4078 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
4079 {
4080         ASSERT(vcpu);
4081         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4082
4083         return init_kvm_mmu(vcpu);
4084 }
4085
4086 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4087 {
4088         struct kvm_mmu_page *sp;
4089         bool flush = false;
4090
4091         list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
4092                 int i;
4093                 u64 *pt;
4094
4095                 if (!test_bit(slot, sp->slot_bitmap))
4096                         continue;
4097
4098                 pt = sp->spt;
4099                 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
4100                         if (!is_shadow_present_pte(pt[i]) ||
4101                               !is_last_spte(pt[i], sp->role.level))
4102                                 continue;
4103
4104                         spte_write_protect(kvm, &pt[i], &flush, false);
4105                 }
4106         }
4107         kvm_flush_remote_tlbs(kvm);
4108 }
4109
4110 void kvm_mmu_zap_all(struct kvm *kvm)
4111 {
4112         struct kvm_mmu_page *sp, *node;
4113         LIST_HEAD(invalid_list);
4114
4115         spin_lock(&kvm->mmu_lock);
4116 restart:
4117         list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
4118                 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
4119                         goto restart;
4120
4121         kvm_mmu_commit_zap_page(kvm, &invalid_list);
4122         spin_unlock(&kvm->mmu_lock);
4123 }
4124
4125 static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
4126                                                 struct list_head *invalid_list)
4127 {
4128         struct kvm_mmu_page *page;
4129
4130         if (list_empty(&kvm->arch.active_mmu_pages))
4131                 return;
4132
4133         page = container_of(kvm->arch.active_mmu_pages.prev,
4134                             struct kvm_mmu_page, link);
4135         kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
4136 }
4137
4138 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
4139 {
4140         struct kvm *kvm;
4141         int nr_to_scan = sc->nr_to_scan;
4142
4143         if (nr_to_scan == 0)
4144                 goto out;
4145
4146         raw_spin_lock(&kvm_lock);
4147
4148         list_for_each_entry(kvm, &vm_list, vm_list) {
4149                 int idx;
4150                 LIST_HEAD(invalid_list);
4151
4152                 /*
4153                  * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4154                  * here. We may skip a VM instance errorneosly, but we do not
4155                  * want to shrink a VM that only started to populate its MMU
4156                  * anyway.
4157                  */
4158                 if (kvm->arch.n_used_mmu_pages > 0) {
4159                         if (!nr_to_scan--)
4160                                 break;
4161                         continue;
4162                 }
4163
4164                 idx = srcu_read_lock(&kvm->srcu);
4165                 spin_lock(&kvm->mmu_lock);
4166
4167                 kvm_mmu_remove_some_alloc_mmu_pages(kvm, &invalid_list);
4168                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4169
4170                 spin_unlock(&kvm->mmu_lock);
4171                 srcu_read_unlock(&kvm->srcu, idx);
4172
4173                 list_move_tail(&kvm->vm_list, &vm_list);
4174                 break;
4175         }
4176
4177         raw_spin_unlock(&kvm_lock);
4178
4179 out:
4180         return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4181 }
4182
4183 static struct shrinker mmu_shrinker = {
4184         .shrink = mmu_shrink,
4185         .seeks = DEFAULT_SEEKS * 10,
4186 };
4187
4188 static void mmu_destroy_caches(void)
4189 {
4190         if (pte_list_desc_cache)
4191                 kmem_cache_destroy(pte_list_desc_cache);
4192         if (mmu_page_header_cache)
4193                 kmem_cache_destroy(mmu_page_header_cache);
4194 }
4195
4196 int kvm_mmu_module_init(void)
4197 {
4198         pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4199                                             sizeof(struct pte_list_desc),
4200                                             0, 0, NULL);
4201         if (!pte_list_desc_cache)
4202                 goto nomem;
4203
4204         mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4205                                                   sizeof(struct kvm_mmu_page),
4206                                                   0, 0, NULL);
4207         if (!mmu_page_header_cache)
4208                 goto nomem;
4209
4210         if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4211                 goto nomem;
4212
4213         register_shrinker(&mmu_shrinker);
4214
4215         return 0;
4216
4217 nomem:
4218         mmu_destroy_caches();
4219         return -ENOMEM;
4220 }
4221
4222 /*
4223  * Caculate mmu pages needed for kvm.
4224  */
4225 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4226 {
4227         unsigned int nr_mmu_pages;
4228         unsigned int  nr_pages = 0;
4229         struct kvm_memslots *slots;
4230         struct kvm_memory_slot *memslot;
4231
4232         slots = kvm_memslots(kvm);
4233
4234         kvm_for_each_memslot(memslot, slots)
4235                 nr_pages += memslot->npages;
4236
4237         nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4238         nr_mmu_pages = max(nr_mmu_pages,
4239                         (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4240
4241         return nr_mmu_pages;
4242 }
4243
4244 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4245 {
4246         struct kvm_shadow_walk_iterator iterator;
4247         u64 spte;
4248         int nr_sptes = 0;
4249
4250         walk_shadow_page_lockless_begin(vcpu);
4251         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4252                 sptes[iterator.level-1] = spte;
4253                 nr_sptes++;
4254                 if (!is_shadow_present_pte(spte))
4255                         break;
4256         }
4257         walk_shadow_page_lockless_end(vcpu);
4258
4259         return nr_sptes;
4260 }
4261 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4262
4263 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4264 {
4265         ASSERT(vcpu);
4266
4267         destroy_kvm_mmu(vcpu);
4268         free_mmu_pages(vcpu);
4269         mmu_free_memory_caches(vcpu);
4270 }
4271
4272 void kvm_mmu_module_exit(void)
4273 {
4274         mmu_destroy_caches();
4275         percpu_counter_destroy(&kvm_total_used_mmu_pages);
4276         unregister_shrinker(&mmu_shrinker);
4277         mmu_audit_disable();
4278 }