KVM: Introduce kvm_unmap_hva_range() for kvm_mmu_notifier_invalidate_range_start()
[linux-3.10.git] / arch / x86 / kvm / mmu.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * MMU support
8  *
9  * Copyright (C) 2006 Qumranet, Inc.
10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11  *
12  * Authors:
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Avi Kivity   <avi@qumranet.com>
15  *
16  * This work is licensed under the terms of the GNU GPL, version 2.  See
17  * the COPYING file in the top-level directory.
18  *
19  */
20
21 #include "irq.h"
22 #include "mmu.h"
23 #include "x86.h"
24 #include "kvm_cache_regs.h"
25
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
29 #include <linux/mm.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
38
39 #include <asm/page.h>
40 #include <asm/cmpxchg.h>
41 #include <asm/io.h>
42 #include <asm/vmx.h>
43
44 /*
45  * When setting this variable to true it enables Two-Dimensional-Paging
46  * where the hardware walks 2 page tables:
47  * 1. the guest-virtual to guest-physical
48  * 2. while doing 1. it walks guest-physical to host-physical
49  * If the hardware supports that we don't need to do shadow paging.
50  */
51 bool tdp_enabled = false;
52
53 enum {
54         AUDIT_PRE_PAGE_FAULT,
55         AUDIT_POST_PAGE_FAULT,
56         AUDIT_PRE_PTE_WRITE,
57         AUDIT_POST_PTE_WRITE,
58         AUDIT_PRE_SYNC,
59         AUDIT_POST_SYNC
60 };
61
62 #undef MMU_DEBUG
63
64 #ifdef MMU_DEBUG
65
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
68
69 #else
70
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
73
74 #endif
75
76 #ifdef MMU_DEBUG
77 static bool dbg = 0;
78 module_param(dbg, bool, 0644);
79 #endif
80
81 #ifndef MMU_DEBUG
82 #define ASSERT(x) do { } while (0)
83 #else
84 #define ASSERT(x)                                                       \
85         if (!(x)) {                                                     \
86                 printk(KERN_WARNING "assertion failed %s:%d: %s\n",     \
87                        __FILE__, __LINE__, #x);                         \
88         }
89 #endif
90
91 #define PTE_PREFETCH_NUM                8
92
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
95
96 #define PT64_LEVEL_BITS 9
97
98 #define PT64_LEVEL_SHIFT(level) \
99                 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
100
101 #define PT64_INDEX(address, level)\
102         (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
103
104
105 #define PT32_LEVEL_BITS 10
106
107 #define PT32_LEVEL_SHIFT(level) \
108                 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
109
110 #define PT32_LVL_OFFSET_MASK(level) \
111         (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112                                                 * PT32_LEVEL_BITS))) - 1))
113
114 #define PT32_INDEX(address, level)\
115         (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
116
117
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123                                                 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125         (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126                                                 * PT64_LEVEL_BITS))) - 1))
127
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133                                             * PT32_LEVEL_BITS))) - 1))
134
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
136                         | PT64_NX_MASK)
137
138 #define ACC_EXEC_MASK    1
139 #define ACC_WRITE_MASK   PT_WRITABLE_MASK
140 #define ACC_USER_MASK    PT_USER_MASK
141 #define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
142
143 #include <trace/events/kvm.h>
144
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
147
148 #define SPTE_HOST_WRITEABLE     (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE      (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
150
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
152
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
155
156 struct pte_list_desc {
157         u64 *sptes[PTE_LIST_EXT];
158         struct pte_list_desc *more;
159 };
160
161 struct kvm_shadow_walk_iterator {
162         u64 addr;
163         hpa_t shadow_addr;
164         u64 *sptep;
165         int level;
166         unsigned index;
167 };
168
169 #define for_each_shadow_entry(_vcpu, _addr, _walker)    \
170         for (shadow_walk_init(&(_walker), _vcpu, _addr);        \
171              shadow_walk_okay(&(_walker));                      \
172              shadow_walk_next(&(_walker)))
173
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte)     \
175         for (shadow_walk_init(&(_walker), _vcpu, _addr);                \
176              shadow_walk_okay(&(_walker)) &&                            \
177                 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; });  \
178              __shadow_walk_next(&(_walker), spte))
179
180 static struct kmem_cache *pte_list_desc_cache;
181 static struct kmem_cache *mmu_page_header_cache;
182 static struct percpu_counter kvm_total_used_mmu_pages;
183
184 static u64 __read_mostly shadow_nx_mask;
185 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask;
187 static u64 __read_mostly shadow_accessed_mask;
188 static u64 __read_mostly shadow_dirty_mask;
189 static u64 __read_mostly shadow_mmio_mask;
190
191 static void mmu_spte_set(u64 *sptep, u64 spte);
192 static void mmu_free_roots(struct kvm_vcpu *vcpu);
193
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
195 {
196         shadow_mmio_mask = mmio_mask;
197 }
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
199
200 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
201 {
202         access &= ACC_WRITE_MASK | ACC_USER_MASK;
203
204         trace_mark_mmio_spte(sptep, gfn, access);
205         mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
206 }
207
208 static bool is_mmio_spte(u64 spte)
209 {
210         return (spte & shadow_mmio_mask) == shadow_mmio_mask;
211 }
212
213 static gfn_t get_mmio_spte_gfn(u64 spte)
214 {
215         return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
216 }
217
218 static unsigned get_mmio_spte_access(u64 spte)
219 {
220         return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
221 }
222
223 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
224 {
225         if (unlikely(is_noslot_pfn(pfn))) {
226                 mark_mmio_spte(sptep, gfn, access);
227                 return true;
228         }
229
230         return false;
231 }
232
233 static inline u64 rsvd_bits(int s, int e)
234 {
235         return ((1ULL << (e - s + 1)) - 1) << s;
236 }
237
238 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
239                 u64 dirty_mask, u64 nx_mask, u64 x_mask)
240 {
241         shadow_user_mask = user_mask;
242         shadow_accessed_mask = accessed_mask;
243         shadow_dirty_mask = dirty_mask;
244         shadow_nx_mask = nx_mask;
245         shadow_x_mask = x_mask;
246 }
247 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
248
249 static int is_cpuid_PSE36(void)
250 {
251         return 1;
252 }
253
254 static int is_nx(struct kvm_vcpu *vcpu)
255 {
256         return vcpu->arch.efer & EFER_NX;
257 }
258
259 static int is_shadow_present_pte(u64 pte)
260 {
261         return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
262 }
263
264 static int is_large_pte(u64 pte)
265 {
266         return pte & PT_PAGE_SIZE_MASK;
267 }
268
269 static int is_dirty_gpte(unsigned long pte)
270 {
271         return pte & PT_DIRTY_MASK;
272 }
273
274 static int is_rmap_spte(u64 pte)
275 {
276         return is_shadow_present_pte(pte);
277 }
278
279 static int is_last_spte(u64 pte, int level)
280 {
281         if (level == PT_PAGE_TABLE_LEVEL)
282                 return 1;
283         if (is_large_pte(pte))
284                 return 1;
285         return 0;
286 }
287
288 static pfn_t spte_to_pfn(u64 pte)
289 {
290         return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
291 }
292
293 static gfn_t pse36_gfn_delta(u32 gpte)
294 {
295         int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
296
297         return (gpte & PT32_DIR_PSE36_MASK) << shift;
298 }
299
300 #ifdef CONFIG_X86_64
301 static void __set_spte(u64 *sptep, u64 spte)
302 {
303         *sptep = spte;
304 }
305
306 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
307 {
308         *sptep = spte;
309 }
310
311 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
312 {
313         return xchg(sptep, spte);
314 }
315
316 static u64 __get_spte_lockless(u64 *sptep)
317 {
318         return ACCESS_ONCE(*sptep);
319 }
320
321 static bool __check_direct_spte_mmio_pf(u64 spte)
322 {
323         /* It is valid if the spte is zapped. */
324         return spte == 0ull;
325 }
326 #else
327 union split_spte {
328         struct {
329                 u32 spte_low;
330                 u32 spte_high;
331         };
332         u64 spte;
333 };
334
335 static void count_spte_clear(u64 *sptep, u64 spte)
336 {
337         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
338
339         if (is_shadow_present_pte(spte))
340                 return;
341
342         /* Ensure the spte is completely set before we increase the count */
343         smp_wmb();
344         sp->clear_spte_count++;
345 }
346
347 static void __set_spte(u64 *sptep, u64 spte)
348 {
349         union split_spte *ssptep, sspte;
350
351         ssptep = (union split_spte *)sptep;
352         sspte = (union split_spte)spte;
353
354         ssptep->spte_high = sspte.spte_high;
355
356         /*
357          * If we map the spte from nonpresent to present, We should store
358          * the high bits firstly, then set present bit, so cpu can not
359          * fetch this spte while we are setting the spte.
360          */
361         smp_wmb();
362
363         ssptep->spte_low = sspte.spte_low;
364 }
365
366 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
367 {
368         union split_spte *ssptep, sspte;
369
370         ssptep = (union split_spte *)sptep;
371         sspte = (union split_spte)spte;
372
373         ssptep->spte_low = sspte.spte_low;
374
375         /*
376          * If we map the spte from present to nonpresent, we should clear
377          * present bit firstly to avoid vcpu fetch the old high bits.
378          */
379         smp_wmb();
380
381         ssptep->spte_high = sspte.spte_high;
382         count_spte_clear(sptep, spte);
383 }
384
385 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
386 {
387         union split_spte *ssptep, sspte, orig;
388
389         ssptep = (union split_spte *)sptep;
390         sspte = (union split_spte)spte;
391
392         /* xchg acts as a barrier before the setting of the high bits */
393         orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
394         orig.spte_high = ssptep->spte_high;
395         ssptep->spte_high = sspte.spte_high;
396         count_spte_clear(sptep, spte);
397
398         return orig.spte;
399 }
400
401 /*
402  * The idea using the light way get the spte on x86_32 guest is from
403  * gup_get_pte(arch/x86/mm/gup.c).
404  * The difference is we can not catch the spte tlb flush if we leave
405  * guest mode, so we emulate it by increase clear_spte_count when spte
406  * is cleared.
407  */
408 static u64 __get_spte_lockless(u64 *sptep)
409 {
410         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
411         union split_spte spte, *orig = (union split_spte *)sptep;
412         int count;
413
414 retry:
415         count = sp->clear_spte_count;
416         smp_rmb();
417
418         spte.spte_low = orig->spte_low;
419         smp_rmb();
420
421         spte.spte_high = orig->spte_high;
422         smp_rmb();
423
424         if (unlikely(spte.spte_low != orig->spte_low ||
425               count != sp->clear_spte_count))
426                 goto retry;
427
428         return spte.spte;
429 }
430
431 static bool __check_direct_spte_mmio_pf(u64 spte)
432 {
433         union split_spte sspte = (union split_spte)spte;
434         u32 high_mmio_mask = shadow_mmio_mask >> 32;
435
436         /* It is valid if the spte is zapped. */
437         if (spte == 0ull)
438                 return true;
439
440         /* It is valid if the spte is being zapped. */
441         if (sspte.spte_low == 0ull &&
442             (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
443                 return true;
444
445         return false;
446 }
447 #endif
448
449 static bool spte_is_locklessly_modifiable(u64 spte)
450 {
451         return !(~spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE));
452 }
453
454 static bool spte_has_volatile_bits(u64 spte)
455 {
456         /*
457          * Always atomicly update spte if it can be updated
458          * out of mmu-lock, it can ensure dirty bit is not lost,
459          * also, it can help us to get a stable is_writable_pte()
460          * to ensure tlb flush is not missed.
461          */
462         if (spte_is_locklessly_modifiable(spte))
463                 return true;
464
465         if (!shadow_accessed_mask)
466                 return false;
467
468         if (!is_shadow_present_pte(spte))
469                 return false;
470
471         if ((spte & shadow_accessed_mask) &&
472               (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
473                 return false;
474
475         return true;
476 }
477
478 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
479 {
480         return (old_spte & bit_mask) && !(new_spte & bit_mask);
481 }
482
483 /* Rules for using mmu_spte_set:
484  * Set the sptep from nonpresent to present.
485  * Note: the sptep being assigned *must* be either not present
486  * or in a state where the hardware will not attempt to update
487  * the spte.
488  */
489 static void mmu_spte_set(u64 *sptep, u64 new_spte)
490 {
491         WARN_ON(is_shadow_present_pte(*sptep));
492         __set_spte(sptep, new_spte);
493 }
494
495 /* Rules for using mmu_spte_update:
496  * Update the state bits, it means the mapped pfn is not changged.
497  *
498  * Whenever we overwrite a writable spte with a read-only one we
499  * should flush remote TLBs. Otherwise rmap_write_protect
500  * will find a read-only spte, even though the writable spte
501  * might be cached on a CPU's TLB, the return value indicates this
502  * case.
503  */
504 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
505 {
506         u64 old_spte = *sptep;
507         bool ret = false;
508
509         WARN_ON(!is_rmap_spte(new_spte));
510
511         if (!is_shadow_present_pte(old_spte)) {
512                 mmu_spte_set(sptep, new_spte);
513                 return ret;
514         }
515
516         if (!spte_has_volatile_bits(old_spte))
517                 __update_clear_spte_fast(sptep, new_spte);
518         else
519                 old_spte = __update_clear_spte_slow(sptep, new_spte);
520
521         /*
522          * For the spte updated out of mmu-lock is safe, since
523          * we always atomicly update it, see the comments in
524          * spte_has_volatile_bits().
525          */
526         if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
527                 ret = true;
528
529         if (!shadow_accessed_mask)
530                 return ret;
531
532         if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
533                 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
534         if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
535                 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
536
537         return ret;
538 }
539
540 /*
541  * Rules for using mmu_spte_clear_track_bits:
542  * It sets the sptep from present to nonpresent, and track the
543  * state bits, it is used to clear the last level sptep.
544  */
545 static int mmu_spte_clear_track_bits(u64 *sptep)
546 {
547         pfn_t pfn;
548         u64 old_spte = *sptep;
549
550         if (!spte_has_volatile_bits(old_spte))
551                 __update_clear_spte_fast(sptep, 0ull);
552         else
553                 old_spte = __update_clear_spte_slow(sptep, 0ull);
554
555         if (!is_rmap_spte(old_spte))
556                 return 0;
557
558         pfn = spte_to_pfn(old_spte);
559         if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
560                 kvm_set_pfn_accessed(pfn);
561         if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
562                 kvm_set_pfn_dirty(pfn);
563         return 1;
564 }
565
566 /*
567  * Rules for using mmu_spte_clear_no_track:
568  * Directly clear spte without caring the state bits of sptep,
569  * it is used to set the upper level spte.
570  */
571 static void mmu_spte_clear_no_track(u64 *sptep)
572 {
573         __update_clear_spte_fast(sptep, 0ull);
574 }
575
576 static u64 mmu_spte_get_lockless(u64 *sptep)
577 {
578         return __get_spte_lockless(sptep);
579 }
580
581 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
582 {
583         /*
584          * Prevent page table teardown by making any free-er wait during
585          * kvm_flush_remote_tlbs() IPI to all active vcpus.
586          */
587         local_irq_disable();
588         vcpu->mode = READING_SHADOW_PAGE_TABLES;
589         /*
590          * Make sure a following spte read is not reordered ahead of the write
591          * to vcpu->mode.
592          */
593         smp_mb();
594 }
595
596 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
597 {
598         /*
599          * Make sure the write to vcpu->mode is not reordered in front of
600          * reads to sptes.  If it does, kvm_commit_zap_page() can see us
601          * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
602          */
603         smp_mb();
604         vcpu->mode = OUTSIDE_GUEST_MODE;
605         local_irq_enable();
606 }
607
608 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
609                                   struct kmem_cache *base_cache, int min)
610 {
611         void *obj;
612
613         if (cache->nobjs >= min)
614                 return 0;
615         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
616                 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
617                 if (!obj)
618                         return -ENOMEM;
619                 cache->objects[cache->nobjs++] = obj;
620         }
621         return 0;
622 }
623
624 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
625 {
626         return cache->nobjs;
627 }
628
629 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
630                                   struct kmem_cache *cache)
631 {
632         while (mc->nobjs)
633                 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
634 }
635
636 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
637                                        int min)
638 {
639         void *page;
640
641         if (cache->nobjs >= min)
642                 return 0;
643         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
644                 page = (void *)__get_free_page(GFP_KERNEL);
645                 if (!page)
646                         return -ENOMEM;
647                 cache->objects[cache->nobjs++] = page;
648         }
649         return 0;
650 }
651
652 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
653 {
654         while (mc->nobjs)
655                 free_page((unsigned long)mc->objects[--mc->nobjs]);
656 }
657
658 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
659 {
660         int r;
661
662         r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
663                                    pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
664         if (r)
665                 goto out;
666         r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
667         if (r)
668                 goto out;
669         r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
670                                    mmu_page_header_cache, 4);
671 out:
672         return r;
673 }
674
675 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
676 {
677         mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
678                                 pte_list_desc_cache);
679         mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
680         mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
681                                 mmu_page_header_cache);
682 }
683
684 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
685 {
686         void *p;
687
688         BUG_ON(!mc->nobjs);
689         p = mc->objects[--mc->nobjs];
690         return p;
691 }
692
693 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
694 {
695         return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
696 }
697
698 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
699 {
700         kmem_cache_free(pte_list_desc_cache, pte_list_desc);
701 }
702
703 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
704 {
705         if (!sp->role.direct)
706                 return sp->gfns[index];
707
708         return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
709 }
710
711 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
712 {
713         if (sp->role.direct)
714                 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
715         else
716                 sp->gfns[index] = gfn;
717 }
718
719 /*
720  * Return the pointer to the large page information for a given gfn,
721  * handling slots that are not large page aligned.
722  */
723 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
724                                               struct kvm_memory_slot *slot,
725                                               int level)
726 {
727         unsigned long idx;
728
729         idx = gfn_to_index(gfn, slot->base_gfn, level);
730         return &slot->arch.lpage_info[level - 2][idx];
731 }
732
733 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
734 {
735         struct kvm_memory_slot *slot;
736         struct kvm_lpage_info *linfo;
737         int i;
738
739         slot = gfn_to_memslot(kvm, gfn);
740         for (i = PT_DIRECTORY_LEVEL;
741              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
742                 linfo = lpage_info_slot(gfn, slot, i);
743                 linfo->write_count += 1;
744         }
745         kvm->arch.indirect_shadow_pages++;
746 }
747
748 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
749 {
750         struct kvm_memory_slot *slot;
751         struct kvm_lpage_info *linfo;
752         int i;
753
754         slot = gfn_to_memslot(kvm, gfn);
755         for (i = PT_DIRECTORY_LEVEL;
756              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
757                 linfo = lpage_info_slot(gfn, slot, i);
758                 linfo->write_count -= 1;
759                 WARN_ON(linfo->write_count < 0);
760         }
761         kvm->arch.indirect_shadow_pages--;
762 }
763
764 static int has_wrprotected_page(struct kvm *kvm,
765                                 gfn_t gfn,
766                                 int level)
767 {
768         struct kvm_memory_slot *slot;
769         struct kvm_lpage_info *linfo;
770
771         slot = gfn_to_memslot(kvm, gfn);
772         if (slot) {
773                 linfo = lpage_info_slot(gfn, slot, level);
774                 return linfo->write_count;
775         }
776
777         return 1;
778 }
779
780 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
781 {
782         unsigned long page_size;
783         int i, ret = 0;
784
785         page_size = kvm_host_page_size(kvm, gfn);
786
787         for (i = PT_PAGE_TABLE_LEVEL;
788              i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
789                 if (page_size >= KVM_HPAGE_SIZE(i))
790                         ret = i;
791                 else
792                         break;
793         }
794
795         return ret;
796 }
797
798 static struct kvm_memory_slot *
799 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
800                             bool no_dirty_log)
801 {
802         struct kvm_memory_slot *slot;
803
804         slot = gfn_to_memslot(vcpu->kvm, gfn);
805         if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
806               (no_dirty_log && slot->dirty_bitmap))
807                 slot = NULL;
808
809         return slot;
810 }
811
812 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
813 {
814         return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
815 }
816
817 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
818 {
819         int host_level, level, max_level;
820
821         host_level = host_mapping_level(vcpu->kvm, large_gfn);
822
823         if (host_level == PT_PAGE_TABLE_LEVEL)
824                 return host_level;
825
826         max_level = kvm_x86_ops->get_lpage_level() < host_level ?
827                 kvm_x86_ops->get_lpage_level() : host_level;
828
829         for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
830                 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
831                         break;
832
833         return level - 1;
834 }
835
836 /*
837  * Pte mapping structures:
838  *
839  * If pte_list bit zero is zero, then pte_list point to the spte.
840  *
841  * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
842  * pte_list_desc containing more mappings.
843  *
844  * Returns the number of pte entries before the spte was added or zero if
845  * the spte was not added.
846  *
847  */
848 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
849                         unsigned long *pte_list)
850 {
851         struct pte_list_desc *desc;
852         int i, count = 0;
853
854         if (!*pte_list) {
855                 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
856                 *pte_list = (unsigned long)spte;
857         } else if (!(*pte_list & 1)) {
858                 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
859                 desc = mmu_alloc_pte_list_desc(vcpu);
860                 desc->sptes[0] = (u64 *)*pte_list;
861                 desc->sptes[1] = spte;
862                 *pte_list = (unsigned long)desc | 1;
863                 ++count;
864         } else {
865                 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
866                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
867                 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
868                         desc = desc->more;
869                         count += PTE_LIST_EXT;
870                 }
871                 if (desc->sptes[PTE_LIST_EXT-1]) {
872                         desc->more = mmu_alloc_pte_list_desc(vcpu);
873                         desc = desc->more;
874                 }
875                 for (i = 0; desc->sptes[i]; ++i)
876                         ++count;
877                 desc->sptes[i] = spte;
878         }
879         return count;
880 }
881
882 static void
883 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
884                            int i, struct pte_list_desc *prev_desc)
885 {
886         int j;
887
888         for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
889                 ;
890         desc->sptes[i] = desc->sptes[j];
891         desc->sptes[j] = NULL;
892         if (j != 0)
893                 return;
894         if (!prev_desc && !desc->more)
895                 *pte_list = (unsigned long)desc->sptes[0];
896         else
897                 if (prev_desc)
898                         prev_desc->more = desc->more;
899                 else
900                         *pte_list = (unsigned long)desc->more | 1;
901         mmu_free_pte_list_desc(desc);
902 }
903
904 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
905 {
906         struct pte_list_desc *desc;
907         struct pte_list_desc *prev_desc;
908         int i;
909
910         if (!*pte_list) {
911                 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
912                 BUG();
913         } else if (!(*pte_list & 1)) {
914                 rmap_printk("pte_list_remove:  %p 1->0\n", spte);
915                 if ((u64 *)*pte_list != spte) {
916                         printk(KERN_ERR "pte_list_remove:  %p 1->BUG\n", spte);
917                         BUG();
918                 }
919                 *pte_list = 0;
920         } else {
921                 rmap_printk("pte_list_remove:  %p many->many\n", spte);
922                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
923                 prev_desc = NULL;
924                 while (desc) {
925                         for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
926                                 if (desc->sptes[i] == spte) {
927                                         pte_list_desc_remove_entry(pte_list,
928                                                                desc, i,
929                                                                prev_desc);
930                                         return;
931                                 }
932                         prev_desc = desc;
933                         desc = desc->more;
934                 }
935                 pr_err("pte_list_remove: %p many->many\n", spte);
936                 BUG();
937         }
938 }
939
940 typedef void (*pte_list_walk_fn) (u64 *spte);
941 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
942 {
943         struct pte_list_desc *desc;
944         int i;
945
946         if (!*pte_list)
947                 return;
948
949         if (!(*pte_list & 1))
950                 return fn((u64 *)*pte_list);
951
952         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
953         while (desc) {
954                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
955                         fn(desc->sptes[i]);
956                 desc = desc->more;
957         }
958 }
959
960 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
961                                     struct kvm_memory_slot *slot)
962 {
963         struct kvm_lpage_info *linfo;
964
965         if (likely(level == PT_PAGE_TABLE_LEVEL))
966                 return &slot->rmap[gfn - slot->base_gfn];
967
968         linfo = lpage_info_slot(gfn, slot, level);
969         return &linfo->rmap_pde;
970 }
971
972 /*
973  * Take gfn and return the reverse mapping to it.
974  */
975 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
976 {
977         struct kvm_memory_slot *slot;
978
979         slot = gfn_to_memslot(kvm, gfn);
980         return __gfn_to_rmap(gfn, level, slot);
981 }
982
983 static bool rmap_can_add(struct kvm_vcpu *vcpu)
984 {
985         struct kvm_mmu_memory_cache *cache;
986
987         cache = &vcpu->arch.mmu_pte_list_desc_cache;
988         return mmu_memory_cache_free_objects(cache);
989 }
990
991 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
992 {
993         struct kvm_mmu_page *sp;
994         unsigned long *rmapp;
995
996         sp = page_header(__pa(spte));
997         kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
998         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
999         return pte_list_add(vcpu, spte, rmapp);
1000 }
1001
1002 static void rmap_remove(struct kvm *kvm, u64 *spte)
1003 {
1004         struct kvm_mmu_page *sp;
1005         gfn_t gfn;
1006         unsigned long *rmapp;
1007
1008         sp = page_header(__pa(spte));
1009         gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1010         rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1011         pte_list_remove(spte, rmapp);
1012 }
1013
1014 /*
1015  * Used by the following functions to iterate through the sptes linked by a
1016  * rmap.  All fields are private and not assumed to be used outside.
1017  */
1018 struct rmap_iterator {
1019         /* private fields */
1020         struct pte_list_desc *desc;     /* holds the sptep if not NULL */
1021         int pos;                        /* index of the sptep */
1022 };
1023
1024 /*
1025  * Iteration must be started by this function.  This should also be used after
1026  * removing/dropping sptes from the rmap link because in such cases the
1027  * information in the itererator may not be valid.
1028  *
1029  * Returns sptep if found, NULL otherwise.
1030  */
1031 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1032 {
1033         if (!rmap)
1034                 return NULL;
1035
1036         if (!(rmap & 1)) {
1037                 iter->desc = NULL;
1038                 return (u64 *)rmap;
1039         }
1040
1041         iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1042         iter->pos = 0;
1043         return iter->desc->sptes[iter->pos];
1044 }
1045
1046 /*
1047  * Must be used with a valid iterator: e.g. after rmap_get_first().
1048  *
1049  * Returns sptep if found, NULL otherwise.
1050  */
1051 static u64 *rmap_get_next(struct rmap_iterator *iter)
1052 {
1053         if (iter->desc) {
1054                 if (iter->pos < PTE_LIST_EXT - 1) {
1055                         u64 *sptep;
1056
1057                         ++iter->pos;
1058                         sptep = iter->desc->sptes[iter->pos];
1059                         if (sptep)
1060                                 return sptep;
1061                 }
1062
1063                 iter->desc = iter->desc->more;
1064
1065                 if (iter->desc) {
1066                         iter->pos = 0;
1067                         /* desc->sptes[0] cannot be NULL */
1068                         return iter->desc->sptes[iter->pos];
1069                 }
1070         }
1071
1072         return NULL;
1073 }
1074
1075 static void drop_spte(struct kvm *kvm, u64 *sptep)
1076 {
1077         if (mmu_spte_clear_track_bits(sptep))
1078                 rmap_remove(kvm, sptep);
1079 }
1080
1081
1082 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1083 {
1084         if (is_large_pte(*sptep)) {
1085                 WARN_ON(page_header(__pa(sptep))->role.level ==
1086                         PT_PAGE_TABLE_LEVEL);
1087                 drop_spte(kvm, sptep);
1088                 --kvm->stat.lpages;
1089                 return true;
1090         }
1091
1092         return false;
1093 }
1094
1095 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1096 {
1097         if (__drop_large_spte(vcpu->kvm, sptep))
1098                 kvm_flush_remote_tlbs(vcpu->kvm);
1099 }
1100
1101 /*
1102  * Write-protect on the specified @sptep, @pt_protect indicates whether
1103  * spte writ-protection is caused by protecting shadow page table.
1104  * @flush indicates whether tlb need be flushed.
1105  *
1106  * Note: write protection is difference between drity logging and spte
1107  * protection:
1108  * - for dirty logging, the spte can be set to writable at anytime if
1109  *   its dirty bitmap is properly set.
1110  * - for spte protection, the spte can be writable only after unsync-ing
1111  *   shadow page.
1112  *
1113  * Return true if the spte is dropped.
1114  */
1115 static bool
1116 spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect)
1117 {
1118         u64 spte = *sptep;
1119
1120         if (!is_writable_pte(spte) &&
1121               !(pt_protect && spte_is_locklessly_modifiable(spte)))
1122                 return false;
1123
1124         rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1125
1126         if (__drop_large_spte(kvm, sptep)) {
1127                 *flush |= true;
1128                 return true;
1129         }
1130
1131         if (pt_protect)
1132                 spte &= ~SPTE_MMU_WRITEABLE;
1133         spte = spte & ~PT_WRITABLE_MASK;
1134
1135         *flush |= mmu_spte_update(sptep, spte);
1136         return false;
1137 }
1138
1139 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1140                                  int level, bool pt_protect)
1141 {
1142         u64 *sptep;
1143         struct rmap_iterator iter;
1144         bool flush = false;
1145
1146         for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1147                 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1148                 if (spte_write_protect(kvm, sptep, &flush, pt_protect)) {
1149                         sptep = rmap_get_first(*rmapp, &iter);
1150                         continue;
1151                 }
1152
1153                 sptep = rmap_get_next(&iter);
1154         }
1155
1156         return flush;
1157 }
1158
1159 /**
1160  * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1161  * @kvm: kvm instance
1162  * @slot: slot to protect
1163  * @gfn_offset: start of the BITS_PER_LONG pages we care about
1164  * @mask: indicates which pages we should protect
1165  *
1166  * Used when we do not need to care about huge page mappings: e.g. during dirty
1167  * logging we do not have any such mappings.
1168  */
1169 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1170                                      struct kvm_memory_slot *slot,
1171                                      gfn_t gfn_offset, unsigned long mask)
1172 {
1173         unsigned long *rmapp;
1174
1175         while (mask) {
1176                 rmapp = &slot->rmap[gfn_offset + __ffs(mask)];
1177                 __rmap_write_protect(kvm, rmapp, PT_PAGE_TABLE_LEVEL, false);
1178
1179                 /* clear the first set bit */
1180                 mask &= mask - 1;
1181         }
1182 }
1183
1184 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1185 {
1186         struct kvm_memory_slot *slot;
1187         unsigned long *rmapp;
1188         int i;
1189         bool write_protected = false;
1190
1191         slot = gfn_to_memslot(kvm, gfn);
1192
1193         for (i = PT_PAGE_TABLE_LEVEL;
1194              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1195                 rmapp = __gfn_to_rmap(gfn, i, slot);
1196                 write_protected |= __rmap_write_protect(kvm, rmapp, i, true);
1197         }
1198
1199         return write_protected;
1200 }
1201
1202 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1203                            unsigned long data)
1204 {
1205         u64 *sptep;
1206         struct rmap_iterator iter;
1207         int need_tlb_flush = 0;
1208
1209         while ((sptep = rmap_get_first(*rmapp, &iter))) {
1210                 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1211                 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1212
1213                 drop_spte(kvm, sptep);
1214                 need_tlb_flush = 1;
1215         }
1216
1217         return need_tlb_flush;
1218 }
1219
1220 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1221                              unsigned long data)
1222 {
1223         u64 *sptep;
1224         struct rmap_iterator iter;
1225         int need_flush = 0;
1226         u64 new_spte;
1227         pte_t *ptep = (pte_t *)data;
1228         pfn_t new_pfn;
1229
1230         WARN_ON(pte_huge(*ptep));
1231         new_pfn = pte_pfn(*ptep);
1232
1233         for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1234                 BUG_ON(!is_shadow_present_pte(*sptep));
1235                 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1236
1237                 need_flush = 1;
1238
1239                 if (pte_write(*ptep)) {
1240                         drop_spte(kvm, sptep);
1241                         sptep = rmap_get_first(*rmapp, &iter);
1242                 } else {
1243                         new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1244                         new_spte |= (u64)new_pfn << PAGE_SHIFT;
1245
1246                         new_spte &= ~PT_WRITABLE_MASK;
1247                         new_spte &= ~SPTE_HOST_WRITEABLE;
1248                         new_spte &= ~shadow_accessed_mask;
1249
1250                         mmu_spte_clear_track_bits(sptep);
1251                         mmu_spte_set(sptep, new_spte);
1252                         sptep = rmap_get_next(&iter);
1253                 }
1254         }
1255
1256         if (need_flush)
1257                 kvm_flush_remote_tlbs(kvm);
1258
1259         return 0;
1260 }
1261
1262 static int kvm_handle_hva_range(struct kvm *kvm,
1263                                 unsigned long start,
1264                                 unsigned long end,
1265                                 unsigned long data,
1266                                 int (*handler)(struct kvm *kvm,
1267                                                unsigned long *rmapp,
1268                                                unsigned long data))
1269 {
1270         int j;
1271         int ret;
1272         int retval = 0;
1273         struct kvm_memslots *slots;
1274         struct kvm_memory_slot *memslot;
1275
1276         slots = kvm_memslots(kvm);
1277
1278         kvm_for_each_memslot(memslot, slots) {
1279                 unsigned long hva_start, hva_end;
1280                 gfn_t gfn, gfn_end;
1281
1282                 hva_start = max(start, memslot->userspace_addr);
1283                 hva_end = min(end, memslot->userspace_addr +
1284                                         (memslot->npages << PAGE_SHIFT));
1285                 if (hva_start >= hva_end)
1286                         continue;
1287                 /*
1288                  * {gfn(page) | page intersects with [hva_start, hva_end)} =
1289                  * {gfn, gfn+1, ..., gfn_end-1}.
1290                  */
1291                 gfn = hva_to_gfn_memslot(hva_start, memslot);
1292                 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1293
1294                 for (; gfn < gfn_end; ++gfn) {
1295                         ret = 0;
1296
1297                         for (j = PT_PAGE_TABLE_LEVEL;
1298                              j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1299                                 unsigned long *rmapp;
1300
1301                                 rmapp = __gfn_to_rmap(gfn, j, memslot);
1302                                 ret |= handler(kvm, rmapp, data);
1303                         }
1304                         trace_kvm_age_page(memslot->userspace_addr +
1305                                         (gfn - memslot->base_gfn) * PAGE_SIZE,
1306                                         memslot, ret);
1307                         retval |= ret;
1308                 }
1309         }
1310
1311         return retval;
1312 }
1313
1314 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1315                           unsigned long data,
1316                           int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1317                                          unsigned long data))
1318 {
1319         return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1320 }
1321
1322 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1323 {
1324         return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1325 }
1326
1327 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1328 {
1329         return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1330 }
1331
1332 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1333 {
1334         kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1335 }
1336
1337 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1338                          unsigned long data)
1339 {
1340         u64 *sptep;
1341         struct rmap_iterator uninitialized_var(iter);
1342         int young = 0;
1343
1344         /*
1345          * In case of absence of EPT Access and Dirty Bits supports,
1346          * emulate the accessed bit for EPT, by checking if this page has
1347          * an EPT mapping, and clearing it if it does. On the next access,
1348          * a new EPT mapping will be established.
1349          * This has some overhead, but not as much as the cost of swapping
1350          * out actively used pages or breaking up actively used hugepages.
1351          */
1352         if (!shadow_accessed_mask)
1353                 return kvm_unmap_rmapp(kvm, rmapp, data);
1354
1355         for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1356              sptep = rmap_get_next(&iter)) {
1357                 BUG_ON(!is_shadow_present_pte(*sptep));
1358
1359                 if (*sptep & shadow_accessed_mask) {
1360                         young = 1;
1361                         clear_bit((ffs(shadow_accessed_mask) - 1),
1362                                  (unsigned long *)sptep);
1363                 }
1364         }
1365
1366         return young;
1367 }
1368
1369 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1370                               unsigned long data)
1371 {
1372         u64 *sptep;
1373         struct rmap_iterator iter;
1374         int young = 0;
1375
1376         /*
1377          * If there's no access bit in the secondary pte set by the
1378          * hardware it's up to gup-fast/gup to set the access bit in
1379          * the primary pte or in the page structure.
1380          */
1381         if (!shadow_accessed_mask)
1382                 goto out;
1383
1384         for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1385              sptep = rmap_get_next(&iter)) {
1386                 BUG_ON(!is_shadow_present_pte(*sptep));
1387
1388                 if (*sptep & shadow_accessed_mask) {
1389                         young = 1;
1390                         break;
1391                 }
1392         }
1393 out:
1394         return young;
1395 }
1396
1397 #define RMAP_RECYCLE_THRESHOLD 1000
1398
1399 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1400 {
1401         unsigned long *rmapp;
1402         struct kvm_mmu_page *sp;
1403
1404         sp = page_header(__pa(spte));
1405
1406         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1407
1408         kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
1409         kvm_flush_remote_tlbs(vcpu->kvm);
1410 }
1411
1412 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1413 {
1414         return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
1415 }
1416
1417 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1418 {
1419         return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1420 }
1421
1422 #ifdef MMU_DEBUG
1423 static int is_empty_shadow_page(u64 *spt)
1424 {
1425         u64 *pos;
1426         u64 *end;
1427
1428         for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1429                 if (is_shadow_present_pte(*pos)) {
1430                         printk(KERN_ERR "%s: %p %llx\n", __func__,
1431                                pos, *pos);
1432                         return 0;
1433                 }
1434         return 1;
1435 }
1436 #endif
1437
1438 /*
1439  * This value is the sum of all of the kvm instances's
1440  * kvm->arch.n_used_mmu_pages values.  We need a global,
1441  * aggregate version in order to make the slab shrinker
1442  * faster
1443  */
1444 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1445 {
1446         kvm->arch.n_used_mmu_pages += nr;
1447         percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1448 }
1449
1450 /*
1451  * Remove the sp from shadow page cache, after call it,
1452  * we can not find this sp from the cache, and the shadow
1453  * page table is still valid.
1454  * It should be under the protection of mmu lock.
1455  */
1456 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1457 {
1458         ASSERT(is_empty_shadow_page(sp->spt));
1459         hlist_del(&sp->hash_link);
1460         if (!sp->role.direct)
1461                 free_page((unsigned long)sp->gfns);
1462 }
1463
1464 /*
1465  * Free the shadow page table and the sp, we can do it
1466  * out of the protection of mmu lock.
1467  */
1468 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1469 {
1470         list_del(&sp->link);
1471         free_page((unsigned long)sp->spt);
1472         kmem_cache_free(mmu_page_header_cache, sp);
1473 }
1474
1475 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1476 {
1477         return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1478 }
1479
1480 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1481                                     struct kvm_mmu_page *sp, u64 *parent_pte)
1482 {
1483         if (!parent_pte)
1484                 return;
1485
1486         pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1487 }
1488
1489 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1490                                        u64 *parent_pte)
1491 {
1492         pte_list_remove(parent_pte, &sp->parent_ptes);
1493 }
1494
1495 static void drop_parent_pte(struct kvm_mmu_page *sp,
1496                             u64 *parent_pte)
1497 {
1498         mmu_page_remove_parent_pte(sp, parent_pte);
1499         mmu_spte_clear_no_track(parent_pte);
1500 }
1501
1502 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1503                                                u64 *parent_pte, int direct)
1504 {
1505         struct kvm_mmu_page *sp;
1506         sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1507         sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1508         if (!direct)
1509                 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1510         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1511         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1512         bitmap_zero(sp->slot_bitmap, KVM_MEM_SLOTS_NUM);
1513         sp->parent_ptes = 0;
1514         mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1515         kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1516         return sp;
1517 }
1518
1519 static void mark_unsync(u64 *spte);
1520 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1521 {
1522         pte_list_walk(&sp->parent_ptes, mark_unsync);
1523 }
1524
1525 static void mark_unsync(u64 *spte)
1526 {
1527         struct kvm_mmu_page *sp;
1528         unsigned int index;
1529
1530         sp = page_header(__pa(spte));
1531         index = spte - sp->spt;
1532         if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1533                 return;
1534         if (sp->unsync_children++)
1535                 return;
1536         kvm_mmu_mark_parents_unsync(sp);
1537 }
1538
1539 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1540                                struct kvm_mmu_page *sp)
1541 {
1542         return 1;
1543 }
1544
1545 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1546 {
1547 }
1548
1549 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1550                                  struct kvm_mmu_page *sp, u64 *spte,
1551                                  const void *pte)
1552 {
1553         WARN_ON(1);
1554 }
1555
1556 #define KVM_PAGE_ARRAY_NR 16
1557
1558 struct kvm_mmu_pages {
1559         struct mmu_page_and_offset {
1560                 struct kvm_mmu_page *sp;
1561                 unsigned int idx;
1562         } page[KVM_PAGE_ARRAY_NR];
1563         unsigned int nr;
1564 };
1565
1566 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1567                          int idx)
1568 {
1569         int i;
1570
1571         if (sp->unsync)
1572                 for (i=0; i < pvec->nr; i++)
1573                         if (pvec->page[i].sp == sp)
1574                                 return 0;
1575
1576         pvec->page[pvec->nr].sp = sp;
1577         pvec->page[pvec->nr].idx = idx;
1578         pvec->nr++;
1579         return (pvec->nr == KVM_PAGE_ARRAY_NR);
1580 }
1581
1582 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1583                            struct kvm_mmu_pages *pvec)
1584 {
1585         int i, ret, nr_unsync_leaf = 0;
1586
1587         for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1588                 struct kvm_mmu_page *child;
1589                 u64 ent = sp->spt[i];
1590
1591                 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1592                         goto clear_child_bitmap;
1593
1594                 child = page_header(ent & PT64_BASE_ADDR_MASK);
1595
1596                 if (child->unsync_children) {
1597                         if (mmu_pages_add(pvec, child, i))
1598                                 return -ENOSPC;
1599
1600                         ret = __mmu_unsync_walk(child, pvec);
1601                         if (!ret)
1602                                 goto clear_child_bitmap;
1603                         else if (ret > 0)
1604                                 nr_unsync_leaf += ret;
1605                         else
1606                                 return ret;
1607                 } else if (child->unsync) {
1608                         nr_unsync_leaf++;
1609                         if (mmu_pages_add(pvec, child, i))
1610                                 return -ENOSPC;
1611                 } else
1612                          goto clear_child_bitmap;
1613
1614                 continue;
1615
1616 clear_child_bitmap:
1617                 __clear_bit(i, sp->unsync_child_bitmap);
1618                 sp->unsync_children--;
1619                 WARN_ON((int)sp->unsync_children < 0);
1620         }
1621
1622
1623         return nr_unsync_leaf;
1624 }
1625
1626 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1627                            struct kvm_mmu_pages *pvec)
1628 {
1629         if (!sp->unsync_children)
1630                 return 0;
1631
1632         mmu_pages_add(pvec, sp, 0);
1633         return __mmu_unsync_walk(sp, pvec);
1634 }
1635
1636 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1637 {
1638         WARN_ON(!sp->unsync);
1639         trace_kvm_mmu_sync_page(sp);
1640         sp->unsync = 0;
1641         --kvm->stat.mmu_unsync;
1642 }
1643
1644 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1645                                     struct list_head *invalid_list);
1646 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1647                                     struct list_head *invalid_list);
1648
1649 #define for_each_gfn_sp(kvm, sp, gfn, pos)                              \
1650   hlist_for_each_entry(sp, pos,                                         \
1651    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1652         if ((sp)->gfn != (gfn)) {} else
1653
1654 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos)               \
1655   hlist_for_each_entry(sp, pos,                                         \
1656    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1657                 if ((sp)->gfn != (gfn) || (sp)->role.direct ||          \
1658                         (sp)->role.invalid) {} else
1659
1660 /* @sp->gfn should be write-protected at the call site */
1661 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1662                            struct list_head *invalid_list, bool clear_unsync)
1663 {
1664         if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1665                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1666                 return 1;
1667         }
1668
1669         if (clear_unsync)
1670                 kvm_unlink_unsync_page(vcpu->kvm, sp);
1671
1672         if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1673                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1674                 return 1;
1675         }
1676
1677         kvm_mmu_flush_tlb(vcpu);
1678         return 0;
1679 }
1680
1681 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1682                                    struct kvm_mmu_page *sp)
1683 {
1684         LIST_HEAD(invalid_list);
1685         int ret;
1686
1687         ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1688         if (ret)
1689                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1690
1691         return ret;
1692 }
1693
1694 #ifdef CONFIG_KVM_MMU_AUDIT
1695 #include "mmu_audit.c"
1696 #else
1697 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1698 static void mmu_audit_disable(void) { }
1699 #endif
1700
1701 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1702                          struct list_head *invalid_list)
1703 {
1704         return __kvm_sync_page(vcpu, sp, invalid_list, true);
1705 }
1706
1707 /* @gfn should be write-protected at the call site */
1708 static void kvm_sync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
1709 {
1710         struct kvm_mmu_page *s;
1711         struct hlist_node *node;
1712         LIST_HEAD(invalid_list);
1713         bool flush = false;
1714
1715         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1716                 if (!s->unsync)
1717                         continue;
1718
1719                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1720                 kvm_unlink_unsync_page(vcpu->kvm, s);
1721                 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1722                         (vcpu->arch.mmu.sync_page(vcpu, s))) {
1723                         kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1724                         continue;
1725                 }
1726                 flush = true;
1727         }
1728
1729         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1730         if (flush)
1731                 kvm_mmu_flush_tlb(vcpu);
1732 }
1733
1734 struct mmu_page_path {
1735         struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1736         unsigned int idx[PT64_ROOT_LEVEL-1];
1737 };
1738
1739 #define for_each_sp(pvec, sp, parents, i)                       \
1740                 for (i = mmu_pages_next(&pvec, &parents, -1),   \
1741                         sp = pvec.page[i].sp;                   \
1742                         i < pvec.nr && ({ sp = pvec.page[i].sp; 1;});   \
1743                         i = mmu_pages_next(&pvec, &parents, i))
1744
1745 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1746                           struct mmu_page_path *parents,
1747                           int i)
1748 {
1749         int n;
1750
1751         for (n = i+1; n < pvec->nr; n++) {
1752                 struct kvm_mmu_page *sp = pvec->page[n].sp;
1753
1754                 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1755                         parents->idx[0] = pvec->page[n].idx;
1756                         return n;
1757                 }
1758
1759                 parents->parent[sp->role.level-2] = sp;
1760                 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1761         }
1762
1763         return n;
1764 }
1765
1766 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1767 {
1768         struct kvm_mmu_page *sp;
1769         unsigned int level = 0;
1770
1771         do {
1772                 unsigned int idx = parents->idx[level];
1773
1774                 sp = parents->parent[level];
1775                 if (!sp)
1776                         return;
1777
1778                 --sp->unsync_children;
1779                 WARN_ON((int)sp->unsync_children < 0);
1780                 __clear_bit(idx, sp->unsync_child_bitmap);
1781                 level++;
1782         } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1783 }
1784
1785 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1786                                struct mmu_page_path *parents,
1787                                struct kvm_mmu_pages *pvec)
1788 {
1789         parents->parent[parent->role.level-1] = NULL;
1790         pvec->nr = 0;
1791 }
1792
1793 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1794                               struct kvm_mmu_page *parent)
1795 {
1796         int i;
1797         struct kvm_mmu_page *sp;
1798         struct mmu_page_path parents;
1799         struct kvm_mmu_pages pages;
1800         LIST_HEAD(invalid_list);
1801
1802         kvm_mmu_pages_init(parent, &parents, &pages);
1803         while (mmu_unsync_walk(parent, &pages)) {
1804                 bool protected = false;
1805
1806                 for_each_sp(pages, sp, parents, i)
1807                         protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1808
1809                 if (protected)
1810                         kvm_flush_remote_tlbs(vcpu->kvm);
1811
1812                 for_each_sp(pages, sp, parents, i) {
1813                         kvm_sync_page(vcpu, sp, &invalid_list);
1814                         mmu_pages_clear_parents(&parents);
1815                 }
1816                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1817                 cond_resched_lock(&vcpu->kvm->mmu_lock);
1818                 kvm_mmu_pages_init(parent, &parents, &pages);
1819         }
1820 }
1821
1822 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1823 {
1824         int i;
1825
1826         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1827                 sp->spt[i] = 0ull;
1828 }
1829
1830 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1831 {
1832         sp->write_flooding_count = 0;
1833 }
1834
1835 static void clear_sp_write_flooding_count(u64 *spte)
1836 {
1837         struct kvm_mmu_page *sp =  page_header(__pa(spte));
1838
1839         __clear_sp_write_flooding_count(sp);
1840 }
1841
1842 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1843                                              gfn_t gfn,
1844                                              gva_t gaddr,
1845                                              unsigned level,
1846                                              int direct,
1847                                              unsigned access,
1848                                              u64 *parent_pte)
1849 {
1850         union kvm_mmu_page_role role;
1851         unsigned quadrant;
1852         struct kvm_mmu_page *sp;
1853         struct hlist_node *node;
1854         bool need_sync = false;
1855
1856         role = vcpu->arch.mmu.base_role;
1857         role.level = level;
1858         role.direct = direct;
1859         if (role.direct)
1860                 role.cr4_pae = 0;
1861         role.access = access;
1862         if (!vcpu->arch.mmu.direct_map
1863             && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1864                 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1865                 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1866                 role.quadrant = quadrant;
1867         }
1868         for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1869                 if (!need_sync && sp->unsync)
1870                         need_sync = true;
1871
1872                 if (sp->role.word != role.word)
1873                         continue;
1874
1875                 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1876                         break;
1877
1878                 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1879                 if (sp->unsync_children) {
1880                         kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1881                         kvm_mmu_mark_parents_unsync(sp);
1882                 } else if (sp->unsync)
1883                         kvm_mmu_mark_parents_unsync(sp);
1884
1885                 __clear_sp_write_flooding_count(sp);
1886                 trace_kvm_mmu_get_page(sp, false);
1887                 return sp;
1888         }
1889         ++vcpu->kvm->stat.mmu_cache_miss;
1890         sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1891         if (!sp)
1892                 return sp;
1893         sp->gfn = gfn;
1894         sp->role = role;
1895         hlist_add_head(&sp->hash_link,
1896                 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1897         if (!direct) {
1898                 if (rmap_write_protect(vcpu->kvm, gfn))
1899                         kvm_flush_remote_tlbs(vcpu->kvm);
1900                 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1901                         kvm_sync_pages(vcpu, gfn);
1902
1903                 account_shadowed(vcpu->kvm, gfn);
1904         }
1905         init_shadow_page_table(sp);
1906         trace_kvm_mmu_get_page(sp, true);
1907         return sp;
1908 }
1909
1910 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1911                              struct kvm_vcpu *vcpu, u64 addr)
1912 {
1913         iterator->addr = addr;
1914         iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1915         iterator->level = vcpu->arch.mmu.shadow_root_level;
1916
1917         if (iterator->level == PT64_ROOT_LEVEL &&
1918             vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1919             !vcpu->arch.mmu.direct_map)
1920                 --iterator->level;
1921
1922         if (iterator->level == PT32E_ROOT_LEVEL) {
1923                 iterator->shadow_addr
1924                         = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1925                 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1926                 --iterator->level;
1927                 if (!iterator->shadow_addr)
1928                         iterator->level = 0;
1929         }
1930 }
1931
1932 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1933 {
1934         if (iterator->level < PT_PAGE_TABLE_LEVEL)
1935                 return false;
1936
1937         iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1938         iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1939         return true;
1940 }
1941
1942 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1943                                u64 spte)
1944 {
1945         if (is_last_spte(spte, iterator->level)) {
1946                 iterator->level = 0;
1947                 return;
1948         }
1949
1950         iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1951         --iterator->level;
1952 }
1953
1954 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1955 {
1956         return __shadow_walk_next(iterator, *iterator->sptep);
1957 }
1958
1959 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1960 {
1961         u64 spte;
1962
1963         spte = __pa(sp->spt)
1964                 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1965                 | PT_WRITABLE_MASK | PT_USER_MASK;
1966         mmu_spte_set(sptep, spte);
1967 }
1968
1969 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1970                                    unsigned direct_access)
1971 {
1972         if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1973                 struct kvm_mmu_page *child;
1974
1975                 /*
1976                  * For the direct sp, if the guest pte's dirty bit
1977                  * changed form clean to dirty, it will corrupt the
1978                  * sp's access: allow writable in the read-only sp,
1979                  * so we should update the spte at this point to get
1980                  * a new sp with the correct access.
1981                  */
1982                 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1983                 if (child->role.access == direct_access)
1984                         return;
1985
1986                 drop_parent_pte(child, sptep);
1987                 kvm_flush_remote_tlbs(vcpu->kvm);
1988         }
1989 }
1990
1991 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1992                              u64 *spte)
1993 {
1994         u64 pte;
1995         struct kvm_mmu_page *child;
1996
1997         pte = *spte;
1998         if (is_shadow_present_pte(pte)) {
1999                 if (is_last_spte(pte, sp->role.level)) {
2000                         drop_spte(kvm, spte);
2001                         if (is_large_pte(pte))
2002                                 --kvm->stat.lpages;
2003                 } else {
2004                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2005                         drop_parent_pte(child, spte);
2006                 }
2007                 return true;
2008         }
2009
2010         if (is_mmio_spte(pte))
2011                 mmu_spte_clear_no_track(spte);
2012
2013         return false;
2014 }
2015
2016 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2017                                          struct kvm_mmu_page *sp)
2018 {
2019         unsigned i;
2020
2021         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2022                 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2023 }
2024
2025 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2026 {
2027         mmu_page_remove_parent_pte(sp, parent_pte);
2028 }
2029
2030 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2031 {
2032         u64 *sptep;
2033         struct rmap_iterator iter;
2034
2035         while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2036                 drop_parent_pte(sp, sptep);
2037 }
2038
2039 static int mmu_zap_unsync_children(struct kvm *kvm,
2040                                    struct kvm_mmu_page *parent,
2041                                    struct list_head *invalid_list)
2042 {
2043         int i, zapped = 0;
2044         struct mmu_page_path parents;
2045         struct kvm_mmu_pages pages;
2046
2047         if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2048                 return 0;
2049
2050         kvm_mmu_pages_init(parent, &parents, &pages);
2051         while (mmu_unsync_walk(parent, &pages)) {
2052                 struct kvm_mmu_page *sp;
2053
2054                 for_each_sp(pages, sp, parents, i) {
2055                         kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2056                         mmu_pages_clear_parents(&parents);
2057                         zapped++;
2058                 }
2059                 kvm_mmu_pages_init(parent, &parents, &pages);
2060         }
2061
2062         return zapped;
2063 }
2064
2065 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2066                                     struct list_head *invalid_list)
2067 {
2068         int ret;
2069
2070         trace_kvm_mmu_prepare_zap_page(sp);
2071         ++kvm->stat.mmu_shadow_zapped;
2072         ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2073         kvm_mmu_page_unlink_children(kvm, sp);
2074         kvm_mmu_unlink_parents(kvm, sp);
2075         if (!sp->role.invalid && !sp->role.direct)
2076                 unaccount_shadowed(kvm, sp->gfn);
2077         if (sp->unsync)
2078                 kvm_unlink_unsync_page(kvm, sp);
2079         if (!sp->root_count) {
2080                 /* Count self */
2081                 ret++;
2082                 list_move(&sp->link, invalid_list);
2083                 kvm_mod_used_mmu_pages(kvm, -1);
2084         } else {
2085                 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2086                 kvm_reload_remote_mmus(kvm);
2087         }
2088
2089         sp->role.invalid = 1;
2090         return ret;
2091 }
2092
2093 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2094                                     struct list_head *invalid_list)
2095 {
2096         struct kvm_mmu_page *sp;
2097
2098         if (list_empty(invalid_list))
2099                 return;
2100
2101         /*
2102          * wmb: make sure everyone sees our modifications to the page tables
2103          * rmb: make sure we see changes to vcpu->mode
2104          */
2105         smp_mb();
2106
2107         /*
2108          * Wait for all vcpus to exit guest mode and/or lockless shadow
2109          * page table walks.
2110          */
2111         kvm_flush_remote_tlbs(kvm);
2112
2113         do {
2114                 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
2115                 WARN_ON(!sp->role.invalid || sp->root_count);
2116                 kvm_mmu_isolate_page(sp);
2117                 kvm_mmu_free_page(sp);
2118         } while (!list_empty(invalid_list));
2119 }
2120
2121 /*
2122  * Changing the number of mmu pages allocated to the vm
2123  * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2124  */
2125 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2126 {
2127         LIST_HEAD(invalid_list);
2128         /*
2129          * If we set the number of mmu pages to be smaller be than the
2130          * number of actived pages , we must to free some mmu pages before we
2131          * change the value
2132          */
2133
2134         if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2135                 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
2136                         !list_empty(&kvm->arch.active_mmu_pages)) {
2137                         struct kvm_mmu_page *page;
2138
2139                         page = container_of(kvm->arch.active_mmu_pages.prev,
2140                                             struct kvm_mmu_page, link);
2141                         kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
2142                 }
2143                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2144                 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2145         }
2146
2147         kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2148 }
2149
2150 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2151 {
2152         struct kvm_mmu_page *sp;
2153         struct hlist_node *node;
2154         LIST_HEAD(invalid_list);
2155         int r;
2156
2157         pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2158         r = 0;
2159         spin_lock(&kvm->mmu_lock);
2160         for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2161                 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2162                          sp->role.word);
2163                 r = 1;
2164                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2165         }
2166         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2167         spin_unlock(&kvm->mmu_lock);
2168
2169         return r;
2170 }
2171 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2172
2173 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
2174 {
2175         int slot = memslot_id(kvm, gfn);
2176         struct kvm_mmu_page *sp = page_header(__pa(pte));
2177
2178         __set_bit(slot, sp->slot_bitmap);
2179 }
2180
2181 /*
2182  * The function is based on mtrr_type_lookup() in
2183  * arch/x86/kernel/cpu/mtrr/generic.c
2184  */
2185 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2186                          u64 start, u64 end)
2187 {
2188         int i;
2189         u64 base, mask;
2190         u8 prev_match, curr_match;
2191         int num_var_ranges = KVM_NR_VAR_MTRR;
2192
2193         if (!mtrr_state->enabled)
2194                 return 0xFF;
2195
2196         /* Make end inclusive end, instead of exclusive */
2197         end--;
2198
2199         /* Look in fixed ranges. Just return the type as per start */
2200         if (mtrr_state->have_fixed && (start < 0x100000)) {
2201                 int idx;
2202
2203                 if (start < 0x80000) {
2204                         idx = 0;
2205                         idx += (start >> 16);
2206                         return mtrr_state->fixed_ranges[idx];
2207                 } else if (start < 0xC0000) {
2208                         idx = 1 * 8;
2209                         idx += ((start - 0x80000) >> 14);
2210                         return mtrr_state->fixed_ranges[idx];
2211                 } else if (start < 0x1000000) {
2212                         idx = 3 * 8;
2213                         idx += ((start - 0xC0000) >> 12);
2214                         return mtrr_state->fixed_ranges[idx];
2215                 }
2216         }
2217
2218         /*
2219          * Look in variable ranges
2220          * Look of multiple ranges matching this address and pick type
2221          * as per MTRR precedence
2222          */
2223         if (!(mtrr_state->enabled & 2))
2224                 return mtrr_state->def_type;
2225
2226         prev_match = 0xFF;
2227         for (i = 0; i < num_var_ranges; ++i) {
2228                 unsigned short start_state, end_state;
2229
2230                 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2231                         continue;
2232
2233                 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2234                        (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2235                 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2236                        (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2237
2238                 start_state = ((start & mask) == (base & mask));
2239                 end_state = ((end & mask) == (base & mask));
2240                 if (start_state != end_state)
2241                         return 0xFE;
2242
2243                 if ((start & mask) != (base & mask))
2244                         continue;
2245
2246                 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2247                 if (prev_match == 0xFF) {
2248                         prev_match = curr_match;
2249                         continue;
2250                 }
2251
2252                 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2253                     curr_match == MTRR_TYPE_UNCACHABLE)
2254                         return MTRR_TYPE_UNCACHABLE;
2255
2256                 if ((prev_match == MTRR_TYPE_WRBACK &&
2257                      curr_match == MTRR_TYPE_WRTHROUGH) ||
2258                     (prev_match == MTRR_TYPE_WRTHROUGH &&
2259                      curr_match == MTRR_TYPE_WRBACK)) {
2260                         prev_match = MTRR_TYPE_WRTHROUGH;
2261                         curr_match = MTRR_TYPE_WRTHROUGH;
2262                 }
2263
2264                 if (prev_match != curr_match)
2265                         return MTRR_TYPE_UNCACHABLE;
2266         }
2267
2268         if (prev_match != 0xFF)
2269                 return prev_match;
2270
2271         return mtrr_state->def_type;
2272 }
2273
2274 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2275 {
2276         u8 mtrr;
2277
2278         mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2279                              (gfn << PAGE_SHIFT) + PAGE_SIZE);
2280         if (mtrr == 0xfe || mtrr == 0xff)
2281                 mtrr = MTRR_TYPE_WRBACK;
2282         return mtrr;
2283 }
2284 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2285
2286 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2287 {
2288         trace_kvm_mmu_unsync_page(sp);
2289         ++vcpu->kvm->stat.mmu_unsync;
2290         sp->unsync = 1;
2291
2292         kvm_mmu_mark_parents_unsync(sp);
2293 }
2294
2295 static void kvm_unsync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
2296 {
2297         struct kvm_mmu_page *s;
2298         struct hlist_node *node;
2299
2300         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2301                 if (s->unsync)
2302                         continue;
2303                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2304                 __kvm_unsync_page(vcpu, s);
2305         }
2306 }
2307
2308 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2309                                   bool can_unsync)
2310 {
2311         struct kvm_mmu_page *s;
2312         struct hlist_node *node;
2313         bool need_unsync = false;
2314
2315         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2316                 if (!can_unsync)
2317                         return 1;
2318
2319                 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2320                         return 1;
2321
2322                 if (!need_unsync && !s->unsync) {
2323                         need_unsync = true;
2324                 }
2325         }
2326         if (need_unsync)
2327                 kvm_unsync_pages(vcpu, gfn);
2328         return 0;
2329 }
2330
2331 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2332                     unsigned pte_access, int user_fault,
2333                     int write_fault, int level,
2334                     gfn_t gfn, pfn_t pfn, bool speculative,
2335                     bool can_unsync, bool host_writable)
2336 {
2337         u64 spte;
2338         int ret = 0;
2339
2340         if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2341                 return 0;
2342
2343         spte = PT_PRESENT_MASK;
2344         if (!speculative)
2345                 spte |= shadow_accessed_mask;
2346
2347         if (pte_access & ACC_EXEC_MASK)
2348                 spte |= shadow_x_mask;
2349         else
2350                 spte |= shadow_nx_mask;
2351
2352         if (pte_access & ACC_USER_MASK)
2353                 spte |= shadow_user_mask;
2354
2355         if (level > PT_PAGE_TABLE_LEVEL)
2356                 spte |= PT_PAGE_SIZE_MASK;
2357         if (tdp_enabled)
2358                 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2359                         kvm_is_mmio_pfn(pfn));
2360
2361         if (host_writable)
2362                 spte |= SPTE_HOST_WRITEABLE;
2363         else
2364                 pte_access &= ~ACC_WRITE_MASK;
2365
2366         spte |= (u64)pfn << PAGE_SHIFT;
2367
2368         if ((pte_access & ACC_WRITE_MASK)
2369             || (!vcpu->arch.mmu.direct_map && write_fault
2370                 && !is_write_protection(vcpu) && !user_fault)) {
2371
2372                 if (level > PT_PAGE_TABLE_LEVEL &&
2373                     has_wrprotected_page(vcpu->kvm, gfn, level)) {
2374                         ret = 1;
2375                         drop_spte(vcpu->kvm, sptep);
2376                         goto done;
2377                 }
2378
2379                 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2380
2381                 if (!vcpu->arch.mmu.direct_map
2382                     && !(pte_access & ACC_WRITE_MASK)) {
2383                         spte &= ~PT_USER_MASK;
2384                         /*
2385                          * If we converted a user page to a kernel page,
2386                          * so that the kernel can write to it when cr0.wp=0,
2387                          * then we should prevent the kernel from executing it
2388                          * if SMEP is enabled.
2389                          */
2390                         if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
2391                                 spte |= PT64_NX_MASK;
2392                 }
2393
2394                 /*
2395                  * Optimization: for pte sync, if spte was writable the hash
2396                  * lookup is unnecessary (and expensive). Write protection
2397                  * is responsibility of mmu_get_page / kvm_sync_page.
2398                  * Same reasoning can be applied to dirty page accounting.
2399                  */
2400                 if (!can_unsync && is_writable_pte(*sptep))
2401                         goto set_pte;
2402
2403                 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2404                         pgprintk("%s: found shadow page for %llx, marking ro\n",
2405                                  __func__, gfn);
2406                         ret = 1;
2407                         pte_access &= ~ACC_WRITE_MASK;
2408                         spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2409                 }
2410         }
2411
2412         if (pte_access & ACC_WRITE_MASK)
2413                 mark_page_dirty(vcpu->kvm, gfn);
2414
2415 set_pte:
2416         if (mmu_spte_update(sptep, spte))
2417                 kvm_flush_remote_tlbs(vcpu->kvm);
2418 done:
2419         return ret;
2420 }
2421
2422 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2423                          unsigned pt_access, unsigned pte_access,
2424                          int user_fault, int write_fault,
2425                          int *emulate, int level, gfn_t gfn,
2426                          pfn_t pfn, bool speculative,
2427                          bool host_writable)
2428 {
2429         int was_rmapped = 0;
2430         int rmap_count;
2431
2432         pgprintk("%s: spte %llx access %x write_fault %d"
2433                  " user_fault %d gfn %llx\n",
2434                  __func__, *sptep, pt_access,
2435                  write_fault, user_fault, gfn);
2436
2437         if (is_rmap_spte(*sptep)) {
2438                 /*
2439                  * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2440                  * the parent of the now unreachable PTE.
2441                  */
2442                 if (level > PT_PAGE_TABLE_LEVEL &&
2443                     !is_large_pte(*sptep)) {
2444                         struct kvm_mmu_page *child;
2445                         u64 pte = *sptep;
2446
2447                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2448                         drop_parent_pte(child, sptep);
2449                         kvm_flush_remote_tlbs(vcpu->kvm);
2450                 } else if (pfn != spte_to_pfn(*sptep)) {
2451                         pgprintk("hfn old %llx new %llx\n",
2452                                  spte_to_pfn(*sptep), pfn);
2453                         drop_spte(vcpu->kvm, sptep);
2454                         kvm_flush_remote_tlbs(vcpu->kvm);
2455                 } else
2456                         was_rmapped = 1;
2457         }
2458
2459         if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2460                       level, gfn, pfn, speculative, true,
2461                       host_writable)) {
2462                 if (write_fault)
2463                         *emulate = 1;
2464                 kvm_mmu_flush_tlb(vcpu);
2465         }
2466
2467         if (unlikely(is_mmio_spte(*sptep) && emulate))
2468                 *emulate = 1;
2469
2470         pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2471         pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2472                  is_large_pte(*sptep)? "2MB" : "4kB",
2473                  *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2474                  *sptep, sptep);
2475         if (!was_rmapped && is_large_pte(*sptep))
2476                 ++vcpu->kvm->stat.lpages;
2477
2478         if (is_shadow_present_pte(*sptep)) {
2479                 page_header_update_slot(vcpu->kvm, sptep, gfn);
2480                 if (!was_rmapped) {
2481                         rmap_count = rmap_add(vcpu, sptep, gfn);
2482                         if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2483                                 rmap_recycle(vcpu, sptep, gfn);
2484                 }
2485         }
2486         kvm_release_pfn_clean(pfn);
2487 }
2488
2489 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2490 {
2491         mmu_free_roots(vcpu);
2492 }
2493
2494 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2495                                      bool no_dirty_log)
2496 {
2497         struct kvm_memory_slot *slot;
2498         unsigned long hva;
2499
2500         slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2501         if (!slot) {
2502                 get_page(fault_page);
2503                 return page_to_pfn(fault_page);
2504         }
2505
2506         hva = gfn_to_hva_memslot(slot, gfn);
2507
2508         return hva_to_pfn_atomic(vcpu->kvm, hva);
2509 }
2510
2511 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2512                                     struct kvm_mmu_page *sp,
2513                                     u64 *start, u64 *end)
2514 {
2515         struct page *pages[PTE_PREFETCH_NUM];
2516         unsigned access = sp->role.access;
2517         int i, ret;
2518         gfn_t gfn;
2519
2520         gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2521         if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2522                 return -1;
2523
2524         ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2525         if (ret <= 0)
2526                 return -1;
2527
2528         for (i = 0; i < ret; i++, gfn++, start++)
2529                 mmu_set_spte(vcpu, start, ACC_ALL,
2530                              access, 0, 0, NULL,
2531                              sp->role.level, gfn,
2532                              page_to_pfn(pages[i]), true, true);
2533
2534         return 0;
2535 }
2536
2537 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2538                                   struct kvm_mmu_page *sp, u64 *sptep)
2539 {
2540         u64 *spte, *start = NULL;
2541         int i;
2542
2543         WARN_ON(!sp->role.direct);
2544
2545         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2546         spte = sp->spt + i;
2547
2548         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2549                 if (is_shadow_present_pte(*spte) || spte == sptep) {
2550                         if (!start)
2551                                 continue;
2552                         if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2553                                 break;
2554                         start = NULL;
2555                 } else if (!start)
2556                         start = spte;
2557         }
2558 }
2559
2560 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2561 {
2562         struct kvm_mmu_page *sp;
2563
2564         /*
2565          * Since it's no accessed bit on EPT, it's no way to
2566          * distinguish between actually accessed translations
2567          * and prefetched, so disable pte prefetch if EPT is
2568          * enabled.
2569          */
2570         if (!shadow_accessed_mask)
2571                 return;
2572
2573         sp = page_header(__pa(sptep));
2574         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2575                 return;
2576
2577         __direct_pte_prefetch(vcpu, sp, sptep);
2578 }
2579
2580 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2581                         int map_writable, int level, gfn_t gfn, pfn_t pfn,
2582                         bool prefault)
2583 {
2584         struct kvm_shadow_walk_iterator iterator;
2585         struct kvm_mmu_page *sp;
2586         int emulate = 0;
2587         gfn_t pseudo_gfn;
2588
2589         for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2590                 if (iterator.level == level) {
2591                         unsigned pte_access = ACC_ALL;
2592
2593                         mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2594                                      0, write, &emulate,
2595                                      level, gfn, pfn, prefault, map_writable);
2596                         direct_pte_prefetch(vcpu, iterator.sptep);
2597                         ++vcpu->stat.pf_fixed;
2598                         break;
2599                 }
2600
2601                 if (!is_shadow_present_pte(*iterator.sptep)) {
2602                         u64 base_addr = iterator.addr;
2603
2604                         base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2605                         pseudo_gfn = base_addr >> PAGE_SHIFT;
2606                         sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2607                                               iterator.level - 1,
2608                                               1, ACC_ALL, iterator.sptep);
2609                         if (!sp) {
2610                                 pgprintk("nonpaging_map: ENOMEM\n");
2611                                 kvm_release_pfn_clean(pfn);
2612                                 return -ENOMEM;
2613                         }
2614
2615                         mmu_spte_set(iterator.sptep,
2616                                      __pa(sp->spt)
2617                                      | PT_PRESENT_MASK | PT_WRITABLE_MASK
2618                                      | shadow_user_mask | shadow_x_mask
2619                                      | shadow_accessed_mask);
2620                 }
2621         }
2622         return emulate;
2623 }
2624
2625 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2626 {
2627         siginfo_t info;
2628
2629         info.si_signo   = SIGBUS;
2630         info.si_errno   = 0;
2631         info.si_code    = BUS_MCEERR_AR;
2632         info.si_addr    = (void __user *)address;
2633         info.si_addr_lsb = PAGE_SHIFT;
2634
2635         send_sig_info(SIGBUS, &info, tsk);
2636 }
2637
2638 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2639 {
2640         kvm_release_pfn_clean(pfn);
2641         if (is_hwpoison_pfn(pfn)) {
2642                 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2643                 return 0;
2644         }
2645
2646         return -EFAULT;
2647 }
2648
2649 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2650                                         gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2651 {
2652         pfn_t pfn = *pfnp;
2653         gfn_t gfn = *gfnp;
2654         int level = *levelp;
2655
2656         /*
2657          * Check if it's a transparent hugepage. If this would be an
2658          * hugetlbfs page, level wouldn't be set to
2659          * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2660          * here.
2661          */
2662         if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2663             level == PT_PAGE_TABLE_LEVEL &&
2664             PageTransCompound(pfn_to_page(pfn)) &&
2665             !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2666                 unsigned long mask;
2667                 /*
2668                  * mmu_notifier_retry was successful and we hold the
2669                  * mmu_lock here, so the pmd can't become splitting
2670                  * from under us, and in turn
2671                  * __split_huge_page_refcount() can't run from under
2672                  * us and we can safely transfer the refcount from
2673                  * PG_tail to PG_head as we switch the pfn to tail to
2674                  * head.
2675                  */
2676                 *levelp = level = PT_DIRECTORY_LEVEL;
2677                 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2678                 VM_BUG_ON((gfn & mask) != (pfn & mask));
2679                 if (pfn & mask) {
2680                         gfn &= ~mask;
2681                         *gfnp = gfn;
2682                         kvm_release_pfn_clean(pfn);
2683                         pfn &= ~mask;
2684                         kvm_get_pfn(pfn);
2685                         *pfnp = pfn;
2686                 }
2687         }
2688 }
2689
2690 static bool mmu_invalid_pfn(pfn_t pfn)
2691 {
2692         return unlikely(is_invalid_pfn(pfn));
2693 }
2694
2695 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2696                                 pfn_t pfn, unsigned access, int *ret_val)
2697 {
2698         bool ret = true;
2699
2700         /* The pfn is invalid, report the error! */
2701         if (unlikely(is_invalid_pfn(pfn))) {
2702                 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2703                 goto exit;
2704         }
2705
2706         if (unlikely(is_noslot_pfn(pfn)))
2707                 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2708
2709         ret = false;
2710 exit:
2711         return ret;
2712 }
2713
2714 static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code)
2715 {
2716         /*
2717          * #PF can be fast only if the shadow page table is present and it
2718          * is caused by write-protect, that means we just need change the
2719          * W bit of the spte which can be done out of mmu-lock.
2720          */
2721         if (!(error_code & PFERR_PRESENT_MASK) ||
2722               !(error_code & PFERR_WRITE_MASK))
2723                 return false;
2724
2725         return true;
2726 }
2727
2728 static bool
2729 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
2730 {
2731         struct kvm_mmu_page *sp = page_header(__pa(sptep));
2732         gfn_t gfn;
2733
2734         WARN_ON(!sp->role.direct);
2735
2736         /*
2737          * The gfn of direct spte is stable since it is calculated
2738          * by sp->gfn.
2739          */
2740         gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2741
2742         if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2743                 mark_page_dirty(vcpu->kvm, gfn);
2744
2745         return true;
2746 }
2747
2748 /*
2749  * Return value:
2750  * - true: let the vcpu to access on the same address again.
2751  * - false: let the real page fault path to fix it.
2752  */
2753 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2754                             u32 error_code)
2755 {
2756         struct kvm_shadow_walk_iterator iterator;
2757         bool ret = false;
2758         u64 spte = 0ull;
2759
2760         if (!page_fault_can_be_fast(vcpu, error_code))
2761                 return false;
2762
2763         walk_shadow_page_lockless_begin(vcpu);
2764         for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2765                 if (!is_shadow_present_pte(spte) || iterator.level < level)
2766                         break;
2767
2768         /*
2769          * If the mapping has been changed, let the vcpu fault on the
2770          * same address again.
2771          */
2772         if (!is_rmap_spte(spte)) {
2773                 ret = true;
2774                 goto exit;
2775         }
2776
2777         if (!is_last_spte(spte, level))
2778                 goto exit;
2779
2780         /*
2781          * Check if it is a spurious fault caused by TLB lazily flushed.
2782          *
2783          * Need not check the access of upper level table entries since
2784          * they are always ACC_ALL.
2785          */
2786          if (is_writable_pte(spte)) {
2787                 ret = true;
2788                 goto exit;
2789         }
2790
2791         /*
2792          * Currently, to simplify the code, only the spte write-protected
2793          * by dirty-log can be fast fixed.
2794          */
2795         if (!spte_is_locklessly_modifiable(spte))
2796                 goto exit;
2797
2798         /*
2799          * Currently, fast page fault only works for direct mapping since
2800          * the gfn is not stable for indirect shadow page.
2801          * See Documentation/virtual/kvm/locking.txt to get more detail.
2802          */
2803         ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
2804 exit:
2805         trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2806                               spte, ret);
2807         walk_shadow_page_lockless_end(vcpu);
2808
2809         return ret;
2810 }
2811
2812 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2813                          gva_t gva, pfn_t *pfn, bool write, bool *writable);
2814
2815 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2816                          gfn_t gfn, bool prefault)
2817 {
2818         int r;
2819         int level;
2820         int force_pt_level;
2821         pfn_t pfn;
2822         unsigned long mmu_seq;
2823         bool map_writable, write = error_code & PFERR_WRITE_MASK;
2824
2825         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2826         if (likely(!force_pt_level)) {
2827                 level = mapping_level(vcpu, gfn);
2828                 /*
2829                  * This path builds a PAE pagetable - so we can map
2830                  * 2mb pages at maximum. Therefore check if the level
2831                  * is larger than that.
2832                  */
2833                 if (level > PT_DIRECTORY_LEVEL)
2834                         level = PT_DIRECTORY_LEVEL;
2835
2836                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2837         } else
2838                 level = PT_PAGE_TABLE_LEVEL;
2839
2840         if (fast_page_fault(vcpu, v, level, error_code))
2841                 return 0;
2842
2843         mmu_seq = vcpu->kvm->mmu_notifier_seq;
2844         smp_rmb();
2845
2846         if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2847                 return 0;
2848
2849         if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2850                 return r;
2851
2852         spin_lock(&vcpu->kvm->mmu_lock);
2853         if (mmu_notifier_retry(vcpu, mmu_seq))
2854                 goto out_unlock;
2855         kvm_mmu_free_some_pages(vcpu);
2856         if (likely(!force_pt_level))
2857                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2858         r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2859                          prefault);
2860         spin_unlock(&vcpu->kvm->mmu_lock);
2861
2862
2863         return r;
2864
2865 out_unlock:
2866         spin_unlock(&vcpu->kvm->mmu_lock);
2867         kvm_release_pfn_clean(pfn);
2868         return 0;
2869 }
2870
2871
2872 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2873 {
2874         int i;
2875         struct kvm_mmu_page *sp;
2876         LIST_HEAD(invalid_list);
2877
2878         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2879                 return;
2880         spin_lock(&vcpu->kvm->mmu_lock);
2881         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2882             (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2883              vcpu->arch.mmu.direct_map)) {
2884                 hpa_t root = vcpu->arch.mmu.root_hpa;
2885
2886                 sp = page_header(root);
2887                 --sp->root_count;
2888                 if (!sp->root_count && sp->role.invalid) {
2889                         kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2890                         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2891                 }
2892                 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2893                 spin_unlock(&vcpu->kvm->mmu_lock);
2894                 return;
2895         }
2896         for (i = 0; i < 4; ++i) {
2897                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2898
2899                 if (root) {
2900                         root &= PT64_BASE_ADDR_MASK;
2901                         sp = page_header(root);
2902                         --sp->root_count;
2903                         if (!sp->root_count && sp->role.invalid)
2904                                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2905                                                          &invalid_list);
2906                 }
2907                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2908         }
2909         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2910         spin_unlock(&vcpu->kvm->mmu_lock);
2911         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2912 }
2913
2914 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2915 {
2916         int ret = 0;
2917
2918         if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2919                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2920                 ret = 1;
2921         }
2922
2923         return ret;
2924 }
2925
2926 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2927 {
2928         struct kvm_mmu_page *sp;
2929         unsigned i;
2930
2931         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2932                 spin_lock(&vcpu->kvm->mmu_lock);
2933                 kvm_mmu_free_some_pages(vcpu);
2934                 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2935                                       1, ACC_ALL, NULL);
2936                 ++sp->root_count;
2937                 spin_unlock(&vcpu->kvm->mmu_lock);
2938                 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2939         } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2940                 for (i = 0; i < 4; ++i) {
2941                         hpa_t root = vcpu->arch.mmu.pae_root[i];
2942
2943                         ASSERT(!VALID_PAGE(root));
2944                         spin_lock(&vcpu->kvm->mmu_lock);
2945                         kvm_mmu_free_some_pages(vcpu);
2946                         sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2947                                               i << 30,
2948                                               PT32_ROOT_LEVEL, 1, ACC_ALL,
2949                                               NULL);
2950                         root = __pa(sp->spt);
2951                         ++sp->root_count;
2952                         spin_unlock(&vcpu->kvm->mmu_lock);
2953                         vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2954                 }
2955                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2956         } else
2957                 BUG();
2958
2959         return 0;
2960 }
2961
2962 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2963 {
2964         struct kvm_mmu_page *sp;
2965         u64 pdptr, pm_mask;
2966         gfn_t root_gfn;
2967         int i;
2968
2969         root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2970
2971         if (mmu_check_root(vcpu, root_gfn))
2972                 return 1;
2973
2974         /*
2975          * Do we shadow a long mode page table? If so we need to
2976          * write-protect the guests page table root.
2977          */
2978         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2979                 hpa_t root = vcpu->arch.mmu.root_hpa;
2980
2981                 ASSERT(!VALID_PAGE(root));
2982
2983                 spin_lock(&vcpu->kvm->mmu_lock);
2984                 kvm_mmu_free_some_pages(vcpu);
2985                 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2986                                       0, ACC_ALL, NULL);
2987                 root = __pa(sp->spt);
2988                 ++sp->root_count;
2989                 spin_unlock(&vcpu->kvm->mmu_lock);
2990                 vcpu->arch.mmu.root_hpa = root;
2991                 return 0;
2992         }
2993
2994         /*
2995          * We shadow a 32 bit page table. This may be a legacy 2-level
2996          * or a PAE 3-level page table. In either case we need to be aware that
2997          * the shadow page table may be a PAE or a long mode page table.
2998          */
2999         pm_mask = PT_PRESENT_MASK;
3000         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3001                 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3002
3003         for (i = 0; i < 4; ++i) {
3004                 hpa_t root = vcpu->arch.mmu.pae_root[i];
3005
3006                 ASSERT(!VALID_PAGE(root));
3007                 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3008                         pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3009                         if (!is_present_gpte(pdptr)) {
3010                                 vcpu->arch.mmu.pae_root[i] = 0;
3011                                 continue;
3012                         }
3013                         root_gfn = pdptr >> PAGE_SHIFT;
3014                         if (mmu_check_root(vcpu, root_gfn))
3015                                 return 1;
3016                 }
3017                 spin_lock(&vcpu->kvm->mmu_lock);
3018                 kvm_mmu_free_some_pages(vcpu);
3019                 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3020                                       PT32_ROOT_LEVEL, 0,
3021                                       ACC_ALL, NULL);
3022                 root = __pa(sp->spt);
3023                 ++sp->root_count;
3024                 spin_unlock(&vcpu->kvm->mmu_lock);
3025
3026                 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3027         }
3028         vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3029
3030         /*
3031          * If we shadow a 32 bit page table with a long mode page
3032          * table we enter this path.
3033          */
3034         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3035                 if (vcpu->arch.mmu.lm_root == NULL) {
3036                         /*
3037                          * The additional page necessary for this is only
3038                          * allocated on demand.
3039                          */
3040
3041                         u64 *lm_root;
3042
3043                         lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3044                         if (lm_root == NULL)
3045                                 return 1;
3046
3047                         lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3048
3049                         vcpu->arch.mmu.lm_root = lm_root;
3050                 }
3051
3052                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3053         }
3054
3055         return 0;
3056 }
3057
3058 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3059 {
3060         if (vcpu->arch.mmu.direct_map)
3061                 return mmu_alloc_direct_roots(vcpu);
3062         else
3063                 return mmu_alloc_shadow_roots(vcpu);
3064 }
3065
3066 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3067 {
3068         int i;
3069         struct kvm_mmu_page *sp;
3070
3071         if (vcpu->arch.mmu.direct_map)
3072                 return;
3073
3074         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3075                 return;
3076
3077         vcpu_clear_mmio_info(vcpu, ~0ul);
3078         kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3079         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3080                 hpa_t root = vcpu->arch.mmu.root_hpa;
3081                 sp = page_header(root);
3082                 mmu_sync_children(vcpu, sp);
3083                 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3084                 return;
3085         }
3086         for (i = 0; i < 4; ++i) {
3087                 hpa_t root = vcpu->arch.mmu.pae_root[i];
3088
3089                 if (root && VALID_PAGE(root)) {
3090                         root &= PT64_BASE_ADDR_MASK;
3091                         sp = page_header(root);
3092                         mmu_sync_children(vcpu, sp);
3093                 }
3094         }
3095         kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3096 }
3097
3098 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3099 {
3100         spin_lock(&vcpu->kvm->mmu_lock);
3101         mmu_sync_roots(vcpu);
3102         spin_unlock(&vcpu->kvm->mmu_lock);
3103 }
3104
3105 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3106                                   u32 access, struct x86_exception *exception)
3107 {
3108         if (exception)
3109                 exception->error_code = 0;
3110         return vaddr;
3111 }
3112
3113 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3114                                          u32 access,
3115                                          struct x86_exception *exception)
3116 {
3117         if (exception)
3118                 exception->error_code = 0;
3119         return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3120 }
3121
3122 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3123 {
3124         if (direct)
3125                 return vcpu_match_mmio_gpa(vcpu, addr);
3126
3127         return vcpu_match_mmio_gva(vcpu, addr);
3128 }
3129
3130
3131 /*
3132  * On direct hosts, the last spte is only allows two states
3133  * for mmio page fault:
3134  *   - It is the mmio spte
3135  *   - It is zapped or it is being zapped.
3136  *
3137  * This function completely checks the spte when the last spte
3138  * is not the mmio spte.
3139  */
3140 static bool check_direct_spte_mmio_pf(u64 spte)
3141 {
3142         return __check_direct_spte_mmio_pf(spte);
3143 }
3144
3145 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3146 {
3147         struct kvm_shadow_walk_iterator iterator;
3148         u64 spte = 0ull;
3149
3150         walk_shadow_page_lockless_begin(vcpu);
3151         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3152                 if (!is_shadow_present_pte(spte))
3153                         break;
3154         walk_shadow_page_lockless_end(vcpu);
3155
3156         return spte;
3157 }
3158
3159 /*
3160  * If it is a real mmio page fault, return 1 and emulat the instruction
3161  * directly, return 0 to let CPU fault again on the address, -1 is
3162  * returned if bug is detected.
3163  */
3164 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3165 {
3166         u64 spte;
3167
3168         if (quickly_check_mmio_pf(vcpu, addr, direct))
3169                 return 1;
3170
3171         spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3172
3173         if (is_mmio_spte(spte)) {
3174                 gfn_t gfn = get_mmio_spte_gfn(spte);
3175                 unsigned access = get_mmio_spte_access(spte);
3176
3177                 if (direct)
3178                         addr = 0;
3179
3180                 trace_handle_mmio_page_fault(addr, gfn, access);
3181                 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3182                 return 1;
3183         }
3184
3185         /*
3186          * It's ok if the gva is remapped by other cpus on shadow guest,
3187          * it's a BUG if the gfn is not a mmio page.
3188          */
3189         if (direct && !check_direct_spte_mmio_pf(spte))
3190                 return -1;
3191
3192         /*
3193          * If the page table is zapped by other cpus, let CPU fault again on
3194          * the address.
3195          */
3196         return 0;
3197 }
3198 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3199
3200 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3201                                   u32 error_code, bool direct)
3202 {
3203         int ret;
3204
3205         ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3206         WARN_ON(ret < 0);
3207         return ret;
3208 }
3209
3210 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3211                                 u32 error_code, bool prefault)
3212 {
3213         gfn_t gfn;
3214         int r;
3215
3216         pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3217
3218         if (unlikely(error_code & PFERR_RSVD_MASK))
3219                 return handle_mmio_page_fault(vcpu, gva, error_code, true);
3220
3221         r = mmu_topup_memory_caches(vcpu);
3222         if (r)
3223                 return r;
3224
3225         ASSERT(vcpu);
3226         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3227
3228         gfn = gva >> PAGE_SHIFT;
3229
3230         return nonpaging_map(vcpu, gva & PAGE_MASK,
3231                              error_code, gfn, prefault);
3232 }
3233
3234 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3235 {
3236         struct kvm_arch_async_pf arch;
3237
3238         arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3239         arch.gfn = gfn;
3240         arch.direct_map = vcpu->arch.mmu.direct_map;
3241         arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3242
3243         return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3244 }
3245
3246 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3247 {
3248         if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3249                      kvm_event_needs_reinjection(vcpu)))
3250                 return false;
3251
3252         return kvm_x86_ops->interrupt_allowed(vcpu);
3253 }
3254
3255 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3256                          gva_t gva, pfn_t *pfn, bool write, bool *writable)
3257 {
3258         bool async;
3259
3260         *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3261
3262         if (!async)
3263                 return false; /* *pfn has correct page already */
3264
3265         put_page(pfn_to_page(*pfn));
3266
3267         if (!prefault && can_do_async_pf(vcpu)) {
3268                 trace_kvm_try_async_get_page(gva, gfn);
3269                 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3270                         trace_kvm_async_pf_doublefault(gva, gfn);
3271                         kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3272                         return true;
3273                 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3274                         return true;
3275         }
3276
3277         *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3278
3279         return false;
3280 }
3281
3282 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3283                           bool prefault)
3284 {
3285         pfn_t pfn;
3286         int r;
3287         int level;
3288         int force_pt_level;
3289         gfn_t gfn = gpa >> PAGE_SHIFT;
3290         unsigned long mmu_seq;
3291         int write = error_code & PFERR_WRITE_MASK;
3292         bool map_writable;
3293
3294         ASSERT(vcpu);
3295         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3296
3297         if (unlikely(error_code & PFERR_RSVD_MASK))
3298                 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3299
3300         r = mmu_topup_memory_caches(vcpu);
3301         if (r)
3302                 return r;
3303
3304         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3305         if (likely(!force_pt_level)) {
3306                 level = mapping_level(vcpu, gfn);
3307                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3308         } else
3309                 level = PT_PAGE_TABLE_LEVEL;
3310
3311         if (fast_page_fault(vcpu, gpa, level, error_code))
3312                 return 0;
3313
3314         mmu_seq = vcpu->kvm->mmu_notifier_seq;
3315         smp_rmb();
3316
3317         if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3318                 return 0;
3319
3320         if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3321                 return r;
3322
3323         spin_lock(&vcpu->kvm->mmu_lock);
3324         if (mmu_notifier_retry(vcpu, mmu_seq))
3325                 goto out_unlock;
3326         kvm_mmu_free_some_pages(vcpu);
3327         if (likely(!force_pt_level))
3328                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3329         r = __direct_map(vcpu, gpa, write, map_writable,
3330                          level, gfn, pfn, prefault);
3331         spin_unlock(&vcpu->kvm->mmu_lock);
3332
3333         return r;
3334
3335 out_unlock:
3336         spin_unlock(&vcpu->kvm->mmu_lock);
3337         kvm_release_pfn_clean(pfn);
3338         return 0;
3339 }
3340
3341 static void nonpaging_free(struct kvm_vcpu *vcpu)
3342 {
3343         mmu_free_roots(vcpu);
3344 }
3345
3346 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3347                                   struct kvm_mmu *context)
3348 {
3349         context->new_cr3 = nonpaging_new_cr3;
3350         context->page_fault = nonpaging_page_fault;
3351         context->gva_to_gpa = nonpaging_gva_to_gpa;
3352         context->free = nonpaging_free;
3353         context->sync_page = nonpaging_sync_page;
3354         context->invlpg = nonpaging_invlpg;
3355         context->update_pte = nonpaging_update_pte;
3356         context->root_level = 0;
3357         context->shadow_root_level = PT32E_ROOT_LEVEL;
3358         context->root_hpa = INVALID_PAGE;
3359         context->direct_map = true;
3360         context->nx = false;
3361         return 0;
3362 }
3363
3364 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3365 {
3366         ++vcpu->stat.tlb_flush;
3367         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3368 }
3369
3370 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3371 {
3372         pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3373         mmu_free_roots(vcpu);
3374 }
3375
3376 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3377 {
3378         return kvm_read_cr3(vcpu);
3379 }
3380
3381 static void inject_page_fault(struct kvm_vcpu *vcpu,
3382                               struct x86_exception *fault)
3383 {
3384         vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3385 }
3386
3387 static void paging_free(struct kvm_vcpu *vcpu)
3388 {
3389         nonpaging_free(vcpu);
3390 }
3391
3392 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3393 {
3394         int bit7;
3395
3396         bit7 = (gpte >> 7) & 1;
3397         return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
3398 }
3399
3400 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3401                            int *nr_present)
3402 {
3403         if (unlikely(is_mmio_spte(*sptep))) {
3404                 if (gfn != get_mmio_spte_gfn(*sptep)) {
3405                         mmu_spte_clear_no_track(sptep);
3406                         return true;
3407                 }
3408
3409                 (*nr_present)++;
3410                 mark_mmio_spte(sptep, gfn, access);
3411                 return true;
3412         }
3413
3414         return false;
3415 }
3416
3417 #define PTTYPE 64
3418 #include "paging_tmpl.h"
3419 #undef PTTYPE
3420
3421 #define PTTYPE 32
3422 #include "paging_tmpl.h"
3423 #undef PTTYPE
3424
3425 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3426                                   struct kvm_mmu *context)
3427 {
3428         int maxphyaddr = cpuid_maxphyaddr(vcpu);
3429         u64 exb_bit_rsvd = 0;
3430
3431         if (!context->nx)
3432                 exb_bit_rsvd = rsvd_bits(63, 63);
3433         switch (context->root_level) {
3434         case PT32_ROOT_LEVEL:
3435                 /* no rsvd bits for 2 level 4K page table entries */
3436                 context->rsvd_bits_mask[0][1] = 0;
3437                 context->rsvd_bits_mask[0][0] = 0;
3438                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3439
3440                 if (!is_pse(vcpu)) {
3441                         context->rsvd_bits_mask[1][1] = 0;
3442                         break;
3443                 }
3444
3445                 if (is_cpuid_PSE36())
3446                         /* 36bits PSE 4MB page */
3447                         context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3448                 else
3449                         /* 32 bits PSE 4MB page */
3450                         context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3451                 break;
3452         case PT32E_ROOT_LEVEL:
3453                 context->rsvd_bits_mask[0][2] =
3454                         rsvd_bits(maxphyaddr, 63) |
3455                         rsvd_bits(7, 8) | rsvd_bits(1, 2);      /* PDPTE */
3456                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3457                         rsvd_bits(maxphyaddr, 62);      /* PDE */
3458                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3459                         rsvd_bits(maxphyaddr, 62);      /* PTE */
3460                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3461                         rsvd_bits(maxphyaddr, 62) |
3462                         rsvd_bits(13, 20);              /* large page */
3463                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3464                 break;
3465         case PT64_ROOT_LEVEL:
3466                 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3467                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3468                 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3469                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3470                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3471                         rsvd_bits(maxphyaddr, 51);
3472                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3473                         rsvd_bits(maxphyaddr, 51);
3474                 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3475                 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3476                         rsvd_bits(maxphyaddr, 51) |
3477                         rsvd_bits(13, 29);
3478                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3479                         rsvd_bits(maxphyaddr, 51) |
3480                         rsvd_bits(13, 20);              /* large page */
3481                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3482                 break;
3483         }
3484 }
3485
3486 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3487                                         struct kvm_mmu *context,
3488                                         int level)
3489 {
3490         context->nx = is_nx(vcpu);
3491         context->root_level = level;
3492
3493         reset_rsvds_bits_mask(vcpu, context);
3494
3495         ASSERT(is_pae(vcpu));
3496         context->new_cr3 = paging_new_cr3;
3497         context->page_fault = paging64_page_fault;
3498         context->gva_to_gpa = paging64_gva_to_gpa;
3499         context->sync_page = paging64_sync_page;
3500         context->invlpg = paging64_invlpg;
3501         context->update_pte = paging64_update_pte;
3502         context->free = paging_free;
3503         context->shadow_root_level = level;
3504         context->root_hpa = INVALID_PAGE;
3505         context->direct_map = false;
3506         return 0;
3507 }
3508
3509 static int paging64_init_context(struct kvm_vcpu *vcpu,
3510                                  struct kvm_mmu *context)
3511 {
3512         return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3513 }
3514
3515 static int paging32_init_context(struct kvm_vcpu *vcpu,
3516                                  struct kvm_mmu *context)
3517 {
3518         context->nx = false;
3519         context->root_level = PT32_ROOT_LEVEL;
3520
3521         reset_rsvds_bits_mask(vcpu, context);
3522
3523         context->new_cr3 = paging_new_cr3;
3524         context->page_fault = paging32_page_fault;
3525         context->gva_to_gpa = paging32_gva_to_gpa;
3526         context->free = paging_free;
3527         context->sync_page = paging32_sync_page;
3528         context->invlpg = paging32_invlpg;
3529         context->update_pte = paging32_update_pte;
3530         context->shadow_root_level = PT32E_ROOT_LEVEL;
3531         context->root_hpa = INVALID_PAGE;
3532         context->direct_map = false;
3533         return 0;
3534 }
3535
3536 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3537                                   struct kvm_mmu *context)
3538 {
3539         return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3540 }
3541
3542 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3543 {
3544         struct kvm_mmu *context = vcpu->arch.walk_mmu;
3545
3546         context->base_role.word = 0;
3547         context->new_cr3 = nonpaging_new_cr3;
3548         context->page_fault = tdp_page_fault;
3549         context->free = nonpaging_free;
3550         context->sync_page = nonpaging_sync_page;
3551         context->invlpg = nonpaging_invlpg;
3552         context->update_pte = nonpaging_update_pte;
3553         context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3554         context->root_hpa = INVALID_PAGE;
3555         context->direct_map = true;
3556         context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3557         context->get_cr3 = get_cr3;
3558         context->get_pdptr = kvm_pdptr_read;
3559         context->inject_page_fault = kvm_inject_page_fault;
3560
3561         if (!is_paging(vcpu)) {
3562                 context->nx = false;
3563                 context->gva_to_gpa = nonpaging_gva_to_gpa;
3564                 context->root_level = 0;
3565         } else if (is_long_mode(vcpu)) {
3566                 context->nx = is_nx(vcpu);
3567                 context->root_level = PT64_ROOT_LEVEL;
3568                 reset_rsvds_bits_mask(vcpu, context);
3569                 context->gva_to_gpa = paging64_gva_to_gpa;
3570         } else if (is_pae(vcpu)) {
3571                 context->nx = is_nx(vcpu);
3572                 context->root_level = PT32E_ROOT_LEVEL;
3573                 reset_rsvds_bits_mask(vcpu, context);
3574                 context->gva_to_gpa = paging64_gva_to_gpa;
3575         } else {
3576                 context->nx = false;
3577                 context->root_level = PT32_ROOT_LEVEL;
3578                 reset_rsvds_bits_mask(vcpu, context);
3579                 context->gva_to_gpa = paging32_gva_to_gpa;
3580         }
3581
3582         return 0;
3583 }
3584
3585 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3586 {
3587         int r;
3588         bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3589         ASSERT(vcpu);
3590         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3591
3592         if (!is_paging(vcpu))
3593                 r = nonpaging_init_context(vcpu, context);
3594         else if (is_long_mode(vcpu))
3595                 r = paging64_init_context(vcpu, context);
3596         else if (is_pae(vcpu))
3597                 r = paging32E_init_context(vcpu, context);
3598         else
3599                 r = paging32_init_context(vcpu, context);
3600
3601         vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3602         vcpu->arch.mmu.base_role.cr0_wp  = is_write_protection(vcpu);
3603         vcpu->arch.mmu.base_role.smep_andnot_wp
3604                 = smep && !is_write_protection(vcpu);
3605
3606         return r;
3607 }
3608 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3609
3610 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3611 {
3612         int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3613
3614         vcpu->arch.walk_mmu->set_cr3           = kvm_x86_ops->set_cr3;
3615         vcpu->arch.walk_mmu->get_cr3           = get_cr3;
3616         vcpu->arch.walk_mmu->get_pdptr         = kvm_pdptr_read;
3617         vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3618
3619         return r;
3620 }
3621
3622 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3623 {
3624         struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3625
3626         g_context->get_cr3           = get_cr3;
3627         g_context->get_pdptr         = kvm_pdptr_read;
3628         g_context->inject_page_fault = kvm_inject_page_fault;
3629
3630         /*
3631          * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3632          * translation of l2_gpa to l1_gpa addresses is done using the
3633          * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3634          * functions between mmu and nested_mmu are swapped.
3635          */
3636         if (!is_paging(vcpu)) {
3637                 g_context->nx = false;
3638                 g_context->root_level = 0;
3639                 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3640         } else if (is_long_mode(vcpu)) {
3641                 g_context->nx = is_nx(vcpu);
3642                 g_context->root_level = PT64_ROOT_LEVEL;
3643                 reset_rsvds_bits_mask(vcpu, g_context);
3644                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3645         } else if (is_pae(vcpu)) {
3646                 g_context->nx = is_nx(vcpu);
3647                 g_context->root_level = PT32E_ROOT_LEVEL;
3648                 reset_rsvds_bits_mask(vcpu, g_context);
3649                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3650         } else {
3651                 g_context->nx = false;
3652                 g_context->root_level = PT32_ROOT_LEVEL;
3653                 reset_rsvds_bits_mask(vcpu, g_context);
3654                 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3655         }
3656
3657         return 0;
3658 }
3659
3660 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3661 {
3662         if (mmu_is_nested(vcpu))
3663                 return init_kvm_nested_mmu(vcpu);
3664         else if (tdp_enabled)
3665                 return init_kvm_tdp_mmu(vcpu);
3666         else
3667                 return init_kvm_softmmu(vcpu);
3668 }
3669
3670 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3671 {
3672         ASSERT(vcpu);
3673         if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3674                 /* mmu.free() should set root_hpa = INVALID_PAGE */
3675                 vcpu->arch.mmu.free(vcpu);
3676 }
3677
3678 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3679 {
3680         destroy_kvm_mmu(vcpu);
3681         return init_kvm_mmu(vcpu);
3682 }
3683 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3684
3685 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3686 {
3687         int r;
3688
3689         r = mmu_topup_memory_caches(vcpu);
3690         if (r)
3691                 goto out;
3692         r = mmu_alloc_roots(vcpu);
3693         spin_lock(&vcpu->kvm->mmu_lock);
3694         mmu_sync_roots(vcpu);
3695         spin_unlock(&vcpu->kvm->mmu_lock);
3696         if (r)
3697                 goto out;
3698         /* set_cr3() should ensure TLB has been flushed */
3699         vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3700 out:
3701         return r;
3702 }
3703 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3704
3705 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3706 {
3707         mmu_free_roots(vcpu);
3708 }
3709 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3710
3711 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3712                                   struct kvm_mmu_page *sp, u64 *spte,
3713                                   const void *new)
3714 {
3715         if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3716                 ++vcpu->kvm->stat.mmu_pde_zapped;
3717                 return;
3718         }
3719
3720         ++vcpu->kvm->stat.mmu_pte_updated;
3721         vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3722 }
3723
3724 static bool need_remote_flush(u64 old, u64 new)
3725 {
3726         if (!is_shadow_present_pte(old))
3727                 return false;
3728         if (!is_shadow_present_pte(new))
3729                 return true;
3730         if ((old ^ new) & PT64_BASE_ADDR_MASK)
3731                 return true;
3732         old ^= PT64_NX_MASK;
3733         new ^= PT64_NX_MASK;
3734         return (old & ~new & PT64_PERM_MASK) != 0;
3735 }
3736
3737 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3738                                     bool remote_flush, bool local_flush)
3739 {
3740         if (zap_page)
3741                 return;
3742
3743         if (remote_flush)
3744                 kvm_flush_remote_tlbs(vcpu->kvm);
3745         else if (local_flush)
3746                 kvm_mmu_flush_tlb(vcpu);
3747 }
3748
3749 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3750                                     const u8 *new, int *bytes)
3751 {
3752         u64 gentry;
3753         int r;
3754
3755         /*
3756          * Assume that the pte write on a page table of the same type
3757          * as the current vcpu paging mode since we update the sptes only
3758          * when they have the same mode.
3759          */
3760         if (is_pae(vcpu) && *bytes == 4) {
3761                 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3762                 *gpa &= ~(gpa_t)7;
3763                 *bytes = 8;
3764                 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, min(*bytes, 8));
3765                 if (r)
3766                         gentry = 0;
3767                 new = (const u8 *)&gentry;
3768         }
3769
3770         switch (*bytes) {
3771         case 4:
3772                 gentry = *(const u32 *)new;
3773                 break;
3774         case 8:
3775                 gentry = *(const u64 *)new;
3776                 break;
3777         default:
3778                 gentry = 0;
3779                 break;
3780         }
3781
3782         return gentry;
3783 }
3784
3785 /*
3786  * If we're seeing too many writes to a page, it may no longer be a page table,
3787  * or we may be forking, in which case it is better to unmap the page.
3788  */
3789 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3790 {
3791         /*
3792          * Skip write-flooding detected for the sp whose level is 1, because
3793          * it can become unsync, then the guest page is not write-protected.
3794          */
3795         if (sp->role.level == PT_PAGE_TABLE_LEVEL)
3796                 return false;
3797
3798         return ++sp->write_flooding_count >= 3;
3799 }
3800
3801 /*
3802  * Misaligned accesses are too much trouble to fix up; also, they usually
3803  * indicate a page is not used as a page table.
3804  */
3805 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3806                                     int bytes)
3807 {
3808         unsigned offset, pte_size, misaligned;
3809
3810         pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3811                  gpa, bytes, sp->role.word);
3812
3813         offset = offset_in_page(gpa);
3814         pte_size = sp->role.cr4_pae ? 8 : 4;
3815
3816         /*
3817          * Sometimes, the OS only writes the last one bytes to update status
3818          * bits, for example, in linux, andb instruction is used in clear_bit().
3819          */
3820         if (!(offset & (pte_size - 1)) && bytes == 1)
3821                 return false;
3822
3823         misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3824         misaligned |= bytes < 4;
3825
3826         return misaligned;
3827 }
3828
3829 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3830 {
3831         unsigned page_offset, quadrant;
3832         u64 *spte;
3833         int level;
3834
3835         page_offset = offset_in_page(gpa);
3836         level = sp->role.level;
3837         *nspte = 1;
3838         if (!sp->role.cr4_pae) {
3839                 page_offset <<= 1;      /* 32->64 */
3840                 /*
3841                  * A 32-bit pde maps 4MB while the shadow pdes map
3842                  * only 2MB.  So we need to double the offset again
3843                  * and zap two pdes instead of one.
3844                  */
3845                 if (level == PT32_ROOT_LEVEL) {
3846                         page_offset &= ~7; /* kill rounding error */
3847                         page_offset <<= 1;
3848                         *nspte = 2;
3849                 }
3850                 quadrant = page_offset >> PAGE_SHIFT;
3851                 page_offset &= ~PAGE_MASK;
3852                 if (quadrant != sp->role.quadrant)
3853                         return NULL;
3854         }
3855
3856         spte = &sp->spt[page_offset / sizeof(*spte)];
3857         return spte;
3858 }
3859
3860 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3861                        const u8 *new, int bytes)
3862 {
3863         gfn_t gfn = gpa >> PAGE_SHIFT;
3864         union kvm_mmu_page_role mask = { .word = 0 };
3865         struct kvm_mmu_page *sp;
3866         struct hlist_node *node;
3867         LIST_HEAD(invalid_list);
3868         u64 entry, gentry, *spte;
3869         int npte;
3870         bool remote_flush, local_flush, zap_page;
3871
3872         /*
3873          * If we don't have indirect shadow pages, it means no page is
3874          * write-protected, so we can exit simply.
3875          */
3876         if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3877                 return;
3878
3879         zap_page = remote_flush = local_flush = false;
3880
3881         pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3882
3883         gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
3884
3885         /*
3886          * No need to care whether allocation memory is successful
3887          * or not since pte prefetch is skiped if it does not have
3888          * enough objects in the cache.
3889          */
3890         mmu_topup_memory_caches(vcpu);
3891
3892         spin_lock(&vcpu->kvm->mmu_lock);
3893         ++vcpu->kvm->stat.mmu_pte_write;
3894         kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3895
3896         mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3897         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3898                 if (detect_write_misaligned(sp, gpa, bytes) ||
3899                       detect_write_flooding(sp)) {
3900                         zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3901                                                      &invalid_list);
3902                         ++vcpu->kvm->stat.mmu_flooded;
3903                         continue;
3904                 }
3905
3906                 spte = get_written_sptes(sp, gpa, &npte);
3907                 if (!spte)
3908                         continue;
3909
3910                 local_flush = true;
3911                 while (npte--) {
3912                         entry = *spte;
3913                         mmu_page_zap_pte(vcpu->kvm, sp, spte);
3914                         if (gentry &&
3915                               !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3916                               & mask.word) && rmap_can_add(vcpu))
3917                                 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3918                         if (!remote_flush && need_remote_flush(entry, *spte))
3919                                 remote_flush = true;
3920                         ++spte;
3921                 }
3922         }
3923         mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3924         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3925         kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3926         spin_unlock(&vcpu->kvm->mmu_lock);
3927 }
3928
3929 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3930 {
3931         gpa_t gpa;
3932         int r;
3933
3934         if (vcpu->arch.mmu.direct_map)
3935                 return 0;
3936
3937         gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3938
3939         r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3940
3941         return r;
3942 }
3943 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3944
3945 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3946 {
3947         LIST_HEAD(invalid_list);
3948
3949         while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3950                !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3951                 struct kvm_mmu_page *sp;
3952
3953                 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3954                                   struct kvm_mmu_page, link);
3955                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3956                 ++vcpu->kvm->stat.mmu_recycled;
3957         }
3958         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3959 }
3960
3961 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
3962 {
3963         if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
3964                 return vcpu_match_mmio_gpa(vcpu, addr);
3965
3966         return vcpu_match_mmio_gva(vcpu, addr);
3967 }
3968
3969 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3970                        void *insn, int insn_len)
3971 {
3972         int r, emulation_type = EMULTYPE_RETRY;
3973         enum emulation_result er;
3974
3975         r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3976         if (r < 0)
3977                 goto out;
3978
3979         if (!r) {
3980                 r = 1;
3981                 goto out;
3982         }
3983
3984         if (is_mmio_page_fault(vcpu, cr2))
3985                 emulation_type = 0;
3986
3987         er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
3988
3989         switch (er) {
3990         case EMULATE_DONE:
3991                 return 1;
3992         case EMULATE_DO_MMIO:
3993                 ++vcpu->stat.mmio_exits;
3994                 /* fall through */
3995         case EMULATE_FAIL:
3996                 return 0;
3997         default:
3998                 BUG();
3999         }
4000 out:
4001         return r;
4002 }
4003 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4004
4005 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4006 {
4007         vcpu->arch.mmu.invlpg(vcpu, gva);
4008         kvm_mmu_flush_tlb(vcpu);
4009         ++vcpu->stat.invlpg;
4010 }
4011 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4012
4013 void kvm_enable_tdp(void)
4014 {
4015         tdp_enabled = true;
4016 }
4017 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4018
4019 void kvm_disable_tdp(void)
4020 {
4021         tdp_enabled = false;
4022 }
4023 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4024
4025 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4026 {
4027         free_page((unsigned long)vcpu->arch.mmu.pae_root);
4028         if (vcpu->arch.mmu.lm_root != NULL)
4029                 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4030 }
4031
4032 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4033 {
4034         struct page *page;
4035         int i;
4036
4037         ASSERT(vcpu);
4038
4039         /*
4040          * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4041          * Therefore we need to allocate shadow page tables in the first
4042          * 4GB of memory, which happens to fit the DMA32 zone.
4043          */
4044         page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4045         if (!page)
4046                 return -ENOMEM;
4047
4048         vcpu->arch.mmu.pae_root = page_address(page);
4049         for (i = 0; i < 4; ++i)
4050                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4051
4052         return 0;
4053 }
4054
4055 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4056 {
4057         ASSERT(vcpu);
4058
4059         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4060         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4061         vcpu->arch.mmu.translate_gpa = translate_gpa;
4062         vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4063
4064         return alloc_mmu_pages(vcpu);
4065 }
4066
4067 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
4068 {
4069         ASSERT(vcpu);
4070         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4071
4072         return init_kvm_mmu(vcpu);
4073 }
4074
4075 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4076 {
4077         struct kvm_mmu_page *sp;
4078         bool flush = false;
4079
4080         list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
4081                 int i;
4082                 u64 *pt;
4083
4084                 if (!test_bit(slot, sp->slot_bitmap))
4085                         continue;
4086
4087                 pt = sp->spt;
4088                 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
4089                         if (!is_shadow_present_pte(pt[i]) ||
4090                               !is_last_spte(pt[i], sp->role.level))
4091                                 continue;
4092
4093                         spte_write_protect(kvm, &pt[i], &flush, false);
4094                 }
4095         }
4096         kvm_flush_remote_tlbs(kvm);
4097 }
4098
4099 void kvm_mmu_zap_all(struct kvm *kvm)
4100 {
4101         struct kvm_mmu_page *sp, *node;
4102         LIST_HEAD(invalid_list);
4103
4104         spin_lock(&kvm->mmu_lock);
4105 restart:
4106         list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
4107                 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
4108                         goto restart;
4109
4110         kvm_mmu_commit_zap_page(kvm, &invalid_list);
4111         spin_unlock(&kvm->mmu_lock);
4112 }
4113
4114 static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
4115                                                 struct list_head *invalid_list)
4116 {
4117         struct kvm_mmu_page *page;
4118
4119         page = container_of(kvm->arch.active_mmu_pages.prev,
4120                             struct kvm_mmu_page, link);
4121         kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
4122 }
4123
4124 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
4125 {
4126         struct kvm *kvm;
4127         int nr_to_scan = sc->nr_to_scan;
4128
4129         if (nr_to_scan == 0)
4130                 goto out;
4131
4132         raw_spin_lock(&kvm_lock);
4133
4134         list_for_each_entry(kvm, &vm_list, vm_list) {
4135                 int idx;
4136                 LIST_HEAD(invalid_list);
4137
4138                 /*
4139                  * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4140                  * here. We may skip a VM instance errorneosly, but we do not
4141                  * want to shrink a VM that only started to populate its MMU
4142                  * anyway.
4143                  */
4144                 if (kvm->arch.n_used_mmu_pages > 0) {
4145                         if (!nr_to_scan--)
4146                                 break;
4147                         continue;
4148                 }
4149
4150                 idx = srcu_read_lock(&kvm->srcu);
4151                 spin_lock(&kvm->mmu_lock);
4152
4153                 kvm_mmu_remove_some_alloc_mmu_pages(kvm, &invalid_list);
4154                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4155
4156                 spin_unlock(&kvm->mmu_lock);
4157                 srcu_read_unlock(&kvm->srcu, idx);
4158
4159                 list_move_tail(&kvm->vm_list, &vm_list);
4160                 break;
4161         }
4162
4163         raw_spin_unlock(&kvm_lock);
4164
4165 out:
4166         return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4167 }
4168
4169 static struct shrinker mmu_shrinker = {
4170         .shrink = mmu_shrink,
4171         .seeks = DEFAULT_SEEKS * 10,
4172 };
4173
4174 static void mmu_destroy_caches(void)
4175 {
4176         if (pte_list_desc_cache)
4177                 kmem_cache_destroy(pte_list_desc_cache);
4178         if (mmu_page_header_cache)
4179                 kmem_cache_destroy(mmu_page_header_cache);
4180 }
4181
4182 int kvm_mmu_module_init(void)
4183 {
4184         pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4185                                             sizeof(struct pte_list_desc),
4186                                             0, 0, NULL);
4187         if (!pte_list_desc_cache)
4188                 goto nomem;
4189
4190         mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4191                                                   sizeof(struct kvm_mmu_page),
4192                                                   0, 0, NULL);
4193         if (!mmu_page_header_cache)
4194                 goto nomem;
4195
4196         if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4197                 goto nomem;
4198
4199         register_shrinker(&mmu_shrinker);
4200
4201         return 0;
4202
4203 nomem:
4204         mmu_destroy_caches();
4205         return -ENOMEM;
4206 }
4207
4208 /*
4209  * Caculate mmu pages needed for kvm.
4210  */
4211 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4212 {
4213         unsigned int nr_mmu_pages;
4214         unsigned int  nr_pages = 0;
4215         struct kvm_memslots *slots;
4216         struct kvm_memory_slot *memslot;
4217
4218         slots = kvm_memslots(kvm);
4219
4220         kvm_for_each_memslot(memslot, slots)
4221                 nr_pages += memslot->npages;
4222
4223         nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4224         nr_mmu_pages = max(nr_mmu_pages,
4225                         (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4226
4227         return nr_mmu_pages;
4228 }
4229
4230 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4231 {
4232         struct kvm_shadow_walk_iterator iterator;
4233         u64 spte;
4234         int nr_sptes = 0;
4235
4236         walk_shadow_page_lockless_begin(vcpu);
4237         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4238                 sptes[iterator.level-1] = spte;
4239                 nr_sptes++;
4240                 if (!is_shadow_present_pte(spte))
4241                         break;
4242         }
4243         walk_shadow_page_lockless_end(vcpu);
4244
4245         return nr_sptes;
4246 }
4247 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4248
4249 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4250 {
4251         ASSERT(vcpu);
4252
4253         destroy_kvm_mmu(vcpu);
4254         free_mmu_pages(vcpu);
4255         mmu_free_memory_caches(vcpu);
4256 }
4257
4258 void kvm_mmu_module_exit(void)
4259 {
4260         mmu_destroy_caches();
4261         percpu_counter_destroy(&kvm_total_used_mmu_pages);
4262         unregister_shrinker(&mmu_shrinker);
4263         mmu_audit_disable();
4264 }