f69fc5077a896e49b56e4d723e90ec6c69eb89cb
[linux-3.10.git] / arch / x86 / kvm / lapic.c
1
2 /*
3  * Local APIC virtualization
4  *
5  * Copyright (C) 2006 Qumranet, Inc.
6  * Copyright (C) 2007 Novell
7  * Copyright (C) 2007 Intel
8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
9  *
10  * Authors:
11  *   Dor Laor <dor.laor@qumranet.com>
12  *   Gregory Haskins <ghaskins@novell.com>
13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
14  *
15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  */
20
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
23 #include <linux/mm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
32 #include <asm/msr.h>
33 #include <asm/page.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include <linux/jump_label.h>
38 #include "kvm_cache_regs.h"
39 #include "irq.h"
40 #include "trace.h"
41 #include "x86.h"
42 #include "cpuid.h"
43
44 #ifndef CONFIG_X86_64
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
46 #else
47 #define mod_64(x, y) ((x) % (y))
48 #endif
49
50 #define PRId64 "d"
51 #define PRIx64 "llx"
52 #define PRIu64 "u"
53 #define PRIo64 "o"
54
55 #define APIC_BUS_CYCLE_NS 1
56
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...)
59
60 #define APIC_LVT_NUM                    6
61 /* 14 is the version for Xeon and Pentium 8.4.8*/
62 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63 #define LAPIC_MMIO_LENGTH               (1 << 12)
64 /* followed define is not in apicdef.h */
65 #define APIC_SHORT_MASK                 0xc0000
66 #define APIC_DEST_NOSHORT               0x0
67 #define APIC_DEST_MASK                  0x800
68 #define MAX_APIC_VECTOR                 256
69 #define APIC_VECTORS_PER_REG            32
70
71 #define VEC_POS(v) ((v) & (32 - 1))
72 #define REG_POS(v) (((v) >> 5) << 4)
73
74 static unsigned int min_timer_period_us = 500;
75 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
76
77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
78 {
79         *((u32 *) (apic->regs + reg_off)) = val;
80 }
81
82 static inline int apic_test_and_set_vector(int vec, void *bitmap)
83 {
84         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
85 }
86
87 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
88 {
89         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
90 }
91
92 static inline int apic_test_vector(int vec, void *bitmap)
93 {
94         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
95 }
96
97 static inline void apic_set_vector(int vec, void *bitmap)
98 {
99         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
100 }
101
102 static inline void apic_clear_vector(int vec, void *bitmap)
103 {
104         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
105 }
106
107 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
108 {
109         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
110 }
111
112 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
113 {
114         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
115 }
116
117 struct static_key_deferred apic_hw_disabled __read_mostly;
118 struct static_key_deferred apic_sw_disabled __read_mostly;
119
120 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
121 {
122         if ((kvm_apic_get_reg(apic, APIC_SPIV) ^ val) & APIC_SPIV_APIC_ENABLED) {
123                 if (val & APIC_SPIV_APIC_ENABLED)
124                         static_key_slow_dec_deferred(&apic_sw_disabled);
125                 else
126                         static_key_slow_inc(&apic_sw_disabled.key);
127         }
128         apic_set_reg(apic, APIC_SPIV, val);
129 }
130
131 static inline int apic_enabled(struct kvm_lapic *apic)
132 {
133         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
134 }
135
136 #define LVT_MASK        \
137         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
138
139 #define LINT_MASK       \
140         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
141          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
142
143 static inline int kvm_apic_id(struct kvm_lapic *apic)
144 {
145         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
146 }
147
148 static inline u16 apic_cluster_id(struct kvm_apic_map *map, u32 ldr)
149 {
150         u16 cid;
151         ldr >>= 32 - map->ldr_bits;
152         cid = (ldr >> map->cid_shift) & map->cid_mask;
153
154         BUG_ON(cid >= ARRAY_SIZE(map->logical_map));
155
156         return cid;
157 }
158
159 static inline u16 apic_logical_id(struct kvm_apic_map *map, u32 ldr)
160 {
161         ldr >>= (32 - map->ldr_bits);
162         return ldr & map->lid_mask;
163 }
164
165 static void recalculate_apic_map(struct kvm *kvm)
166 {
167         struct kvm_apic_map *new, *old = NULL;
168         struct kvm_vcpu *vcpu;
169         int i;
170
171         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
172
173         mutex_lock(&kvm->arch.apic_map_lock);
174
175         if (!new)
176                 goto out;
177
178         new->ldr_bits = 8;
179         /* flat mode is default */
180         new->cid_shift = 8;
181         new->cid_mask = 0;
182         new->lid_mask = 0xff;
183
184         kvm_for_each_vcpu(i, vcpu, kvm) {
185                 struct kvm_lapic *apic = vcpu->arch.apic;
186                 u16 cid, lid;
187                 u32 ldr;
188
189                 if (!kvm_apic_present(vcpu))
190                         continue;
191
192                 /*
193                  * All APICs have to be configured in the same mode by an OS.
194                  * We take advatage of this while building logical id loockup
195                  * table. After reset APICs are in xapic/flat mode, so if we
196                  * find apic with different setting we assume this is the mode
197                  * OS wants all apics to be in; build lookup table accordingly.
198                  */
199                 if (apic_x2apic_mode(apic)) {
200                         new->ldr_bits = 32;
201                         new->cid_shift = 16;
202                         new->cid_mask = new->lid_mask = 0xffff;
203                 } else if (kvm_apic_sw_enabled(apic) &&
204                                 !new->cid_mask /* flat mode */ &&
205                                 kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_CLUSTER) {
206                         new->cid_shift = 4;
207                         new->cid_mask = 0xf;
208                         new->lid_mask = 0xf;
209                 }
210
211                 new->phys_map[kvm_apic_id(apic)] = apic;
212
213                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
214                 cid = apic_cluster_id(new, ldr);
215                 lid = apic_logical_id(new, ldr);
216
217                 if (lid)
218                         new->logical_map[cid][ffs(lid) - 1] = apic;
219         }
220 out:
221         old = rcu_dereference_protected(kvm->arch.apic_map,
222                         lockdep_is_held(&kvm->arch.apic_map_lock));
223         rcu_assign_pointer(kvm->arch.apic_map, new);
224         mutex_unlock(&kvm->arch.apic_map_lock);
225
226         if (old)
227                 kfree_rcu(old, rcu);
228 }
229
230 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
231 {
232         apic_set_reg(apic, APIC_ID, id << 24);
233         recalculate_apic_map(apic->vcpu->kvm);
234 }
235
236 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
237 {
238         apic_set_reg(apic, APIC_LDR, id);
239         recalculate_apic_map(apic->vcpu->kvm);
240 }
241
242 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
243 {
244         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
245 }
246
247 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
248 {
249         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
250 }
251
252 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
253 {
254         return ((kvm_apic_get_reg(apic, APIC_LVTT) &
255                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
256 }
257
258 static inline int apic_lvtt_period(struct kvm_lapic *apic)
259 {
260         return ((kvm_apic_get_reg(apic, APIC_LVTT) &
261                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
262 }
263
264 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
265 {
266         return ((kvm_apic_get_reg(apic, APIC_LVTT) &
267                 apic->lapic_timer.timer_mode_mask) ==
268                         APIC_LVT_TIMER_TSCDEADLINE);
269 }
270
271 static inline int apic_lvt_nmi_mode(u32 lvt_val)
272 {
273         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
274 }
275
276 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
277 {
278         struct kvm_lapic *apic = vcpu->arch.apic;
279         struct kvm_cpuid_entry2 *feat;
280         u32 v = APIC_VERSION;
281
282         if (!kvm_vcpu_has_lapic(vcpu))
283                 return;
284
285         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
286         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
287                 v |= APIC_LVR_DIRECTED_EOI;
288         apic_set_reg(apic, APIC_LVR, v);
289 }
290
291 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
292         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
293         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
294         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
295         LINT_MASK, LINT_MASK,   /* LVT0-1 */
296         LVT_MASK                /* LVTERR */
297 };
298
299 static int find_highest_vector(void *bitmap)
300 {
301         int vec;
302         u32 *reg;
303
304         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
305              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
306                 reg = bitmap + REG_POS(vec);
307                 if (*reg)
308                         return fls(*reg) - 1 + vec;
309         }
310
311         return -1;
312 }
313
314 static u8 count_vectors(void *bitmap)
315 {
316         int vec;
317         u32 *reg;
318         u8 count = 0;
319
320         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
321                 reg = bitmap + REG_POS(vec);
322                 count += hweight32(*reg);
323         }
324
325         return count;
326 }
327
328 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
329 {
330         apic->irr_pending = true;
331         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
332 }
333
334 static inline int apic_search_irr(struct kvm_lapic *apic)
335 {
336         return find_highest_vector(apic->regs + APIC_IRR);
337 }
338
339 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
340 {
341         int result;
342
343         if (!apic->irr_pending)
344                 return -1;
345
346         result = apic_search_irr(apic);
347         ASSERT(result == -1 || result >= 16);
348
349         return result;
350 }
351
352 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
353 {
354         apic->irr_pending = false;
355         apic_clear_vector(vec, apic->regs + APIC_IRR);
356         if (apic_search_irr(apic) != -1)
357                 apic->irr_pending = true;
358 }
359
360 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
361 {
362         if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
363                 ++apic->isr_count;
364         BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
365         /*
366          * ISR (in service register) bit is set when injecting an interrupt.
367          * The highest vector is injected. Thus the latest bit set matches
368          * the highest bit in ISR.
369          */
370         apic->highest_isr_cache = vec;
371 }
372
373 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
374 {
375         if (__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
376                 --apic->isr_count;
377         BUG_ON(apic->isr_count < 0);
378         apic->highest_isr_cache = -1;
379 }
380
381 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
382 {
383         int highest_irr;
384
385         /* This may race with setting of irr in __apic_accept_irq() and
386          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
387          * will cause vmexit immediately and the value will be recalculated
388          * on the next vmentry.
389          */
390         if (!kvm_vcpu_has_lapic(vcpu))
391                 return 0;
392         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
393
394         return highest_irr;
395 }
396
397 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
398                              int vector, int level, int trig_mode);
399
400 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
401 {
402         struct kvm_lapic *apic = vcpu->arch.apic;
403
404         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
405                         irq->level, irq->trig_mode);
406 }
407
408 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
409 {
410
411         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
412                                       sizeof(val));
413 }
414
415 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
416 {
417
418         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
419                                       sizeof(*val));
420 }
421
422 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
423 {
424         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
425 }
426
427 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
428 {
429         u8 val;
430         if (pv_eoi_get_user(vcpu, &val) < 0)
431                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
432                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
433         return val & 0x1;
434 }
435
436 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
437 {
438         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
439                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
440                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
441                 return;
442         }
443         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
444 }
445
446 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
447 {
448         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
449                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
450                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
451                 return;
452         }
453         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
454 }
455
456 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
457 {
458         int result;
459         if (!apic->isr_count)
460                 return -1;
461         if (likely(apic->highest_isr_cache != -1))
462                 return apic->highest_isr_cache;
463
464         result = find_highest_vector(apic->regs + APIC_ISR);
465         ASSERT(result == -1 || result >= 16);
466
467         return result;
468 }
469
470 static void apic_update_ppr(struct kvm_lapic *apic)
471 {
472         u32 tpr, isrv, ppr, old_ppr;
473         int isr;
474
475         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
476         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
477         isr = apic_find_highest_isr(apic);
478         isrv = (isr != -1) ? isr : 0;
479
480         if ((tpr & 0xf0) >= (isrv & 0xf0))
481                 ppr = tpr & 0xff;
482         else
483                 ppr = isrv & 0xf0;
484
485         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
486                    apic, ppr, isr, isrv);
487
488         if (old_ppr != ppr) {
489                 apic_set_reg(apic, APIC_PROCPRI, ppr);
490                 if (ppr < old_ppr)
491                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
492         }
493 }
494
495 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
496 {
497         apic_set_reg(apic, APIC_TASKPRI, tpr);
498         apic_update_ppr(apic);
499 }
500
501 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
502 {
503         return dest == 0xff || kvm_apic_id(apic) == dest;
504 }
505
506 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
507 {
508         int result = 0;
509         u32 logical_id;
510
511         if (apic_x2apic_mode(apic)) {
512                 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
513                 return logical_id & mda;
514         }
515
516         logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
517
518         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
519         case APIC_DFR_FLAT:
520                 if (logical_id & mda)
521                         result = 1;
522                 break;
523         case APIC_DFR_CLUSTER:
524                 if (((logical_id >> 4) == (mda >> 0x4))
525                     && (logical_id & mda & 0xf))
526                         result = 1;
527                 break;
528         default:
529                 apic_debug("Bad DFR vcpu %d: %08x\n",
530                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
531                 break;
532         }
533
534         return result;
535 }
536
537 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
538                            int short_hand, int dest, int dest_mode)
539 {
540         int result = 0;
541         struct kvm_lapic *target = vcpu->arch.apic;
542
543         apic_debug("target %p, source %p, dest 0x%x, "
544                    "dest_mode 0x%x, short_hand 0x%x\n",
545                    target, source, dest, dest_mode, short_hand);
546
547         ASSERT(target);
548         switch (short_hand) {
549         case APIC_DEST_NOSHORT:
550                 if (dest_mode == 0)
551                         /* Physical mode. */
552                         result = kvm_apic_match_physical_addr(target, dest);
553                 else
554                         /* Logical mode. */
555                         result = kvm_apic_match_logical_addr(target, dest);
556                 break;
557         case APIC_DEST_SELF:
558                 result = (target == source);
559                 break;
560         case APIC_DEST_ALLINC:
561                 result = 1;
562                 break;
563         case APIC_DEST_ALLBUT:
564                 result = (target != source);
565                 break;
566         default:
567                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
568                            short_hand);
569                 break;
570         }
571
572         return result;
573 }
574
575 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
576                 struct kvm_lapic_irq *irq, int *r)
577 {
578         struct kvm_apic_map *map;
579         unsigned long bitmap = 1;
580         struct kvm_lapic **dst;
581         int i;
582         bool ret = false;
583
584         *r = -1;
585
586         if (irq->shorthand == APIC_DEST_SELF) {
587                 *r = kvm_apic_set_irq(src->vcpu, irq);
588                 return true;
589         }
590
591         if (irq->shorthand)
592                 return false;
593
594         rcu_read_lock();
595         map = rcu_dereference(kvm->arch.apic_map);
596
597         if (!map)
598                 goto out;
599
600         if (irq->dest_mode == 0) { /* physical mode */
601                 if (irq->delivery_mode == APIC_DM_LOWEST ||
602                                 irq->dest_id == 0xff)
603                         goto out;
604                 dst = &map->phys_map[irq->dest_id & 0xff];
605         } else {
606                 u32 mda = irq->dest_id << (32 - map->ldr_bits);
607
608                 dst = map->logical_map[apic_cluster_id(map, mda)];
609
610                 bitmap = apic_logical_id(map, mda);
611
612                 if (irq->delivery_mode == APIC_DM_LOWEST) {
613                         int l = -1;
614                         for_each_set_bit(i, &bitmap, 16) {
615                                 if (!dst[i])
616                                         continue;
617                                 if (l < 0)
618                                         l = i;
619                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
620                                         l = i;
621                         }
622
623                         bitmap = (l >= 0) ? 1 << l : 0;
624                 }
625         }
626
627         for_each_set_bit(i, &bitmap, 16) {
628                 if (!dst[i])
629                         continue;
630                 if (*r < 0)
631                         *r = 0;
632                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq);
633         }
634
635         ret = true;
636 out:
637         rcu_read_unlock();
638         return ret;
639 }
640
641 /*
642  * Add a pending IRQ into lapic.
643  * Return 1 if successfully added and 0 if discarded.
644  */
645 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
646                              int vector, int level, int trig_mode)
647 {
648         int result = 0;
649         struct kvm_vcpu *vcpu = apic->vcpu;
650
651         switch (delivery_mode) {
652         case APIC_DM_LOWEST:
653                 vcpu->arch.apic_arb_prio++;
654         case APIC_DM_FIXED:
655                 /* FIXME add logic for vcpu on reset */
656                 if (unlikely(!apic_enabled(apic)))
657                         break;
658
659                 if (trig_mode) {
660                         apic_debug("level trig mode for vector %d", vector);
661                         apic_set_vector(vector, apic->regs + APIC_TMR);
662                 } else
663                         apic_clear_vector(vector, apic->regs + APIC_TMR);
664
665                 result = !apic_test_and_set_irr(vector, apic);
666                 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
667                                           trig_mode, vector, !result);
668                 if (!result) {
669                         if (trig_mode)
670                                 apic_debug("level trig mode repeatedly for "
671                                                 "vector %d", vector);
672                         break;
673                 }
674
675                 kvm_make_request(KVM_REQ_EVENT, vcpu);
676                 kvm_vcpu_kick(vcpu);
677                 break;
678
679         case APIC_DM_REMRD:
680                 apic_debug("Ignoring delivery mode 3\n");
681                 break;
682
683         case APIC_DM_SMI:
684                 apic_debug("Ignoring guest SMI\n");
685                 break;
686
687         case APIC_DM_NMI:
688                 result = 1;
689                 kvm_inject_nmi(vcpu);
690                 kvm_vcpu_kick(vcpu);
691                 break;
692
693         case APIC_DM_INIT:
694                 if (!trig_mode || level) {
695                         result = 1;
696                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
697                         kvm_make_request(KVM_REQ_EVENT, vcpu);
698                         kvm_vcpu_kick(vcpu);
699                 } else {
700                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
701                                    vcpu->vcpu_id);
702                 }
703                 break;
704
705         case APIC_DM_STARTUP:
706                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
707                            vcpu->vcpu_id, vector);
708                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
709                         result = 1;
710                         vcpu->arch.sipi_vector = vector;
711                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
712                         kvm_make_request(KVM_REQ_EVENT, vcpu);
713                         kvm_vcpu_kick(vcpu);
714                 }
715                 break;
716
717         case APIC_DM_EXTINT:
718                 /*
719                  * Should only be called by kvm_apic_local_deliver() with LVT0,
720                  * before NMI watchdog was enabled. Already handled by
721                  * kvm_apic_accept_pic_intr().
722                  */
723                 break;
724
725         default:
726                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
727                        delivery_mode);
728                 break;
729         }
730         return result;
731 }
732
733 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
734 {
735         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
736 }
737
738 static int apic_set_eoi(struct kvm_lapic *apic)
739 {
740         int vector = apic_find_highest_isr(apic);
741
742         trace_kvm_eoi(apic, vector);
743
744         /*
745          * Not every write EOI will has corresponding ISR,
746          * one example is when Kernel check timer on setup_IO_APIC
747          */
748         if (vector == -1)
749                 return vector;
750
751         apic_clear_isr(vector, apic);
752         apic_update_ppr(apic);
753
754         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
755             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
756                 int trigger_mode;
757                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
758                         trigger_mode = IOAPIC_LEVEL_TRIG;
759                 else
760                         trigger_mode = IOAPIC_EDGE_TRIG;
761                 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
762         }
763         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
764         return vector;
765 }
766
767 static void apic_send_ipi(struct kvm_lapic *apic)
768 {
769         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
770         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
771         struct kvm_lapic_irq irq;
772
773         irq.vector = icr_low & APIC_VECTOR_MASK;
774         irq.delivery_mode = icr_low & APIC_MODE_MASK;
775         irq.dest_mode = icr_low & APIC_DEST_MASK;
776         irq.level = icr_low & APIC_INT_ASSERT;
777         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
778         irq.shorthand = icr_low & APIC_SHORT_MASK;
779         if (apic_x2apic_mode(apic))
780                 irq.dest_id = icr_high;
781         else
782                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
783
784         trace_kvm_apic_ipi(icr_low, irq.dest_id);
785
786         apic_debug("icr_high 0x%x, icr_low 0x%x, "
787                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
788                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
789                    icr_high, icr_low, irq.shorthand, irq.dest_id,
790                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
791                    irq.vector);
792
793         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
794 }
795
796 static u32 apic_get_tmcct(struct kvm_lapic *apic)
797 {
798         ktime_t remaining;
799         s64 ns;
800         u32 tmcct;
801
802         ASSERT(apic != NULL);
803
804         /* if initial count is 0, current count should also be 0 */
805         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0)
806                 return 0;
807
808         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
809         if (ktime_to_ns(remaining) < 0)
810                 remaining = ktime_set(0, 0);
811
812         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
813         tmcct = div64_u64(ns,
814                          (APIC_BUS_CYCLE_NS * apic->divide_count));
815
816         return tmcct;
817 }
818
819 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
820 {
821         struct kvm_vcpu *vcpu = apic->vcpu;
822         struct kvm_run *run = vcpu->run;
823
824         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
825         run->tpr_access.rip = kvm_rip_read(vcpu);
826         run->tpr_access.is_write = write;
827 }
828
829 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
830 {
831         if (apic->vcpu->arch.tpr_access_reporting)
832                 __report_tpr_access(apic, write);
833 }
834
835 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
836 {
837         u32 val = 0;
838
839         if (offset >= LAPIC_MMIO_LENGTH)
840                 return 0;
841
842         switch (offset) {
843         case APIC_ID:
844                 if (apic_x2apic_mode(apic))
845                         val = kvm_apic_id(apic);
846                 else
847                         val = kvm_apic_id(apic) << 24;
848                 break;
849         case APIC_ARBPRI:
850                 apic_debug("Access APIC ARBPRI register which is for P6\n");
851                 break;
852
853         case APIC_TMCCT:        /* Timer CCR */
854                 if (apic_lvtt_tscdeadline(apic))
855                         return 0;
856
857                 val = apic_get_tmcct(apic);
858                 break;
859         case APIC_PROCPRI:
860                 apic_update_ppr(apic);
861                 val = kvm_apic_get_reg(apic, offset);
862                 break;
863         case APIC_TASKPRI:
864                 report_tpr_access(apic, false);
865                 /* fall thru */
866         default:
867                 val = kvm_apic_get_reg(apic, offset);
868                 break;
869         }
870
871         return val;
872 }
873
874 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
875 {
876         return container_of(dev, struct kvm_lapic, dev);
877 }
878
879 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
880                 void *data)
881 {
882         unsigned char alignment = offset & 0xf;
883         u32 result;
884         /* this bitmask has a bit cleared for each reserved register */
885         static const u64 rmask = 0x43ff01ffffffe70cULL;
886
887         if ((alignment + len) > 4) {
888                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
889                            offset, len);
890                 return 1;
891         }
892
893         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
894                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
895                            offset);
896                 return 1;
897         }
898
899         result = __apic_read(apic, offset & ~0xf);
900
901         trace_kvm_apic_read(offset, result);
902
903         switch (len) {
904         case 1:
905         case 2:
906         case 4:
907                 memcpy(data, (char *)&result + alignment, len);
908                 break;
909         default:
910                 printk(KERN_ERR "Local APIC read with len = %x, "
911                        "should be 1,2, or 4 instead\n", len);
912                 break;
913         }
914         return 0;
915 }
916
917 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
918 {
919         return kvm_apic_hw_enabled(apic) &&
920             addr >= apic->base_address &&
921             addr < apic->base_address + LAPIC_MMIO_LENGTH;
922 }
923
924 static int apic_mmio_read(struct kvm_io_device *this,
925                            gpa_t address, int len, void *data)
926 {
927         struct kvm_lapic *apic = to_lapic(this);
928         u32 offset = address - apic->base_address;
929
930         if (!apic_mmio_in_range(apic, address))
931                 return -EOPNOTSUPP;
932
933         apic_reg_read(apic, offset, len, data);
934
935         return 0;
936 }
937
938 static void update_divide_count(struct kvm_lapic *apic)
939 {
940         u32 tmp1, tmp2, tdcr;
941
942         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
943         tmp1 = tdcr & 0xf;
944         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
945         apic->divide_count = 0x1 << (tmp2 & 0x7);
946
947         apic_debug("timer divide count is 0x%x\n",
948                                    apic->divide_count);
949 }
950
951 static void start_apic_timer(struct kvm_lapic *apic)
952 {
953         ktime_t now;
954         atomic_set(&apic->lapic_timer.pending, 0);
955
956         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
957                 /* lapic timer in oneshot or periodic mode */
958                 now = apic->lapic_timer.timer.base->get_time();
959                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
960                             * APIC_BUS_CYCLE_NS * apic->divide_count;
961
962                 if (!apic->lapic_timer.period)
963                         return;
964                 /*
965                  * Do not allow the guest to program periodic timers with small
966                  * interval, since the hrtimers are not throttled by the host
967                  * scheduler.
968                  */
969                 if (apic_lvtt_period(apic)) {
970                         s64 min_period = min_timer_period_us * 1000LL;
971
972                         if (apic->lapic_timer.period < min_period) {
973                                 pr_info_ratelimited(
974                                     "kvm: vcpu %i: requested %lld ns "
975                                     "lapic timer period limited to %lld ns\n",
976                                     apic->vcpu->vcpu_id,
977                                     apic->lapic_timer.period, min_period);
978                                 apic->lapic_timer.period = min_period;
979                         }
980                 }
981
982                 hrtimer_start(&apic->lapic_timer.timer,
983                               ktime_add_ns(now, apic->lapic_timer.period),
984                               HRTIMER_MODE_ABS);
985
986                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
987                            PRIx64 ", "
988                            "timer initial count 0x%x, period %lldns, "
989                            "expire @ 0x%016" PRIx64 ".\n", __func__,
990                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
991                            kvm_apic_get_reg(apic, APIC_TMICT),
992                            apic->lapic_timer.period,
993                            ktime_to_ns(ktime_add_ns(now,
994                                         apic->lapic_timer.period)));
995         } else if (apic_lvtt_tscdeadline(apic)) {
996                 /* lapic timer in tsc deadline mode */
997                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
998                 u64 ns = 0;
999                 struct kvm_vcpu *vcpu = apic->vcpu;
1000                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1001                 unsigned long flags;
1002
1003                 if (unlikely(!tscdeadline || !this_tsc_khz))
1004                         return;
1005
1006                 local_irq_save(flags);
1007
1008                 now = apic->lapic_timer.timer.base->get_time();
1009                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1010                 if (likely(tscdeadline > guest_tsc)) {
1011                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1012                         do_div(ns, this_tsc_khz);
1013                 }
1014                 hrtimer_start(&apic->lapic_timer.timer,
1015                         ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1016
1017                 local_irq_restore(flags);
1018         }
1019 }
1020
1021 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1022 {
1023         int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1024
1025         if (apic_lvt_nmi_mode(lvt0_val)) {
1026                 if (!nmi_wd_enabled) {
1027                         apic_debug("Receive NMI setting on APIC_LVT0 "
1028                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1029                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1030                 }
1031         } else if (nmi_wd_enabled)
1032                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1033 }
1034
1035 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1036 {
1037         int ret = 0;
1038
1039         trace_kvm_apic_write(reg, val);
1040
1041         switch (reg) {
1042         case APIC_ID:           /* Local APIC ID */
1043                 if (!apic_x2apic_mode(apic))
1044                         kvm_apic_set_id(apic, val >> 24);
1045                 else
1046                         ret = 1;
1047                 break;
1048
1049         case APIC_TASKPRI:
1050                 report_tpr_access(apic, true);
1051                 apic_set_tpr(apic, val & 0xff);
1052                 break;
1053
1054         case APIC_EOI:
1055                 apic_set_eoi(apic);
1056                 break;
1057
1058         case APIC_LDR:
1059                 if (!apic_x2apic_mode(apic))
1060                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1061                 else
1062                         ret = 1;
1063                 break;
1064
1065         case APIC_DFR:
1066                 if (!apic_x2apic_mode(apic)) {
1067                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1068                         recalculate_apic_map(apic->vcpu->kvm);
1069                 } else
1070                         ret = 1;
1071                 break;
1072
1073         case APIC_SPIV: {
1074                 u32 mask = 0x3ff;
1075                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1076                         mask |= APIC_SPIV_DIRECTED_EOI;
1077                 apic_set_spiv(apic, val & mask);
1078                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1079                         int i;
1080                         u32 lvt_val;
1081
1082                         for (i = 0; i < APIC_LVT_NUM; i++) {
1083                                 lvt_val = kvm_apic_get_reg(apic,
1084                                                        APIC_LVTT + 0x10 * i);
1085                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1086                                              lvt_val | APIC_LVT_MASKED);
1087                         }
1088                         atomic_set(&apic->lapic_timer.pending, 0);
1089
1090                 }
1091                 break;
1092         }
1093         case APIC_ICR:
1094                 /* No delay here, so we always clear the pending bit */
1095                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1096                 apic_send_ipi(apic);
1097                 break;
1098
1099         case APIC_ICR2:
1100                 if (!apic_x2apic_mode(apic))
1101                         val &= 0xff000000;
1102                 apic_set_reg(apic, APIC_ICR2, val);
1103                 break;
1104
1105         case APIC_LVT0:
1106                 apic_manage_nmi_watchdog(apic, val);
1107         case APIC_LVTTHMR:
1108         case APIC_LVTPC:
1109         case APIC_LVT1:
1110         case APIC_LVTERR:
1111                 /* TODO: Check vector */
1112                 if (!kvm_apic_sw_enabled(apic))
1113                         val |= APIC_LVT_MASKED;
1114
1115                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1116                 apic_set_reg(apic, reg, val);
1117
1118                 break;
1119
1120         case APIC_LVTT:
1121                 if ((kvm_apic_get_reg(apic, APIC_LVTT) &
1122                     apic->lapic_timer.timer_mode_mask) !=
1123                    (val & apic->lapic_timer.timer_mode_mask))
1124                         hrtimer_cancel(&apic->lapic_timer.timer);
1125
1126                 if (!kvm_apic_sw_enabled(apic))
1127                         val |= APIC_LVT_MASKED;
1128                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1129                 apic_set_reg(apic, APIC_LVTT, val);
1130                 break;
1131
1132         case APIC_TMICT:
1133                 if (apic_lvtt_tscdeadline(apic))
1134                         break;
1135
1136                 hrtimer_cancel(&apic->lapic_timer.timer);
1137                 apic_set_reg(apic, APIC_TMICT, val);
1138                 start_apic_timer(apic);
1139                 break;
1140
1141         case APIC_TDCR:
1142                 if (val & 4)
1143                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1144                 apic_set_reg(apic, APIC_TDCR, val);
1145                 update_divide_count(apic);
1146                 break;
1147
1148         case APIC_ESR:
1149                 if (apic_x2apic_mode(apic) && val != 0) {
1150                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1151                         ret = 1;
1152                 }
1153                 break;
1154
1155         case APIC_SELF_IPI:
1156                 if (apic_x2apic_mode(apic)) {
1157                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1158                 } else
1159                         ret = 1;
1160                 break;
1161         default:
1162                 ret = 1;
1163                 break;
1164         }
1165         if (ret)
1166                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1167         return ret;
1168 }
1169
1170 static int apic_mmio_write(struct kvm_io_device *this,
1171                             gpa_t address, int len, const void *data)
1172 {
1173         struct kvm_lapic *apic = to_lapic(this);
1174         unsigned int offset = address - apic->base_address;
1175         u32 val;
1176
1177         if (!apic_mmio_in_range(apic, address))
1178                 return -EOPNOTSUPP;
1179
1180         /*
1181          * APIC register must be aligned on 128-bits boundary.
1182          * 32/64/128 bits registers must be accessed thru 32 bits.
1183          * Refer SDM 8.4.1
1184          */
1185         if (len != 4 || (offset & 0xf)) {
1186                 /* Don't shout loud, $infamous_os would cause only noise. */
1187                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1188                 return 0;
1189         }
1190
1191         val = *(u32*)data;
1192
1193         /* too common printing */
1194         if (offset != APIC_EOI)
1195                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1196                            "0x%x\n", __func__, offset, len, val);
1197
1198         apic_reg_write(apic, offset & 0xff0, val);
1199
1200         return 0;
1201 }
1202
1203 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1204 {
1205         if (kvm_vcpu_has_lapic(vcpu))
1206                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1207 }
1208 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1209
1210 /* emulate APIC access in a trap manner */
1211 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1212 {
1213         u32 val = 0;
1214
1215         /* hw has done the conditional check and inst decode */
1216         offset &= 0xff0;
1217
1218         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1219
1220         /* TODO: optimize to just emulate side effect w/o one more write */
1221         apic_reg_write(vcpu->arch.apic, offset, val);
1222 }
1223 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1224
1225 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1226 {
1227         struct kvm_lapic *apic = vcpu->arch.apic;
1228
1229         if (!vcpu->arch.apic)
1230                 return;
1231
1232         hrtimer_cancel(&apic->lapic_timer.timer);
1233
1234         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1235                 static_key_slow_dec_deferred(&apic_hw_disabled);
1236
1237         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED))
1238                 static_key_slow_dec_deferred(&apic_sw_disabled);
1239
1240         if (apic->regs)
1241                 free_page((unsigned long)apic->regs);
1242
1243         kfree(apic);
1244 }
1245
1246 /*
1247  *----------------------------------------------------------------------
1248  * LAPIC interface
1249  *----------------------------------------------------------------------
1250  */
1251
1252 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1253 {
1254         struct kvm_lapic *apic = vcpu->arch.apic;
1255
1256         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1257                         apic_lvtt_period(apic))
1258                 return 0;
1259
1260         return apic->lapic_timer.tscdeadline;
1261 }
1262
1263 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1264 {
1265         struct kvm_lapic *apic = vcpu->arch.apic;
1266
1267         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1268                         apic_lvtt_period(apic))
1269                 return;
1270
1271         hrtimer_cancel(&apic->lapic_timer.timer);
1272         apic->lapic_timer.tscdeadline = data;
1273         start_apic_timer(apic);
1274 }
1275
1276 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1277 {
1278         struct kvm_lapic *apic = vcpu->arch.apic;
1279
1280         if (!kvm_vcpu_has_lapic(vcpu))
1281                 return;
1282
1283         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1284                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1285 }
1286
1287 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1288 {
1289         u64 tpr;
1290
1291         if (!kvm_vcpu_has_lapic(vcpu))
1292                 return 0;
1293
1294         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1295
1296         return (tpr & 0xf0) >> 4;
1297 }
1298
1299 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1300 {
1301         u64 old_value = vcpu->arch.apic_base;
1302         struct kvm_lapic *apic = vcpu->arch.apic;
1303
1304         if (!apic) {
1305                 value |= MSR_IA32_APICBASE_BSP;
1306                 vcpu->arch.apic_base = value;
1307                 return;
1308         }
1309
1310         /* update jump label if enable bit changes */
1311         if ((vcpu->arch.apic_base ^ value) & MSR_IA32_APICBASE_ENABLE) {
1312                 if (value & MSR_IA32_APICBASE_ENABLE)
1313                         static_key_slow_dec_deferred(&apic_hw_disabled);
1314                 else
1315                         static_key_slow_inc(&apic_hw_disabled.key);
1316                 recalculate_apic_map(vcpu->kvm);
1317         }
1318
1319         if (!kvm_vcpu_is_bsp(apic->vcpu))
1320                 value &= ~MSR_IA32_APICBASE_BSP;
1321
1322         vcpu->arch.apic_base = value;
1323         if ((old_value ^ value) & X2APIC_ENABLE) {
1324                 if (value & X2APIC_ENABLE) {
1325                         u32 id = kvm_apic_id(apic);
1326                         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1327                         kvm_apic_set_ldr(apic, ldr);
1328                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1329                 } else
1330                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1331         }
1332
1333         apic->base_address = apic->vcpu->arch.apic_base &
1334                              MSR_IA32_APICBASE_BASE;
1335
1336         /* with FSB delivery interrupt, we can restart APIC functionality */
1337         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1338                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1339
1340 }
1341
1342 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1343 {
1344         struct kvm_lapic *apic;
1345         int i;
1346
1347         apic_debug("%s\n", __func__);
1348
1349         ASSERT(vcpu);
1350         apic = vcpu->arch.apic;
1351         ASSERT(apic != NULL);
1352
1353         /* Stop the timer in case it's a reset to an active apic */
1354         hrtimer_cancel(&apic->lapic_timer.timer);
1355
1356         kvm_apic_set_id(apic, vcpu->vcpu_id);
1357         kvm_apic_set_version(apic->vcpu);
1358
1359         for (i = 0; i < APIC_LVT_NUM; i++)
1360                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1361         apic_set_reg(apic, APIC_LVT0,
1362                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1363
1364         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1365         apic_set_spiv(apic, 0xff);
1366         apic_set_reg(apic, APIC_TASKPRI, 0);
1367         kvm_apic_set_ldr(apic, 0);
1368         apic_set_reg(apic, APIC_ESR, 0);
1369         apic_set_reg(apic, APIC_ICR, 0);
1370         apic_set_reg(apic, APIC_ICR2, 0);
1371         apic_set_reg(apic, APIC_TDCR, 0);
1372         apic_set_reg(apic, APIC_TMICT, 0);
1373         for (i = 0; i < 8; i++) {
1374                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1375                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1376                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1377         }
1378         apic->irr_pending = false;
1379         apic->isr_count = 0;
1380         apic->highest_isr_cache = -1;
1381         update_divide_count(apic);
1382         atomic_set(&apic->lapic_timer.pending, 0);
1383         if (kvm_vcpu_is_bsp(vcpu))
1384                 kvm_lapic_set_base(vcpu,
1385                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1386         vcpu->arch.pv_eoi.msr_val = 0;
1387         apic_update_ppr(apic);
1388
1389         vcpu->arch.apic_arb_prio = 0;
1390         vcpu->arch.apic_attention = 0;
1391
1392         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1393                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1394                    vcpu, kvm_apic_id(apic),
1395                    vcpu->arch.apic_base, apic->base_address);
1396 }
1397
1398 /*
1399  *----------------------------------------------------------------------
1400  * timer interface
1401  *----------------------------------------------------------------------
1402  */
1403
1404 static bool lapic_is_periodic(struct kvm_lapic *apic)
1405 {
1406         return apic_lvtt_period(apic);
1407 }
1408
1409 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1410 {
1411         struct kvm_lapic *apic = vcpu->arch.apic;
1412
1413         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1414                         apic_lvt_enabled(apic, APIC_LVTT))
1415                 return atomic_read(&apic->lapic_timer.pending);
1416
1417         return 0;
1418 }
1419
1420 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1421 {
1422         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1423         int vector, mode, trig_mode;
1424
1425         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1426                 vector = reg & APIC_VECTOR_MASK;
1427                 mode = reg & APIC_MODE_MASK;
1428                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1429                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1430         }
1431         return 0;
1432 }
1433
1434 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1435 {
1436         struct kvm_lapic *apic = vcpu->arch.apic;
1437
1438         if (apic)
1439                 kvm_apic_local_deliver(apic, APIC_LVT0);
1440 }
1441
1442 static const struct kvm_io_device_ops apic_mmio_ops = {
1443         .read     = apic_mmio_read,
1444         .write    = apic_mmio_write,
1445 };
1446
1447 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1448 {
1449         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1450         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1451         struct kvm_vcpu *vcpu = apic->vcpu;
1452         wait_queue_head_t *q = &vcpu->wq;
1453
1454         /*
1455          * There is a race window between reading and incrementing, but we do
1456          * not care about potentially losing timer events in the !reinject
1457          * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked
1458          * in vcpu_enter_guest.
1459          */
1460         if (!atomic_read(&ktimer->pending)) {
1461                 atomic_inc(&ktimer->pending);
1462                 /* FIXME: this code should not know anything about vcpus */
1463                 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1464         }
1465
1466         if (waitqueue_active(q))
1467                 wake_up_interruptible(q);
1468
1469         if (lapic_is_periodic(apic)) {
1470                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1471                 return HRTIMER_RESTART;
1472         } else
1473                 return HRTIMER_NORESTART;
1474 }
1475
1476 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1477 {
1478         struct kvm_lapic *apic;
1479
1480         ASSERT(vcpu != NULL);
1481         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1482
1483         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1484         if (!apic)
1485                 goto nomem;
1486
1487         vcpu->arch.apic = apic;
1488
1489         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1490         if (!apic->regs) {
1491                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1492                        vcpu->vcpu_id);
1493                 goto nomem_free_apic;
1494         }
1495         apic->vcpu = vcpu;
1496
1497         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1498                      HRTIMER_MODE_ABS);
1499         apic->lapic_timer.timer.function = apic_timer_fn;
1500
1501         /*
1502          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1503          * thinking that APIC satet has changed.
1504          */
1505         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1506         kvm_lapic_set_base(vcpu,
1507                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1508
1509         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1510         kvm_lapic_reset(vcpu);
1511         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1512
1513         return 0;
1514 nomem_free_apic:
1515         kfree(apic);
1516 nomem:
1517         return -ENOMEM;
1518 }
1519
1520 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1521 {
1522         struct kvm_lapic *apic = vcpu->arch.apic;
1523         int highest_irr;
1524
1525         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1526                 return -1;
1527
1528         apic_update_ppr(apic);
1529         highest_irr = apic_find_highest_irr(apic);
1530         if ((highest_irr == -1) ||
1531             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1532                 return -1;
1533         return highest_irr;
1534 }
1535
1536 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1537 {
1538         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1539         int r = 0;
1540
1541         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1542                 r = 1;
1543         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1544             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1545                 r = 1;
1546         return r;
1547 }
1548
1549 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1550 {
1551         struct kvm_lapic *apic = vcpu->arch.apic;
1552
1553         if (!kvm_vcpu_has_lapic(vcpu))
1554                 return;
1555
1556         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1557                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1558                         atomic_dec(&apic->lapic_timer.pending);
1559         }
1560 }
1561
1562 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1563 {
1564         int vector = kvm_apic_has_interrupt(vcpu);
1565         struct kvm_lapic *apic = vcpu->arch.apic;
1566
1567         if (vector == -1)
1568                 return -1;
1569
1570         apic_set_isr(vector, apic);
1571         apic_update_ppr(apic);
1572         apic_clear_irr(vector, apic);
1573         return vector;
1574 }
1575
1576 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1577                 struct kvm_lapic_state *s)
1578 {
1579         struct kvm_lapic *apic = vcpu->arch.apic;
1580
1581         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1582         /* set SPIV separately to get count of SW disabled APICs right */
1583         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1584         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1585         /* call kvm_apic_set_id() to put apic into apic_map */
1586         kvm_apic_set_id(apic, kvm_apic_id(apic));
1587         kvm_apic_set_version(vcpu);
1588
1589         apic_update_ppr(apic);
1590         hrtimer_cancel(&apic->lapic_timer.timer);
1591         update_divide_count(apic);
1592         start_apic_timer(apic);
1593         apic->irr_pending = true;
1594         apic->isr_count = count_vectors(apic->regs + APIC_ISR);
1595         apic->highest_isr_cache = -1;
1596         kvm_make_request(KVM_REQ_EVENT, vcpu);
1597 }
1598
1599 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1600 {
1601         struct hrtimer *timer;
1602
1603         if (!kvm_vcpu_has_lapic(vcpu))
1604                 return;
1605
1606         timer = &vcpu->arch.apic->lapic_timer.timer;
1607         if (hrtimer_cancel(timer))
1608                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1609 }
1610
1611 /*
1612  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1613  *
1614  * Detect whether guest triggered PV EOI since the
1615  * last entry. If yes, set EOI on guests's behalf.
1616  * Clear PV EOI in guest memory in any case.
1617  */
1618 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1619                                         struct kvm_lapic *apic)
1620 {
1621         bool pending;
1622         int vector;
1623         /*
1624          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1625          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1626          *
1627          * KVM_APIC_PV_EOI_PENDING is unset:
1628          *      -> host disabled PV EOI.
1629          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1630          *      -> host enabled PV EOI, guest did not execute EOI yet.
1631          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1632          *      -> host enabled PV EOI, guest executed EOI.
1633          */
1634         BUG_ON(!pv_eoi_enabled(vcpu));
1635         pending = pv_eoi_get_pending(vcpu);
1636         /*
1637          * Clear pending bit in any case: it will be set again on vmentry.
1638          * While this might not be ideal from performance point of view,
1639          * this makes sure pv eoi is only enabled when we know it's safe.
1640          */
1641         pv_eoi_clr_pending(vcpu);
1642         if (pending)
1643                 return;
1644         vector = apic_set_eoi(apic);
1645         trace_kvm_pv_eoi(apic, vector);
1646 }
1647
1648 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1649 {
1650         u32 data;
1651         void *vapic;
1652
1653         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1654                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1655
1656         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1657                 return;
1658
1659         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1660         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1661         kunmap_atomic(vapic);
1662
1663         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1664 }
1665
1666 /*
1667  * apic_sync_pv_eoi_to_guest - called before vmentry
1668  *
1669  * Detect whether it's safe to enable PV EOI and
1670  * if yes do so.
1671  */
1672 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1673                                         struct kvm_lapic *apic)
1674 {
1675         if (!pv_eoi_enabled(vcpu) ||
1676             /* IRR set or many bits in ISR: could be nested. */
1677             apic->irr_pending ||
1678             /* Cache not set: could be safe but we don't bother. */
1679             apic->highest_isr_cache == -1 ||
1680             /* Need EOI to update ioapic. */
1681             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1682                 /*
1683                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1684                  * so we need not do anything here.
1685                  */
1686                 return;
1687         }
1688
1689         pv_eoi_set_pending(apic->vcpu);
1690 }
1691
1692 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1693 {
1694         u32 data, tpr;
1695         int max_irr, max_isr;
1696         struct kvm_lapic *apic = vcpu->arch.apic;
1697         void *vapic;
1698
1699         apic_sync_pv_eoi_to_guest(vcpu, apic);
1700
1701         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1702                 return;
1703
1704         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1705         max_irr = apic_find_highest_irr(apic);
1706         if (max_irr < 0)
1707                 max_irr = 0;
1708         max_isr = apic_find_highest_isr(apic);
1709         if (max_isr < 0)
1710                 max_isr = 0;
1711         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1712
1713         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1714         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1715         kunmap_atomic(vapic);
1716 }
1717
1718 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1719 {
1720         vcpu->arch.apic->vapic_addr = vapic_addr;
1721         if (vapic_addr)
1722                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1723         else
1724                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1725 }
1726
1727 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1728 {
1729         struct kvm_lapic *apic = vcpu->arch.apic;
1730         u32 reg = (msr - APIC_BASE_MSR) << 4;
1731
1732         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1733                 return 1;
1734
1735         /* if this is ICR write vector before command */
1736         if (msr == 0x830)
1737                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1738         return apic_reg_write(apic, reg, (u32)data);
1739 }
1740
1741 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1742 {
1743         struct kvm_lapic *apic = vcpu->arch.apic;
1744         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1745
1746         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1747                 return 1;
1748
1749         if (apic_reg_read(apic, reg, 4, &low))
1750                 return 1;
1751         if (msr == 0x830)
1752                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1753
1754         *data = (((u64)high) << 32) | low;
1755
1756         return 0;
1757 }
1758
1759 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1760 {
1761         struct kvm_lapic *apic = vcpu->arch.apic;
1762
1763         if (!kvm_vcpu_has_lapic(vcpu))
1764                 return 1;
1765
1766         /* if this is ICR write vector before command */
1767         if (reg == APIC_ICR)
1768                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1769         return apic_reg_write(apic, reg, (u32)data);
1770 }
1771
1772 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1773 {
1774         struct kvm_lapic *apic = vcpu->arch.apic;
1775         u32 low, high = 0;
1776
1777         if (!kvm_vcpu_has_lapic(vcpu))
1778                 return 1;
1779
1780         if (apic_reg_read(apic, reg, 4, &low))
1781                 return 1;
1782         if (reg == APIC_ICR)
1783                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1784
1785         *data = (((u64)high) << 32) | low;
1786
1787         return 0;
1788 }
1789
1790 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1791 {
1792         u64 addr = data & ~KVM_MSR_ENABLED;
1793         if (!IS_ALIGNED(addr, 4))
1794                 return 1;
1795
1796         vcpu->arch.pv_eoi.msr_val = data;
1797         if (!pv_eoi_enabled(vcpu))
1798                 return 0;
1799         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1800                                          addr);
1801 }
1802
1803 void kvm_lapic_init(void)
1804 {
1805         /* do not patch jump label more than once per second */
1806         jump_label_rate_limit(&apic_hw_disabled, HZ);
1807         jump_label_rate_limit(&apic_sw_disabled, HZ);
1808 }