x86, apicv: add virtual interrupt delivery support
[linux-3.10.git] / arch / x86 / include / asm / vmx.h
1 #ifndef VMX_H
2 #define VMX_H
3
4 /*
5  * vmx.h: VMX Architecture related definitions
6  * Copyright (c) 2004, Intel Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2, as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19  * Place - Suite 330, Boston, MA 02111-1307 USA.
20  *
21  * A few random additions are:
22  * Copyright (C) 2006 Qumranet
23  *    Avi Kivity <avi@qumranet.com>
24  *    Yaniv Kamay <yaniv@qumranet.com>
25  *
26  */
27
28 #define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000
29
30 #define EXIT_REASON_EXCEPTION_NMI       0
31 #define EXIT_REASON_EXTERNAL_INTERRUPT  1
32 #define EXIT_REASON_TRIPLE_FAULT        2
33
34 #define EXIT_REASON_PENDING_INTERRUPT   7
35 #define EXIT_REASON_NMI_WINDOW          8
36 #define EXIT_REASON_TASK_SWITCH         9
37 #define EXIT_REASON_CPUID               10
38 #define EXIT_REASON_HLT                 12
39 #define EXIT_REASON_INVD                13
40 #define EXIT_REASON_INVLPG              14
41 #define EXIT_REASON_RDPMC               15
42 #define EXIT_REASON_RDTSC               16
43 #define EXIT_REASON_VMCALL              18
44 #define EXIT_REASON_VMCLEAR             19
45 #define EXIT_REASON_VMLAUNCH            20
46 #define EXIT_REASON_VMPTRLD             21
47 #define EXIT_REASON_VMPTRST             22
48 #define EXIT_REASON_VMREAD              23
49 #define EXIT_REASON_VMRESUME            24
50 #define EXIT_REASON_VMWRITE             25
51 #define EXIT_REASON_VMOFF               26
52 #define EXIT_REASON_VMON                27
53 #define EXIT_REASON_CR_ACCESS           28
54 #define EXIT_REASON_DR_ACCESS           29
55 #define EXIT_REASON_IO_INSTRUCTION      30
56 #define EXIT_REASON_MSR_READ            31
57 #define EXIT_REASON_MSR_WRITE           32
58 #define EXIT_REASON_INVALID_STATE       33
59 #define EXIT_REASON_MWAIT_INSTRUCTION   36
60 #define EXIT_REASON_MONITOR_INSTRUCTION 39
61 #define EXIT_REASON_PAUSE_INSTRUCTION   40
62 #define EXIT_REASON_MCE_DURING_VMENTRY  41
63 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
64 #define EXIT_REASON_APIC_ACCESS         44
65 #define EXIT_REASON_EOI_INDUCED         45
66 #define EXIT_REASON_EPT_VIOLATION       48
67 #define EXIT_REASON_EPT_MISCONFIG       49
68 #define EXIT_REASON_WBINVD              54
69 #define EXIT_REASON_XSETBV              55
70 #define EXIT_REASON_APIC_WRITE          56
71 #define EXIT_REASON_INVPCID             58
72
73 #define VMX_EXIT_REASONS \
74         { EXIT_REASON_EXCEPTION_NMI,         "EXCEPTION_NMI" }, \
75         { EXIT_REASON_EXTERNAL_INTERRUPT,    "EXTERNAL_INTERRUPT" }, \
76         { EXIT_REASON_TRIPLE_FAULT,          "TRIPLE_FAULT" }, \
77         { EXIT_REASON_PENDING_INTERRUPT,     "PENDING_INTERRUPT" }, \
78         { EXIT_REASON_NMI_WINDOW,            "NMI_WINDOW" }, \
79         { EXIT_REASON_TASK_SWITCH,           "TASK_SWITCH" }, \
80         { EXIT_REASON_CPUID,                 "CPUID" }, \
81         { EXIT_REASON_HLT,                   "HLT" }, \
82         { EXIT_REASON_INVLPG,                "INVLPG" }, \
83         { EXIT_REASON_RDPMC,                 "RDPMC" }, \
84         { EXIT_REASON_RDTSC,                 "RDTSC" }, \
85         { EXIT_REASON_VMCALL,                "VMCALL" }, \
86         { EXIT_REASON_VMCLEAR,               "VMCLEAR" }, \
87         { EXIT_REASON_VMLAUNCH,              "VMLAUNCH" }, \
88         { EXIT_REASON_VMPTRLD,               "VMPTRLD" }, \
89         { EXIT_REASON_VMPTRST,               "VMPTRST" }, \
90         { EXIT_REASON_VMREAD,                "VMREAD" }, \
91         { EXIT_REASON_VMRESUME,              "VMRESUME" }, \
92         { EXIT_REASON_VMWRITE,               "VMWRITE" }, \
93         { EXIT_REASON_VMOFF,                 "VMOFF" }, \
94         { EXIT_REASON_VMON,                  "VMON" }, \
95         { EXIT_REASON_CR_ACCESS,             "CR_ACCESS" }, \
96         { EXIT_REASON_DR_ACCESS,             "DR_ACCESS" }, \
97         { EXIT_REASON_IO_INSTRUCTION,        "IO_INSTRUCTION" }, \
98         { EXIT_REASON_MSR_READ,              "MSR_READ" }, \
99         { EXIT_REASON_MSR_WRITE,             "MSR_WRITE" }, \
100         { EXIT_REASON_MWAIT_INSTRUCTION,     "MWAIT_INSTRUCTION" }, \
101         { EXIT_REASON_MONITOR_INSTRUCTION,   "MONITOR_INSTRUCTION" }, \
102         { EXIT_REASON_PAUSE_INSTRUCTION,     "PAUSE_INSTRUCTION" }, \
103         { EXIT_REASON_MCE_DURING_VMENTRY,    "MCE_DURING_VMENTRY" }, \
104         { EXIT_REASON_TPR_BELOW_THRESHOLD,   "TPR_BELOW_THRESHOLD" }, \
105         { EXIT_REASON_APIC_ACCESS,           "APIC_ACCESS" }, \
106         { EXIT_REASON_EPT_VIOLATION,         "EPT_VIOLATION" }, \
107         { EXIT_REASON_EPT_MISCONFIG,         "EPT_MISCONFIG" }, \
108         { EXIT_REASON_WBINVD,                "WBINVD" }
109
110 #ifdef __KERNEL__
111
112 #include <linux/types.h>
113
114 /*
115  * Definitions of Primary Processor-Based VM-Execution Controls.
116  */
117 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
118 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
119 #define CPU_BASED_HLT_EXITING                   0x00000080
120 #define CPU_BASED_INVLPG_EXITING                0x00000200
121 #define CPU_BASED_MWAIT_EXITING                 0x00000400
122 #define CPU_BASED_RDPMC_EXITING                 0x00000800
123 #define CPU_BASED_RDTSC_EXITING                 0x00001000
124 #define CPU_BASED_CR3_LOAD_EXITING              0x00008000
125 #define CPU_BASED_CR3_STORE_EXITING             0x00010000
126 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
127 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
128 #define CPU_BASED_TPR_SHADOW                    0x00200000
129 #define CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
130 #define CPU_BASED_MOV_DR_EXITING                0x00800000
131 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
132 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
133 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
134 #define CPU_BASED_MONITOR_EXITING               0x20000000
135 #define CPU_BASED_PAUSE_EXITING                 0x40000000
136 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
137 /*
138  * Definitions of Secondary Processor-Based VM-Execution Controls.
139  */
140 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
141 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
142 #define SECONDARY_EXEC_RDTSCP                   0x00000008
143 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x00000010
144 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
145 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
146 #define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
147 #define SECONDARY_EXEC_APIC_REGISTER_VIRT       0x00000100
148 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    0x00000200
149 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
150 #define SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
151
152
153 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
154 #define PIN_BASED_NMI_EXITING                   0x00000008
155 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
156
157 #define VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000002
158 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
159 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
160 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
161 #define VM_EXIT_SAVE_IA32_PAT                   0x00040000
162 #define VM_EXIT_LOAD_IA32_PAT                   0x00080000
163 #define VM_EXIT_SAVE_IA32_EFER                  0x00100000
164 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
165 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
166
167 #define VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000002
168 #define VM_ENTRY_IA32E_MODE                     0x00000200
169 #define VM_ENTRY_SMM                            0x00000400
170 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
171 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
172 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
173 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
174
175 /* VMCS Encodings */
176 enum vmcs_field {
177         VIRTUAL_PROCESSOR_ID            = 0x00000000,
178         GUEST_ES_SELECTOR               = 0x00000800,
179         GUEST_CS_SELECTOR               = 0x00000802,
180         GUEST_SS_SELECTOR               = 0x00000804,
181         GUEST_DS_SELECTOR               = 0x00000806,
182         GUEST_FS_SELECTOR               = 0x00000808,
183         GUEST_GS_SELECTOR               = 0x0000080a,
184         GUEST_LDTR_SELECTOR             = 0x0000080c,
185         GUEST_TR_SELECTOR               = 0x0000080e,
186         GUEST_INTR_STATUS               = 0x00000810,
187         HOST_ES_SELECTOR                = 0x00000c00,
188         HOST_CS_SELECTOR                = 0x00000c02,
189         HOST_SS_SELECTOR                = 0x00000c04,
190         HOST_DS_SELECTOR                = 0x00000c06,
191         HOST_FS_SELECTOR                = 0x00000c08,
192         HOST_GS_SELECTOR                = 0x00000c0a,
193         HOST_TR_SELECTOR                = 0x00000c0c,
194         IO_BITMAP_A                     = 0x00002000,
195         IO_BITMAP_A_HIGH                = 0x00002001,
196         IO_BITMAP_B                     = 0x00002002,
197         IO_BITMAP_B_HIGH                = 0x00002003,
198         MSR_BITMAP                      = 0x00002004,
199         MSR_BITMAP_HIGH                 = 0x00002005,
200         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
201         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
202         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
203         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
204         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
205         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
206         TSC_OFFSET                      = 0x00002010,
207         TSC_OFFSET_HIGH                 = 0x00002011,
208         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
209         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
210         APIC_ACCESS_ADDR                = 0x00002014,
211         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
212         EPT_POINTER                     = 0x0000201a,
213         EPT_POINTER_HIGH                = 0x0000201b,
214         EOI_EXIT_BITMAP0                = 0x0000201c,
215         EOI_EXIT_BITMAP0_HIGH           = 0x0000201d,
216         EOI_EXIT_BITMAP1                = 0x0000201e,
217         EOI_EXIT_BITMAP1_HIGH           = 0x0000201f,
218         EOI_EXIT_BITMAP2                = 0x00002020,
219         EOI_EXIT_BITMAP2_HIGH           = 0x00002021,
220         EOI_EXIT_BITMAP3                = 0x00002022,
221         EOI_EXIT_BITMAP3_HIGH           = 0x00002023,
222         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
223         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
224         VMCS_LINK_POINTER               = 0x00002800,
225         VMCS_LINK_POINTER_HIGH          = 0x00002801,
226         GUEST_IA32_DEBUGCTL             = 0x00002802,
227         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
228         GUEST_IA32_PAT                  = 0x00002804,
229         GUEST_IA32_PAT_HIGH             = 0x00002805,
230         GUEST_IA32_EFER                 = 0x00002806,
231         GUEST_IA32_EFER_HIGH            = 0x00002807,
232         GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
233         GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
234         GUEST_PDPTR0                    = 0x0000280a,
235         GUEST_PDPTR0_HIGH               = 0x0000280b,
236         GUEST_PDPTR1                    = 0x0000280c,
237         GUEST_PDPTR1_HIGH               = 0x0000280d,
238         GUEST_PDPTR2                    = 0x0000280e,
239         GUEST_PDPTR2_HIGH               = 0x0000280f,
240         GUEST_PDPTR3                    = 0x00002810,
241         GUEST_PDPTR3_HIGH               = 0x00002811,
242         HOST_IA32_PAT                   = 0x00002c00,
243         HOST_IA32_PAT_HIGH              = 0x00002c01,
244         HOST_IA32_EFER                  = 0x00002c02,
245         HOST_IA32_EFER_HIGH             = 0x00002c03,
246         HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
247         HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
248         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
249         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
250         EXCEPTION_BITMAP                = 0x00004004,
251         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
252         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
253         CR3_TARGET_COUNT                = 0x0000400a,
254         VM_EXIT_CONTROLS                = 0x0000400c,
255         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
256         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
257         VM_ENTRY_CONTROLS               = 0x00004012,
258         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
259         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
260         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
261         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
262         TPR_THRESHOLD                   = 0x0000401c,
263         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
264         PLE_GAP                         = 0x00004020,
265         PLE_WINDOW                      = 0x00004022,
266         VM_INSTRUCTION_ERROR            = 0x00004400,
267         VM_EXIT_REASON                  = 0x00004402,
268         VM_EXIT_INTR_INFO               = 0x00004404,
269         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
270         IDT_VECTORING_INFO_FIELD        = 0x00004408,
271         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
272         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
273         VMX_INSTRUCTION_INFO            = 0x0000440e,
274         GUEST_ES_LIMIT                  = 0x00004800,
275         GUEST_CS_LIMIT                  = 0x00004802,
276         GUEST_SS_LIMIT                  = 0x00004804,
277         GUEST_DS_LIMIT                  = 0x00004806,
278         GUEST_FS_LIMIT                  = 0x00004808,
279         GUEST_GS_LIMIT                  = 0x0000480a,
280         GUEST_LDTR_LIMIT                = 0x0000480c,
281         GUEST_TR_LIMIT                  = 0x0000480e,
282         GUEST_GDTR_LIMIT                = 0x00004810,
283         GUEST_IDTR_LIMIT                = 0x00004812,
284         GUEST_ES_AR_BYTES               = 0x00004814,
285         GUEST_CS_AR_BYTES               = 0x00004816,
286         GUEST_SS_AR_BYTES               = 0x00004818,
287         GUEST_DS_AR_BYTES               = 0x0000481a,
288         GUEST_FS_AR_BYTES               = 0x0000481c,
289         GUEST_GS_AR_BYTES               = 0x0000481e,
290         GUEST_LDTR_AR_BYTES             = 0x00004820,
291         GUEST_TR_AR_BYTES               = 0x00004822,
292         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
293         GUEST_ACTIVITY_STATE            = 0X00004826,
294         GUEST_SYSENTER_CS               = 0x0000482A,
295         HOST_IA32_SYSENTER_CS           = 0x00004c00,
296         CR0_GUEST_HOST_MASK             = 0x00006000,
297         CR4_GUEST_HOST_MASK             = 0x00006002,
298         CR0_READ_SHADOW                 = 0x00006004,
299         CR4_READ_SHADOW                 = 0x00006006,
300         CR3_TARGET_VALUE0               = 0x00006008,
301         CR3_TARGET_VALUE1               = 0x0000600a,
302         CR3_TARGET_VALUE2               = 0x0000600c,
303         CR3_TARGET_VALUE3               = 0x0000600e,
304         EXIT_QUALIFICATION              = 0x00006400,
305         GUEST_LINEAR_ADDRESS            = 0x0000640a,
306         GUEST_CR0                       = 0x00006800,
307         GUEST_CR3                       = 0x00006802,
308         GUEST_CR4                       = 0x00006804,
309         GUEST_ES_BASE                   = 0x00006806,
310         GUEST_CS_BASE                   = 0x00006808,
311         GUEST_SS_BASE                   = 0x0000680a,
312         GUEST_DS_BASE                   = 0x0000680c,
313         GUEST_FS_BASE                   = 0x0000680e,
314         GUEST_GS_BASE                   = 0x00006810,
315         GUEST_LDTR_BASE                 = 0x00006812,
316         GUEST_TR_BASE                   = 0x00006814,
317         GUEST_GDTR_BASE                 = 0x00006816,
318         GUEST_IDTR_BASE                 = 0x00006818,
319         GUEST_DR7                       = 0x0000681a,
320         GUEST_RSP                       = 0x0000681c,
321         GUEST_RIP                       = 0x0000681e,
322         GUEST_RFLAGS                    = 0x00006820,
323         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
324         GUEST_SYSENTER_ESP              = 0x00006824,
325         GUEST_SYSENTER_EIP              = 0x00006826,
326         HOST_CR0                        = 0x00006c00,
327         HOST_CR3                        = 0x00006c02,
328         HOST_CR4                        = 0x00006c04,
329         HOST_FS_BASE                    = 0x00006c06,
330         HOST_GS_BASE                    = 0x00006c08,
331         HOST_TR_BASE                    = 0x00006c0a,
332         HOST_GDTR_BASE                  = 0x00006c0c,
333         HOST_IDTR_BASE                  = 0x00006c0e,
334         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
335         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
336         HOST_RSP                        = 0x00006c14,
337         HOST_RIP                        = 0x00006c16,
338 };
339
340 /*
341  * Interruption-information format
342  */
343 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
344 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
345 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
346 #define INTR_INFO_UNBLOCK_NMI           0x1000          /* 12 */
347 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
348 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
349
350 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
351 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
352 #define VECTORING_INFO_DELIVER_CODE_MASK        INTR_INFO_DELIVER_CODE_MASK
353 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
354
355 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
356 #define INTR_TYPE_NMI_INTR              (2 << 8) /* NMI */
357 #define INTR_TYPE_HARD_EXCEPTION        (3 << 8) /* processor exception */
358 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
359 #define INTR_TYPE_SOFT_EXCEPTION        (6 << 8) /* software exception */
360
361 /* GUEST_INTERRUPTIBILITY_INFO flags. */
362 #define GUEST_INTR_STATE_STI            0x00000001
363 #define GUEST_INTR_STATE_MOV_SS         0x00000002
364 #define GUEST_INTR_STATE_SMI            0x00000004
365 #define GUEST_INTR_STATE_NMI            0x00000008
366
367 /* GUEST_ACTIVITY_STATE flags */
368 #define GUEST_ACTIVITY_ACTIVE           0
369 #define GUEST_ACTIVITY_HLT              1
370 #define GUEST_ACTIVITY_SHUTDOWN         2
371 #define GUEST_ACTIVITY_WAIT_SIPI        3
372
373 /*
374  * Exit Qualifications for MOV for Control Register Access
375  */
376 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
377 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
378 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
379 #define LMSW_SOURCE_DATA_SHIFT 16
380 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
381 #define REG_EAX                         (0 << 8)
382 #define REG_ECX                         (1 << 8)
383 #define REG_EDX                         (2 << 8)
384 #define REG_EBX                         (3 << 8)
385 #define REG_ESP                         (4 << 8)
386 #define REG_EBP                         (5 << 8)
387 #define REG_ESI                         (6 << 8)
388 #define REG_EDI                         (7 << 8)
389 #define REG_R8                         (8 << 8)
390 #define REG_R9                         (9 << 8)
391 #define REG_R10                        (10 << 8)
392 #define REG_R11                        (11 << 8)
393 #define REG_R12                        (12 << 8)
394 #define REG_R13                        (13 << 8)
395 #define REG_R14                        (14 << 8)
396 #define REG_R15                        (15 << 8)
397
398 /*
399  * Exit Qualifications for MOV for Debug Register Access
400  */
401 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
402 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
403 #define TYPE_MOV_TO_DR                  (0 << 4)
404 #define TYPE_MOV_FROM_DR                (1 << 4)
405 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
406
407
408 /*
409  * Exit Qualifications for APIC-Access
410  */
411 #define APIC_ACCESS_OFFSET              0xfff   /* 11:0, offset within the APIC page */
412 #define APIC_ACCESS_TYPE                0xf000  /* 15:12, access type */
413 #define TYPE_LINEAR_APIC_INST_READ      (0 << 12)
414 #define TYPE_LINEAR_APIC_INST_WRITE     (1 << 12)
415 #define TYPE_LINEAR_APIC_INST_FETCH     (2 << 12)
416 #define TYPE_LINEAR_APIC_EVENT          (3 << 12)
417 #define TYPE_PHYSICAL_APIC_EVENT        (10 << 12)
418 #define TYPE_PHYSICAL_APIC_INST         (15 << 12)
419
420 /* segment AR */
421 #define SEGMENT_AR_L_MASK (1 << 13)
422
423 #define AR_TYPE_ACCESSES_MASK 1
424 #define AR_TYPE_READABLE_MASK (1 << 1)
425 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
426 #define AR_TYPE_CODE_MASK (1 << 3)
427 #define AR_TYPE_MASK 0x0f
428 #define AR_TYPE_BUSY_64_TSS 11
429 #define AR_TYPE_BUSY_32_TSS 11
430 #define AR_TYPE_BUSY_16_TSS 3
431 #define AR_TYPE_LDT 2
432
433 #define AR_UNUSABLE_MASK (1 << 16)
434 #define AR_S_MASK (1 << 4)
435 #define AR_P_MASK (1 << 7)
436 #define AR_L_MASK (1 << 13)
437 #define AR_DB_MASK (1 << 14)
438 #define AR_G_MASK (1 << 15)
439 #define AR_DPL_SHIFT 5
440 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
441
442 #define AR_RESERVD_MASK 0xfffe0f00
443
444 #define TSS_PRIVATE_MEMSLOT                     (KVM_USER_MEM_SLOTS + 0)
445 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        (KVM_USER_MEM_SLOTS + 1)
446 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT      (KVM_USER_MEM_SLOTS + 2)
447
448 #define VMX_NR_VPIDS                            (1 << 16)
449 #define VMX_VPID_EXTENT_SINGLE_CONTEXT          1
450 #define VMX_VPID_EXTENT_ALL_CONTEXT             2
451
452 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR          0
453 #define VMX_EPT_EXTENT_CONTEXT                  1
454 #define VMX_EPT_EXTENT_GLOBAL                   2
455
456 #define VMX_EPT_EXECUTE_ONLY_BIT                (1ull)
457 #define VMX_EPT_PAGE_WALK_4_BIT                 (1ull << 6)
458 #define VMX_EPTP_UC_BIT                         (1ull << 8)
459 #define VMX_EPTP_WB_BIT                         (1ull << 14)
460 #define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
461 #define VMX_EPT_1GB_PAGE_BIT                    (1ull << 17)
462 #define VMX_EPT_AD_BIT                              (1ull << 21)
463 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
464 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
465
466 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT      (1ull << 9) /* (41 - 32) */
467 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT      (1ull << 10) /* (42 - 32) */
468
469 #define VMX_EPT_DEFAULT_GAW                     3
470 #define VMX_EPT_MAX_GAW                         0x4
471 #define VMX_EPT_MT_EPTE_SHIFT                   3
472 #define VMX_EPT_GAW_EPTP_SHIFT                  3
473 #define VMX_EPT_AD_ENABLE_BIT                   (1ull << 6)
474 #define VMX_EPT_DEFAULT_MT                      0x6ull
475 #define VMX_EPT_READABLE_MASK                   0x1ull
476 #define VMX_EPT_WRITABLE_MASK                   0x2ull
477 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
478 #define VMX_EPT_IPAT_BIT                        (1ull << 6)
479 #define VMX_EPT_ACCESS_BIT                              (1ull << 8)
480 #define VMX_EPT_DIRTY_BIT                               (1ull << 9)
481
482 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
483
484
485 #define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
486 #define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
487 #define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
488 #define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
489 #define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
490 #define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
491 #define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
492 #define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
493 #define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
494 #define ASM_VMX_INVEPT            ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
495 #define ASM_VMX_INVVPID           ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
496
497 struct vmx_msr_entry {
498         u32 index;
499         u32 reserved;
500         u64 value;
501 } __aligned(16);
502
503 /*
504  * Exit Qualifications for entry failure during or after loading guest state
505  */
506 #define ENTRY_FAIL_DEFAULT              0
507 #define ENTRY_FAIL_PDPTE                2
508 #define ENTRY_FAIL_NMI                  3
509 #define ENTRY_FAIL_VMCS_LINK_PTR        4
510
511 /*
512  * VM-instruction error numbers
513  */
514 enum vm_instruction_error_number {
515         VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
516         VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
517         VMXERR_VMCLEAR_VMXON_POINTER = 3,
518         VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
519         VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
520         VMXERR_VMRESUME_AFTER_VMXOFF = 6,
521         VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
522         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
523         VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
524         VMXERR_VMPTRLD_VMXON_POINTER = 10,
525         VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
526         VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
527         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
528         VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
529         VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
530         VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
531         VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
532         VMXERR_VMCALL_NONCLEAR_VMCS = 19,
533         VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
534         VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
535         VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
536         VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
537         VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
538         VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
539         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
540 };
541
542 #endif
543
544 #endif