[ARM] 3257/1: ixp2000: map in scratch and sram
Lennert Buytenhek [Fri, 13 Jan 2006 20:51:43 +0000 (20:51 +0000)]
Patch from Lennert Buytenhek

For the ixp2000 netdev driver, we need to map in a chunk of SRAM (to
store the transmit and receive descriptors) and the scratch get/put
area (so that we can use the scratchpad rings in the cpu for managing
the descriptors.)  These are the final two mappings needed for the
netdev driver and the last missing piece for the driver in mainline
to work.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

arch/arm/mach-ixp2000/core.c
include/asm-arm/arch-ixp2000/ixp2000-regs.h

index 6851aba..cfd5bef 100644 (file)
@@ -106,6 +106,16 @@ static struct map_desc ixp2000_io_desc[] __initdata = {
                .length         = IXP2000_MSF_SIZE,
                .type           = MT_IXP2000_DEVICE,
        }, {
+               .virtual        = IXP2000_SCRATCH_RING_VIRT_BASE,
+               .pfn            = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
+               .length         = IXP2000_SCRATCH_RING_SIZE,
+               .type           = MT_IXP2000_DEVICE,
+       }, {
+               .virtual        = IXP2000_SRAM0_VIRT_BASE,
+               .pfn            = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
+               .length         = IXP2000_SRAM0_SIZE,
+               .type           = MT_IXP2000_DEVICE,
+       }, {
                .virtual        = IXP2000_PCI_IO_VIRT_BASE,
                .pfn            = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
                .length         = IXP2000_PCI_IO_SIZE,
index 8cf70ff..2b57f91 100644 (file)
@@ -26,6 +26,8 @@
  * fc000000    da000000        16M             PCI CFG0
  * fd000000    d8000000        16M             PCI I/O
  * fe[0-7]00000                        8M              per-platform mappings
+ * fe900000    80000000        1M              SRAM #0 (first MB)
+ * fea00000    cb400000        1M              SCRATCH ring get/put
  * feb00000    c8000000        1M              MSF
  * fec00000    df000000        1M              PCI CSRs
  * fed00000    de000000        1M              PCI CREG
 #define IXP2000_MSF_VIRT_BASE          0xfeb00000
 #define IXP2000_MSF_SIZE               0x00100000
 
+#define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000
+#define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000
+#define IXP2000_SCRATCH_RING_SIZE      0x00100000
+
+#define IXP2000_SRAM0_PHYS_BASE                0x80000000
+#define IXP2000_SRAM0_VIRT_BASE                0xfe900000
+#define IXP2000_SRAM0_SIZE             0x00100000
+
 #define IXP2000_PCI_IO_PHYS_BASE       0xd8000000
 #define        IXP2000_PCI_IO_VIRT_BASE        0xfd000000
 #define IXP2000_PCI_IO_SIZE            0x01000000