Merge branch 'master' of /home/trondmy/kernel/linux-2.6/
Trond Myklebust [Tue, 20 Jun 2006 12:59:45 +0000 (08:59 -0400)]
711 files changed:
Documentation/feature-removal-schedule.txt
Documentation/infiniband/ipoib.txt
Documentation/kernel-parameters.txt
Documentation/memory-barriers.txt
Documentation/networking/README.ipw2200
Documentation/networking/bonding.txt
Documentation/networking/ip-sysctl.txt
Documentation/networking/netdevices.txt
MAINTAINERS
Makefile
arch/alpha/Kconfig
arch/arm/mach-imx/irq.c
arch/arm/mach-integrator/integrator_cp.c
arch/arm/mach-pxa/spitz.c
arch/arm/mach-sa1100/neponset.c
arch/arm/mach-versatile/core.c
arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c
arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
arch/i386/kernel/cpu/cpufreq/longhaul.c
arch/i386/kernel/cpu/cpufreq/longrun.c
arch/i386/kernel/cpu/cpufreq/powernow-k7.c
arch/i386/kernel/cpu/cpufreq/powernow-k8.c
arch/i386/kernel/cpu/cpufreq/powernow-k8.h
arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c
arch/mips/Kconfig
arch/mips/Makefile
arch/mips/au1000/common/au1xxx_irqmap.c
arch/mips/au1000/common/pci.c
arch/mips/au1000/common/setup.c
arch/mips/au1000/common/time.c
arch/mips/au1000/csb250/irqmap.c
arch/mips/au1000/db1x00/irqmap.c
arch/mips/au1000/hydrogen3/irqmap.c
arch/mips/au1000/mtx-1/irqmap.c
arch/mips/au1000/pb1000/irqmap.c
arch/mips/au1000/pb1100/irqmap.c
arch/mips/au1000/pb1200/irqmap.c
arch/mips/au1000/pb1500/irqmap.c
arch/mips/au1000/pb1550/irqmap.c
arch/mips/au1000/xxs1500/irqmap.c
arch/mips/basler/excite/Makefile [new file with mode: 0644]
arch/mips/basler/excite/excite_dbg_io.c [new file with mode: 0644]
arch/mips/basler/excite/excite_device.c [new file with mode: 0644]
arch/mips/basler/excite/excite_flashtest.c [new file with mode: 0644]
arch/mips/basler/excite/excite_fpga.h [new file with mode: 0644]
arch/mips/basler/excite/excite_iodev.c [new file with mode: 0644]
arch/mips/basler/excite/excite_iodev.h [new file with mode: 0644]
arch/mips/basler/excite/excite_irq.c [new file with mode: 0644]
arch/mips/basler/excite/excite_procfs.c [new file with mode: 0644]
arch/mips/basler/excite/excite_prom.c [new file with mode: 0644]
arch/mips/basler/excite/excite_setup.c [new file with mode: 0644]
arch/mips/cobalt/console.c
arch/mips/cobalt/setup.c
arch/mips/configs/atlas_defconfig
arch/mips/configs/bigsur_defconfig
arch/mips/configs/capcella_defconfig
arch/mips/configs/cobalt_defconfig
arch/mips/configs/db1000_defconfig
arch/mips/configs/db1100_defconfig
arch/mips/configs/db1200_defconfig
arch/mips/configs/db1500_defconfig
arch/mips/configs/db1550_defconfig
arch/mips/configs/ddb5477_defconfig
arch/mips/configs/decstation_defconfig
arch/mips/configs/e55_defconfig
arch/mips/configs/emma2rh_defconfig [new file with mode: 0644]
arch/mips/configs/ev64120_defconfig
arch/mips/configs/ev96100_defconfig
arch/mips/configs/excite_defconfig [copied from arch/mips/configs/ddb5476_defconfig with 51% similarity]
arch/mips/configs/ip22_defconfig
arch/mips/configs/ip27_defconfig
arch/mips/configs/ip32_defconfig
arch/mips/configs/it8172_defconfig
arch/mips/configs/ivr_defconfig
arch/mips/configs/jaguar-atx_defconfig
arch/mips/configs/jmr3927_defconfig
arch/mips/configs/lasat200_defconfig
arch/mips/configs/malta_defconfig
arch/mips/configs/mipssim_defconfig
arch/mips/configs/mpc30x_defconfig
arch/mips/configs/ocelot_3_defconfig
arch/mips/configs/ocelot_c_defconfig
arch/mips/configs/ocelot_defconfig
arch/mips/configs/ocelot_g_defconfig
arch/mips/configs/pb1100_defconfig
arch/mips/configs/pb1500_defconfig
arch/mips/configs/pb1550_defconfig
arch/mips/configs/pnx8550-jbs_defconfig
arch/mips/configs/pnx8550-v2pci_defconfig
arch/mips/configs/qemu_defconfig
arch/mips/configs/rbhma4500_defconfig
arch/mips/configs/rm200_defconfig
arch/mips/configs/sb1250-swarm_defconfig
arch/mips/configs/sead_defconfig
arch/mips/configs/tb0226_defconfig
arch/mips/configs/tb0229_defconfig
arch/mips/configs/tb0287_defconfig
arch/mips/configs/workpad_defconfig
arch/mips/configs/wrppmc_defconfig [moved from arch/mips/configs/ddb5476_defconfig with 68% similarity]
arch/mips/configs/yosemite_defconfig
arch/mips/ddb5xxx/common/prom.c
arch/mips/ddb5xxx/ddb5074/Makefile [deleted file]
arch/mips/ddb5xxx/ddb5074/irq.c [deleted file]
arch/mips/ddb5xxx/ddb5074/nile4_pic.c [deleted file]
arch/mips/ddb5xxx/ddb5074/setup.c [deleted file]
arch/mips/ddb5xxx/ddb5476/Makefile [deleted file]
arch/mips/ddb5xxx/ddb5476/dbg_io.c [deleted file]
arch/mips/ddb5xxx/ddb5476/irq.c [deleted file]
arch/mips/ddb5xxx/ddb5476/nile4_pic.c [deleted file]
arch/mips/ddb5xxx/ddb5476/setup.c [deleted file]
arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c [deleted file]
arch/mips/ddb5xxx/ddb5477/setup.c
arch/mips/dec/setup.c
arch/mips/dec/time.c
arch/mips/defconfig
arch/mips/emma2rh/common/Makefile [new file with mode: 0644]
arch/mips/emma2rh/common/irq.c [new file with mode: 0644]
arch/mips/emma2rh/common/irq_emma2rh.c [new file with mode: 0644]
arch/mips/emma2rh/common/prom.c [new file with mode: 0644]
arch/mips/emma2rh/markeins/Makefile [new file with mode: 0644]
arch/mips/emma2rh/markeins/irq.c [new file with mode: 0644]
arch/mips/emma2rh/markeins/irq_markeins.c [new file with mode: 0644]
arch/mips/emma2rh/markeins/led.c [new file with mode: 0644]
arch/mips/emma2rh/markeins/platform.c [new file with mode: 0644]
arch/mips/emma2rh/markeins/setup.c [new file with mode: 0644]
arch/mips/galileo-boards/ev96100/setup.c
arch/mips/gt64120/ev64120/setup.c
arch/mips/gt64120/momenco_ocelot/setup.c
arch/mips/gt64120/wrppmc/Makefile [new file with mode: 0644]
arch/mips/gt64120/wrppmc/int-handler.S [new file with mode: 0644]
arch/mips/gt64120/wrppmc/irq.c [new file with mode: 0644]
arch/mips/gt64120/wrppmc/pci.c [new file with mode: 0644]
arch/mips/gt64120/wrppmc/reset.c [new file with mode: 0644]
arch/mips/gt64120/wrppmc/setup.c [new file with mode: 0644]
arch/mips/gt64120/wrppmc/time.c [new file with mode: 0644]
arch/mips/ite-boards/generic/it8172_setup.c
arch/mips/jazz/setup.c
arch/mips/jmr3927/rbhma3100/setup.c
arch/mips/kernel/Makefile
arch/mips/kernel/apm.c [new file with mode: 0644]
arch/mips/kernel/asm-offsets.c
arch/mips/kernel/branch.c
arch/mips/kernel/i8259.c
arch/mips/kernel/irixsig.c
arch/mips/kernel/ptrace.c
arch/mips/kernel/ptrace32.c
arch/mips/kernel/r4k_switch.S
arch/mips/kernel/setup.c
arch/mips/kernel/traps.c
arch/mips/lasat/setup.c
arch/mips/lib/Makefile
arch/mips/lib/ashldi3.c [new file with mode: 0644]
arch/mips/lib/ashrdi3.c [new file with mode: 0644]
arch/mips/lib/libgcc.h [new file with mode: 0644]
arch/mips/lib/lshrdi3.c [new file with mode: 0644]
arch/mips/math-emu/cp1emu.c
arch/mips/math-emu/ieee754.h
arch/mips/math-emu/kernel_linkage.c
arch/mips/mips-boards/atlas/atlas_setup.c
arch/mips/mips-boards/generic/memory.c
arch/mips/mips-boards/malta/malta_setup.c
arch/mips/mips-boards/malta/malta_smp.c
arch/mips/mips-boards/sead/sead_setup.c
arch/mips/mips-boards/sim/sim_setup.c
arch/mips/mips-boards/sim/sim_smp.c
arch/mips/mm/tlb-r4k.c
arch/mips/momentum/jaguar_atx/setup.c
arch/mips/momentum/ocelot_3/setup.c
arch/mips/momentum/ocelot_c/setup.c
arch/mips/momentum/ocelot_g/setup.c
arch/mips/pci/Makefile
arch/mips/pci/fixup-ddb5074.c [deleted file]
arch/mips/pci/fixup-emma2rh.c [new file with mode: 0644]
arch/mips/pci/fixup-excite.c [new file with mode: 0644]
arch/mips/pci/fixup-wrppmc.c [new file with mode: 0644]
arch/mips/pci/ops-bridge.c [new file with mode: 0644]
arch/mips/pci/ops-ddb5074.c [deleted file]
arch/mips/pci/ops-ddb5476.c [deleted file]
arch/mips/pci/ops-emma2rh.c [new file with mode: 0644]
arch/mips/pci/ops-it8172.c
arch/mips/pci/ops-sni.c
arch/mips/pci/ops-titan.c
arch/mips/pci/pci-ddb5074.c [deleted file]
arch/mips/pci/pci-ddb5476.c [deleted file]
arch/mips/pci/pci-ddb5477.c
arch/mips/pci/pci-emma2rh.c [new file with mode: 0644]
arch/mips/pci/pci-excite.c [new file with mode: 0644]
arch/mips/pci/pci-ip27.c
arch/mips/pci/pci-jmr3927.c
arch/mips/pci/pci-ocelot.c
arch/mips/pci/pci-yosemite.c
arch/mips/pci/pci.c
arch/mips/philips/pnx8550/common/pci.c
arch/mips/philips/pnx8550/common/setup.c
arch/mips/pmc-sierra/yosemite/setup.c
arch/mips/qemu/Makefile
arch/mips/qemu/q-reset.c [new file with mode: 0644]
arch/mips/qemu/q-setup.c
arch/mips/sgi-ip22/ip22-setup.c
arch/mips/sgi-ip27/Kconfig
arch/mips/sgi-ip27/ip27-init.c
arch/mips/sgi-ip27/ip27-irq.c
arch/mips/sgi-ip27/ip27-timer.c
arch/mips/sgi-ip32/ip32-setup.c
arch/mips/sibyte/bcm1480/time.c
arch/mips/sibyte/sb1250/irq.c
arch/mips/sibyte/swarm/setup.c
arch/mips/sni/Makefile
arch/mips/sni/setup.c
arch/mips/sni/sniprom.c [new file with mode: 0644]
arch/mips/tx4927/common/tx4927_setup.c
arch/mips/tx4938/common/setup.c
arch/mips/tx4938/toshiba_rbtx4938/setup.c
arch/mips/vr41xx/Kconfig
arch/mips/vr41xx/common/init.c
arch/powerpc/kernel/prom_init.c
arch/powerpc/kernel/signal_32.c
arch/powerpc/kernel/signal_64.c
arch/powerpc/mm/hash_native_64.c
arch/powerpc/platforms/cell/setup.c
arch/powerpc/platforms/pseries/setup.c
arch/sparc/kernel/smp.c
arch/sparc64/kernel/pci_sun4v.c
arch/sparc64/kernel/smp.c
arch/sparc64/kernel/sparc64_ksyms.c
arch/sparc64/kernel/traps.c
block/cfq-iosched.c
drivers/Kconfig
drivers/Makefile
drivers/acpi/pci_link.c
drivers/acpi/processor_perflib.c
drivers/block/aoe/aoenet.c
drivers/cdrom/cdrom.c
drivers/char/Makefile
drivers/char/agp/alpha-agp.c
drivers/char/agp/generic.c
drivers/char/agp/intel-agp.c
drivers/char/agp/uninorth-agp.c
drivers/char/n_tty.c
drivers/connector/cn_queue.c
drivers/cpufreq/cpufreq.c
drivers/cpufreq/cpufreq_stats.c
drivers/cpufreq/freq_table.c
drivers/dma/Kconfig [new file with mode: 0644]
drivers/dma/Makefile [new file with mode: 0644]
drivers/dma/dmaengine.c [new file with mode: 0644]
drivers/dma/ioatdma.c [new file with mode: 0644]
drivers/dma/ioatdma.h [new file with mode: 0644]
drivers/dma/ioatdma_hw.h [new file with mode: 0644]
drivers/dma/ioatdma_io.h [new file with mode: 0644]
drivers/dma/ioatdma_registers.h [new file with mode: 0644]
drivers/dma/iovlock.c [new file with mode: 0644]
drivers/infiniband/Kconfig
drivers/infiniband/core/Makefile
drivers/infiniband/core/addr.c [new file with mode: 0644]
drivers/infiniband/core/cache.c
drivers/infiniband/core/cm.c
drivers/infiniband/core/cma.c [new file with mode: 0644]
drivers/infiniband/core/fmr_pool.c
drivers/infiniband/core/mad.c
drivers/infiniband/core/mad_priv.h
drivers/infiniband/core/sa_query.c
drivers/infiniband/core/ucm.c
drivers/infiniband/core/uverbs.h
drivers/infiniband/core/uverbs_cmd.c
drivers/infiniband/core/uverbs_main.c
drivers/infiniband/core/uverbs_marshall.c [new file with mode: 0644]
drivers/infiniband/core/verbs.c
drivers/infiniband/hw/ipath/ipath_mad.c
drivers/infiniband/hw/mthca/mthca_cmd.c
drivers/infiniband/hw/mthca/mthca_cq.c
drivers/infiniband/hw/mthca/mthca_eq.c
drivers/infiniband/hw/mthca/mthca_mad.c
drivers/infiniband/hw/mthca/mthca_provider.c
drivers/infiniband/hw/mthca/mthca_provider.h
drivers/infiniband/hw/mthca/mthca_qp.c
drivers/infiniband/hw/mthca/mthca_reset.c
drivers/infiniband/hw/mthca/mthca_srq.c
drivers/infiniband/ulp/ipoib/ipoib.h
drivers/infiniband/ulp/ipoib/ipoib_ib.c
drivers/infiniband/ulp/ipoib/ipoib_main.c
drivers/infiniband/ulp/ipoib/ipoib_multicast.c
drivers/infiniband/ulp/ipoib/ipoib_verbs.c
drivers/infiniband/ulp/srp/ib_srp.c
drivers/infiniband/ulp/srp/ib_srp.h
drivers/media/dvb/dvb-core/dvb_net.c
drivers/message/fusion/mptspi.c
drivers/message/i2o/exec-osm.c
drivers/message/i2o/iop.c
drivers/net/3c501.c
drivers/net/3c503.c
drivers/net/3c505.c
drivers/net/3c507.c
drivers/net/3c523.c
drivers/net/3c527.c
drivers/net/8139cp.c
drivers/net/8139too.c
drivers/net/Kconfig
drivers/net/Makefile
drivers/net/au1000_eth.c
drivers/net/au1000_eth.h
drivers/net/bnx2.c
drivers/net/bnx2.h
drivers/net/bnx2_fw.h
drivers/net/bonding/bond_main.c
drivers/net/cassini.c
drivers/net/e100.c
drivers/net/e1000/Makefile
drivers/net/e1000/e1000.h
drivers/net/e1000/e1000_ethtool.c
drivers/net/e1000/e1000_hw.c
drivers/net/e1000/e1000_hw.h
drivers/net/e1000/e1000_main.c
drivers/net/e1000/e1000_osdep.h
drivers/net/e1000/e1000_param.c
drivers/net/epic100.c
drivers/net/forcedeth.c
drivers/net/hamradio/6pack.c
drivers/net/hamradio/mkiss.c
drivers/net/hp-plus.c
drivers/net/hp.c
drivers/net/ibmlana.c
drivers/net/ibmlana.h
drivers/net/ibmveth.c
drivers/net/ibmveth.h
drivers/net/ifb.c
drivers/net/irda/Kconfig
drivers/net/irda/Makefile
drivers/net/irda/ali-ircc.c
drivers/net/irda/irda-usb.c
drivers/net/irda/irda-usb.h
drivers/net/irda/mcs7780.c [new file with mode: 0644]
drivers/net/irda/mcs7780.h [new file with mode: 0644]
drivers/net/irda/stir4200.c
drivers/net/irda/vlsi_ir.c
drivers/net/ixgb/Makefile
drivers/net/ixgb/ixgb.h
drivers/net/ixgb/ixgb_ee.c
drivers/net/ixgb/ixgb_ee.h
drivers/net/ixgb/ixgb_ethtool.c
drivers/net/ixgb/ixgb_hw.c
drivers/net/ixgb/ixgb_hw.h
drivers/net/ixgb/ixgb_ids.h
drivers/net/ixgb/ixgb_main.c
drivers/net/ixgb/ixgb_osdep.h
drivers/net/ixgb/ixgb_param.c
drivers/net/mv643xx_eth.c
drivers/net/myri10ge/Makefile [new file with mode: 0644]
drivers/net/myri10ge/myri10ge.c [new file with mode: 0644]
drivers/net/myri10ge/myri10ge_mcp.h [new file with mode: 0644]
drivers/net/myri10ge/myri10ge_mcp_gen_header.h [new file with mode: 0644]
drivers/net/natsemi.c
drivers/net/ne.c
drivers/net/ne2.c
drivers/net/pcmcia/pcnet_cs.c
drivers/net/phy/Kconfig
drivers/net/phy/Makefile
drivers/net/phy/smsc.c [new file with mode: 0644]
drivers/net/ppp_generic.c
drivers/net/r8169.c
drivers/net/s2io-regs.h
drivers/net/s2io.c
drivers/net/s2io.h
drivers/net/sis900.c
drivers/net/sis900.h
drivers/net/skge.c
drivers/net/skge.h
drivers/net/sky2.c
drivers/net/smc-ultra.c
drivers/net/smc-ultra32.c
drivers/net/smc911x.c [new file with mode: 0644]
drivers/net/smc911x.h [new file with mode: 0644]
drivers/net/smc9194.c
drivers/net/smc91x.h
drivers/net/sungem_phy.c
drivers/net/tg3.c
drivers/net/tg3.h
drivers/net/tulip/de2104x.c
drivers/net/tulip/de4x5.c
drivers/net/tulip/de4x5.h
drivers/net/tulip/dmfe.c
drivers/net/tulip/eeprom.c
drivers/net/tulip/interrupt.c
drivers/net/tulip/media.c
drivers/net/tulip/tulip.h
drivers/net/tulip/tulip_core.c
drivers/net/tulip/uli526x.c
drivers/net/tulip/winbond-840.c
drivers/net/tulip/xircom_cb.c
drivers/net/via-velocity.c
drivers/net/via-velocity.h
drivers/net/wan/pci200syn.c
drivers/net/wireless/Kconfig
drivers/net/wireless/Makefile
drivers/net/wireless/airo.c
drivers/net/wireless/bcm43xx/bcm43xx.h
drivers/net/wireless/bcm43xx/bcm43xx_debugfs.c
drivers/net/wireless/bcm43xx/bcm43xx_main.c
drivers/net/wireless/hermes.c
drivers/net/wireless/hermes.h
drivers/net/wireless/hostap/hostap_80211_tx.c
drivers/net/wireless/hostap/hostap_ap.c
drivers/net/wireless/hostap/hostap_cs.c
drivers/net/wireless/hostap/hostap_main.c
drivers/net/wireless/ipw2200.c
drivers/net/wireless/ipw2200.h
drivers/net/wireless/orinoco.c
drivers/net/wireless/orinoco.h
drivers/net/wireless/orinoco_cs.c
drivers/net/wireless/orinoco_nortel.c
drivers/net/wireless/orinoco_pci.c
drivers/net/wireless/orinoco_pci.h [new file with mode: 0644]
drivers/net/wireless/orinoco_plx.c
drivers/net/wireless/orinoco_tmd.c
drivers/net/wireless/spectrum_cs.c
drivers/net/wireless/zd1201.c [moved from drivers/usb/net/zd1201.c with 97% similarity]
drivers/net/wireless/zd1201.h [moved from drivers/usb/net/zd1201.h with 100% similarity]
drivers/pci/pci-driver.c
drivers/pci/pci.c
drivers/s390/net/Makefile
drivers/s390/net/ctcmain.c
drivers/s390/net/ctcmain.h
drivers/s390/net/ctctty.c [deleted file]
drivers/s390/net/ctctty.h [deleted file]
drivers/scsi/libata-core.c
drivers/scsi/sata_mv.c
drivers/usb/host/ohci-pxa27x.c
drivers/usb/net/Kconfig
drivers/usb/net/Makefile
drivers/video/Kconfig
drivers/video/intelfb/intelfb.h
drivers/video/intelfb/intelfbdrv.c
drivers/video/intelfb/intelfbhw.c
drivers/video/intelfb/intelfbhw.h
fs/bio.c
fs/locks.c
include/asm-arm/arch-pxa/ohci.h
include/asm-mips/addrspace.h
include/asm-mips/apm.h [new file with mode: 0644]
include/asm-mips/asmmacro-32.h
include/asm-mips/asmmacro-64.h
include/asm-mips/bootinfo.h
include/asm-mips/ddb5074.h [deleted file]
include/asm-mips/ddb5xxx/ddb5074.h [deleted file]
include/asm-mips/ddb5xxx/ddb5476.h [deleted file]
include/asm-mips/ddb5xxx/ddb5xxx.h
include/asm-mips/emma2rh/emma2rh.h [new file with mode: 0644]
include/asm-mips/emma2rh/markeins.h [new file with mode: 0644]
include/asm-mips/fpu.h
include/asm-mips/fpu_emulator.h
include/asm-mips/futex.h
include/asm-mips/mach-ddb5074/mc146818rtc.h [deleted file]
include/asm-mips/mach-dec/param.h [deleted file]
include/asm-mips/mach-emma2rh/irq.h [moved from include/asm-mips/mach-mips/param.h with 58% similarity]
include/asm-mips/mach-excite/cpu-feature-overrides.h [new file with mode: 0644]
include/asm-mips/mach-excite/excite.h [new file with mode: 0644]
include/asm-mips/mach-excite/excite_nandflash.h [new file with mode: 0644]
include/asm-mips/mach-excite/rm9k_eth.h [new file with mode: 0644]
include/asm-mips/mach-excite/rm9k_wdt.h [new file with mode: 0644]
include/asm-mips/mach-excite/rm9k_xicap.h [new file with mode: 0644]
include/asm-mips/mach-generic/param.h [deleted file]
include/asm-mips/mach-ip22/cpu-feature-overrides.h
include/asm-mips/mach-ip27/cpu-feature-overrides.h
include/asm-mips/mach-ip32/cpu-feature-overrides.h
include/asm-mips/mach-jazz/param.h [deleted file]
include/asm-mips/mach-mips/cpu-feature-overrides.h
include/asm-mips/mach-qemu/param.h [deleted file]
include/asm-mips/mach-rm200/cpu-feature-overrides.h
include/asm-mips/mach-sim/cpu-feature-overrides.h
include/asm-mips/mach-wrppmc/mach-gt64120.h [new file with mode: 0644]
include/asm-mips/mipsregs.h
include/asm-mips/mmzone.h
include/asm-mips/page.h
include/asm-mips/param.h
include/asm-mips/pci/bridge.h
include/asm-mips/pgtable.h
include/asm-mips/processor.h
include/asm-mips/qemu.h
include/asm-mips/rm9k-ocd.h [new file with mode: 0644]
include/asm-mips/sn/addrs.h
include/asm-mips/sn/fru.h [moved from include/asm-mips/sn/sn0/sn0_fru.h with 90% similarity]
include/asm-mips/sn/klconfig.h
include/asm-mips/sn/kldir.h
include/asm-mips/sn/sn0/addrs.h
include/asm-mips/sn/sn0/arch.h
include/asm-mips/sn/sn0/hub.h
include/asm-mips/sn/sn0/hubio.h
include/asm-mips/sn/sn0/hubmd.h
include/asm-mips/sn/sn0/hubpi.h
include/asm-mips/sn/sn0/ip27.h
include/asm-mips/sni.h
include/asm-mips/war.h
include/asm-powerpc/cputable.h
include/linux/console.h
include/linux/dmaengine.h [new file with mode: 0644]
include/linux/i2o.h
include/linux/igmp.h
include/linux/netdevice.h
include/linux/netfilter/nf_conntrack_common.h
include/linux/netfilter/nfnetlink_conntrack.h
include/linux/netfilter/xt_CONNSECMARK.h [new file with mode: 0644]
include/linux/netfilter/xt_SECMARK.h [new file with mode: 0644]
include/linux/netfilter/xt_quota.h [new file with mode: 0644]
include/linux/netfilter/xt_statistic.h [new file with mode: 0644]
include/linux/netfilter_ipv4/ip_conntrack.h
include/linux/netfilter_ipv4/ip_conntrack_h323.h
include/linux/netfilter_ipv4/ip_conntrack_helper_h323_types.h
include/linux/netfilter_ipv4/ip_conntrack_sip.h [new file with mode: 0644]
include/linux/pci-acpi.h
include/linux/pci.h
include/linux/pci_ids.h
include/linux/pfkeyv2.h
include/linux/security.h
include/linux/selinux.h
include/linux/skbuff.h
include/linux/sysctl.h
include/linux/tcp.h
include/linux/xfrm.h
include/net/ieee80211.h
include/net/ieee80211softmac.h
include/net/ieee80211softmac_wx.h
include/net/ip.h
include/net/llc_if.h
include/net/netdma.h [new file with mode: 0644]
include/net/netfilter/nf_conntrack.h
include/net/netfilter/nf_conntrack_compat.h
include/net/raw.h
include/net/sctp/sctp.h
include/net/sctp/structs.h
include/net/sock.h
include/net/tcp.h
include/net/xfrm.h
include/rdma/ib_addr.h [new file with mode: 0644]
include/rdma/ib_cache.h
include/rdma/ib_cm.h
include/rdma/ib_marshall.h [new file with mode: 0644]
include/rdma/ib_sa.h
include/rdma/ib_smi.h
include/rdma/ib_user_cm.h
include/rdma/ib_user_sa.h [new file with mode: 0644]
include/rdma/ib_user_verbs.h
include/rdma/ib_verbs.h
include/rdma/rdma_cm.h [new file with mode: 0644]
include/rdma/rdma_cm_ib.h [new file with mode: 0644]
include/scsi/srp.h
kernel/exit.c
kernel/posix-cpu-timers.c
kernel/power/main.c
kernel/printk.c
mm/shmem.c
mm/vmscan.c
net/Kconfig
net/atm/clip.c
net/bridge/Makefile
net/bridge/br.c
net/bridge/br_device.c
net/bridge/br_forward.c
net/bridge/br_if.c
net/bridge/br_netfilter.c
net/bridge/br_netlink.c [new file with mode: 0644]
net/bridge/br_notify.c
net/bridge/br_private.h
net/bridge/br_stp_if.c
net/core/Makefile
net/core/dev.c
net/core/dev_mcast.c
net/core/ethtool.c
net/core/netpoll.c
net/core/pktgen.c
net/core/skbuff.c
net/core/sock.c
net/core/user_dma.c [new file with mode: 0644]
net/dccp/ackvec.c
net/dccp/proto.c
net/decnet/dn_nsp_in.c
net/decnet/dn_route.c
net/ieee80211/ieee80211_crypt_tkip.c
net/ieee80211/ieee80211_rx.c
net/ieee80211/ieee80211_tx.c
net/ieee80211/ieee80211_wx.c
net/ieee80211/softmac/Kconfig
net/ieee80211/softmac/ieee80211softmac_assoc.c
net/ieee80211/softmac/ieee80211softmac_auth.c
net/ieee80211/softmac/ieee80211softmac_event.c
net/ieee80211/softmac/ieee80211softmac_io.c
net/ieee80211/softmac/ieee80211softmac_module.c
net/ieee80211/softmac/ieee80211softmac_priv.h
net/ieee80211/softmac/ieee80211softmac_wx.c
net/ipv4/Kconfig
net/ipv4/Makefile
net/ipv4/ah4.c
net/ipv4/esp4.c
net/ipv4/fib_frontend.c
net/ipv4/icmp.c
net/ipv4/igmp.c
net/ipv4/ip_forward.c
net/ipv4/ip_output.c
net/ipv4/ipcomp.c
net/ipv4/netfilter/Kconfig
net/ipv4/netfilter/Makefile
net/ipv4/netfilter/ip_conntrack_amanda.c
net/ipv4/netfilter/ip_conntrack_core.c
net/ipv4/netfilter/ip_conntrack_ftp.c
net/ipv4/netfilter/ip_conntrack_helper_h323.c
net/ipv4/netfilter/ip_conntrack_helper_h323_types.c
net/ipv4/netfilter/ip_conntrack_netlink.c
net/ipv4/netfilter/ip_conntrack_proto_gre.c
net/ipv4/netfilter/ip_conntrack_proto_icmp.c
net/ipv4/netfilter/ip_conntrack_proto_tcp.c
net/ipv4/netfilter/ip_conntrack_proto_udp.c
net/ipv4/netfilter/ip_conntrack_sip.c [new file with mode: 0644]
net/ipv4/netfilter/ip_conntrack_standalone.c
net/ipv4/netfilter/ip_nat_helper_h323.c
net/ipv4/netfilter/ip_nat_sip.c [new file with mode: 0644]
net/ipv4/netfilter/ip_nat_snmp_basic.c
net/ipv4/netfilter/ipt_CLUSTERIP.c
net/ipv4/netfilter/ipt_REJECT.c
net/ipv4/netfilter/ipt_hashlimit.c
net/ipv4/netfilter/ipt_recent.c
net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
net/ipv4/netfilter/nf_conntrack_proto_icmp.c
net/ipv4/raw.c
net/ipv4/sysctl_net_ipv4.c
net/ipv4/tcp.c
net/ipv4/tcp_bic.c
net/ipv4/tcp_compound.c [new file with mode: 0644]
net/ipv4/tcp_cong.c
net/ipv4/tcp_cubic.c
net/ipv4/tcp_highspeed.c
net/ipv4/tcp_htcp.c
net/ipv4/tcp_input.c
net/ipv4/tcp_ipv4.c
net/ipv4/tcp_lp.c [new file with mode: 0644]
net/ipv4/tcp_output.c
net/ipv4/tcp_probe.c [new file with mode: 0644]
net/ipv4/tcp_veno.c [new file with mode: 0644]
net/ipv4/tcp_westwood.c
net/ipv4/xfrm4_input.c
net/ipv4/xfrm4_mode_transport.c [new file with mode: 0644]
net/ipv4/xfrm4_mode_tunnel.c [new file with mode: 0644]
net/ipv4/xfrm4_output.c
net/ipv4/xfrm4_policy.c
net/ipv4/xfrm4_state.c
net/ipv6/Kconfig
net/ipv6/Makefile
net/ipv6/addrconf.c
net/ipv6/ah6.c
net/ipv6/esp6.c
net/ipv6/ip6_output.c
net/ipv6/ipcomp6.c
net/ipv6/netfilter/nf_conntrack_l3proto_ipv6.c
net/ipv6/netfilter/nf_conntrack_proto_icmpv6.c
net/ipv6/netfilter/nf_conntrack_reasm.c
net/ipv6/tcp_ipv6.c
net/ipv6/xfrm6_input.c
net/ipv6/xfrm6_mode_transport.c [new file with mode: 0644]
net/ipv6/xfrm6_mode_tunnel.c [new file with mode: 0644]
net/ipv6/xfrm6_output.c
net/ipv6/xfrm6_policy.c
net/ipv6/xfrm6_state.c
net/ipx/ipx_route.c
net/irda/irlmp.c
net/key/af_key.c
net/llc/af_llc.c
net/llc/llc_if.c
net/llc/llc_input.c
net/llc/llc_sap.c
net/netfilter/Kconfig
net/netfilter/Makefile
net/netfilter/nf_conntrack_core.c
net/netfilter/nf_conntrack_ftp.c
net/netfilter/nf_conntrack_netlink.c
net/netfilter/nf_conntrack_proto_tcp.c
net/netfilter/nf_conntrack_proto_udp.c
net/netfilter/nf_conntrack_standalone.c
net/netfilter/xt_CONNSECMARK.c [new file with mode: 0644]
net/netfilter/xt_SECMARK.c [new file with mode: 0644]
net/netfilter/xt_connmark.c
net/netfilter/xt_dccp.c
net/netfilter/xt_mark.c
net/netfilter/xt_multiport.c
net/netfilter/xt_quota.c [new file with mode: 0644]
net/netfilter/xt_sctp.c
net/netfilter/xt_statistic.c [new file with mode: 0644]
net/netfilter/xt_string.c
net/sched/sch_generic.c
net/sched/sch_teql.c
net/sctp/input.c
net/sctp/ipv6.c
net/sctp/output.c
net/sctp/outqueue.c
net/sctp/protocol.c
net/sctp/sm_statefuns.c
net/sctp/socket.c
net/sctp/ulpevent.c
net/xfrm/xfrm_policy.c
net/xfrm/xfrm_state.c
net/xfrm/xfrm_user.c
security/dummy.c
security/selinux/Kconfig
security/selinux/exports.c
security/selinux/hooks.c
security/selinux/include/av_inherit.h
security/selinux/include/av_perm_to_string.h
security/selinux/include/av_permissions.h
security/selinux/include/class_to_string.h
security/selinux/include/flask.h
security/selinux/include/xfrm.h
security/selinux/selinuxfs.c
security/selinux/xfrm.c
sound/oss/Kconfig

index 43ab119..f50cf8f 100644 (file)
@@ -212,15 +212,6 @@ Who:       Greg Kroah-Hartman <gregkh@suse.de>
 
 ---------------------------
 
-What:  Support for NEC DDB5074 and DDB5476 evaluation boards.
-When:  June 2006
-Why:   Board specific code doesn't build anymore since ~2.6.0 and no
-       users have complained indicating there is no more need for these
-       boards.  This should really be considered a last call.
-Who:   Ralf Baechle <ralf@linux-mips.org>
-
----------------------------
-
 What:  USB driver API moves to EXPORT_SYMBOL_GPL
 When:  Febuary 2008
 Files: include/linux/usb.h, drivers/usb/core/driver.c
index 5c5a4cc..1870355 100644 (file)
@@ -1,10 +1,10 @@
 IP OVER INFINIBAND
 
   The ib_ipoib driver is an implementation of the IP over InfiniBand
-  protocol as specified by the latest Internet-Drafts issued by the
-  IETF ipoib working group.  It is a "native" implementation in the
-  sense of setting the interface type to ARPHRD_INFINIBAND and the
-  hardware address length to 20 (earlier proprietary implementations
+  protocol as specified by RFC 4391 and 4392, issued by the IETF ipoib
+  working group.  It is a "native" implementation in the sense of
+  setting the interface type to ARPHRD_INFINIBAND and the hardware
+  address length to 20 (earlier proprietary implementations
   masqueraded to the kernel as ethernet interfaces).
 
 Partitions and P_Keys
@@ -53,3 +53,7 @@ References
 
   IETF IP over InfiniBand (ipoib) Working Group
     http://ietf.org/html.charters/ipoib-charter.html
+  Transmission of IP over InfiniBand (IPoIB) (RFC 4391)
+    http://ietf.org/rfc/rfc4391.txt 
+  IP over InfiniBand (IPoIB) Architecture (RFC 4392)
+    http://ietf.org/rfc/rfc4392.txt 
index b3a6187..a9d3a17 100644 (file)
@@ -1402,6 +1402,15 @@ running once the system is up.
                        If enabled at boot time, /selinux/disable can be used
                        later to disable prior to initial policy load.
 
+       selinux_compat_net =
+                       [SELINUX] Set initial selinux_compat_net flag value.
+                        Format: { "0" | "1" }
+                        0 -- use new secmark-based packet controls
+                        1 -- use legacy packet controls
+                        Default value is 0 (preferred).
+                        Value can be changed at runtime via
+                        /selinux/compat_net.
+
        serialnumber    [BUGS=IA-32]
 
        sg_def_reserved_size=   [SCSI]
index c61d8b8..4710845 100644 (file)
@@ -19,6 +19,7 @@ Contents:
      - Control dependencies.
      - SMP barrier pairing.
      - Examples of memory barrier sequences.
+     - Read memory barriers vs load speculation.
 
  (*) Explicit kernel barriers.
 
@@ -248,7 +249,7 @@ And there are a number of things that _must_ or _must_not_ be assumed:
      we may get either of:
 
        STORE *A = X; Y = LOAD *A;
-       STORE *A = Y;
+       STORE *A = Y = X;
 
 
 =========================
@@ -344,9 +345,12 @@ Memory barriers come in four basic varieties:
 
  (4) General memory barriers.
 
-     A general memory barrier is a combination of both a read memory barrier
-     and a write memory barrier.  It is a partial ordering over both loads and
-     stores.
+     A general memory barrier gives a guarantee that all the LOAD and STORE
+     operations specified before the barrier will appear to happen before all
+     the LOAD and STORE operations specified after the barrier with respect to
+     the other components of the system.
+
+     A general memory barrier is a partial ordering over both loads and stores.
 
      General memory barriers imply both read and write memory barriers, and so
      can substitute for either.
@@ -546,9 +550,9 @@ write barrier, though, again, a general barrier is viable:
        =============== ===============
        a = 1;
        <write barrier>
-       b = 2;          x = a;
+       b = 2;          x = b;
                        <read barrier>
-                       y = b;
+                       y = a;
 
 Or:
 
@@ -563,6 +567,18 @@ Or:
 Basically, the read barrier always has to be there, even though it can be of
 the "weaker" type.
 
+[!] Note that the stores before the write barrier would normally be expected to
+match the loads after the read barrier or data dependency barrier, and vice
+versa:
+
+       CPU 1                           CPU 2
+       ===============                 ===============
+       a = 1;           }----   --->{  v = c
+       b = 2;           }    \ /    {  w = d
+       <write barrier>        \        <read barrier>
+       c = 3;           }    / \    {  x = a;
+       d = 4;           }----   --->{  y = b;
+
 
 EXAMPLES OF MEMORY BARRIER SEQUENCES
 ------------------------------------
@@ -600,8 +616,8 @@ STORE B, STORE C } all occuring before the unordered set of { STORE D, STORE E
        |       |       +------+
        +-------+       :      :
                           |
-                          | Sequence in which stores committed to memory system
-                          | by CPU 1
+                          | Sequence in which stores are committed to the
+                          | memory system by CPU 1
                           V
 
 
@@ -683,14 +699,12 @@ then the following will occur:
                                       |        :       :       |       |
                                       |        :       :       | CPU 2 |
                                       |        +-------+       |       |
-                                       \       | X->9  |------>|       |
-                                        \      +-------+       |       |
-                                         ----->| B->2  |       |       |
-                                               +-------+       |       |
-            Makes sure all effects --->    ddddddddddddddddd   |       |
-            prior to the store of C            +-------+       |       |
-            are perceptible to                 | B->2  |------>|       |
-            successive loads                   +-------+       |       |
+                                      |        | X->9  |------>|       |
+                                      |        +-------+       |       |
+         Makes sure all effects --->   \   ddddddddddddddddd   |       |
+         prior to the store of C        \      +-------+       |       |
+         are perceptible to              ----->| B->2  |------>|       |
+         subsequent loads                      +-------+       |       |
                                                :       :       +-------+
 
 
@@ -699,73 +713,239 @@ following sequence of events:
 
        CPU 1                   CPU 2
        ======================= =======================
+               { A = 0, B = 9 }
        STORE A=1
-       STORE B=2
-       STORE C=3
        <write barrier>
-       STORE D=4
-       STORE E=5
-                               LOAD A
+       STORE B=2
                                LOAD B
-                               LOAD C
-                               LOAD D
-                               LOAD E
+                               LOAD A
 
 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
 some effectively random order, despite the write barrier issued by CPU 1:
 
-       +-------+       :      :
-       |       |       +------+
-       |       |------>| C=3  | }
-       |       |  :    +------+ }
-       |       |  :    | A=1  | }
-       |       |  :    +------+ }
-       | CPU 1 |  :    | B=2  | }---
-       |       |       +------+ }   \
-       |       |   wwwwwwwwwwwww}    \
-       |       |       +------+ }     \          :       :       +-------+
-       |       |  :    | E=5  | }      \         +-------+       |       |
-       |       |  :    +------+ }       \      { | C->3  |------>|       |
-       |       |------>| D=4  | }        \     { +-------+    :  |       |
-       |       |       +------+           \    { | E->5  |    :  |       |
-       +-------+       :      :            \   { +-------+    :  |       |
-                                  Transfer  -->{ | A->1  |    :  | CPU 2 |
-                                 from CPU 1    { +-------+    :  |       |
-                                  to CPU 2     { | D->4  |    :  |       |
-                                               { +-------+    :  |       |
-                                               { | B->2  |------>|       |
-                                                 +-------+       |       |
-                                                 :       :       +-------+
-
-
-If, however, a read barrier were to be placed between the load of C and the
-load of D on CPU 2, then the partial ordering imposed by CPU 1 will be
-perceived correctly by CPU 2.
+       +-------+       :      :                :       :
+       |       |       +------+                +-------+
+       |       |------>| A=1  |------      --->| A->0  |
+       |       |       +------+      \         +-------+
+       | CPU 1 |   wwwwwwwwwwwwwwww   \    --->| B->9  |
+       |       |       +------+        |       +-------+
+       |       |------>| B=2  |---     |       :       :
+       |       |       +------+   \    |       :       :       +-------+
+       +-------+       :      :    \   |       +-------+       |       |
+                                    ---------->| B->2  |------>|       |
+                                       |       +-------+       | CPU 2 |
+                                       |       | A->0  |------>|       |
+                                       |       +-------+       |       |
+                                       |       :       :       +-------+
+                                        \      :       :
+                                         \     +-------+
+                                          ---->| A->1  |
+                                               +-------+
+                                               :       :
 
-       +-------+       :      :
-       |       |       +------+
-       |       |------>| C=3  | }
-       |       |  :    +------+ }
-       |       |  :    | A=1  | }---
-       |       |  :    +------+ }   \
-       | CPU 1 |  :    | B=2  | }    \
-       |       |       +------+       \
-       |       |   wwwwwwwwwwwwwwww    \
-       |       |       +------+         \        :       :       +-------+
-       |       |  :    | E=5  | }        \       +-------+       |       |
-       |       |  :    +------+ }---      \    { | C->3  |------>|       |
-       |       |------>| D=4  | }   \      \   { +-------+    :  |       |
-       |       |       +------+      \      -->{ | B->2  |    :  |       |
-       +-------+       :      :       \        { +-------+    :  |       |
-                                       \       { | A->1  |    :  | CPU 2 |
-                                        \        +-------+       |       |
-          At this point the read ---->   \   rrrrrrrrrrrrrrrrr   |       |
-          barrier causes all effects      \      +-------+       |       |
-          prior to the storage of C        \   { | E->5  |    :  |       |
-          to be perceptible to CPU 2        -->{ +-------+    :  |       |
-                                               { | D->4  |------>|       |
-                                                 +-------+       |       |
-                                                 :       :       +-------+
+
+If, however, a read barrier were to be placed between the load of E and the
+load of A on CPU 2:
+
+       CPU 1                   CPU 2
+       ======================= =======================
+               { A = 0, B = 9 }
+       STORE A=1
+       <write barrier>
+       STORE B=2
+                               LOAD B
+                               <read barrier>
+                               LOAD A
+
+then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
+2:
+
+       +-------+       :      :                :       :
+       |       |       +------+                +-------+
+       |       |------>| A=1  |------      --->| A->0  |
+       |       |       +------+      \         +-------+
+       | CPU 1 |   wwwwwwwwwwwwwwww   \    --->| B->9  |
+       |       |       +------+        |       +-------+
+       |       |------>| B=2  |---     |       :       :
+       |       |       +------+   \    |       :       :       +-------+
+       +-------+       :      :    \   |       +-------+       |       |
+                                    ---------->| B->2  |------>|       |
+                                       |       +-------+       | CPU 2 |
+                                       |       :       :       |       |
+                                       |       :       :       |       |
+         At this point the read ---->   \  rrrrrrrrrrrrrrrrr   |       |
+         barrier causes all effects      \     +-------+       |       |
+         prior to the storage of B        ---->| A->1  |------>|       |
+         to be perceptible to CPU 2            +-------+       |       |
+                                               :       :       +-------+
+
+
+To illustrate this more completely, consider what could happen if the code
+contained a load of A either side of the read barrier:
+
+       CPU 1                   CPU 2
+       ======================= =======================
+               { A = 0, B = 9 }
+       STORE A=1
+       <write barrier>
+       STORE B=2
+                               LOAD B
+                               LOAD A [first load of A]
+                               <read barrier>
+                               LOAD A [second load of A]
+
+Even though the two loads of A both occur after the load of B, they may both
+come up with different values:
+
+       +-------+       :      :                :       :
+       |       |       +------+                +-------+
+       |       |------>| A=1  |------      --->| A->0  |
+       |       |       +------+      \         +-------+
+       | CPU 1 |   wwwwwwwwwwwwwwww   \    --->| B->9  |
+       |       |       +------+        |       +-------+
+       |       |------>| B=2  |---     |       :       :
+       |       |       +------+   \    |       :       :       +-------+
+       +-------+       :      :    \   |       +-------+       |       |
+                                    ---------->| B->2  |------>|       |
+                                       |       +-------+       | CPU 2 |
+                                       |       :       :       |       |
+                                       |       :       :       |       |
+                                       |       +-------+       |       |
+                                       |       | A->0  |------>| 1st   |
+                                       |       +-------+       |       |
+         At this point the read ---->   \  rrrrrrrrrrrrrrrrr   |       |
+         barrier causes all effects      \     +-------+       |       |
+         prior to the storage of B        ---->| A->1  |------>| 2nd   |
+         to be perceptible to CPU 2            +-------+       |       |
+                                               :       :       +-------+
+
+
+But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
+before the read barrier completes anyway:
+
+       +-------+       :      :                :       :
+       |       |       +------+                +-------+
+       |       |------>| A=1  |------      --->| A->0  |
+       |       |       +------+      \         +-------+
+       | CPU 1 |   wwwwwwwwwwwwwwww   \    --->| B->9  |
+       |       |       +------+        |       +-------+
+       |       |------>| B=2  |---     |       :       :
+       |       |       +------+   \    |       :       :       +-------+
+       +-------+       :      :    \   |       +-------+       |       |
+                                    ---------->| B->2  |------>|       |
+                                       |       +-------+       | CPU 2 |
+                                       |       :       :       |       |
+                                        \      :       :       |       |
+                                         \     +-------+       |       |
+                                          ---->| A->1  |------>| 1st   |
+                                               +-------+       |       |
+                                           rrrrrrrrrrrrrrrrr   |       |
+                                               +-------+       |       |
+                                               | A->1  |------>| 2nd   |
+                                               +-------+       |       |
+                                               :       :       +-------+
+
+
+The guarantee is that the second load will always come up with A == 1 if the
+load of B came up with B == 2.  No such guarantee exists for the first load of
+A; that may come up with either A == 0 or A == 1.
+
+
+READ MEMORY BARRIERS VS LOAD SPECULATION
+----------------------------------------
+
+Many CPUs speculate with loads: that is they see that they will need to load an
+item from memory, and they find a time where they're not using the bus for any
+other loads, and so do the load in advance - even though they haven't actually
+got to that point in the instruction execution flow yet.  This permits the
+actual load instruction to potentially complete immediately because the CPU
+already has the value to hand.
+
+It may turn out that the CPU didn't actually need the value - perhaps because a
+branch circumvented the load - in which case it can discard the value or just
+cache it for later use.
+
+Consider:
+
+       CPU 1                   CPU 2
+       ======================= =======================
+                               LOAD B
+                               DIVIDE          } Divide instructions generally
+                               DIVIDE          } take a long time to perform
+                               LOAD A
+
+Which might appear as this:
+
+                                               :       :       +-------+
+                                               +-------+       |       |
+                                           --->| B->2  |------>|       |
+                                               +-------+       | CPU 2 |
+                                               :       :DIVIDE |       |
+                                               +-------+       |       |
+       The CPU being busy doing a --->     --->| A->0  |~~~~   |       |
+       division speculates on the              +-------+   ~   |       |
+       LOAD of A                               :       :   ~   |       |
+                                               :       :DIVIDE |       |
+                                               :       :   ~   |       |
+       Once the divisions are complete -->     :       :   ~-->|       |
+       the CPU can then perform the            :       :       |       |
+       LOAD with immediate effect              :       :       +-------+
+
+
+Placing a read barrier or a data dependency barrier just before the second
+load:
+
+       CPU 1                   CPU 2
+       ======================= =======================
+                               LOAD B
+                               DIVIDE
+                               DIVIDE
+                               <read barrier>
+                               LOAD A
+
+will force any value speculatively obtained to be reconsidered to an extent
+dependent on the type of barrier used.  If there was no change made to the
+speculated memory location, then the speculated value will just be used:
+
+                                               :       :       +-------+
+                                               +-------+       |       |
+                                           --->| B->2  |------>|       |
+                                               +-------+       | CPU 2 |
+                                               :       :DIVIDE |       |
+                                               +-------+       |       |
+       The CPU being busy doing a --->     --->| A->0  |~~~~   |       |
+       division speculates on the              +-------+   ~   |       |
+       LOAD of A                               :       :   ~   |       |
+                                               :       :DIVIDE |       |
+                                               :       :   ~   |       |
+                                               :       :   ~   |       |
+                                           rrrrrrrrrrrrrrrr~   |       |
+                                               :       :   ~   |       |
+                                               :       :   ~-->|       |
+                                               :       :       |       |
+                                               :       :       +-------+
+
+
+but if there was an update or an invalidation from another CPU pending, then
+the speculation will be cancelled and the value reloaded:
+
+                                               :       :       +-------+
+                                               +-------+       |       |
+                                           --->| B->2  |------>|       |
+                                               +-------+       | CPU 2 |
+                                               :       :DIVIDE |       |
+                                               +-------+       |       |
+       The CPU being busy doing a --->     --->| A->0  |~~~~   |       |
+       division speculates on the              +-------+   ~   |       |
+       LOAD of A                               :       :   ~   |       |
+                                               :       :DIVIDE |       |
+                                               :       :   ~   |       |
+                                               :       :   ~   |       |
+                                           rrrrrrrrrrrrrrrrr   |       |
+                                               +-------+       |       |
+       The speculation is discarded --->   --->| A->1  |------>|       |
+       and an updated value is                 +-------+       |       |
+       retrieved                               :       :       +-------+
 
 
 ========================
@@ -901,7 +1081,7 @@ IMPLICIT KERNEL MEMORY BARRIERS
 ===============================
 
 Some of the other functions in the linux kernel imply memory barriers, amongst
-which are locking, scheduling and memory allocation functions.
+which are locking and scheduling functions.
 
 This specification is a _minimum_ guarantee; any particular architecture may
 provide more substantial guarantees, but these may not be relied upon outside
@@ -966,6 +1146,20 @@ equivalent to a full barrier, but a LOCK followed by an UNLOCK is not.
     barriers is that the effects instructions outside of a critical section may
     seep into the inside of the critical section.
 
+A LOCK followed by an UNLOCK may not be assumed to be full memory barrier
+because it is possible for an access preceding the LOCK to happen after the
+LOCK, and an access following the UNLOCK to happen before the UNLOCK, and the
+two accesses can themselves then cross:
+
+       *A = a;
+       LOCK
+       UNLOCK
+       *B = b;
+
+may occur as:
+
+       LOCK, STORE *B, STORE *A, UNLOCK
+
 Locks and semaphores may not provide any guarantee of ordering on UP compiled
 systems, and so cannot be counted on in such a situation to actually achieve
 anything at all - especially with respect to I/O accesses - unless combined
@@ -1016,8 +1210,6 @@ Other functions that imply barriers:
 
  (*) schedule() and similar imply full memory barriers.
 
- (*) Memory allocation and release functions imply full memory barriers.
-
 
 =================================
 INTER-CPU LOCKING BARRIER EFFECTS
index acb30c5..4f2a40f 100644 (file)
@@ -14,8 +14,8 @@ Copyright (C) 2004-2006, Intel Corporation
 
 README.ipw2200
 
-Version: 1.0.8
-Date   : October 20, 2005
+Version: 1.1.2
+Date   : March 30, 2006
 
 
 Index
@@ -103,7 +103,7 @@ file.
 
 1.1. Overview of Features
 -----------------------------------------------
-The current release (1.0.8) supports the following features:
+The current release (1.1.2) supports the following features:
 
 + BSS mode (Infrastructure, Managed)
 + IBSS mode (Ad-Hoc)
@@ -247,8 +247,8 @@ and can set the contents via echo.  For example:
 % cat /sys/bus/pci/drivers/ipw2200/debug_level
 
 Will report the current debug level of the driver's logging subsystem 
-(only available if CONFIG_IPW_DEBUG was configured when the driver was 
-built).
+(only available if CONFIG_IPW2200_DEBUG was configured when the driver
+was built).
 
 You can set the debug level via:
 
index 8d8b4e5..afac780 100644 (file)
@@ -1,7 +1,7 @@
 
                Linux Ethernet Bonding Driver HOWTO
 
-               Latest update: 21 June 2005
+               Latest update: 24 April 2006
 
 Initial release : Thomas Davis <tadavis at lbl.gov>
 Corrections, HA extensions : 2000/10/03-15 :
@@ -12,6 +12,8 @@ Corrections, HA extensions : 2000/10/03-15 :
   - Jay Vosburgh <fubar at us dot ibm dot com>
 
 Reorganized and updated Feb 2005 by Jay Vosburgh
+Added Sysfs information: 2006/04/24
+  - Mitch Williams <mitch.a.williams at intel.com>
 
 Introduction
 ============
@@ -38,61 +40,62 @@ Table of Contents
 2. Bonding Driver Options
 
 3. Configuring Bonding Devices
-3.1    Configuration with sysconfig support
-3.1.1          Using DHCP with sysconfig
-3.1.2          Configuring Multiple Bonds with sysconfig
-3.2    Configuration with initscripts support
-3.2.1          Using DHCP with initscripts
-3.2.2          Configuring Multiple Bonds with initscripts
-3.3    Configuring Bonding Manually
+3.1    Configuration with Sysconfig Support
+3.1.1          Using DHCP with Sysconfig
+3.1.2          Configuring Multiple Bonds with Sysconfig
+3.2    Configuration with Initscripts Support
+3.2.1          Using DHCP with Initscripts
+3.2.2          Configuring Multiple Bonds with Initscripts
+3.3    Configuring Bonding Manually with Ifenslave
 3.3.1          Configuring Multiple Bonds Manually
+3.4    Configuring Bonding Manually via Sysfs
 
-5. Querying Bonding Configuration
-5.1    Bonding Configuration
-5.2    Network Configuration
+4. Querying Bonding Configuration
+4.1    Bonding Configuration
+4.2    Network Configuration
 
-6. Switch Configuration
+5. Switch Configuration
 
-7. 802.1q VLAN Support
+6. 802.1q VLAN Support
 
-8. Link Monitoring
-8.1    ARP Monitor Operation
-8.2    Configuring Multiple ARP Targets
-8.3    MII Monitor Operation
+7. Link Monitoring
+7.1    ARP Monitor Operation
+7.2    Configuring Multiple ARP Targets
+7.3    MII Monitor Operation
 
-9. Potential Trouble Sources
-9.1    Adventures in Routing
-9.2    Ethernet Device Renaming
-9.3    Painfully Slow Or No Failed Link Detection By Miimon
+8. Potential Trouble Sources
+8.1    Adventures in Routing
+8.2    Ethernet Device Renaming
+8.3    Painfully Slow Or No Failed Link Detection By Miimon
 
-10. SNMP agents
+9. SNMP agents
 
-11. Promiscuous mode
+10. Promiscuous mode
 
-12. Configuring Bonding for High Availability
-12.1   High Availability in a Single Switch Topology
-12.2   High Availability in a Multiple Switch Topology
-12.2.1         HA Bonding Mode Selection for Multiple Switch Topology
-12.2.2         HA Link Monitoring for Multiple Switch Topology
+11. Configuring Bonding for High Availability
+11.1   High Availability in a Single Switch Topology
+11.2   High Availability in a Multiple Switch Topology
+11.2.1         HA Bonding Mode Selection for Multiple Switch Topology
+11.2.2         HA Link Monitoring for Multiple Switch Topology
 
-13. Configuring Bonding for Maximum Throughput
-13.1   Maximum Throughput in a Single Switch Topology
-13.1.1         MT Bonding Mode Selection for Single Switch Topology
-13.1.2         MT Link Monitoring for Single Switch Topology
-13.2   Maximum Throughput in a Multiple Switch Topology
-13.2.1         MT Bonding Mode Selection for Multiple Switch Topology
-13.2.2         MT Link Monitoring for Multiple Switch Topology
+12. Configuring Bonding for Maximum Throughput
+12.1   Maximum Throughput in a Single Switch Topology
+12.1.1         MT Bonding Mode Selection for Single Switch Topology
+12.1.2         MT Link Monitoring for Single Switch Topology
+12.2   Maximum Throughput in a Multiple Switch Topology
+12.2.1         MT Bonding Mode Selection for Multiple Switch Topology
+12.2.2         MT Link Monitoring for Multiple Switch Topology
 
-14. Switch Behavior Issues
-14.1   Link Establishment and Failover Delays
-14.2   Duplicated Incoming Packets
+13. Switch Behavior Issues
+13.1   Link Establishment and Failover Delays
+13.2   Duplicated Incoming Packets
 
-15. Hardware Specific Considerations
-15.1   IBM BladeCenter
+14. Hardware Specific Considerations
+14.1   IBM BladeCenter
 
-16. Frequently Asked Questions
+15. Frequently Asked Questions
 
-17. Resources and Links
+16. Resources and Links
 
 
 1. Bonding Driver Installation
@@ -156,6 +159,9 @@ you're trying to build it for.  Some distros (e.g., Red Hat from 7.1
 onwards) do not have /usr/include/linux symbolically linked to the
 default kernel source include directory.
 
+SECOND IMPORTANT NOTE:
+       If you plan to configure bonding using sysfs, you do not need
+to use ifenslave.
 
 2. Bonding Driver Options
 =========================
@@ -270,7 +276,7 @@ mode
                In bonding version 2.6.2 or later, when a failover
                occurs in active-backup mode, bonding will issue one
                or more gratuitous ARPs on the newly active slave.
-               One gratutious ARP is issued for the bonding master
+               One gratuitous ARP is issued for the bonding master
                interface and each VLAN interfaces configured above
                it, provided that the interface has at least one IP
                address configured.  Gratuitous ARPs issued for VLAN
@@ -377,7 +383,7 @@ mode
                When a link is reconnected or a new slave joins the
                bond the receive traffic is redistributed among all
                active slaves in the bond by initiating ARP Replies
-               with the selected mac address to each of the
+               with the selected MAC address to each of the
                clients. The updelay parameter (detailed below) must
                be set to a value equal or greater than the switch's
                forwarding delay so that the ARP Replies sent to the
@@ -498,11 +504,12 @@ not exist, and the layer2 policy is the only policy.
 3. Configuring Bonding Devices
 ==============================
 
-       There are, essentially, two methods for configuring bonding:
-with support from the distro's network initialization scripts, and
-without.  Distros generally use one of two packages for the network
-initialization scripts: initscripts or sysconfig.  Recent versions of
-these packages have support for bonding, while older versions do not.
+       You can configure bonding using either your distro's network
+initialization scripts, or manually using either ifenslave or the
+sysfs interface.  Distros generally use one of two packages for the
+network initialization scripts: initscripts or sysconfig.  Recent
+versions of these packages have support for bonding, while older
+versions do not.
 
        We will first describe the options for configuring bonding for
 distros using versions of initscripts and sysconfig with full or
@@ -530,7 +537,7 @@ $ grep ifenslave /sbin/ifup
        If this returns any matches, then your initscripts or
 sysconfig has support for bonding.
 
-3.1 Configuration with sysconfig support
+3.1 Configuration with Sysconfig Support
 ----------------------------------------
 
        This section applies to distros using a version of sysconfig
@@ -538,7 +545,7 @@ with bonding support, for example, SuSE Linux Enterprise Server 9.
 
        SuSE SLES 9's networking configuration system does support
 bonding, however, at this writing, the YaST system configuration
-frontend does not provide any means to work with bonding devices.
+front end does not provide any means to work with bonding devices.
 Bonding devices can be managed by hand, however, as follows.
 
        First, if they have not already been configured, configure the
@@ -660,7 +667,7 @@ format can be found in an example ifcfg template file:
        Note that the template does not document the various BONDING_
 settings described above, but does describe many of the other options.
 
-3.1.1 Using DHCP with sysconfig
+3.1.1 Using DHCP with Sysconfig
 -------------------------------
 
        Under sysconfig, configuring a device with BOOTPROTO='dhcp'
@@ -670,7 +677,7 @@ attempt to obtain the device address from DHCP prior to adding any of
 the slave devices.  Without active slaves, the DHCP requests are not
 sent to the network.
 
-3.1.2 Configuring Multiple Bonds with sysconfig
+3.1.2 Configuring Multiple Bonds with Sysconfig
 -----------------------------------------------
 
        The sysconfig network initialization system is capable of
@@ -685,7 +692,7 @@ ifcfg-bondX files.
 options in the ifcfg-bondX file, it is not necessary to add them to
 the system /etc/modules.conf or /etc/modprobe.conf configuration file.
 
-3.2 Configuration with initscripts support
+3.2 Configuration with Initscripts Support
 ------------------------------------------
 
        This section applies to distros using a version of initscripts
@@ -756,7 +763,7 @@ options for your configuration.
 will restart the networking subsystem and your bond link should be now
 up and running.
 
-3.2.1 Using DHCP with initscripts
+3.2.1 Using DHCP with Initscripts
 ---------------------------------
 
        Recent versions of initscripts (the version supplied with
@@ -768,7 +775,7 @@ above, except replace the line "BOOTPROTO=none" with "BOOTPROTO=dhcp"
 and add a line consisting of "TYPE=Bonding".  Note that the TYPE value
 is case sensitive.
 
-3.2.2 Configuring Multiple Bonds with initscripts
+3.2.2 Configuring Multiple Bonds with Initscripts
 -------------------------------------------------
 
        At this writing, the initscripts package does not directly
@@ -784,8 +791,8 @@ Fedora Core kernels, and has been seen on RHEL 4 as well.  On kernels
 exhibiting this problem, it will be impossible to configure multiple
 bonds with differing parameters.
 
-3.3 Configuring Bonding Manually
---------------------------------
+3.3 Configuring Bonding Manually with Ifenslave
+-----------------------------------------------
 
        This section applies to distros whose network initialization
 scripts (the sysconfig or initscripts package) do not have specific
@@ -889,11 +896,139 @@ install bond1 /sbin/modprobe --ignore-install bonding -o bond1 \
        This may be repeated any number of times, specifying a new and
 unique name in place of bond1 for each subsequent instance.
 
+3.4 Configuring Bonding Manually via Sysfs
+------------------------------------------
+
+       Starting with version 3.0, Channel Bonding may be configured
+via the sysfs interface.  This interface allows dynamic configuration
+of all bonds in the system without unloading the module.  It also
+allows for adding and removing bonds at runtime.  Ifenslave is no
+longer required, though it is still supported.
+
+       Use of the sysfs interface allows you to use multiple bonds
+with different configurations without having to reload the module.
+It also allows you to use multiple, differently configured bonds when
+bonding is compiled into the kernel.
+
+       You must have the sysfs filesystem mounted to configure
+bonding this way.  The examples in this document assume that you
+are using the standard mount point for sysfs, e.g. /sys.  If your
+sysfs filesystem is mounted elsewhere, you will need to adjust the
+example paths accordingly.
+
+Creating and Destroying Bonds
+-----------------------------
+To add a new bond foo:
+# echo +foo > /sys/class/net/bonding_masters
+
+To remove an existing bond bar:
+# echo -bar > /sys/class/net/bonding_masters
+
+To show all existing bonds:
+# cat /sys/class/net/bonding_masters
+
+NOTE: due to 4K size limitation of sysfs files, this list may be
+truncated if you have more than a few hundred bonds.  This is unlikely
+to occur under normal operating conditions.
+
+Adding and Removing Slaves
+--------------------------
+       Interfaces may be enslaved to a bond using the file
+/sys/class/net/<bond>/bonding/slaves.  The semantics for this file
+are the same as for the bonding_masters file.
+
+To enslave interface eth0 to bond bond0:
+# ifconfig bond0 up
+# echo +eth0 > /sys/class/net/bond0/bonding/slaves
+
+To free slave eth0 from bond bond0:
+# echo -eth0 > /sys/class/net/bond0/bonding/slaves
+
+       NOTE: The bond must be up before slaves can be added.  All
+slaves are freed when the interface is brought down.
+
+       When an interface is enslaved to a bond, symlinks between the
+two are created in the sysfs filesystem.  In this case, you would get
+/sys/class/net/bond0/slave_eth0 pointing to /sys/class/net/eth0, and
+/sys/class/net/eth0/master pointing to /sys/class/net/bond0.
+
+       This means that you can tell quickly whether or not an
+interface is enslaved by looking for the master symlink.  Thus:
+# echo -eth0 > /sys/class/net/eth0/master/bonding/slaves
+will free eth0 from whatever bond it is enslaved to, regardless of
+the name of the bond interface.
+
+Changing a Bond's Configuration
+-------------------------------
+       Each bond may be configured individually by manipulating the
+files located in /sys/class/net/<bond name>/bonding
+
+       The names of these files correspond directly with the command-
+line parameters described elsewhere in in this file, and, with the
+exception of arp_ip_target, they accept the same values.  To see the
+current setting, simply cat the appropriate file.
+
+       A few examples will be given here; for specific usage
+guidelines for each parameter, see the appropriate section in this
+document.
+
+To configure bond0 for balance-alb mode:
+# ifconfig bond0 down
+# echo 6 > /sys/class/net/bond0/bonding/mode
+ - or -
+# echo balance-alb > /sys/class/net/bond0/bonding/mode
+       NOTE: The bond interface must be down before the mode can be
+changed.
+
+To enable MII monitoring on bond0 with a 1 second interval:
+# echo 1000 > /sys/class/net/bond0/bonding/miimon
+       NOTE: If ARP monitoring is enabled, it will disabled when MII
+monitoring is enabled, and vice-versa.
+
+To add ARP targets:
+# echo +192.168.0.100 > /sys/class/net/bond0/bonding/arp_ip_target
+# echo +192.168.0.101 > /sys/class/net/bond0/bonding/arp_ip_target
+       NOTE:  up to 10 target addresses may be specified.
+
+To remove an ARP target:
+# echo -192.168.0.100 > /sys/class/net/bond0/bonding/arp_ip_target
+
+Example Configuration
+---------------------
+       We begin with the same example that is shown in section 3.3,
+executed with sysfs, and without using ifenslave.
+
+       To make a simple bond of two e100 devices (presumed to be eth0
+and eth1), and have it persist across reboots, edit the appropriate
+file (/etc/init.d/boot.local or /etc/rc.d/rc.local), and add the
+following:
+
+modprobe bonding
+modprobe e100
+echo balance-alb > /sys/class/net/bond0/bonding/mode
+ifconfig bond0 192.168.1.1 netmask 255.255.255.0 up
+echo 100 > /sys/class/net/bond0/bonding/miimon
+echo +eth0 > /sys/class/net/bond0/bonding/slaves
+echo +eth1 > /sys/class/net/bond0/bonding/slaves
+
+       To add a second bond, with two e1000 interfaces in
+active-backup mode, using ARP monitoring, add the following lines to
+your init script:
+
+modprobe e1000
+echo +bond1 > /sys/class/net/bonding_masters
+echo active-backup > /sys/class/net/bond1/bonding/mode
+ifconfig bond1 192.168.2.1 netmask 255.255.255.0 up
+echo +192.168.2.100 /sys/class/net/bond1/bonding/arp_ip_target
+echo 2000 > /sys/class/net/bond1/bonding/arp_interval
+echo +eth2 > /sys/class/net/bond1/bonding/slaves
+echo +eth3 > /sys/class/net/bond1/bonding/slaves
+
 
-5. Querying Bonding Configuration 
+4. Querying Bonding Configuration 
 =================================
 
-5.1 Bonding Configuration
+4.1 Bonding Configuration
 -------------------------
 
        Each bonding device has a read-only file residing in the
@@ -923,7 +1058,7 @@ generally as follows:
        The precise format and contents will change depending upon the
 bonding configuration, state, and version of the bonding driver.
 
-5.2 Network configuration
+4.2 Network configuration
 -------------------------
 
        The network configuration can be inspected using the ifconfig
@@ -958,7 +1093,7 @@ eth1      Link encap:Ethernet  HWaddr 00:C0:F0:1F:37:B4
           collisions:0 txqueuelen:100
           Interrupt:9 Base address:0x1400
 
-6. Switch Configuration
+5. Switch Configuration
 =======================
 
        For this section, "switch" refers to whatever system the
@@ -991,7 +1126,7 @@ transmit policy for an EtherChannel group; all three will interoperate
 with another EtherChannel group.
 
 
-7. 802.1q VLAN Support
+6. 802.1q VLAN Support
 ======================
 
        It is possible to configure VLAN devices over a bond interface
@@ -1042,7 +1177,7 @@ underlying device -- i.e. the bonding interface -- to promiscuous
 mode, which might not be what you want.
 
 
-8. Link Monitoring
+7. Link Monitoring
 ==================
 
        The bonding driver at present supports two schemes for
@@ -1053,7 +1188,7 @@ monitor.
 bonding driver itself, it is not possible to enable both ARP and MII
 monitoring simultaneously.
 
-8.1 ARP Monitor Operation
+7.1 ARP Monitor Operation
 -------------------------
 
        The ARP monitor operates as its name suggests: it sends ARP
@@ -1071,7 +1206,7 @@ those slaves will stay down.  If networking monitoring (tcpdump, etc)
 shows the ARP requests and replies on the network, then it may be that
 your device driver is not updating last_rx and trans_start.
 
-8.2 Configuring Multiple ARP Targets
+7.2 Configuring Multiple ARP Targets
 ------------------------------------
 
        While ARP monitoring can be done with just one target, it can
@@ -1094,7 +1229,7 @@ alias bond0 bonding
 options bond0 arp_interval=60 arp_ip_target=192.168.0.100
 
 
-8.3 MII Monitor Operation
+7.3 MII Monitor Operation
 -------------------------
 
        The MII monitor monitors only the carrier state of the local
@@ -1120,14 +1255,14 @@ does not support or had some error in processing both the MII register
 and ethtool requests), then the MII monitor will assume the link is
 up.
 
-9. Potential Sources of Trouble
+8. Potential Sources of Trouble
 ===============================
 
-9.1 Adventures in Routing
+8.1 Adventures in Routing
 -------------------------
 
        When bonding is configured, it is important that the slave
-devices not have routes that supercede routes of the master (or,
+devices not have routes that supersede routes of the master (or,
 generally, not have routes at all).  For example, suppose the bonding
 device bond0 has two slaves, eth0 and eth1, and the routing table is
 as follows:
@@ -1154,11 +1289,11 @@ by the state of the routing table.
 
        The solution here is simply to insure that slaves do not have
 routes of their own, and if for some reason they must, those routes do
-not supercede routes of their master.  This should generally be the
+not supersede routes of their master.  This should generally be the
 case, but unusual configurations or errant manual or automatic static
 route additions may cause trouble.
 
-9.2 Ethernet Device Renaming
+8.2 Ethernet Device Renaming
 ----------------------------
 
        On systems with network configuration scripts that do not
@@ -1207,7 +1342,7 @@ modprobe with --ignore-install to cause the normal action to then take
 place.  Full documentation on this can be found in the modprobe.conf
 and modprobe manual pages.
 
-9.3. Painfully Slow Or No Failed Link Detection By Miimon
+8.3. Painfully Slow Or No Failed Link Detection By Miimon
 ---------------------------------------------------------
 
        By default, bonding enables the use_carrier option, which
@@ -1235,7 +1370,7 @@ carrier state.  It has no way to determine the state of devices on or
 beyond other ports of a switch, or if a switch is refusing to pass
 traffic while still maintaining carrier on.
 
-10. SNMP agents
+9. SNMP agents
 ===============
 
        If running SNMP agents, the bonding driver should be loaded
@@ -1281,7 +1416,7 @@ ifDescr, the association between the IP address and IfIndex remains
 and SNMP functions such as Interface_Scan_Next will report that
 association.
 
-11. Promiscuous mode
+10. Promiscuous mode
 ====================
 
        When running network monitoring tools, e.g., tcpdump, it is
@@ -1308,7 +1443,7 @@ sending to peers that are unassigned or if the load is unbalanced.
 the active slave changes (e.g., due to a link failure), the
 promiscuous setting will be propagated to the new active slave.
 
-12. Configuring Bonding for High Availability
+11. Configuring Bonding for High Availability
 =============================================
 
        High Availability refers to configurations that provide
@@ -1318,7 +1453,7 @@ goal is to provide the maximum availability of network connectivity
 (i.e., the network always works), even though other configurations
 could provide higher throughput.
 
-12.1 High Availability in a Single Switch Topology
+11.1 High Availability in a Single Switch Topology
 --------------------------------------------------
 
        If two hosts (or a host and a single switch) are directly
@@ -1332,7 +1467,7 @@ the load will be rebalanced across the remaining devices.
        See Section 13, "Configuring Bonding for Maximum Throughput"
 for information on configuring bonding with one peer device.
 
-12.2 High Availability in a Multiple Switch Topology
+11.2 High Availability in a Multiple Switch Topology
 ----------------------------------------------------
 
        With multiple switches, the configuration of bonding and the
@@ -1359,7 +1494,7 @@ switches (ISL, or inter switch link), and multiple ports connecting to
 the outside world ("port3" on each switch).  There is no technical
 reason that this could not be extended to a third switch.
 
-12.2.1 HA Bonding Mode Selection for Multiple Switch Topology
+11.2.1 HA Bonding Mode Selection for Multiple Switch Topology
 -------------------------------------------------------------
 
        In a topology such as the example above, the active-backup and
@@ -1381,7 +1516,7 @@ broadcast: This mode is really a special purpose mode, and is suitable
        necessary for some specific one-way traffic to reach both
        independent networks, then the broadcast mode may be suitable.
 
-12.2.2 HA Link Monitoring Selection for Multiple Switch Topology
+11.2.2 HA Link Monitoring Selection for Multiple Switch Topology
 ----------------------------------------------------------------
 
        The choice of link monitoring ultimately depends upon your
@@ -1402,10 +1537,10 @@ regardless of which switch is active, the ARP monitor has a suitable
 target to query.
 
 
-13. Configuring Bonding for Maximum Throughput
+12. Configuring Bonding for Maximum Throughput
 ==============================================
 
-13.1 Maximizing Throughput in a Single Switch Topology
+12.1 Maximizing Throughput in a Single Switch Topology
 ------------------------------------------------------
 
        In a single switch configuration, the best method to maximize
@@ -1476,7 +1611,7 @@ destination to make load balancing decisions.  The behavior of each
 mode is described below.
 
 
-13.1.1 MT Bonding Mode Selection for Single Switch Topology
+12.1.1 MT Bonding Mode Selection for Single Switch Topology
 -----------------------------------------------------------
 
        This configuration is the easiest to set up and to understand,
@@ -1607,7 +1742,7 @@ balance-alb: This mode is everything that balance-tlb is, and more.
        device driver must support changing the hardware address while
        the device is open.
 
-13.1.2 MT Link Monitoring for Single Switch Topology
+12.1.2 MT Link Monitoring for Single Switch Topology
 ----------------------------------------------------
 
        The choice of link monitoring may largely depend upon which
@@ -1616,7 +1751,7 @@ support the use of the ARP monitor, and are thus restricted to using
 the MII monitor (which does not provide as high a level of end to end
 assurance as the ARP monitor).
 
-13.2 Maximum Throughput in a Multiple Switch Topology
+12.2 Maximum Throughput in a Multiple Switch Topology
 -----------------------------------------------------
 
        Multiple switches may be utilized to optimize for throughput
@@ -1651,7 +1786,7 @@ a single 72 port switch.
 can be equipped with an additional network device connected to an
 external network; this host then additionally acts as a gateway.
 
-13.2.1 MT Bonding Mode Selection for Multiple Switch Topology
+12.2.1 MT Bonding Mode Selection for Multiple Switch Topology
 -------------------------------------------------------------
 
        In actual practice, the bonding mode typically employed in
@@ -1664,7 +1799,7 @@ packets has arrived).  When employed in this fashion, the balance-rr
 mode allows individual connections between two hosts to effectively
 utilize greater than one interface's bandwidth.
 
-13.2.2 MT Link Monitoring for Multiple Switch Topology
+12.2.2 MT Link Monitoring for Multiple Switch Topology
 ------------------------------------------------------
 
        Again, in actual practice, the MII monitor is most often used
@@ -1674,10 +1809,10 @@ advantages over the MII monitor are mitigated by the volume of probes
 needed as the number of systems involved grows (remember that each
 host in the network is configured with bonding).
 
-14. Switch Behavior Issues
+13. Switch Behavior Issues
 ==========================
 
-14.1 Link Establishment and Failover Delays
+13.1 Link Establishment and Failover Delays
 -------------------------------------------
 
        Some switches exhibit undesirable behavior with regard to the
@@ -1712,7 +1847,7 @@ switches take a long time to go into backup mode, it may be desirable
 to not activate a backup interface immediately after a link goes down.
 Failover may be delayed via the downdelay bonding module option.
 
-14.2 Duplicated Incoming Packets
+13.2 Duplicated Incoming Packets
 --------------------------------
 
        It is not uncommon to observe a short burst of duplicated
@@ -1751,14 +1886,14 @@ behavior, it can be induced by clearing the MAC forwarding table (on
 most Cisco switches, the privileged command "clear mac address-table
 dynamic" will accomplish this).
 
-15. Hardware Specific Considerations
+14. Hardware Specific Considerations
 ====================================
 
        This section contains additional information for configuring
 bonding on specific hardware platforms, or for interfacing bonding
 with particular switches or other devices.
 
-15.1 IBM BladeCenter
+14.1 IBM BladeCenter
 --------------------
 
        This applies to the JS20 and similar systems.
@@ -1861,7 +1996,7 @@ bonding driver.
 avoid fail-over delay issues when using bonding.
 
        
-16. Frequently Asked Questions
+15. Frequently Asked Questions
 ==============================
 
 1.  Is it SMP safe?
@@ -1925,7 +2060,7 @@ not have special switch requirements, but do need device drivers that
 support specific features (described in the appropriate section under
 module parameters, above).
 
-       In 802.3ad mode, it works with with systems that support IEEE
+       In 802.3ad mode, it works with systems that support IEEE
 802.3ad Dynamic Link Aggregation.  Most managed and many unmanaged
 switches currently available support 802.3ad.
 
index f12007b..d46338a 100644 (file)
@@ -362,6 +362,13 @@ tcp_workaround_signed_windows - BOOLEAN
        not receive a window scaling option from them.
        Default: 0
 
+tcp_slow_start_after_idle - BOOLEAN
+       If set, provide RFC2861 behavior and time out the congestion
+       window after an idle period.  An idle period is defined at
+       the current RTO.  If unset, the congestion window will not
+       be timed out after an idle period.
+       Default: 1
+
 IP Variables:
 
 ip_local_port_range - 2 INTEGERS
index 3c0a5ba..847cedb 100644 (file)
@@ -42,9 +42,9 @@ dev->get_stats:
        Context: nominally process, but don't sleep inside an rwlock
 
 dev->hard_start_xmit:
-       Synchronization: dev->xmit_lock spinlock.
+       Synchronization: netif_tx_lock spinlock.
        When the driver sets NETIF_F_LLTX in dev->features this will be
-       called without holding xmit_lock. In this case the driver 
+       called without holding netif_tx_lock. In this case the driver
        has to lock by itself when needed. It is recommended to use a try lock
        for this and return -1 when the spin lock fails. 
        The locking there should also properly protect against 
@@ -62,12 +62,12 @@ dev->hard_start_xmit:
          Only valid when NETIF_F_LLTX is set.
 
 dev->tx_timeout:
-       Synchronization: dev->xmit_lock spinlock.
+       Synchronization: netif_tx_lock spinlock.
        Context: BHs disabled
        Notes: netif_queue_stopped() is guaranteed true
 
 dev->set_multicast_list:
-       Synchronization: dev->xmit_lock spinlock.
+       Synchronization: netif_tx_lock spinlock.
        Context: BHs disabled
 
 dev->poll:
index c3c5842..1421f74 100644 (file)
@@ -1425,6 +1425,8 @@ P:        Jesse Brandeburg
 M:     jesse.brandeburg@intel.com
 P:     Jeff Kirsher
 M:     jeffrey.t.kirsher@intel.com
+P:     Auke Kok
+M:     auke-jan.h.kok@intel.com
 W:     http://sourceforge.net/projects/e1000/
 S:     Supported
 
@@ -1437,6 +1439,8 @@ P:        Jesse Brandeburg
 M:     jesse.brandeburg@intel.com
 P:     Jeff Kirsher
 M:     jeffrey.t.kirsher@intel.com
+P:     Auke Kok
+M:     auke-jan.h.kok@intel.com
 W:     http://sourceforge.net/projects/e1000/
 S:     Supported
 
@@ -1449,6 +1453,8 @@ P:        John Ronciak
 M:     john.ronciak@intel.com
 P:     Jesse Brandeburg
 M:     jesse.brandeburg@intel.com
+P:     Auke Kok
+M:     auke-jan.h.kok@intel.com
 W:     http://sourceforge.net/projects/e1000/
 S:     Supported
 
index a3a7baa..1700d3f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
 SUBLEVEL = 17
-EXTRAVERSION =-rc6
+EXTRAVERSION =
 NAME=Crazed Snow-Weasel
 
 # *DOCUMENTATION*
index 8290b69..213c785 100644 (file)
@@ -453,7 +453,7 @@ config ALPHA_IRONGATE
 
 config GENERIC_HWEIGHT
        bool
-       default y if !ALPHA_EV6 && !ALPHA_EV67
+       default y if !ALPHA_EV67
 
 config ALPHA_AVANTI
        bool
index eeb8a6d..a5de5f1 100644 (file)
@@ -127,7 +127,7 @@ static void
 imx_gpio_ack_irq(unsigned int irq)
 {
        DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
-       ISR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32);
+       ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32);
 }
 
 static void
index a0724f2..9f55f5a 100644 (file)
@@ -232,8 +232,6 @@ static void __init intcp_init_irq(void)
        for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
                if (i == 11)
                        i = 22;
-               if (i == IRQ_CP_CPPLDINT)
-                       i++;
                if (i == 29)
                        break;
                set_irq_chip(i, &pic_chip);
@@ -259,8 +257,7 @@ static void __init intcp_init_irq(void)
                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
        }
 
-       set_irq_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
-       pic_unmask_irq(IRQ_CP_CPPLDINT);
+       set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
 }
 
 /*
index 19b372d..44bcb80 100644 (file)
@@ -371,6 +371,7 @@ static int spitz_ohci_init(struct device *dev)
 static struct pxaohci_platform_data spitz_ohci_platform_data = {
        .port_mode      = PMM_NPS_MODE,
        .init           = spitz_ohci_init,
+       .power_budget   = 150,
 };
 
 
index 9e02bc3..af6d277 100644 (file)
@@ -59,6 +59,14 @@ neponset_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *reg
                if (irr & (IRR_ETHERNET | IRR_USAR)) {
                        desc->chip->mask(irq);
 
+                       /*
+                        * Ack the interrupt now to prevent re-entering
+                        * this neponset handler.  Again, this is safe
+                        * since we'll check the IRR register prior to
+                        * leaving.
+                        */
+                       desc->chip->ack(irq);
+
                        if (irr & IRR_ETHERNET) {
                                d = irq_desc + IRQ_NEPONSET_SMC9196;
                                desc_handle_irq(IRQ_NEPONSET_SMC9196, d, regs);
index 799697d..cebd48a 100644 (file)
@@ -112,10 +112,9 @@ void __init versatile_init_irq(void)
 {
        unsigned int i;
 
-       vic_init(VA_VIC_BASE, IRQ_VIC_START, ~(1 << 31));
+       vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
 
-       set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
-       enable_irq(IRQ_VICSOURCE31);
+       set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
 
        /* Do second interrupt controller */
        writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
index 3852d0a..1a7bdce 100644 (file)
@@ -104,7 +104,7 @@ acpi_processor_set_performance (
 {
        u16                     port = 0;
        u8                      bit_width = 0;
-       int                     ret = 0;
+       int                     ret;
        u32                     value = 0;
        int                     i = 0;
        struct cpufreq_freqs    cpufreq_freqs;
@@ -195,7 +195,6 @@ acpi_processor_set_performance (
                        udelay(10);
                }
        } else {
-               i = 0;
                value = (u32) data->acpi_data.states[state].status;
        }
 
@@ -444,14 +443,15 @@ static struct freq_attr* acpi_cpufreq_attr[] = {
 };
 
 static struct cpufreq_driver acpi_cpufreq_driver = {
-       .verify         = acpi_cpufreq_verify,
-       .target         = acpi_cpufreq_target,
-       .init           = acpi_cpufreq_cpu_init,
-       .exit           = acpi_cpufreq_cpu_exit,
-       .resume         = acpi_cpufreq_resume,
-       .name           = "acpi-cpufreq",
-       .owner          = THIS_MODULE,
-       .attr           = acpi_cpufreq_attr,
+       .verify = acpi_cpufreq_verify,
+       .target = acpi_cpufreq_target,
+       .init   = acpi_cpufreq_cpu_init,
+       .exit   = acpi_cpufreq_cpu_exit,
+       .resume = acpi_cpufreq_resume,
+       .name   = "acpi-cpufreq",
+       .owner  = THIS_MODULE,
+       .attr   = acpi_cpufreq_attr,
+       .flags  = CPUFREQ_STICKY,
 };
 
 
index f275e0d..0d49d73 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * (C) 2004  Sebastian Witt <se.witt@gmx.net>
+ * (C) 2004-2006  Sebastian Witt <se.witt@gmx.net>
  *
  *  Licensed under the terms of the GNU GPL License version 2.
  *  Based upon reverse engineered information
@@ -90,7 +90,7 @@ static int nforce2_calc_pll(unsigned int fsb)
 
        /* Try to calculate multiplier and divider up to 4 times */
        while (((mul == 0) || (div == 0)) && (tried <= 3)) {
-               for (xdiv = 1; xdiv <= 0x80; xdiv++)
+               for (xdiv = 2; xdiv <= 0x80; xdiv++)
                        for (xmul = 1; xmul <= 0xfe; xmul++)
                                if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
                                    fsb + tried) {
@@ -117,8 +117,7 @@ static void nforce2_write_pll(int pll)
        int temp;
 
        /* Set the pll addr. to 0x00 */
-       temp = 0x00;
-       pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp);
+       pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, 0);
 
        /* Now write the value in all 64 registers */
        for (temp = 0; temp <= 0x3f; temp++)
@@ -266,7 +265,7 @@ static int nforce2_target(struct cpufreq_policy *policy,
        if (freqs.old == freqs.new)
                return 0;
 
-       dprintk(KERN_INFO "cpufreq: Old CPU frequency %d kHz, new %d kHz\n",
+       dprintk("Old CPU frequency %d kHz, new %d kHz\n",
               freqs.old, freqs.new);
 
        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
@@ -278,7 +277,7 @@ static int nforce2_target(struct cpufreq_policy *policy,
                printk(KERN_ERR "cpufreq: Changing FSB to %d failed\n",
                        target_fsb);
        else
-               dprintk(KERN_INFO "cpufreq: Changed FSB successfully to %d\n",
+               dprintk("Changed FSB successfully to %d\n",
                        target_fsb);
 
        /* Enable IRQs */
index 8ef3854..146f607 100644 (file)
@@ -77,13 +77,17 @@ static char speedbuffer[8];
 
 static char *print_speed(int speed)
 {
-       if (speed > 1000) {
-               if (speed%1000 == 0)
-                       sprintf (speedbuffer, "%dGHz", speed/1000);
-               else
-                       sprintf (speedbuffer, "%d.%dGHz", speed/1000, (speed%1000)/100);
-       } else
-               sprintf (speedbuffer, "%dMHz", speed);
+       if (speed < 1000) {
+               snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
+               return speedbuffer;
+       }
+
+       if (speed%1000 == 0)
+               snprintf(speedbuffer, sizeof(speedbuffer),
+                       "%dGHz", speed/1000);
+       else
+               snprintf(speedbuffer, sizeof(speedbuffer),
+                       "%d.%dGHz", speed/1000, (speed%1000)/100);
 
        return speedbuffer;
 }
@@ -675,7 +679,7 @@ static int __init longhaul_init(void)
 
 static void __exit longhaul_exit(void)
 {
-       int i=0;
+       int i;
 
        for (i=0; i < numscales; i++) {
                if (clock_ratio[i] == maxmult) {
index e3868de..b268951 100644 (file)
@@ -223,7 +223,6 @@ static unsigned int __init longrun_determine_freqs(unsigned int *low_freq,
                /* set to 0 to try_hi perf_pctg */
                msr_lo &= 0xFFFFFF80;
                msr_hi &= 0xFFFFFF80;
-               msr_lo |= 0;
                msr_hi |= try_hi;
                wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
 
index 2bf4237..694d479 100644 (file)
@@ -452,23 +452,23 @@ static int powernow_decode_bios (int maxfid, int startvid)
 
                        pst = (struct pst_s *) p;
 
-                       for (i = 0 ; i <psb->numpst; i++) {
+                       for (j=0; j<psb->numpst; j++) {
                                pst = (struct pst_s *) p;
                                number_scales = pst->numpstates;
 
                                if ((etuple == pst->cpuid) && check_fsb(pst->fsbspeed) &&
                                    (maxfid==pst->maxfid) && (startvid==pst->startvid))
                                {
-                                       dprintk ("PST:%d (@%p)\n", i, pst);
+                                       dprintk ("PST:%d (@%p)\n", j, pst);
                                        dprintk (" cpuid: 0x%x  fsb: %d  maxFID: 0x%x  startvid: 0x%x\n",
                                                 pst->cpuid, pst->fsbspeed, pst->maxfid, pst->startvid);
 
                                        ret = get_ranges ((char *) pst + sizeof (struct pst_s));
                                        return ret;
-
                                } else {
+                                       unsigned int k;
                                        p = (char *) pst + sizeof (struct pst_s);
-                                       for (j=0 ; j < number_scales; j++)
+                                       for (k=0; k<number_scales; k++)
                                                p+=2;
                                }
                        }
@@ -581,10 +581,7 @@ static int __init powernow_cpu_init (struct cpufreq_policy *policy)
 
        rdmsrl (MSR_K7_FID_VID_STATUS, fidvidstatus.val);
 
-       /* recalibrate cpu_khz */
-       result = recalibrate_cpu_khz();
-       if (result)
-               return result;
+       recalibrate_cpu_khz();
 
        fsb = (10 * cpu_khz) / fid_codes[fidvidstatus.bits.CFID];
        if (!fsb) {
index 71fffa1..b4277f5 100644 (file)
@@ -1,5 +1,5 @@
 /*
- *   (c) 2003, 2004, 2005 Advanced Micro Devices, Inc.
+ *   (c) 2003-2006 Advanced Micro Devices, Inc.
  *  Your use of this code is subject to the terms and conditions of the
  *  GNU general public license version 2. See "COPYING" or
  *  http://www.gnu.org/licenses/gpl.html
  *  Based upon datasheets & sample CPUs kindly provided by AMD.
  *
  *  Valuable input gratefully received from Dave Jones, Pavel Machek,
- *  Dominik Brodowski, and others.
+ *  Dominik Brodowski, Jacob Shin, and others.
  *  Originally developed by Paul Devriendt.
  *  Processor information obtained from Chapter 9 (Power and Thermal Management)
  *  of the "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
  *  Opteron Processors" available for download from www.amd.com
  *
- *  Tables for specific CPUs can be infrerred from
+ *  Tables for specific CPUs can be inferred from
  *     http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/30430.pdf
  */
 
@@ -46,7 +46,7 @@
 
 #define PFX "powernow-k8: "
 #define BFX PFX "BIOS error: "
-#define VERSION "version 1.60.2"
+#define VERSION "version 2.00.00"
 #include "powernow-k8.h"
 
 /* serialize freq changes  */
@@ -54,6 +54,8 @@ static DEFINE_MUTEX(fidvid_mutex);
 
 static struct powernow_k8_data *powernow_data[NR_CPUS];
 
+static int cpu_family = CPU_OPTERON;
+
 #ifndef CONFIG_SMP
 static cpumask_t cpu_core_map[1];
 #endif
@@ -64,16 +66,36 @@ static u32 find_freq_from_fid(u32 fid)
        return 800 + (fid * 100);
 }
 
+
 /* Return a frequency in KHz, given an input fid */
 static u32 find_khz_freq_from_fid(u32 fid)
 {
        return 1000 * find_freq_from_fid(fid);
 }
 
-/* Return a voltage in miliVolts, given an input vid */
-static u32 find_millivolts_from_vid(struct powernow_k8_data *data, u32 vid)
+/* Return a frequency in MHz, given an input fid and did */
+static u32 find_freq_from_fiddid(u32 fid, u32 did)
+{
+       return 100 * (fid + 0x10) >> did;
+}
+
+static u32 find_khz_freq_from_fiddid(u32 fid, u32 did)
 {
-       return 1550-vid*25;
+       return 1000 * find_freq_from_fiddid(fid, did);
+}
+
+static u32 find_fid_from_pstate(u32 pstate)
+{
+       u32 hi, lo;
+       rdmsr(MSR_PSTATE_DEF_BASE + pstate, lo, hi);
+       return lo & HW_PSTATE_FID_MASK;
+}
+
+static u32 find_did_from_pstate(u32 pstate)
+{
+       u32 hi, lo;
+       rdmsr(MSR_PSTATE_DEF_BASE + pstate, lo, hi);
+       return (lo & HW_PSTATE_DID_MASK) >> HW_PSTATE_DID_SHIFT;
 }
 
 /* Return the vco fid for an input fid
@@ -98,6 +120,9 @@ static int pending_bit_stuck(void)
 {
        u32 lo, hi;
 
+       if (cpu_family)
+               return 0;
+
        rdmsr(MSR_FIDVID_STATUS, lo, hi);
        return lo & MSR_S_LO_CHANGE_PENDING ? 1 : 0;
 }
@@ -111,6 +136,14 @@ static int query_current_values_with_pending_wait(struct powernow_k8_data *data)
        u32 lo, hi;
        u32 i = 0;
 
+       if (cpu_family) {
+               rdmsr(MSR_PSTATE_STATUS, lo, hi);
+               i = lo & HW_PSTATE_MASK;
+               rdmsr(MSR_PSTATE_DEF_BASE + i, lo, hi);
+               data->currfid = lo & HW_PSTATE_FID_MASK;
+               data->currdid = (lo & HW_PSTATE_DID_MASK) >> HW_PSTATE_DID_SHIFT;
+               return 0;
+       }
        do {
                if (i++ > 10000) {
                        dprintk("detected change pending stuck\n");
@@ -175,7 +208,7 @@ static int write_new_fid(struct powernow_k8_data *data, u32 fid)
        do {
                wrmsr(MSR_FIDVID_CTL, lo, data->plllock * PLL_LOCK_CONVERSION);
                if (i++ > 100) {
-                       printk(KERN_ERR PFX "internal error - pending bit very stuck - no further pstate changes possible\n");
+                       printk(KERN_ERR PFX "Hardware error - pending bit very stuck - no further pstate changes possible\n");
                        return 1;
                }
        } while (query_current_values_with_pending_wait(data));
@@ -255,7 +288,15 @@ static int decrease_vid_code_by_step(struct powernow_k8_data *data, u32 reqvid,
        return 0;
 }
 
-/* Change the fid and vid, by the 3 phases. */
+/* Change hardware pstate by single MSR write */
+static int transition_pstate(struct powernow_k8_data *data, u32 pstate)
+{
+       wrmsr(MSR_PSTATE_CTRL, pstate, 0);
+       data->currfid = find_fid_from_pstate(pstate);
+       return 0;
+}
+
+/* Change Opteron/Athlon64 fid and vid, by the 3 phases. */
 static int transition_fid_vid(struct powernow_k8_data *data, u32 reqfid, u32 reqvid)
 {
        if (core_voltage_pre_transition(data, reqvid))
@@ -474,26 +515,35 @@ static int check_supported_cpu(unsigned int cpu)
                goto out;
 
        eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
-       if ((eax & CPUID_XFAM) != CPUID_XFAM_K8)
+       if (((eax & CPUID_XFAM) != CPUID_XFAM_K8) &&
+           ((eax & CPUID_XFAM) < CPUID_XFAM_10H))
                goto out;
 
-       if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) ||
-           ((eax & CPUID_XMOD) > CPUID_XMOD_REV_G)) {
-               printk(KERN_INFO PFX "Processor cpuid %x not supported\n", eax);
-               goto out;
-       }
+       if ((eax & CPUID_XFAM) == CPUID_XFAM_K8) {
+               if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) ||
+                   ((eax & CPUID_XMOD) > CPUID_XMOD_REV_G)) {
+                       printk(KERN_INFO PFX "Processor cpuid %x not supported\n", eax);
+                       goto out;
+               }
 
-       eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES);
-       if (eax < CPUID_FREQ_VOLT_CAPABILITIES) {
-               printk(KERN_INFO PFX
-                      "No frequency change capabilities detected\n");
-               goto out;
-       }
+               eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES);
+               if (eax < CPUID_FREQ_VOLT_CAPABILITIES) {
+                       printk(KERN_INFO PFX
+                              "No frequency change capabilities detected\n");
+                       goto out;
+               }
 
-       cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
-       if ((edx & P_STATE_TRANSITION_CAPABLE) != P_STATE_TRANSITION_CAPABLE) {
-               printk(KERN_INFO PFX "Power state transitions not supported\n");
-               goto out;
+               cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
+               if ((edx & P_STATE_TRANSITION_CAPABLE) != P_STATE_TRANSITION_CAPABLE) {
+                       printk(KERN_INFO PFX "Power state transitions not supported\n");
+                       goto out;
+               }
+       } else { /* must be a HW Pstate capable processor */
+               cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
+               if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE)
+                       cpu_family = CPU_HW_PSTATE;
+               else
+                       goto out;
        }
 
        rc = 1;
@@ -547,12 +597,18 @@ static void print_basics(struct powernow_k8_data *data)
 {
        int j;
        for (j = 0; j < data->numps; j++) {
-               if (data->powernow_table[j].frequency != CPUFREQ_ENTRY_INVALID)
-                       printk(KERN_INFO PFX "   %d : fid 0x%x (%d MHz), vid 0x%x (%d mV)\n", j,
+               if (data->powernow_table[j].frequency != CPUFREQ_ENTRY_INVALID) {
+                       if (cpu_family) {
+                       printk(KERN_INFO PFX "   %d : fid 0x%x gid 0x%x (%d MHz)\n", j, (data->powernow_table[j].index & 0xff00) >> 8,
+                               (data->powernow_table[j].index & 0xff0000) >> 16,
+                               data->powernow_table[j].frequency/1000);
+                       } else {
+                       printk(KERN_INFO PFX "   %d : fid 0x%x (%d MHz), vid 0x%x\n", j,
                                data->powernow_table[j].index & 0xff,
                                data->powernow_table[j].frequency/1000,
-                               data->powernow_table[j].index >> 8,
-                               find_millivolts_from_vid(data, data->powernow_table[j].index >> 8));
+                               data->powernow_table[j].index >> 8);
+                       }
+               }
        }
        if (data->batps)
                printk(KERN_INFO PFX "Only %d pstates on battery\n", data->batps);
@@ -702,7 +758,7 @@ static int find_psb_table(struct powernow_k8_data *data)
 #ifdef CONFIG_X86_POWERNOW_K8_ACPI
 static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index)
 {
-       if (!data->acpi_data.state_count)
+       if (!data->acpi_data.state_count || cpu_family)
                return;
 
        data->irt = (data->acpi_data.states[index].control >> IRT_SHIFT) & IRT_MASK;
@@ -715,9 +771,8 @@ static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned
 
 static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
 {
-       int i;
-       int cntlofreq = 0;
        struct cpufreq_frequency_table *powernow_table;
+       int ret_val;
 
        if (acpi_processor_register_performance(&data->acpi_data, data->cpu)) {
                dprintk("register performance failed: bad ACPI data\n");
@@ -746,6 +801,85 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
                goto err_out;
        }
 
+       if (cpu_family)
+               ret_val = fill_powernow_table_pstate(data, powernow_table);
+       else
+               ret_val = fill_powernow_table_fidvid(data, powernow_table);
+       if (ret_val)
+               goto err_out_mem;
+
+       powernow_table[data->acpi_data.state_count].frequency = CPUFREQ_TABLE_END;
+       powernow_table[data->acpi_data.state_count].index = 0;
+       data->powernow_table = powernow_table;
+
+       /* fill in data */
+       data->numps = data->acpi_data.state_count;
+       print_basics(data);
+       powernow_k8_acpi_pst_values(data, 0);
+
+       /* notify BIOS that we exist */
+       acpi_processor_notify_smm(THIS_MODULE);
+
+       return 0;
+
+err_out_mem:
+       kfree(powernow_table);
+
+err_out:
+       acpi_processor_unregister_performance(&data->acpi_data, data->cpu);
+
+       /* data->acpi_data.state_count informs us at ->exit() whether ACPI was used */
+       data->acpi_data.state_count = 0;
+
+       return -ENODEV;
+}
+
+static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table)
+{
+       int i;
+
+       for (i = 0; i < data->acpi_data.state_count; i++) {
+               u32 index;
+               u32 hi = 0, lo = 0;
+               u32 fid;
+               u32 did;
+
+               index = data->acpi_data.states[i].control & HW_PSTATE_MASK;
+               if (index > MAX_HW_PSTATE) {
+                       printk(KERN_ERR PFX "invalid pstate %d - bad value %d.\n", i, index);
+                       printk(KERN_ERR PFX "Please report to BIOS manufacturer\n");
+               }
+               rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi);
+               if (!(hi & HW_PSTATE_VALID_MASK)) {
+                       dprintk("invalid pstate %d, ignoring\n", index);
+                       powernow_table[i].frequency = CPUFREQ_ENTRY_INVALID;
+                       continue;
+               }
+
+               fid = lo & HW_PSTATE_FID_MASK;
+               did = (lo & HW_PSTATE_DID_MASK) >> HW_PSTATE_DID_SHIFT;
+
+               dprintk("   %d : fid 0x%x, did 0x%x\n", index, fid, did);
+
+               powernow_table[i].index = index | (fid << HW_FID_INDEX_SHIFT) | (did << HW_DID_INDEX_SHIFT);
+
+               powernow_table[i].frequency = find_khz_freq_from_fiddid(fid, did);
+
+               if (powernow_table[i].frequency != (data->acpi_data.states[i].core_frequency * 1000)) {
+                       printk(KERN_INFO PFX "invalid freq entries %u kHz vs. %u kHz\n",
+                               powernow_table[i].frequency,
+                               (unsigned int) (data->acpi_data.states[i].core_frequency * 1000));
+                       powernow_table[i].frequency = CPUFREQ_ENTRY_INVALID;
+                       continue;
+               }
+       }
+       return 0;
+}
+
+static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table)
+{
+       int i;
+       int cntlofreq = 0;
        for (i = 0; i < data->acpi_data.state_count; i++) {
                u32 fid;
                u32 vid;
@@ -786,7 +920,7 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
                                if ((powernow_table[i].frequency != powernow_table[cntlofreq].frequency) ||
                                    (powernow_table[i].index != powernow_table[cntlofreq].index)) {
                                        printk(KERN_ERR PFX "Too many lo freq table entries\n");
-                                       goto err_out_mem;
+                                       return 1;
                                }
 
                                dprintk("double low frequency table entry, ignoring it.\n");
@@ -804,31 +938,7 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
                        continue;
                }
        }
-
-       powernow_table[data->acpi_data.state_count].frequency = CPUFREQ_TABLE_END;
-       powernow_table[data->acpi_data.state_count].index = 0;
-       data->powernow_table = powernow_table;
-
-       /* fill in data */
-       data->numps = data->acpi_data.state_count;
-       print_basics(data);
-       powernow_k8_acpi_pst_values(data, 0);
-
-       /* notify BIOS that we exist */
-       acpi_processor_notify_smm(THIS_MODULE);
-
        return 0;
-
-err_out_mem:
-       kfree(powernow_table);
-
-err_out:
-       acpi_processor_unregister_performance(&data->acpi_data, data->cpu);
-
-       /* data->acpi_data.state_count informs us at ->exit() whether ACPI was used */
-       data->acpi_data.state_count = 0;
-
-       return -ENODEV;
 }
 
 static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data)
@@ -844,20 +954,20 @@ static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned
 #endif /* CONFIG_X86_POWERNOW_K8_ACPI */
 
 /* Take a frequency, and issue the fid/vid transition command */
-static int transition_frequency(struct powernow_k8_data *data, unsigned int index)
+static int transition_frequency_fidvid(struct powernow_k8_data *data, unsigned int index)
 {
-       u32 fid;
-       u32 vid;
+       u32 fid = 0;
+       u32 vid = 0;
        int res, i;
        struct cpufreq_freqs freqs;
 
        dprintk("cpu %d transition to index %u\n", smp_processor_id(), index);
 
+       /* fid/vid correctness check for k8 */
        /* fid are the lower 8 bits of the index we stored into
-        * the cpufreq frequency table in find_psb_table, vid are
-        * the upper 8 bits.
+        * the cpufreq frequency table in find_psb_table, vid
+        * are the upper 8 bits.
         */
-
        fid = data->powernow_table[index].index & 0xFF;
        vid = (data->powernow_table[index].index & 0xFF00) >> 8;
 
@@ -881,22 +991,58 @@ static int transition_frequency(struct powernow_k8_data *data, unsigned int inde
 
        dprintk("cpu %d, changing to fid 0x%x, vid 0x%x\n",
                smp_processor_id(), fid, vid);
-
-       freqs.cpu = data->cpu;
        freqs.old = find_khz_freq_from_fid(data->currfid);
        freqs.new = find_khz_freq_from_fid(fid);
-       for_each_cpu_mask(i, cpu_core_map[data->cpu]) {
+
+       for_each_cpu_mask(i, *(data->available_cores)) {
                freqs.cpu = i;
                cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
        }
 
        res = transition_fid_vid(data, fid, vid);
-
        freqs.new = find_khz_freq_from_fid(data->currfid);
-       for_each_cpu_mask(i, cpu_core_map[data->cpu]) {
+
+       for_each_cpu_mask(i, *(data->available_cores)) {
                freqs.cpu = i;
                cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-        }
+       }
+       return res;
+}
+
+/* Take a frequency, and issue the hardware pstate transition command */
+static int transition_frequency_pstate(struct powernow_k8_data *data, unsigned int index)
+{
+       u32 fid = 0;
+       u32 did = 0;
+       u32 pstate = 0;
+       int res, i;
+       struct cpufreq_freqs freqs;
+
+       dprintk("cpu %d transition to index %u\n", smp_processor_id(), index);
+
+       /* get fid did for hardware pstate transition */
+       pstate = index & HW_PSTATE_MASK;
+       if (pstate > MAX_HW_PSTATE)
+               return 0;
+       fid = (index & HW_FID_INDEX_MASK) >> HW_FID_INDEX_SHIFT;
+       did = (index & HW_DID_INDEX_MASK) >> HW_DID_INDEX_SHIFT;
+       freqs.old = find_khz_freq_from_fiddid(data->currfid, data->currdid);
+       freqs.new = find_khz_freq_from_fiddid(fid, did);
+
+       for_each_cpu_mask(i, *(data->available_cores)) {
+               freqs.cpu = i;
+               cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+       }
+
+       res = transition_pstate(data, pstate);
+       data->currfid = find_fid_from_pstate(pstate);
+       data->currdid = find_did_from_pstate(pstate);
+       freqs.new = find_khz_freq_from_fiddid(data->currfid, data->currdid);
+
+       for_each_cpu_mask(i, *(data->available_cores)) {
+               freqs.cpu = i;
+               cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+       }
        return res;
 }
 
@@ -933,18 +1079,21 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi
        dprintk("targ: cpu %d, %d kHz, min %d, max %d, relation %d\n",
                pol->cpu, targfreq, pol->min, pol->max, relation);
 
-       if (query_current_values_with_pending_wait(data)) {
-               ret = -EIO;
+       if (query_current_values_with_pending_wait(data))
                goto err_out;
-       }
 
-       dprintk("targ: curr fid 0x%x, vid 0x%x\n",
+       if (cpu_family)
+               dprintk("targ: curr fid 0x%x, did 0x%x\n",
+                       data->currfid, data->currvid);
+       else {
+               dprintk("targ: curr fid 0x%x, vid 0x%x\n",
                data->currfid, data->currvid);
 
-       if ((checkvid != data->currvid) || (checkfid != data->currfid)) {
-               printk(KERN_INFO PFX
-                       "error - out of sync, fix 0x%x 0x%x, vid 0x%x 0x%x\n",
-                       checkfid, data->currfid, checkvid, data->currvid);
+               if ((checkvid != data->currvid) || (checkfid != data->currfid)) {
+                       printk(KERN_INFO PFX
+                               "error - out of sync, fix 0x%x 0x%x, vid 0x%x 0x%x\n",
+                               checkfid, data->currfid, checkvid, data->currvid);
+               }
        }
 
        if (cpufreq_frequency_table_target(pol, data->powernow_table, targfreq, relation, &newstate))
@@ -954,7 +1103,11 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi
 
        powernow_k8_acpi_pst_values(data, newstate);
 
-       if (transition_frequency(data, newstate)) {
+       if (cpu_family)
+               ret = transition_frequency_pstate(data, newstate);
+       else
+               ret = transition_frequency_fidvid(data, newstate);
+       if (ret) {
                printk(KERN_ERR PFX "transition frequency failed\n");
                ret = 1;
                mutex_unlock(&fidvid_mutex);
@@ -962,7 +1115,10 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi
        }
        mutex_unlock(&fidvid_mutex);
 
-       pol->cur = find_khz_freq_from_fid(data->currfid);
+       if (cpu_family)
+               pol->cur = find_khz_freq_from_fiddid(data->currfid, data->currdid);
+       else
+               pol->cur = find_khz_freq_from_fid(data->currfid);
        ret = 0;
 
 err_out:
@@ -1007,14 +1163,13 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
                 * Use the PSB BIOS structure. This is only availabe on
                 * an UP version, and is deprecated by AMD.
                 */
-
                if ((num_online_cpus() != 1) || (num_possible_cpus() != 1)) {
                        printk(KERN_ERR PFX "MP systems not supported by PSB BIOS structure\n");
                        kfree(data);
                        return -ENODEV;
                }
                if (pol->cpu != 0) {
-                       printk(KERN_ERR PFX "init not cpu 0\n");
+                       printk(KERN_ERR PFX "No _PSS objects for CPU other than CPU0\n");
                        kfree(data);
                        return -ENODEV;
                }
@@ -1042,20 +1197,28 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
        if (query_current_values_with_pending_wait(data))
                goto err_out;
 
-       fidvid_msr_init();
+       if (!cpu_family)
+               fidvid_msr_init();
 
        /* run on any CPU again */
        set_cpus_allowed(current, oldmask);
 
        pol->governor = CPUFREQ_DEFAULT_GOVERNOR;
-       pol->cpus = cpu_core_map[pol->cpu];
+       if (cpu_family)
+               pol->cpus = cpumask_of_cpu(pol->cpu);
+       else
+               pol->cpus = cpu_core_map[pol->cpu];
+       data->available_cores = &(pol->cpus);
 
        /* Take a crude guess here.
         * That guess was in microseconds, so multiply with 1000 */
        pol->cpuinfo.transition_latency = (((data->rvo + 8) * data->vstable * VST_UNITS_20US)
            + (3 * (1 << data->irt) * 10)) * 1000;
 
-       pol->cur = find_khz_freq_from_fid(data->currfid);
+       if (cpu_family)
+               pol->cur = find_khz_freq_from_fiddid(data->currfid, data->currdid);
+       else
+               pol->cur = find_khz_freq_from_fid(data->currfid);
        dprintk("policy current frequency %d kHz\n", pol->cur);
 
        /* min/max the cpu is capable of */
@@ -1069,8 +1232,12 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
 
        cpufreq_frequency_table_get_attr(data->powernow_table, pol->cpu);
 
-       printk("cpu_init done, current fid 0x%x, vid 0x%x\n",
-              data->currfid, data->currvid);
+       if (cpu_family)
+               dprintk("cpu_init done, current fid 0x%x, did 0x%x\n",
+                       data->currfid, data->currdid);
+       else
+               dprintk("cpu_init done, current fid 0x%x, vid 0x%x\n",
+                       data->currfid, data->currvid);
 
        powernow_data[pol->cpu] = data;
 
@@ -1156,8 +1323,9 @@ static int __cpuinit powernowk8_init(void)
        }
 
        if (supported_cpus == num_online_cpus()) {
-               printk(KERN_INFO PFX "Found %d AMD Athlon 64 / Opteron "
-                       "processors (" VERSION ")\n", supported_cpus);
+               printk(KERN_INFO PFX "Found %d %s "
+                       "processors (" VERSION ")\n", supported_cpus,
+                       boot_cpu_data.x86_model_id);
                return cpufreq_register_driver(&cpufreq_amd64_driver);
        }
 
index 79a7c5c..bf8ad9e 100644 (file)
@@ -1,5 +1,5 @@
 /*
- *  (c) 2003, 2004, 2005 Advanced Micro Devices, Inc.
+ *  (c) 2003-2006 Advanced Micro Devices, Inc.
  *  Your use of this code is subject to the terms and conditions of the
  *  GNU general public license version 2. See "COPYING" or
  *  http://www.gnu.org/licenses/gpl.html
@@ -21,8 +21,8 @@ struct powernow_k8_data {
        u32 plllock; /* pll lock time, units 1 us */
         u32 exttype; /* extended interface = 1 */
 
-       /* keep track of the current fid / vid */
-       u32 currvid, currfid;
+       /* keep track of the current fid / vid or did */
+       u32 currvid, currfid, currdid;
 
        /* the powernow_table includes all frequency and vid/fid pairings:
         * fid are the lower 8 bits of the index, vid are the upper 8 bits.
@@ -34,6 +34,10 @@ struct powernow_k8_data {
         * used to determine valid frequency/vid/fid states */
        struct acpi_processor_performance acpi_data;
 #endif
+       /* we need to keep track of associated cores, but let cpufreq
+        * handle hotplug events - so just point at cpufreq pol->cpus
+        * structure */
+       cpumask_t *available_cores;
 };
 
 
@@ -43,6 +47,7 @@ struct powernow_k8_data {
 #define CPUID_XFAM_K8                  0
 #define CPUID_XMOD                     0x000f0000      /* extended model */
 #define CPUID_XMOD_REV_G               0x00060000
+#define CPUID_XFAM_10H                         0x00100000      /* family 0x10 */
 #define CPUID_USE_XFAM_XMOD            0x00000f00
 #define CPUID_GET_MAX_CAPABILITIES     0x80000000
 #define CPUID_FREQ_VOLT_CAPABILITIES   0x80000007
@@ -79,6 +84,32 @@ struct powernow_k8_data {
 #define MSR_S_HI_CURRENT_VID      0x0000003f
 #define MSR_C_HI_STP_GNT_BENIGN          0x00000001
 
+
+/* Hardware Pstate _PSS and MSR definitions */
+#define USE_HW_PSTATE          0x00000080
+#define HW_PSTATE_FID_MASK     0x0000003f
+#define HW_PSTATE_DID_MASK     0x000001c0
+#define HW_PSTATE_DID_SHIFT    6
+#define HW_PSTATE_MASK                 0x00000007
+#define HW_PSTATE_VALID_MASK   0x80000000
+#define HW_FID_INDEX_SHIFT     8
+#define HW_FID_INDEX_MASK      0x0000ff00
+#define HW_DID_INDEX_SHIFT     16
+#define HW_DID_INDEX_MASK      0x00ff0000
+#define HW_WATTS_MASK          0xff
+#define HW_PWR_DVR_MASK                0x300
+#define HW_PWR_DVR_SHIFT       8
+#define HW_PWR_MAX_MULT                3
+#define MAX_HW_PSTATE          8       /* hw pstate supports up to 8 */
+#define MSR_PSTATE_DEF_BASE    0xc0010064 /* base of Pstate MSRs */
+#define MSR_PSTATE_STATUS      0xc0010063 /* Pstate Status MSR */
+#define MSR_PSTATE_CTRL        0xc0010062 /* Pstate control MSR */
+
+/* define the two driver architectures */
+#define CPU_OPTERON 0
+#define CPU_HW_PSTATE 1
+
+
 /*
  * There are restrictions frequencies have to follow:
  * - only 1 entry in the low fid table ( <=1.4GHz )
@@ -182,6 +213,9 @@ static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);
 
 static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);
 
+static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
+static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
+
 #ifdef CONFIG_SMP
 static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[])
 {
index b0ff907..ce54ff1 100644 (file)
@@ -250,7 +250,7 @@ static int centrino_cpu_init_table(struct cpufreq_policy *policy)
 
        if (model->cpu_id == NULL) {
                /* No match at all */
-               dprintk(KERN_INFO PFX "no support for CPU model \"%s\": "
+               dprintk("no support for CPU model \"%s\": "
                       "send /proc/cpuinfo to " MAINTAINER "\n",
                       cpu->x86_model_id);
                return -ENOENT;
@@ -258,10 +258,10 @@ static int centrino_cpu_init_table(struct cpufreq_policy *policy)
 
        if (model->op_points == NULL) {
                /* Matched a non-match */
-               dprintk(KERN_INFO PFX "no table support for CPU model \"%s\"\n",
+               dprintk("no table support for CPU model \"%s\"\n",
                       cpu->x86_model_id);
 #ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
-               dprintk(KERN_INFO PFX "try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
+               dprintk("try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
 #endif
                return -ENOENT;
        }
@@ -368,7 +368,7 @@ static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
 
        /* register with ACPI core */
        if (acpi_processor_register_performance(&p, cpu)) {
-               dprintk(KERN_INFO PFX "obtaining ACPI data failed\n");
+               dprintk("obtaining ACPI data failed\n");
                return -EIO;
        }
 
@@ -465,7 +465,7 @@ static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
        kfree(centrino_model[cpu]);
  err_unreg:
        acpi_processor_unregister_performance(&p, cpu);
-       dprintk(KERN_INFO PFX "invalid ACPI data\n");
+       dprintk("invalid ACPI data\n");
        return (result);
 }
 #else
@@ -499,7 +499,7 @@ static int centrino_cpu_init(struct cpufreq_policy *policy)
                        centrino_cpu[policy->cpu] = &cpu_ids[i];
 
                if (!centrino_cpu[policy->cpu]) {
-                       dprintk(KERN_INFO PFX "found unsupported CPU with "
+                       dprintk("found unsupported CPU with "
                        "Enhanced SpeedStep: send /proc/cpuinfo to "
                        MAINTAINER "\n");
                        return -ENODEV;
index e8ff09f..35e038a 100644 (file)
@@ -119,6 +119,32 @@ config MIPS_MIRAGE
        select SYS_HAS_CPU_MIPS32_R1
        select SYS_SUPPORTS_LITTLE_ENDIAN
 
+config BASLER_EXCITE
+       bool "Basler eXcite smart camera support"
+       select DMA_COHERENT
+       select HW_HAS_PCI
+       select IRQ_CPU
+       select IRQ_CPU_RM7K
+       select IRQ_CPU_RM9K
+       select SERIAL_RM9000
+       select SYS_HAS_CPU_RM9000
+       select SYS_SUPPORTS_32BIT_KERNEL
+       select SYS_SUPPORTS_64BIT_KERNEL
+       select SYS_SUPPORTS_BIG_ENDIAN
+       help
+         The eXcite is a smart camera platform manufactured by
+         Basler Vision Technologies AG
+
+config BASLER_EXCITE_PROTOTYPE
+       bool "Support for pre-release units"
+       depends on BASLER_EXCITE
+       default n
+       help
+         Pre-series (prototype) units are different from later ones in
+         some ways. Select this option if you have one of these. Please
+         note that a kernel built with this option selected will not be
+         able to run on normal units.
+
 config MIPS_COBALT
        bool "Cobalt Server"
        select DMA_NONCOHERENT
@@ -142,6 +168,9 @@ config MACH_DECSTATION
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
        select SYS_SUPPORTS_LITTLE_ENDIAN
+       select SYS_SUPPORTS_128HZ
+       select SYS_SUPPORTS_256HZ
+       select SYS_SUPPORTS_1024HZ
        help
          This enables support for DEC's MIPS based workstations.  For details
          see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
@@ -239,6 +268,7 @@ config MACH_JAZZ
        select SYS_HAS_CPU_R4X00
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+       select SYS_SUPPORTS_100HZ
        help
         This a family of machines based on the MIPS R4030 chipset which was
         used by several vendors to build RISC/os and Windows NT workstations.
@@ -327,6 +357,27 @@ config MIPS_SEAD
          This enables support for the MIPS Technologies SEAD evaluation
          board.
 
+config WR_PPMC
+       bool "Support for Wind River PPMC board"
+       select IRQ_CPU
+       select BOOT_ELF32
+       select DMA_NONCOHERENT
+       select HW_HAS_PCI
+       select MIPS_GT64120
+       select SWAP_IO_SPACE
+       select SYS_HAS_CPU_MIPS32_R1
+       select SYS_HAS_CPU_MIPS32_R2
+       select SYS_HAS_CPU_MIPS64_R1
+       select SYS_HAS_CPU_NEVADA
+       select SYS_HAS_CPU_RM7000
+       select SYS_SUPPORTS_32BIT_KERNEL
+       select SYS_SUPPORTS_64BIT_KERNEL
+       select SYS_SUPPORTS_BIG_ENDIAN
+       select SYS_SUPPORTS_LITTLE_ENDIAN
+       help
+         This enables support for the Wind River MIPS32 4KC PPMC evaluation
+         board, which is based on GT64120 bridge chip.
+
 config MIPS_SIM
        bool 'MIPS simulator (MIPSsim)'
        select DMA_NONCOHERENT
@@ -438,53 +489,16 @@ config MIPS_XXS1500
 
 config PNX8550_V2PCI
        bool "Philips PNX8550 based Viper2-PCI board"
+       depends on BROKEN
        select PNX8550
        select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config PNX8550_JBS
        bool "Philips PNX8550 based JBS board"
+       depends on BROKEN
        select PNX8550
        select SYS_SUPPORTS_LITTLE_ENDIAN
 
-config DDB5074
-       bool "NEC DDB Vrc-5074 (EXPERIMENTAL)"
-       depends on EXPERIMENTAL
-       select DDB5XXX_COMMON
-       select DMA_NONCOHERENT
-       select HAVE_STD_PC_SERIAL_PORT
-       select HW_HAS_PCI
-       select IRQ_CPU
-       select I8259
-       select ISA
-       select SYS_HAS_CPU_R5000
-       select SYS_SUPPORTS_32BIT_KERNEL
-       select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-       select SYS_SUPPORTS_LITTLE_ENDIAN
-       help
-         This enables support for the VR5000-based NEC DDB Vrc-5074
-         evaluation board.
-
-config DDB5476
-       bool "NEC DDB Vrc-5476"
-       select DDB5XXX_COMMON
-       select DMA_NONCOHERENT
-       select HAVE_STD_PC_SERIAL_PORT
-       select HW_HAS_PCI
-       select IRQ_CPU
-       select I8259
-       select ISA
-       select SYS_HAS_CPU_R5432
-       select SYS_SUPPORTS_32BIT_KERNEL
-       select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-       select SYS_SUPPORTS_LITTLE_ENDIAN
-       help
-         This enables support for the R5432-based NEC DDB Vrc-5476
-         evaluation board.
-
-         Features : kernel debugging, serial terminal, NFS root fs, on-board
-         ether port USB, AC97, PCI, PCI VGA card & framebuffer console,
-         IDE controller, PS2 keyboard, PS2 mouse, etc.
-
 config DDB5477
        bool "NEC DDB Vrc-5477"
        select DDB5XXX_COMMON
@@ -546,6 +560,20 @@ config QEMU
          simulate actual MIPS hardware platforms.  More information on Qemu
          can be found at http://www.linux-mips.org/wiki/Qemu.
 
+config MARKEINS
+       bool "Support for NEC EMMA2RH Mark-eins"
+       select DMA_NONCOHERENT
+       select HW_HAS_PCI
+       select IRQ_CPU
+       select SWAP_IO_SPACE
+       select SYS_SUPPORTS_32BIT_KERNEL
+       select SYS_SUPPORTS_BIG_ENDIAN
+       select SYS_SUPPORTS_LITTLE_ENDIAN
+       select SYS_HAS_CPU_R5000
+       help
+         This enables support for the R5432-based NEC Mark-eins
+         boards with R5500 CPU.
+
 config SGI_IP22
        bool "SGI IP22 (Indy/Indigo2)"
        select ARC
@@ -555,6 +583,7 @@ config SGI_IP22
        select HW_HAS_EISA
        select IP22_CPU_SCACHE
        select IRQ_CPU
+       select NO_ISA if ISA
        select SWAP_IO_SPACE
        select SYS_HAS_CPU_R4X00
        select SYS_HAS_CPU_R5000
@@ -577,6 +606,7 @@ config SGI_IP27
        select SYS_HAS_CPU_R10000
        select SYS_SUPPORTS_64BIT_KERNEL
        select SYS_SUPPORTS_BIG_ENDIAN
+       select SYS_SUPPORTS_NUMA
        help
          This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
          workstations.  To compile a Linux kernel that runs on these, say Y
@@ -707,8 +737,8 @@ config SIBYTE_CRHONE
 
 config SNI_RM200_PCI
        bool "SNI RM200 PCI"
-       select ARC
-       select ARC32
+       select ARC if CPU_LITTLE_ENDIAN
+       select ARC32 if CPU_LITTLE_ENDIAN
        select ARCH_MAY_HAVE_PC_FDC
        select BOOT_ELF32
        select DMA_NONCOHERENT
@@ -719,10 +749,13 @@ config SNI_RM200_PCI
        select I8253
        select I8259
        select ISA
+       select SWAP_IO_SPACE if CPU_BIG_ENDIAN
        select SYS_HAS_CPU_R4X00
+       select SYS_HAS_CPU_R5000
+       select R5000_CPU_SCACHE
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-       select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL
+       select SYS_SUPPORTS_BIG_ENDIAN
        select SYS_SUPPORTS_HIGHMEM
        select SYS_SUPPORTS_LITTLE_ENDIAN
        help
@@ -979,6 +1012,11 @@ config SOC_PNX8550
 config SWAP_IO_SPACE
        bool
 
+config EMMA2RH
+       bool
+       depends on MARKEINS
+       default y
+
 #
 # Unfortunately not all GT64120 systems run the chip at the same clock.
 # As the user for the clock rate and try to minimize the available options.
@@ -1607,6 +1645,28 @@ config ARCH_FLATMEM_ENABLE
        def_bool y
        depends on !NUMA
 
+config ARCH_DISCONTIGMEM_ENABLE
+       bool
+       default y if SGI_IP27
+       help
+         Say Y to upport efficient handling of discontiguous physical memory,
+         for architectures which are either NUMA (Non-Uniform Memory Access)
+         or have huge holes in the physical address space for other reasons.
+         See <file:Documentation/vm/numa> for more.
+
+config NUMA
+       bool "NUMA Support"
+       depends on SYS_SUPPORTS_NUMA
+       help
+         Say Y to compile the kernel to support NUMA (Non-Uniform Memory
+         Access).  This option improves performance on systems with more
+         than two nodes; on two node systems it is generally better to
+         leave it disabled; on single node systems disable this option
+         disabled.
+
+config SYS_SUPPORTS_NUMA
+       bool
+
 config NODES_SHIFT
        int
        default "6"
@@ -1651,6 +1711,77 @@ config NR_CPUS
          This is purely to save memory - each supported CPU adds
          approximately eight kilobytes to the kernel image.
 
+#
+# Timer Interrupt Frequency Configuration
+#
+
+choice
+       prompt "Timer frequency"
+       default HZ_250
+       help
+        Allows the configuration of the timer frequency.
+
+       config HZ_48
+               bool "48 HZ" if SYS_SUPPORTS_48HZ
+
+       config HZ_100
+               bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
+
+       config HZ_128
+               bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
+
+       config HZ_250
+               bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
+
+       config HZ_256
+               bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
+
+       config HZ_1000
+               bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
+
+       config HZ_1024
+               bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
+
+endchoice
+
+config SYS_SUPPORTS_48HZ
+       bool
+
+config SYS_SUPPORTS_100HZ
+       bool
+
+config SYS_SUPPORTS_128HZ
+       bool
+
+config SYS_SUPPORTS_250HZ
+       bool
+
+config SYS_SUPPORTS_256HZ
+       bool
+
+config SYS_SUPPORTS_1000HZ
+       bool
+
+config SYS_SUPPORTS_1024HZ
+       bool
+
+config SYS_SUPPORTS_ARBIT_HZ
+       bool
+       default y if !SYS_SUPPORTS_48HZ && !SYS_SUPPORTS_100HZ && \
+                    !SYS_SUPPORTS_128HZ && !SYS_SUPPORTS_250HZ && \
+                    !SYS_SUPPORTS_256HZ && !SYS_SUPPORTS_1000HZ && \
+                    !SYS_SUPPORTS_1024HZ
+
+config HZ
+       int
+       default 48 if HZ_48
+       default 100 if HZ_100
+       default 128 if HZ_128
+       default 250 if HZ_250
+       default 256 if HZ_256
+       default 1000 if HZ_1000
+       default 1024 if HZ_1024
+
 source "kernel/Kconfig.preempt"
 
 config RTC_DS1742
@@ -1710,6 +1841,9 @@ source "drivers/pci/Kconfig"
 config ISA
        bool
 
+config NO_ISA
+       bool
+
 config EISA
        bool "EISA support"
        depends on HW_HAS_EISA
@@ -1840,6 +1974,32 @@ config PM
        bool "Power Management support (EXPERIMENTAL)"
        depends on EXPERIMENTAL && SOC_AU1X00
 
+config APM
+        tristate "Advanced Power Management Emulation"
+       depends on PM
+        ---help---
+         APM is a BIOS specification for saving power using several different
+         techniques. This is mostly useful for battery powered systems with
+         APM compliant BIOSes. If you say Y here, the system time will be
+         reset after a RESUME operation, the /proc/apm device will provide
+         battery status information, and user-space programs will receive
+         notification of APM "events" (e.g. battery status change).
+
+         In order to use APM, you will need supporting software. For location
+         and more information, read <file:Documentation/pm.txt> and the
+         Battery Powered Linux mini-HOWTO, available from
+         <http://www.tldp.org/docs.html#howto>.
+
+         This driver does not spin down disk drives (see the hdparm(8)
+         manpage ("man 8 hdparm") for that), and it doesn't turn off
+         VESA-compliant "green" monitors.
+
+         Generally, if you don't have a battery in your machine, there isn't
+         much point in using this driver and you should say N. If you get
+         random kernel OOPSes or reboots that don't seem to be related to
+         anything, try disabling/enabling this option (or disabling/enabling
+         APM in your BIOS).
+
 endmenu
 
 source "net/Kconfig"
index 133900a..d593014 100644 (file)
@@ -83,6 +83,8 @@ cflags-y                      += -msoft-float
 LDFLAGS_vmlinux                        += -G 0 -static -n -nostdlib
 MODFLAGS                       += -mlong-calls
 
+cflags-y += -ffreestanding
+
 #
 # We explicitly add the endianness specifier if needed, this allows
 # to compile kernels with a toolchain for the other endianness. We
@@ -285,6 +287,13 @@ cflags-$(CONFIG_MIPS_EV96100)      += -Iinclude/asm-mips/mach-ev96100
 load-$(CONFIG_MIPS_EV96100)    += 0xffffffff80100000
 
 #
+# Wind River PPMC Board (4KC + GT64120)
+#
+core-$(CONFIG_WR_PPMC)         += arch/mips/gt64120/wrppmc/
+cflags-$(CONFIG_WR_PPMC)               += -Iinclude/asm-mips/mach-wrppmc
+load-$(CONFIG_WR_PPMC)         += 0xffffffff80100000
+
+#
 # Globespan IVR eval board with QED 5231 CPU
 #
 core-$(CONFIG_ITE_BOARD_GEN)   += arch/mips/ite-boards/generic/
@@ -379,6 +388,13 @@ cflags-$(CONFIG_MOMENCO_OCELOT_3)  += -Iinclude/asm-mips/mach-ocelot3
 load-$(CONFIG_MOMENCO_OCELOT_3)        += 0xffffffff80100000
 
 #
+# Basler eXcite
+#
+core-$(CONFIG_BASLER_EXCITE)   += arch/mips/basler/excite/
+cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite
+load-$(CONFIG_BASLER_EXCITE)   += 0x80100000
+
+#
 # Momentum Jaguar ATX
 #
 core-$(CONFIG_MOMENCO_JAGUAR_ATX)      += arch/mips/momentum/jaguar_atx/
@@ -395,18 +411,6 @@ load-$(CONFIG_MOMENCO_JAGUAR_ATX)  += 0xffffffff80100000
 core-$(CONFIG_DDB5XXX_COMMON)  += arch/mips/ddb5xxx/common/
 
 #
-# NEC DDB Vrc-5074
-#
-core-$(CONFIG_DDB5074)         += arch/mips/ddb5xxx/ddb5074/
-load-$(CONFIG_DDB5074)         += 0xffffffff80080000
-
-#
-# NEC DDB Vrc-5476
-#
-core-$(CONFIG_DDB5476)         += arch/mips/ddb5xxx/ddb5476/
-load-$(CONFIG_DDB5476)         += 0xffffffff80080000
-
-#
 # NEC DDB Vrc-5477
 #
 core-$(CONFIG_DDB5477)         += arch/mips/ddb5xxx/ddb5477/
@@ -468,6 +472,15 @@ libs-$(CONFIG_PNX8550_JBS) += arch/mips/philips/pnx8550/jbs/
 #cflags-$(CONFIG_PNX8550_JBS)  += -Iinclude/asm-mips/mach-pnx8550
 load-$(CONFIG_PNX8550_JBS)     += 0xffffffff80060000
 
+# NEC EMMA2RH boards
+#
+core-$(CONFIG_EMMA2RH)          += arch/mips/emma2rh/common/
+cflags-$(CONFIG_EMMA2RH)        += -Iinclude/asm-mips/mach-emma2rh
+
+# NEC EMMA2RH Mark-eins
+core-$(CONFIG_MARKEINS)         += arch/mips/emma2rh/markeins/
+load-$(CONFIG_MARKEINS)         += 0xffffffff88100000
+
 #
 # SGI IP22 (Indy/Indigo2)
 #
index 0b2c03c..5a1e368 100644 (file)
@@ -55,7 +55,7 @@
  * Careful if you change match 2 request!
  * The interrupt handler is called directly from the low level dispatch code.
  */
-au1xxx_irq_map_t au1xxx_ic0_map[] = {
+au1xxx_irq_map_t __initdata au1xxx_ic0_map[] = {
 
 #if defined(CONFIG_SOC_AU1000)
        { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
@@ -220,5 +220,5 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = {
 
 };
 
-int au1xxx_ic0_nr_irqs = sizeof(au1xxx_ic0_map)/sizeof(au1xxx_irq_map_t);
+int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map);
 
index 4e5a6e1..b1392ab 100644 (file)
 
 /* TBD */
 static struct resource pci_io_resource = {
-       "pci IO space",
-       (u32)PCI_IO_START,
-       (u32)PCI_IO_END,
-       IORESOURCE_IO
+       .start  = PCI_IO_START,
+       .end    = PCI_IO_END,
+       .name   = "PCI IO space",
+       .flags  = IORESOURCE_IO
 };
 
 static struct resource pci_mem_resource = {
-       "pci memory space",
-       (u32)PCI_MEM_START,
-       (u32)PCI_MEM_END,
-       IORESOURCE_MEM
+       .start  = PCI_MEM_START,
+       .end    = PCI_MEM_END,
+       .name   = "PCI memory space",
+       .flags  = IORESOURCE_MEM
 };
 
 extern struct pci_ops au1x_pci_ops;
index 307e98c..97165b6 100644 (file)
@@ -49,17 +49,13 @@ extern void __init board_setup(void);
 extern void au1000_restart(char *);
 extern void au1000_halt(void);
 extern void au1000_power_off(void);
-extern struct resource ioport_resource;
-extern struct resource iomem_resource;
-extern void (*board_time_init)(void);
 extern void au1x_time_init(void);
-extern void (*board_timer_setup)(struct irqaction *irq);
 extern void au1x_timer_setup(struct irqaction *irq);
 extern void au1xxx_time_init(void);
 extern void au1xxx_timer_setup(struct irqaction *irq);
 extern void set_cpuspec(void);
 
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
 {
        struct  cpu_spec *sp;
        char *argptr;
index f74d66a..842e1b5 100644 (file)
 #include <linux/mc146818rtc.h>
 #include <linux/timex.h>
 
-extern void do_softirq(void);
-extern volatile unsigned long wall_jiffies;
-unsigned long missed_heart_beats = 0;
-
 static unsigned long r4k_offset; /* Amount to increment compare reg each time */
 static unsigned long r4k_cur;    /* What counter should be at next timer irq */
 int    no_au1xxx_32khz;
@@ -388,10 +384,9 @@ static unsigned long do_fast_pm_gettimeoffset(void)
 }
 #endif
 
-void au1xxx_timer_setup(struct irqaction *irq)
+void __init au1xxx_timer_setup(struct irqaction *irq)
 {
-        unsigned int est_freq;
-       extern unsigned long (*do_gettimeoffset)(void);
+       unsigned int est_freq;
 
        printk("calculating r4koff... ");
        r4k_offset = cal_r4koff();
index 5cb1166..57d6040 100644 (file)
@@ -47,7 +47,7 @@
 #include <asm/system.h>
 #include <asm/au1000.h>
 
-au1xxx_irq_map_t au1xxx_irq_map[] = {
+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
 
        { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
        { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
@@ -57,4 +57,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
        { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 },
 };
 
-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
index f63024a..0138c5b 100644 (file)
@@ -80,7 +80,7 @@ char irq_tab_alchemy[][5] __initdata = {
 #endif
 
 
-au1xxx_irq_map_t au1xxx_irq_map[] = {
+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
 
 #ifndef CONFIG_MIPS_MIRAGE
 #ifdef CONFIG_MIPS_DB1550
@@ -101,4 +101,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
 
 };
 
-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
index 6eacaa0..14e1ed3 100644 (file)
 #include <asm/system.h>
 #include <asm/au1000.h>
 
-au1xxx_irq_map_t au1xxx_irq_map[] = {
+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
 
        /* { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, */
        { AU1000_GPIO_21, INTC_INT_LOW_LEVEL, 0 },
 };
 
-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
index f9a0a8b..4693a4e 100644 (file)
@@ -58,7 +58,7 @@ char irq_tab_alchemy[][5] __initdata = {
  [7] = { -1, INTD, INTC, INTX, INTX},   /* IDSEL 07 - AdapterD-Slot1 (bottom) */
 };
 
-au1xxx_irq_map_t au1xxx_irq_map[] = {
+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
        { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
        { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
        { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
@@ -66,4 +66,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
        { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 },
 };
 
-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
index a3c460e..156500b 100644 (file)
@@ -47,8 +47,8 @@
 #include <asm/system.h>
 #include <asm/mach-au1x00/au1000.h>
 
-au1xxx_irq_map_t au1xxx_irq_map[] = {
+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
        { AU1000_GPIO_15, INTC_INT_LOW_LEVEL, 0 },
 };
 
-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
index 43be715..d986916 100644 (file)
 #include <asm/system.h>
 #include <asm/mach-au1x00/au1000.h>
 
-au1xxx_irq_map_t au1xxx_irq_map[] = {
+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
        { AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card Fully_Interted#
        { AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card STSCHG#
        { AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card IRQ#
        { AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, // DC_IRQ#
 };
 
-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
index 59e70e5..bacc0c6 100644 (file)
 #define PB1200_INT_END DB1200_INT_END
 #endif
 
-au1xxx_irq_map_t au1xxx_irq_map[] = {
+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
        { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
 };
 
-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
 
 /*
  *     Support for External interrupts on the PbAu1200 Development platform.
index 8cb76c2..409d161 100644 (file)
@@ -52,7 +52,7 @@ char irq_tab_alchemy[][5] __initdata = {
  [13] = { -1, INTA, INTB, INTC, INTD},   /* IDSEL 13 - PCI slot */
 };
 
-au1xxx_irq_map_t au1xxx_irq_map[] = {
+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
        { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
        { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
        { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
@@ -60,4 +60,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
        { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 },
 };
 
-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
index 47c7a1c..24a9d18 100644 (file)
@@ -52,9 +52,9 @@ char irq_tab_alchemy[][5] __initdata = {
  [13] =        { -1, INTA, INTB, INTC, INTD},   /* IDSEL 13 - PCI slot 1 (right) */
 };
 
-au1xxx_irq_map_t au1xxx_irq_map[] = {
+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
        { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
        { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
 };
 
-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
index 52f2f7d..3844c64 100644 (file)
@@ -47,7 +47,7 @@
 #include <asm/system.h>
 #include <asm/au1000.h>
 
-au1xxx_irq_map_t au1xxx_irq_map[] = {
+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
        { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
        { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
        { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
@@ -63,4 +63,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
        { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 },
 };
 
-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/basler/excite/Makefile b/arch/mips/basler/excite/Makefile
new file mode 100644 (file)
index 0000000..519142c
--- /dev/null
@@ -0,0 +1,9 @@
+#
+# Makefile for Basler eXcite
+#
+
+obj-$(CONFIG_BASLER_EXCITE)    += excite_irq.o excite_prom.o excite_setup.o \
+                                  excite_device.o excite_procfs.o
+
+obj-$(CONFIG_KGDB)             += excite_dbg_io.o
+obj-m                          += excite_iodev.o
diff --git a/arch/mips/basler/excite/excite_dbg_io.c b/arch/mips/basler/excite/excite_dbg_io.c
new file mode 100644 (file)
index 0000000..83f6bdd
--- /dev/null
@@ -0,0 +1,122 @@
+/*
+ *  Copyright (C) 2004 by Basler Vision Technologies AG
+ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <asm/gdb-stub.h>
+#include <asm/rm9k-ocd.h>
+#include <excite.h>
+
+#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1
+#error Debug port used by serial driver
+#endif
+
+#define UART_CLK               25000000
+#define BASE_BAUD              (UART_CLK / 16)
+#define REGISTER_BASE_0                0x0208UL
+#define REGISTER_BASE_1                0x0238UL
+
+#define REGISTER_BASE_DBG      REGISTER_BASE_1
+
+#define CPRR   0x0004
+#define UACFG  0x0200
+#define UAINTS 0x0204
+#define UARBR  (REGISTER_BASE_DBG + 0x0000)
+#define UATHR  (REGISTER_BASE_DBG + 0x0004)
+#define UADLL  (REGISTER_BASE_DBG + 0x0008)
+#define UAIER  (REGISTER_BASE_DBG + 0x000c)
+#define UADLH  (REGISTER_BASE_DBG + 0x0010)
+#define UAIIR  (REGISTER_BASE_DBG + 0x0014)
+#define UAFCR  (REGISTER_BASE_DBG + 0x0018)
+#define UALCR  (REGISTER_BASE_DBG + 0x001c)
+#define UAMCR  (REGISTER_BASE_DBG + 0x0020)
+#define UALSR  (REGISTER_BASE_DBG + 0x0024)
+#define UAMSR  (REGISTER_BASE_DBG + 0x0028)
+#define UASCR  (REGISTER_BASE_DBG + 0x002c)
+
+#define        PARITY_NONE     0
+#define        PARITY_ODD      0x08
+#define        PARITY_EVEN     0x18
+#define        PARITY_MARK     0x28
+#define        PARITY_SPACE    0x38
+
+#define        DATA_5BIT       0x0
+#define        DATA_6BIT       0x1
+#define        DATA_7BIT       0x2
+#define        DATA_8BIT       0x3
+
+#define        STOP_1BIT       0x0
+#define        STOP_2BIT       0x4
+
+#define BAUD_DBG       57600
+#define        PARITY_DBG      PARITY_NONE
+#define        DATA_DBG        DATA_8BIT
+#define        STOP_DBG        STOP_1BIT
+
+/* Initialize the serial port for KGDB debugging */
+void __init excite_kgdb_init(void)
+{
+       const u32 divisor = BASE_BAUD / BAUD_DBG;
+
+       /* Take the UART out of reset */
+       titan_writel(0x00ff1cff, CPRR);
+       titan_writel(0x00000000, UACFG);
+       titan_writel(0x00000002, UACFG);
+
+       titan_writel(0x0, UALCR);
+       titan_writel(0x0, UAIER);
+
+       /* Disable FIFOs */
+       titan_writel(0x00, UAFCR);
+
+       titan_writel(0x80, UALCR);
+       titan_writel(divisor & 0xff, UADLL);
+       titan_writel((divisor & 0xff00) >> 8, UADLH);
+       titan_writel(0x0, UALCR);
+
+       titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR);
+
+       /* Enable receiver interrupt */
+       titan_readl(UARBR);
+       titan_writel(0x1, UAIER);
+}
+
+int getDebugChar(void)
+{
+       while (!(titan_readl(UALSR) & 0x1));
+       return titan_readl(UARBR);
+}
+
+int putDebugChar(int data)
+{
+       while (!(titan_readl(UALSR) & 0x20));
+       titan_writel(data, UATHR);
+       return 1;
+}
+
+/* KGDB interrupt handler */
+asmlinkage void excite_kgdb_inthdl(struct pt_regs *regs)
+{
+       if (unlikely(
+               ((titan_readl(UAIIR) & 0x7) == 4)
+               && ((titan_readl(UARBR) & 0xff) == 0x3)))
+                       set_async_breakpoint(&regs->cp0_epc);
+}
diff --git a/arch/mips/basler/excite/excite_device.c b/arch/mips/basler/excite/excite_device.c
new file mode 100644 (file)
index 0000000..34ec767
--- /dev/null
@@ -0,0 +1,404 @@
+/*
+ *  Copyright (C) 2004 by Basler Vision Technologies AG
+ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ioport.h>
+#include <linux/err.h>
+#include <linux/jiffies.h>
+#include <linux/sched.h>
+#include <asm/types.h>
+#include <asm/rm9k-ocd.h>
+
+#include <excite.h>
+#include <rm9k_eth.h>
+#include <rm9k_wdt.h>
+#include <rm9k_xicap.h>
+#include <excite_nandflash.h>
+
+#include "excite_iodev.h"
+
+#define RM9K_GE_UNIT   0
+#define XICAP_UNIT     0
+#define NAND_UNIT      0
+
+#define DLL_TIMEOUT    3               /* seconds */
+
+
+#define RINIT(__start__, __end__, __name__, __parent__) {      \
+       .name   = __name__ "_0",                                \
+       .start  = (__start__),                                  \
+       .end    = (__end__),                                    \
+       .flags  = 0,                                            \
+       .parent = (__parent__)                                  \
+}
+
+#define RINIT_IRQ(__irq__, __name__) { \
+       .name   = __name__ "_0",        \
+       .start  = (__irq__),            \
+       .end    = (__irq__),            \
+       .flags  = IORESOURCE_IRQ,       \
+       .parent = NULL                  \
+}
+
+
+
+enum {
+       slice_xicap,
+       slice_eth
+};
+
+
+
+static struct resource
+       excite_ctr_resource = {
+               .name           = "GPI counters",
+               .start          = 0,
+               .end            = 5,
+               .flags          = 0,
+               .parent         = NULL,
+               .sibling        = NULL,
+               .child          = NULL
+       },
+       excite_gpislice_resource = {
+               .name           = "GPI slices",
+               .start          = 0,
+               .end            = 1,
+               .flags          = 0,
+               .parent         = NULL,
+               .sibling        = NULL,
+               .child          = NULL
+       },
+       excite_mdio_channel_resource = {
+               .name           = "MDIO channels",
+               .start          = 0,
+               .end            = 1,
+               .flags          = 0,
+               .parent         = NULL,
+               .sibling        = NULL,
+               .child          = NULL
+       },
+       excite_fifomem_resource = {
+               .name           = "FIFO memory",
+               .start          = 0,
+               .end            = 767,
+               .flags          = 0,
+               .parent         = NULL,
+               .sibling        = NULL,
+               .child          = NULL
+       },
+       excite_scram_resource = {
+               .name           = "Scratch RAM",
+               .start          = EXCITE_PHYS_SCRAM,
+               .end            = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
+               .flags          = IORESOURCE_MEM,
+               .parent         = NULL,
+               .sibling        = NULL,
+               .child          = NULL
+       },
+       excite_fpga_resource = {
+               .name           = "System FPGA",
+               .start          = EXCITE_PHYS_FPGA,
+               .end            = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
+               .flags          = IORESOURCE_MEM,
+               .parent         = NULL,
+               .sibling        = NULL,
+               .child          = NULL
+       },
+       excite_nand_resource = {
+               .name           = "NAND flash control",
+               .start          = EXCITE_PHYS_NAND,
+               .end            = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
+               .flags          = IORESOURCE_MEM,
+               .parent         = NULL,
+               .sibling        = NULL,
+               .child          = NULL
+       },
+       excite_titan_resource = {
+               .name           = "TITAN registers",
+               .start          = EXCITE_PHYS_TITAN,
+               .end            = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
+               .flags          = IORESOURCE_MEM,
+               .parent         = NULL,
+               .sibling        = NULL,
+               .child          = NULL
+       };
+
+
+
+static void adjust_resources(struct resource *res, unsigned int n)
+{
+       struct resource *p;
+       const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
+                                  | IORESOURCE_IRQ | IORESOURCE_DMA;
+
+       for (p = res; p < res + n; p++) {
+               const struct resource * const parent = p->parent;
+               if (parent) {
+                       p->start += parent->start;
+                       p->end   += parent->start;
+                       p->flags =  parent->flags & mask;
+               }
+       }
+}
+
+
+
+#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
+static struct resource xicap_rsrc[] = {
+       RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
+       RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
+       RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
+       RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
+       RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
+       RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
+       RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
+       RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
+       RINIT_IRQ(TITAN_IRQ,  XICAP_RESOURCE_IRQ)
+};
+
+static struct platform_device xicap_pdev = {
+       .name           = XICAP_NAME,
+       .id             = XICAP_UNIT,
+       .num_resources  = ARRAY_SIZE(xicap_rsrc),
+       .resource       = xicap_rsrc
+};
+
+/*
+ * Create a platform device for the GPI port that receives the
+ * image data from the embedded camera.
+ */
+static int __init xicap_devinit(void)
+{
+       unsigned long tend;
+       u32 reg;
+       int retval;
+
+       adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
+
+       /* Power up the slice and configure it. */
+       reg = titan_readl(CPTC1R);
+       reg &= ~(0x11100 << slice_xicap);
+       titan_writel(reg, CPTC1R);
+
+       /* Enable slice & DLL. */
+       reg= titan_readl(CPRR);
+       reg &= ~(0x00030003 << (slice_xicap * 2));
+       titan_writel(reg, CPRR);
+
+       /* Wait for DLLs to lock */
+       tend = jiffies + DLL_TIMEOUT * HZ;
+       while (time_before(jiffies, tend)) {
+               if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
+                       break;
+               yield();
+       }
+
+       if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
+               printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
+                      xicap_pdev.name, DLL_TIMEOUT);
+               retval = -ETIME;
+       } else {
+               /* Register platform device */
+               retval = platform_device_register(&xicap_pdev);
+       }
+
+       return retval;
+}
+
+device_initcall(xicap_devinit);
+#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
+
+
+
+#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
+static struct resource wdt_rsrc[] = {
+       RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
+       RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
+       RINIT_IRQ(TITAN_IRQ,  WDT_RESOURCE_IRQ)
+};
+
+static struct platform_device wdt_pdev = {
+       .name           = WDT_NAME,
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(wdt_rsrc),
+       .resource       = wdt_rsrc
+};
+
+/*
+ * Create a platform device for the GPI port that receives the
+ * image data from the embedded camera.
+ */
+static int __init wdt_devinit(void)
+{
+       adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
+       return platform_device_register(&wdt_pdev);
+}
+
+device_initcall(wdt_devinit);
+#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
+
+
+
+static struct resource excite_nandflash_rsrc[] = {
+       RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS,  &excite_nand_resource)
+};
+
+static struct platform_device excite_nandflash_pdev = {
+       .name           = "excite_nand",
+       .id             = NAND_UNIT,
+       .num_resources  = ARRAY_SIZE(excite_nandflash_rsrc),
+       .resource       = excite_nandflash_rsrc
+};
+
+/*
+ * Create a platform device for the access to the nand-flash
+ * port
+ */
+static int __init excite_nandflash_devinit(void)
+{
+       adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
+
+        /* nothing to be done here */
+
+        /* Register platform device */
+       return platform_device_register(&excite_nandflash_pdev);
+}
+
+device_initcall(excite_nandflash_devinit);
+
+
+
+static struct resource iodev_rsrc[] = {
+       RINIT_IRQ(FPGA1_IRQ,  IODEV_RESOURCE_IRQ)
+};
+
+static struct platform_device io_pdev = {
+       .name           = IODEV_NAME,
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(iodev_rsrc),
+       .resource       = iodev_rsrc
+};
+
+/*
+ * Create a platform device for the external I/O ports.
+ */
+static int __init io_devinit(void)
+{
+       adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
+       return platform_device_register(&io_pdev);
+}
+
+device_initcall(io_devinit);
+
+
+
+
+#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
+static struct resource rm9k_ge_rsrc[] = {
+       RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
+       RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
+       RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
+       RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
+       RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
+       RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
+       RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
+       RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
+       RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
+       RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
+       RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
+       RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
+       RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
+       RINIT_IRQ(TITAN_IRQ,  RM9K_GE_RESOURCE_IRQ_MAIN),
+       RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
+};
+
+static struct platform_device rm9k_ge_pdev = {
+       .name           = RM9K_GE_NAME,
+       .id             = RM9K_GE_UNIT,
+       .num_resources  = ARRAY_SIZE(rm9k_ge_rsrc),
+       .resource       = rm9k_ge_rsrc
+};
+
+
+
+/*
+ * Create a platform device for the Ethernet port.
+ */
+static int __init rm9k_ge_devinit(void)
+{
+       u32 reg;
+
+       adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
+
+       /* Power up the slice and configure it. */
+       reg = titan_readl(CPTC1R);
+       reg &= ~(0x11000 << slice_eth);
+       reg |= 0x100 << slice_eth;
+       titan_writel(reg, CPTC1R);
+
+       /* Take the MAC out of reset, reset the DLLs. */
+       reg = titan_readl(CPRR);
+       reg &= ~(0x00030000 << (slice_eth * 2));
+       reg |= 0x3 << (slice_eth * 2);
+       titan_writel(reg, CPRR);
+
+       return platform_device_register(&rm9k_ge_pdev);
+}
+
+device_initcall(rm9k_ge_devinit);
+#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
+
+
+
+static int __init excite_setup_devs(void)
+{
+       int res;
+       u32 reg;
+
+       /* Enable xdma and fifo interrupts */
+       reg = titan_readl(0x0050);
+       titan_writel(reg | 0x18000000, 0x0050);
+
+       res = request_resource(&iomem_resource, &excite_titan_resource);
+       if (res)
+               return res;
+       res = request_resource(&iomem_resource, &excite_scram_resource);
+       if (res)
+               return res;
+       res = request_resource(&iomem_resource, &excite_fpga_resource);
+       if (res)
+               return res;
+       res = request_resource(&iomem_resource, &excite_nand_resource);
+       if (res)
+               return res;
+       excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
+                                  ( IORESOURCE_IO | IORESOURCE_MEM
+                                  | IORESOURCE_IRQ | IORESOURCE_DMA);
+       excite_nand_resource.flags = excite_nand_resource.parent->flags &
+                                  ( IORESOURCE_IO | IORESOURCE_MEM
+                                  | IORESOURCE_IRQ | IORESOURCE_DMA);
+
+       return 0;
+}
+
+arch_initcall(excite_setup_devs);
+
diff --git a/arch/mips/basler/excite/excite_flashtest.c b/arch/mips/basler/excite/excite_flashtest.c
new file mode 100644 (file)
index 0000000..f0024a8
--- /dev/null
@@ -0,0 +1,294 @@
+/*
+*  Copyright (C) 2005 by Basler Vision Technologies AG
+*  Author: Thies Moeller <thies.moeller@baslerweb.com>
+*
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+*
+*  You should have received a copy of the GNU General Public License
+*  along with this program; if not, write to the Free Software
+*  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+
+#include <excite.h>
+
+#include <asm/io.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <asm/rm9k-ocd.h> // for ocd_write
+#include <linux/workqueue.h> // for queue
+
+#include "excite_nandflash.h"
+#include "nandflash.h"
+
+#define PFX "excite flashtest: "
+typedef void __iomem *io_reg_t;
+
+#define io_readb(__a__)                __raw_readb((__a__))
+#define io_writeb(__v__, __a__)        __raw_writeb((__v__), (__a__))
+
+
+
+static inline const struct resource *excite_nandflash_get_resource(
+       struct platform_device *d, unsigned long flags, const char *basename)
+{
+       const char fmt[] = "%s_%u";
+       char buf[80];
+
+       if (unlikely(snprintf(buf, sizeof buf, fmt, basename, d->id) >= sizeof buf))
+               return NULL;
+
+       return platform_get_resource_byname(d, flags, buf);
+}
+
+static inline io_reg_t
+excite_nandflash_map_regs(struct platform_device *d, const char *basename)
+{
+       void *result = NULL;
+       const struct resource *const r =
+           excite_nandflash_get_resource(d, IORESOURCE_MEM, basename);
+       if (r)
+          result = ioremap_nocache(r->start, r->end + 1 - r->start);
+       return result;
+}
+
+/* controller and mtd information */
+
+struct excite_nandflash_drvdata {
+       struct mtd_info board_mtd;
+       struct nand_chip board_chip;
+       io_reg_t regs;
+};
+
+
+/* command and control functions */
+static void excite_nandflash_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+       struct nand_chip *this = mtd->priv;
+       io_reg_t regs = container_of(mtd,struct excite_nandflash_drvdata,board_mtd)->regs;
+
+       switch (cmd) {
+       /* Select the command latch */
+       case NAND_CTL_SETCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_CMD;
+               break;
+       /* Deselect the command latch */
+       case NAND_CTL_CLRCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_DATA;
+               break;
+       /* Select the address latch */
+       case NAND_CTL_SETALE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_ADDR;
+               break;
+       /* Deselect the address latch */
+       case NAND_CTL_CLRALE: this->IO_ADDR_W = regs  + EXCITE_NANDFLASH_DATA;
+               break;
+       /* Select the chip  -- not used */
+       case NAND_CTL_SETNCE:
+               break;
+       /* Deselect the chip -- not used */
+       case NAND_CTL_CLRNCE:
+               break;
+       }
+
+       this->IO_ADDR_R = this->IO_ADDR_W;
+}
+
+/* excite_nandflash_devready()
+ *
+ * returns 0 if the nand is busy, 1 if it is ready
+ */
+static int excite_nandflash_devready(struct mtd_info *mtd)
+{
+       struct excite_nandflash_drvdata *drvdata =
+           container_of(mtd, struct excite_nandflash_drvdata, board_mtd);
+
+       return io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
+}
+
+/* device management functions */
+
+/* excite_nandflash_remove
+ *
+ * called by device layer to remove the driver
+ * the binding to the mtd and all allocated
+ * resources are released
+ */
+static int excite_nandflash_remove(struct device *dev)
+{
+       struct excite_nandflash_drvdata *this = dev_get_drvdata(dev);
+
+       pr_info(PFX "remove");
+
+       dev_set_drvdata(dev, NULL);
+
+       if (this == NULL) {
+               pr_debug(PFX "call remove without private data!!");
+               return 0;
+       }
+
+
+       /* free the common resources */
+       if (this->regs != NULL) {
+               iounmap(this->regs);
+               this->regs = NULL;
+       }
+
+       kfree(this);
+
+       return 0;
+}
+
+static int elapsed;
+
+void my_workqueue_handler(void *arg)
+{
+       elapsed = 1;
+}
+
+DECLARE_WORK(sigElapsed, my_workqueue_handler, 0);
+
+
+/* excite_nandflash_probe
+ *
+ * called by device layer when it finds a device matching
+ * one our driver can handled. This code checks to see if
+ * it can allocate all necessary resources then calls the
+ * nand layer to look for devices
+*/
+static int excite_nandflash_probe(struct device *dev)
+{
+       struct platform_device *pdev = to_platform_device(dev);
+
+       struct excite_nandflash_drvdata *drvdata;           /* private driver data     */
+       struct nand_chip              *board_chip;  /* private flash chip data */
+       struct mtd_info               *board_mtd;   /* mtd info for this board */
+
+       int err      = 0;
+       int count    = 0;
+       struct timeval tv,endtv;
+       unsigned int dt;
+
+       pr_info(PFX "probe dev: (%p)\n", dev);
+
+       pr_info(PFX "adjust LB timing\n");
+       ocd_writel(0x00000330, LDP2);
+
+       drvdata = kmalloc(sizeof(*drvdata), GFP_KERNEL);
+       if (unlikely(!drvdata)) {
+               printk(KERN_ERR PFX "no memory for drvdata\n");
+               err = -ENOMEM;
+               goto mem_error;
+       }
+
+       /* Initialize structures */
+       memset(drvdata, 0, sizeof(*drvdata));
+
+       /* bind private data into driver */
+       dev_set_drvdata(dev, drvdata);
+
+       /* allocate and map the resource */
+       drvdata->regs =
+           excite_nandflash_map_regs(pdev, EXCITE_NANDFLASH_RESOURCE_REGS);
+
+       if (unlikely(!drvdata->regs)) {
+               printk(KERN_ERR PFX "cannot reserve register region\n");
+               err = -ENXIO;
+               goto io_error;
+       }
+
+       /* initialise our chip */
+       board_chip = &drvdata->board_chip;
+
+       board_chip->IO_ADDR_R = drvdata->regs + EXCITE_NANDFLASH_DATA;
+       board_chip->IO_ADDR_W = drvdata->regs + EXCITE_NANDFLASH_DATA;
+
+       board_chip->hwcontrol = excite_nandflash_hwcontrol;
+       board_chip->dev_ready = excite_nandflash_devready;
+
+       board_chip->chip_delay = 25;
+       #if 0
+       /* TODO: speedup the initial scan */
+       board_chip->options = NAND_USE_FLASH_BBT;
+       #endif
+       board_chip->eccmode = NAND_ECC_SOFT;
+
+       /* link chip to mtd */
+       board_mtd = &drvdata->board_mtd;
+       board_mtd->priv = board_chip;
+
+
+       pr_info(PFX "FlashTest\n");
+       elapsed = 0;
+/*     schedule_delayed_work(&sigElapsed, 1*HZ);
+       while (!elapsed) {
+               io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
+               count++;
+       }
+       pr_info(PFX "reads in 1 sec --> %d\n",count);
+*/
+       do_gettimeofday(&tv);
+       for (count = 0 ; count < 1000000; count ++) {
+               io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
+       }
+       do_gettimeofday(&endtv);
+       dt = (endtv.tv_sec - tv.tv_sec) * 1000000 + endtv.tv_usec  - tv.tv_usec;
+       pr_info(PFX "%8d us timeval\n",dt);
+       pr_info(PFX "EndFlashTest\n");
+
+/*      return with error to unload everything
+*/
+io_error:
+       iounmap(drvdata->regs);
+
+mem_error:
+       kfree(drvdata);
+
+       if (err == 0)
+               err = -EINVAL;
+       return err;
+}
+
+static struct device_driver excite_nandflash_driver = {
+       .name = "excite_nand",
+       .bus = &platform_bus_type,
+       .probe = excite_nandflash_probe,
+       .remove = excite_nandflash_remove,
+};
+
+static int __init excite_nandflash_init(void)
+{
+       pr_info(PFX "register Driver (Rev: $Revision:$)\n");
+       return driver_register(&excite_nandflash_driver);
+}
+
+static void __exit excite_nandflash_exit(void)
+{
+       driver_unregister(&excite_nandflash_driver);
+       pr_info(PFX "Driver unregistered");
+}
+
+module_init(excite_nandflash_init);
+module_exit(excite_nandflash_exit);
+
+MODULE_AUTHOR("Thies Moeller <thies.moeller@baslerweb.com>");
+MODULE_DESCRIPTION("Basler eXcite NAND-Flash driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/mips/basler/excite/excite_fpga.h b/arch/mips/basler/excite/excite_fpga.h
new file mode 100644 (file)
index 0000000..38fcda7
--- /dev/null
@@ -0,0 +1,80 @@
+#ifndef EXCITE_FPGA_H_INCLUDED
+#define EXCITE_FPGA_H_INCLUDED
+
+
+/**
+ * Adress alignment of the individual FPGA bytes.
+ * The address arrangement of the individual bytes of the FPGA is two
+ * byte aligned at the embedded MK2 platform.
+ */
+#ifdef EXCITE_CCI_FPGA_MK2
+typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
+#else
+typedef unsigned char excite_cci_fpga_align_t;
+#endif
+
+
+/**
+ * Size of Dual Ported RAM.
+ */
+#define EXCITE_DPR_SIZE 263
+
+
+/**
+ * Size of Reserved Status Fields in Dual Ported RAM.
+ */
+#define EXCITE_DPR_STATUS_SIZE 7
+
+
+
+/**
+ * FPGA.
+ * Hardware register layout of the FPGA interface. The FPGA must accessed
+ * byte wise solely.
+ * @see EXCITE_CCI_DPR_MK2
+ */
+typedef struct excite_fpga {
+
+       /**
+        * Dual Ported RAM.
+        */
+       excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
+
+       /**
+        * Status.
+        */
+       excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
+
+#ifdef EXCITE_CCI_FPGA_MK2
+       /**
+        * RM9000 Interrupt.
+        * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
+        */
+       excite_cci_fpga_align_t rm9k_int;
+#else
+       /**
+        * MK2 Interrupt.
+        * Write access initiates interrupt at the ARM processor of the MK2.
+        */
+       excite_cci_fpga_align_t mk2_int;
+
+       excite_cci_fpga_align_t gap[0x1000-0x10f];
+
+       /**
+        * IRQ Source/Acknowledge.
+        */
+       excite_cci_fpga_align_t rm9k_irq_src;
+
+       /**
+        * IRQ Mask.
+        * Set bits enable the related interrupt.
+        */
+       excite_cci_fpga_align_t rm9k_irq_mask;
+#endif
+
+
+} excite_fpga;
+
+
+
+#endif /* ndef EXCITE_FPGA_H_INCLUDED */
diff --git a/arch/mips/basler/excite/excite_iodev.c b/arch/mips/basler/excite/excite_iodev.c
new file mode 100644 (file)
index 0000000..91121e5
--- /dev/null
@@ -0,0 +1,183 @@
+/*
+ *  Copyright (C) 2005 by Basler Vision Technologies AG
+ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/config.h>
+#include <linux/compiler.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/poll.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/miscdevice.h>
+
+#include "excite_iodev.h"
+
+
+
+static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
+static int __init iodev_probe(struct device *);
+static int __exit iodev_remove(struct device *);
+static int iodev_open(struct inode *, struct file *);
+static int iodev_release(struct inode *, struct file *);
+static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
+static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
+static irqreturn_t iodev_irqhdl(int, void *, struct pt_regs *);
+
+
+
+static const char iodev_name[] = "iodev";
+static unsigned int iodev_irq;
+static DECLARE_WAIT_QUEUE_HEAD(wq);
+
+
+
+static struct file_operations fops =
+{
+       .owner          = THIS_MODULE,
+       .open           = iodev_open,
+       .release        = iodev_release,
+       .read           = iodev_read,
+       .poll           = iodev_poll
+};
+
+static struct miscdevice miscdev =
+{
+       .minor          = MISC_DYNAMIC_MINOR,
+       .name           = iodev_name,
+       .fops           = &fops
+};
+
+static struct device_driver iodev_driver =
+{
+       .name           = (char *) iodev_name,
+       .bus            = &platform_bus_type,
+       .owner          = THIS_MODULE,
+       .probe          = iodev_probe,
+       .remove         = __exit_p(iodev_remove)
+};
+
+
+
+static const struct resource *
+iodev_get_resource(struct platform_device *pdv, const char *name,
+                    unsigned int type)
+{
+       char buf[80];
+       if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
+               return NULL;
+       return platform_get_resource_byname(pdv, type, buf);
+}
+
+
+
+/* No hotplugging on the platform bus - use __init */
+static int __init iodev_probe(struct device *dev)
+{
+       struct platform_device * const pdv = to_platform_device(dev);
+       const struct resource * const ri =
+               iodev_get_resource(pdv, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
+
+       if (unlikely(!ri))
+               return -ENXIO;
+
+       iodev_irq = ri->start;
+       return misc_register(&miscdev);
+}
+
+
+
+static int __exit iodev_remove(struct device *dev)
+{
+       return misc_deregister(&miscdev);
+}
+
+
+
+static int iodev_open(struct inode *i, struct file *f)
+{
+       return request_irq(iodev_irq, iodev_irqhdl, SA_INTERRUPT,
+                          iodev_name, &miscdev);
+}
+
+
+
+static int iodev_release(struct inode *i, struct file *f)
+{
+       free_irq(iodev_irq, &miscdev);
+       return 0;
+}
+
+
+
+
+static ssize_t
+iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
+{
+       ssize_t ret;
+       DEFINE_WAIT(w);
+
+       prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
+       if (!signal_pending(current))
+               schedule();
+       ret = signal_pending(current) ? -ERESTARTSYS : 0;
+       finish_wait(&wq, &w);
+       return ret;
+}
+
+
+static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
+{
+       poll_wait(f, &wq, p);
+       return POLLOUT | POLLWRNORM;
+}
+
+
+
+
+static irqreturn_t iodev_irqhdl(int irq, void *ctxt, struct pt_regs *regs)
+{
+       wake_up(&wq);
+       return IRQ_HANDLED;
+}
+
+
+
+static int __init iodev_init_module(void)
+{
+       return driver_register(&iodev_driver);
+}
+
+
+
+static void __exit iodev_cleanup_module(void)
+{
+       driver_unregister(&iodev_driver);
+}
+
+module_init(iodev_init_module);
+module_exit(iodev_cleanup_module);
+
+
+
+MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
+MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
+MODULE_VERSION("0.0");
+MODULE_LICENSE("GPL");
diff --git a/arch/mips/basler/excite/excite_iodev.h b/arch/mips/basler/excite/excite_iodev.h
new file mode 100644 (file)
index 0000000..cbfbb5d
--- /dev/null
@@ -0,0 +1,10 @@
+#ifndef __EXCITE_IODEV_H__
+#define __EXCITE_IODEV_H__
+
+/* Device name */
+#define IODEV_NAME             "iodev"
+
+/* Resource names */
+#define IODEV_RESOURCE_IRQ     "excite_iodev_irq"
+
+#endif /* __EXCITE_IODEV_H__ */
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
new file mode 100644 (file)
index 0000000..511ad87
--- /dev/null
@@ -0,0 +1,129 @@
+/*
+ *  Copyright (C) by Basler Vision Technologies AG
+ *  Author: Thomas Koeller <thomas.koeller@baslereb.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/rm9k-ocd.h>
+
+#include <excite.h>
+
+extern asmlinkage void excite_handle_int(void);
+
+/*
+ * Initialize the interrupt handler
+ */
+void __init arch_init_irq(void)
+{
+       mips_cpu_irq_init(0);
+       rm7k_cpu_irq_init(8);
+       rm9k_cpu_irq_init(12);
+
+#ifdef CONFIG_KGDB
+       excite_kgdb_init();
+#endif
+}
+
+asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+{
+       const u32
+               interrupts = read_c0_cause() >> 8,
+               mask = ((read_c0_status() >> 8) & 0x000000ff) |
+                      (read_c0_intcontrol() & 0x0000ff00),
+               pending = interrupts & mask;
+       u32 msgintflags, msgintmask, msgint;
+
+       /* process timer interrupt */
+       if (pending & (1 << TIMER_IRQ)) {
+               do_IRQ(TIMER_IRQ, regs);
+               return;
+       }
+
+       /* Process PCI interrupts */
+#if USB_IRQ < 10
+       msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
+       msgintmask  = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
+       msgint      = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
+       if ((pending & (1 << USB_IRQ)) && msgint) {
+#else
+       if (pending & (1 << USB_IRQ)) {
+#endif
+               do_IRQ(USB_IRQ, regs);
+               return;
+       }
+
+       /* Process TITAN interrupts */
+       msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
+       msgintmask  = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
+       msgint      = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
+       if ((pending & (1 << TITAN_IRQ)) && msgint) {
+               ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));