[ARM] 3388/1: ixp23xx: add core ixp23xx support
Lennert Buytenhek [Tue, 28 Mar 2006 20:18:54 +0000 (21:18 +0100)]
Patch from Lennert Buytenhek

This patch adds support for the Intel ixp23xx series of CPUs.  The
ixp23xx is an XSC3 based CPU with 512K of L2 cache, a 64bit 66MHz PCI
interface, two DDR RAM interfaces, QDR RAM interfaces, two gigabit
MACs, two 10/100 MACs, expansion bus, four microengines, a Media and
Switch Fabric unit almost identical to the one on the ixp2400, two
xscale (8250ish) UARTs and a bunch of other stuff.

This patch adds the core ixp23xx support code, and support for the
ADI Engineering Roadrunner, Intel IXDP2351, and IP Fabrics Double
Espresso platforms.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

25 files changed:
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/mach-ixp23xx/Kconfig [new file with mode: 0644]
arch/arm/mach-ixp23xx/Makefile [new file with mode: 0644]
arch/arm/mach-ixp23xx/Makefile.boot [new file with mode: 0644]
arch/arm/mach-ixp23xx/core.c [new file with mode: 0644]
arch/arm/mach-ixp23xx/espresso.c [new file with mode: 0644]
arch/arm/mach-ixp23xx/ixdp2351.c [new file with mode: 0644]
arch/arm/mach-ixp23xx/pci.c [new file with mode: 0644]
arch/arm/mach-ixp23xx/roadrunner.c [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/debug-macro.S [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/dma.h [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/entry-macro.S [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/hardware.h [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/io.h [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/irqs.h [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/ixdp2351.h [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/ixp23xx.h [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/memory.h [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/platform.h [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/system.h [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/time.h [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/timex.h [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/uncompress.h [new file with mode: 0644]
include/asm-arm/arch-ixp23xx/vmalloc.h [new file with mode: 0644]

index 0dd24eb..427c721 100644 (file)
@@ -148,6 +148,12 @@ config ARCH_IXP2000
        help
          Support for Intel's IXP2400/2800 (XScale) family of processors.
 
+config ARCH_IXP23XX
+       bool "IXP23XX-based"
+       select PCI
+       help
+         Support for Intel's IXP23xx (XScale) family of processors.
+
 config ARCH_L7200
        bool "LinkUp-L7200"
        select FIQ
@@ -269,6 +275,8 @@ source "arch/arm/mach-ixp4xx/Kconfig"
 
 source "arch/arm/mach-ixp2000/Kconfig"
 
+source "arch/arm/mach-ixp23xx/Kconfig"
+
 source "arch/arm/mach-pxa/Kconfig"
 
 source "arch/arm/mach-sa1100/Kconfig"
@@ -787,7 +795,8 @@ source "drivers/acorn/block/Kconfig"
 
 if PCMCIA || ARCH_CLPS7500 || ARCH_IOP3XX || ARCH_IXP4XX \
        || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \
-       || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE
+       || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE \
+       || ARCH_IXP23XX
 source "drivers/ide/Kconfig"
 endif
 
index 0f571d3..ce3e804 100644 (file)
@@ -98,6 +98,7 @@ endif
  machine-$(CONFIG_ARCH_IOP3XX)    := iop3xx
  machine-$(CONFIG_ARCH_IXP4XX)    := ixp4xx
  machine-$(CONFIG_ARCH_IXP2000)    := ixp2000
+ machine-$(CONFIG_ARCH_IXP23XX)    := ixp23xx
  machine-$(CONFIG_ARCH_OMAP1)     := omap1
  machine-$(CONFIG_ARCH_OMAP2)     := omap2
   incdir-$(CONFIG_ARCH_OMAP)      := omap
diff --git a/arch/arm/mach-ixp23xx/Kconfig b/arch/arm/mach-ixp23xx/Kconfig
new file mode 100644 (file)
index 0000000..982670e
--- /dev/null
@@ -0,0 +1,25 @@
+if ARCH_IXP23XX
+
+config ARCH_SUPPORTS_BIG_ENDIAN
+       bool
+       default y
+
+menu "Intel IXP23xx Implementation Options"
+
+comment "IXP23xx Platforms"
+
+config MACH_ESPRESSO
+       bool "Support IP Fabrics Double Espresso platform"
+       help
+
+config MACH_IXDP2351
+       bool "Support Intel IXDP2351 platform"
+       help
+
+config MACH_ROADRUNNER
+       bool "Support ADI RoadRunner platform"
+       help
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-ixp23xx/Makefile b/arch/arm/mach-ixp23xx/Makefile
new file mode 100644 (file)
index 0000000..288b371
--- /dev/null
@@ -0,0 +1,11 @@
+#
+# Makefile for the linux kernel.
+#
+obj-y                  := core.o pci.o
+obj-m                  :=
+obj-n                  :=
+obj-                   :=
+
+obj-$(CONFIG_MACH_ESPRESSO)    += espresso.o
+obj-$(CONFIG_MACH_IXDP2351)    += ixdp2351.o
+obj-$(CONFIG_MACH_ROADRUNNER)  += roadrunner.o
diff --git a/arch/arm/mach-ixp23xx/Makefile.boot b/arch/arm/mach-ixp23xx/Makefile.boot
new file mode 100644 (file)
index 0000000..d5561ad
--- /dev/null
@@ -0,0 +1,2 @@
+   zreladdr-y  := 0x00008000
+params_phys-y  := 0x00000100
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
new file mode 100644 (file)
index 0000000..092ee12
--- /dev/null
@@ -0,0 +1,431 @@
+/*
+ * arch/arm/mach-ixp23xx/core.c
+ *
+ * Core routines for IXP23xx chips
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2005 (c) MontaVista Software, Inc.
+ *
+ * Based on 2.4 code Copyright 2004 (c) Intel Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/bitops.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_core.h>
+#include <linux/device.h>
+#include <linux/mm.h>
+#include <linux/time.h>
+#include <linux/timex.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/tlbflush.h>
+#include <asm/pgtable.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/arch.h>
+
+
+/*************************************************************************
+ * Chip specific mappings shared by all IXP23xx systems
+ *************************************************************************/
+static struct map_desc ixp23xx_io_desc[] __initdata = {
+       { /* XSI-CPP CSRs */
+               .virtual        = IXP23XX_XSI2CPP_CSR_VIRT,
+               .pfn            = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS),
+               .length         = IXP23XX_XSI2CPP_CSR_SIZE,
+               .type           = MT_DEVICE,
+       }, { /* Expansion Bus Config */
+               .virtual        = IXP23XX_EXP_CFG_VIRT,
+               .pfn            = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS),
+               .length         = IXP23XX_EXP_CFG_SIZE,
+               .type           = MT_DEVICE,
+       }, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */
+               .virtual        = IXP23XX_PERIPHERAL_VIRT,
+               .pfn            = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS),
+               .length         = IXP23XX_PERIPHERAL_SIZE,
+               .type           = MT_DEVICE,
+       }, { /* CAP CSRs */
+               .virtual        = IXP23XX_CAP_CSR_VIRT,
+               .pfn            = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS),
+               .length         = IXP23XX_CAP_CSR_SIZE,
+               .type           = MT_DEVICE,
+       }, { /* MSF CSRs */
+               .virtual        = IXP23XX_MSF_CSR_VIRT,
+               .pfn            = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
+               .length         = IXP23XX_MSF_CSR_SIZE,
+               .type           = MT_DEVICE,
+       }, { /* PCI I/O Space */
+               .virtual        = IXP23XX_PCI_IO_VIRT,
+               .pfn            = __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
+               .length         = IXP23XX_PCI_IO_SIZE,
+               .type           = MT_DEVICE,
+       }, { /* PCI Config Space */
+               .virtual        = IXP23XX_PCI_CFG_VIRT,
+               .pfn            = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
+               .length         = IXP23XX_PCI_CFG_SIZE,
+               .type           = MT_DEVICE,
+       }, { /* PCI local CFG CSRs */
+               .virtual        = IXP23XX_PCI_CREG_VIRT,
+               .pfn            = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS),
+               .length         = IXP23XX_PCI_CREG_SIZE,
+               .type           = MT_DEVICE,
+       }, { /* PCI MEM Space */
+               .virtual        = IXP23XX_PCI_MEM_VIRT,
+               .pfn            = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS),
+               .length         = IXP23XX_PCI_MEM_SIZE,
+               .type           = MT_DEVICE,
+       }
+};
+
+void __init ixp23xx_map_io(void)
+{
+       iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
+}
+
+
+/***************************************************************************
+ * IXP23xx Interrupt Handling
+ ***************************************************************************/
+enum ixp23xx_irq_type {
+       IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE
+};
+
+static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
+
+static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
+{
+       int line = irq - IRQ_IXP23XX_GPIO6 + 6;
+       u32 int_style;
+       enum ixp23xx_irq_type irq_type;
+       volatile u32 *int_reg;
+
+       /*
+        * Only GPIOs 6-15 are wired to interrupts on IXP23xx
+        */
+       if (line < 6 || line > 15)
+               return -EINVAL;
+
+       switch (type) {
+       case IRQT_BOTHEDGE:
+               int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
+               irq_type = IXP23XX_IRQ_EDGE;
+               break;
+       case IRQT_RISING:
+               int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
+               irq_type = IXP23XX_IRQ_EDGE;
+               break;
+       case IRQT_FALLING:
+               int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
+               irq_type = IXP23XX_IRQ_EDGE;
+               break;
+       case IRQT_HIGH:
+               int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
+               irq_type = IXP23XX_IRQ_LEVEL;
+               break;
+       case IRQT_LOW:
+               int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
+               irq_type = IXP23XX_IRQ_LEVEL;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       ixp23xx_config_irq(irq, irq_type);
+
+       if (line >= 8) {        /* pins 8-15 */
+               line -= 8;
+               int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R;
+       } else {                /* pins 0-7 */
+               int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R;
+       }
+
+       /*
+        * Clear pending interrupts
+        */
+       *IXP23XX_GPIO_GPISR = (1 << line);
+
+       /* Clear the style for the appropriate pin */
+       *int_reg &= ~(IXP23XX_GPIO_STYLE_MASK <<
+                       (line * IXP23XX_GPIO_STYLE_SIZE));
+
+       /* Set the new style */
+       *int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE));
+
+       return 0;
+}
+
+static void ixp23xx_irq_mask(unsigned int irq)
+{
+       volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
+
+       *intr_reg &= ~(1 << (irq % 32));
+}
+
+static void ixp23xx_irq_ack(unsigned int irq)
+{
+       int line = irq - IRQ_IXP23XX_GPIO6 + 6;
+
+       if ((line < 6) || (line > 15))
+               return;
+
+       *IXP23XX_GPIO_GPISR = (1 << line);
+}
+
+/*
+ * Level triggered interrupts on GPIO lines can only be cleared when the
+ * interrupt condition disappears.
+ */
+static void ixp23xx_irq_level_unmask(unsigned int irq)
+{
+       volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
+
+       ixp23xx_irq_ack(irq);
+
+       *intr_reg |= (1 << (irq % 32));
+}
+
+static void ixp23xx_irq_edge_unmask(unsigned int irq)
+{
+       volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
+
+       *intr_reg |= (1 << (irq % 32));
+}
+
+static struct irqchip ixp23xx_irq_level_chip = {
+       .ack            = ixp23xx_irq_mask,
+       .mask           = ixp23xx_irq_mask,
+       .unmask         = ixp23xx_irq_level_unmask,
+       .set_type       = ixp23xx_irq_set_type
+};
+
+static struct irqchip ixp23xx_irq_edge_chip = {
+       .ack            = ixp23xx_irq_ack,
+       .mask           = ixp23xx_irq_mask,
+       .unmask         = ixp23xx_irq_edge_unmask,
+       .set_type       = ixp23xx_irq_set_type
+};
+
+static void ixp23xx_pci_irq_mask(unsigned int irq)
+{
+       *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
+}
+
+static void ixp23xx_pci_irq_unmask(unsigned int irq)
+{
+       *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
+}
+
+/*
+ * TODO: Should this just be done at ASM level?
+ */
+static void pci_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+       u32 pci_interrupt;
+       unsigned int irqno;
+       struct irqdesc *int_desc;
+
+       pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
+
+       desc->chip->ack(irq);
+
+       /* See which PCI_INTA, or PCI_INTB interrupted */
+       if (pci_interrupt & (1 << 26)) {
+               irqno = IRQ_IXP23XX_INTB;
+       } else if (pci_interrupt & (1 << 27)) {
+               irqno = IRQ_IXP23XX_INTA;
+       } else {
+               BUG();
+       }
+
+       int_desc = irq_desc + irqno;
+       int_desc->handle(irqno, int_desc, regs);
+
+       desc->chip->unmask(irq);
+}
+
+static struct irqchip ixp23xx_pci_irq_chip = {
+       .ack    = ixp23xx_pci_irq_mask,
+       .mask   = ixp23xx_pci_irq_mask,
+       .unmask = ixp23xx_pci_irq_unmask
+};
+
+static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
+{
+       switch (type) {
+       case IXP23XX_IRQ_LEVEL:
+               set_irq_chip(irq, &ixp23xx_irq_level_chip);
+               set_irq_handler(irq, do_level_IRQ);
+               break;
+       case IXP23XX_IRQ_EDGE:
+               set_irq_chip(irq, &ixp23xx_irq_edge_chip);
+               set_irq_handler(irq, do_edge_IRQ);
+               break;
+       }
+       set_irq_flags(irq, IRQF_VALID);
+}
+
+void __init ixp23xx_init_irq(void)
+{
+       int irq;
+
+       /* Route everything to IRQ */
+       *IXP23XX_INTR_SEL1 = 0x0;
+       *IXP23XX_INTR_SEL2 = 0x0;
+       *IXP23XX_INTR_SEL3 = 0x0;
+       *IXP23XX_INTR_SEL4 = 0x0;
+
+       /* Mask all sources */
+       *IXP23XX_INTR_EN1 = 0x0;
+       *IXP23XX_INTR_EN2 = 0x0;
+       *IXP23XX_INTR_EN3 = 0x0;
+       *IXP23XX_INTR_EN4 = 0x0;
+
+       /*
+        * Configure all IRQs for level-sensitive operation
+        */
+       for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
+               ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
+       }
+
+       for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
+               set_irq_chip(irq, &ixp23xx_pci_irq_chip);
+               set_irq_handler(irq, do_level_IRQ);
+               set_irq_flags(irq, IRQF_VALID);
+       }
+
+       set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
+}
+
+
+/*************************************************************************
+ * Timer-tick functions for IXP23xx
+ *************************************************************************/
+#define CLOCK_TICKS_PER_USEC   CLOCK_TICK_RATE / (USEC_PER_SEC)
+
+static unsigned long next_jiffy_time;
+
+static unsigned long
+ixp23xx_gettimeoffset(void)
+{
+       unsigned long elapsed;
+
+       elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH);
+
+       return elapsed / CLOCK_TICKS_PER_USEC;
+}
+
+static irqreturn_t
+ixp23xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+       /* Clear Pending Interrupt by writing '1' to it */
+       *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
+       while ((*IXP23XX_TIMER_CONT - next_jiffy_time) > LATCH) {
+               timer_tick(regs);
+               next_jiffy_time += LATCH;
+       }
+
+       return IRQ_HANDLED;
+}
+
+static struct irqaction ixp23xx_timer_irq = {
+       .name           = "IXP23xx Timer Tick",
+       .handler        = ixp23xx_timer_interrupt,
+       .flags          = SA_INTERRUPT | SA_TIMER,
+};
+
+void __init ixp23xx_init_timer(void)
+{
+       /* Clear Pending Interrupt by writing '1' to it */
+       *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
+
+       /* Setup the Timer counter value */
+       *IXP23XX_TIMER1_RELOAD =
+               (LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE;
+
+       *IXP23XX_TIMER_CONT = 0;
+       next_jiffy_time = LATCH;
+
+       /* Connect the interrupt handler and enable the interrupt */
+       setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq);
+}
+
+struct sys_timer ixp23xx_timer = {
+       .init           = ixp23xx_init_timer,
+       .offset         = ixp23xx_gettimeoffset,
+};
+
+
+/*************************************************************************
+ * IXP23xx Platform Initializaion
+ *************************************************************************/
+static struct resource ixp23xx_uart_resources[] = {
+       {
+               .start          = IXP23XX_UART1_PHYS,
+               .end            = IXP23XX_UART1_PHYS + 0x0fff,
+               .flags          = IORESOURCE_MEM
+       }, {
+               .start          = IXP23XX_UART2_PHYS,
+               .end            = IXP23XX_UART2_PHYS + 0x0fff,
+               .flags          = IORESOURCE_MEM
+       }
+};
+
+static struct plat_serial8250_port ixp23xx_uart_data[] = {
+       {
+               .mapbase        = IXP23XX_UART1_PHYS,
+               .membase        = (char *)(IXP23XX_UART1_VIRT + 3),
+               .irq            = IRQ_IXP23XX_UART1,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = IXP23XX_UART_XTAL,
+       }, {
+               .mapbase        = IXP23XX_UART2_PHYS,
+               .membase        = (char *)(IXP23XX_UART2_VIRT + 3),
+               .irq            = IRQ_IXP23XX_UART2,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = IXP23XX_UART_XTAL,
+       },
+       { },
+};
+
+static struct platform_device ixp23xx_uart = {
+       .name                   = "serial8250",
+       .id                     = 0,
+       .dev.platform_data      = ixp23xx_uart_data,
+       .num_resources          = 2,
+       .resource               = ixp23xx_uart_resources,
+};
+
+static struct platform_device *ixp23xx_devices[] __initdata = {
+       &ixp23xx_uart,
+};
+
+void __init ixp23xx_sys_init(void)
+{
+       platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
+}
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
new file mode 100644 (file)
index 0000000..2327c97
--- /dev/null
@@ -0,0 +1,69 @@
+/*
+ * arch/arm/mach-ixp23xx/espresso.c
+ *
+ * Double Espresso-specific routines
+ *
+ * Author: Lennert Buytenhek <buytenh@wantstofly.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/bitops.h>
+#include <linux/ioport.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_core.h>
+#include <linux/device.h>
+#include <linux/mm.h>
+#include <linux/pci.h>
+#include <linux/mtd/physmap.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/tlbflush.h>
+#include <asm/pgtable.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/pci.h>
+
+static void __init espresso_init(void)
+{
+       physmap_configure(0x90000000, 0x02000000, 2, NULL);
+
+       /*
+        * Mark flash as writeable.
+        */
+       IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
+       IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
+
+       ixp23xx_sys_init();
+}
+
+MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso")
+       /* Maintainer: Lennert Buytenhek */
+       .phys_io        = IXP23XX_PERIPHERAL_PHYS,
+       .io_pg_offst    = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
+       .map_io         = ixp23xx_map_io,
+       .init_irq       = ixp23xx_init_irq,
+       .timer          = &ixp23xx_timer,
+       .boot_params    = 0x00000100,
+       .init_machine   = espresso_init,
+MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
new file mode 100644 (file)
index 0000000..00146c3
--- /dev/null
@@ -0,0 +1,325 @@
+/*
+ * arch/arm/mach-ixp23xx/ixdp2351.c
+ *
+ * IXDP2351 board-specific routines
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2005 (c) MontaVista Software, Inc.
+ *
+ * Based on 2.4 code Copyright 2004 (c) Intel Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/bitops.h>
+#include <linux/ioport.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_core.h>
+#include <linux/device.h>
+#include <linux/mm.h>
+#include <linux/pci.h>
+#include <linux/mtd/physmap.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/tlbflush.h>
+#include <asm/pgtable.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/pci.h>
+
+/*
+ * IXDP2351 Interrupt Handling
+ */
+static void ixdp2351_inta_mask(unsigned int irq)
+{
+       *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(irq);
+}
+
+static void ixdp2351_inta_unmask(unsigned int irq)
+{
+       *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
+}
+
+static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+       u16 ex_interrupt =
+               *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
+       int i;
+
+       desc->chip->mask(irq);
+
+       for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
+               if (ex_interrupt & (1 << i)) {
+                       struct irqdesc *cpld_desc;
+                       int cpld_irq =
+                               IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
+                       cpld_desc = irq_desc + cpld_irq;
+                       cpld_desc->handle(cpld_irq, cpld_desc, regs);
+               }
+       }
+
+       desc->chip->unmask(irq);
+}
+
+static struct irqchip ixdp2351_inta_chip = {
+       .ack    = ixdp2351_inta_mask,
+       .mask   = ixdp2351_inta_mask,
+       .unmask = ixdp2351_inta_unmask
+};
+
+static void ixdp2351_intb_mask(unsigned int irq)
+{
+       *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(irq);
+}
+
+static void ixdp2351_intb_unmask(unsigned int irq)
+{
+       *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
+}
+
+static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+       u16 ex_interrupt =
+               *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
+       int i;
+
+       desc->chip->ack(irq);
+
+       for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
+               if (ex_interrupt & (1 << i)) {
+                       struct irqdesc *cpld_desc;
+                       int cpld_irq =
+                               IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
+                       cpld_desc = irq_desc + cpld_irq;
+                       cpld_desc->handle(cpld_irq, cpld_desc, regs);
+               }
+       }
+
+       desc->chip->unmask(irq);
+}
+
+static struct irqchip ixdp2351_intb_chip = {
+       .ack    = ixdp2351_intb_mask,
+       .mask   = ixdp2351_intb_mask,
+       .unmask = ixdp2351_intb_unmask
+};
+
+void ixdp2351_init_irq(void)
+{
+       int irq;
+
+       /* Mask all interrupts from CPLD, disable simulation */
+       *IXDP2351_CPLD_INTA_MASK_SET_REG = (u16) -1;
+       *IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1;
+       *IXDP2351_CPLD_INTA_SIM_REG = 0;
+       *IXDP2351_CPLD_INTB_SIM_REG = 0;
+
+       ixp23xx_init_irq();
+
+       for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE);
+            irq <
+            IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM);
+            irq++) {
+               if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
+                       set_irq_flags(irq, IRQF_VALID);
+                       set_irq_handler(irq, do_level_IRQ);
+                       set_irq_chip(irq, &ixdp2351_inta_chip);
+               }
+       }
+
+       for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE);
+            irq <
+            IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM);
+            irq++) {
+               if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
+                       set_irq_flags(irq, IRQF_VALID);
+                       set_irq_handler(irq, do_level_IRQ);
+                       set_irq_chip(irq, &ixdp2351_intb_chip);
+               }
+       }
+
+       set_irq_chained_handler(IRQ_IXP23XX_INTA, &ixdp2351_inta_handler);
+       set_irq_chained_handler(IRQ_IXP23XX_INTB, &ixdp2351_intb_handler);
+}
+
+/*
+ * IXDP2351 PCI
+ */
+
+/*
+ * This board does not do normal PCI IRQ routing, or any
+ * sort of swizzling, so we just need to check where on the
+ * bus the device is and figure out what CPLD pin it is
+ * being routed to.
+ */
+#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
+
+static int __init ixdp2351_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+       u8 bus = dev->bus->number;
+       u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
+       struct pci_bus *tmp_bus = dev->bus;
+
+       /* Primary bus, no interrupts here */
+       if (!bus)
+               return -1;
+
+       /* Lookup first leaf in bus tree */
+       while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL))
+               tmp_bus = tmp_bus->parent;
+
+       /* Select between known bridges */
+       switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
+               /* Device is located after first bridge */
+       case 0x0008:
+               if (tmp_bus == dev->bus) {
+                       /* Device is located directy after first bridge */
+                       switch (devpin) {
+                               /* Onboard 82546 */
+                       case DEVPIN(1, 1):      /* Onboard 82546 ch 0 */
+                               return IRQ_IXDP2351_INTA_82546;
+                       case DEVPIN(1, 2):      /* Onboard 82546 ch 1 */
+                               return IRQ_IXDP2351_INTB_82546;
+                               /* PMC SLOT */
+                       case DEVPIN(0, 1):      /* PMCP INTA# */
+                       case DEVPIN(2, 4):      /* PMCS INTD# */
+                               return IRQ_IXDP2351_SPCI_PMC_INTA;
+                       case DEVPIN(0, 2):      /* PMCP INTB# */
+                       case DEVPIN(2, 1):      /* PMCS INTA# */
+                               return IRQ_IXDP2351_SPCI_PMC_INTB;
+                       case DEVPIN(0, 3):      /* PMCP INTC# */
+                       case DEVPIN(2, 2):      /* PMCS INTB# */
+                               return IRQ_IXDP2351_SPCI_PMC_INTC;
+                       case DEVPIN(0, 4):      /* PMCP INTD# */
+                       case DEVPIN(2, 3):      /* PMCS INTC# */
+                               return IRQ_IXDP2351_SPCI_PMC_INTD;
+                       }
+               } else {
+                       /* Device is located indirectly after first bridge */
+                       /* Not supported now */
+                       return -1;
+               }
+               break;
+       case 0x0010:
+               if (tmp_bus == dev->bus) {
+                       /* Device is located directy after second bridge */
+                       /* Secondary bus of second bridge */
+                       switch (devpin) {
+                       case DEVPIN(0, 1):      /* DB#0 */
+                       case DEVPIN(0, 2):
+                       case DEVPIN(0, 3):
+                       case DEVPIN(0, 4):
+                               return IRQ_IXDP2351_SPCI_DB_0;
+                       case DEVPIN(1, 1):      /* DB#1 */
+                       case DEVPIN(1, 2):
+                       case DEVPIN(1, 3):
+                       case DEVPIN(1, 4):
+                               return IRQ_IXDP2351_SPCI_DB_1;
+                       case DEVPIN(2, 1):      /* FIC1 */
+                       case DEVPIN(2, 2):
+                       case DEVPIN(2, 3):
+                       case DEVPIN(2, 4):
+                       case DEVPIN(3, 1):      /* FIC2 */
+                       case DEVPIN(3, 2):
+                       case DEVPIN(3, 3):
+                       case DEVPIN(3, 4):
+                               return IRQ_IXDP2351_SPCI_FIC;
+                       }
+               } else {
+                       /* Device is located indirectly after second bridge */
+                       /* Not supported now */
+                       return -1;
+               }
+               break;
+       }
+
+       return -1;
+}
+
+struct hw_pci ixdp2351_pci __initdata = {
+       .nr_controllers = 1,
+       .preinit        = ixp23xx_pci_preinit,
+       .setup          = ixp23xx_pci_setup,
+       .scan           = ixp23xx_pci_scan_bus,
+       .map_irq        = ixdp2351_map_irq,
+};
+
+int __init ixdp2351_pci_init(void)
+{
+       if (machine_is_ixdp2351())
+               pci_common_init(&ixdp2351_pci);
+
+       return 0;
+}
+
+subsys_initcall(ixdp2351_pci_init);
+
+/*
+ * IXDP2351 Static Mapped I/O
+ */
+static struct map_desc ixdp2351_io_desc[] __initdata = {
+       {
+               .virtual        = IXDP2351_NP_VIRT_BASE,
+               .pfn            = __phys_to_pfn((u64)IXDP2351_NP_PHYS_BASE),
+               .length         = IXDP2351_NP_PHYS_SIZE,
+               .type           = MT_DEVICE
+       }, {
+               .virtual        = IXDP2351_BB_BASE_VIRT,
+               .pfn            = __phys_to_pfn((u64)IXDP2351_BB_BASE_PHYS),
+               .length         = IXDP2351_BB_SIZE,
+               .type           = MT_DEVICE
+       }
+};
+
+static void __init ixdp2351_map_io(void)
+{
+       ixp23xx_map_io();
+       iotable_init(ixdp2351_io_desc, ARRAY_SIZE(ixdp2351_io_desc));
+}
+
+static void __init ixdp2351_init(void)
+{
+       physmap_configure(0x90000000, 0x04000000, 1, NULL);
+
+       /*
+        * Mark flash as writeable
+        */
+       IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
+       IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
+       IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
+       IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
+
+       ixp23xx_sys_init();
+}
+
+MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
+       /* Maintainer: MontaVista Software, Inc. */
+       .phys_io        = IXP23XX_PERIPHERAL_PHYS,
+       .io_pg_offst    = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
+       .map_io         = ixdp2351_map_io,
+       .init_irq       = ixdp2351_init_irq,
+       .timer          = &ixp23xx_timer,
+       .boot_params    = 0x00000100,
+       .init_machine   = ixdp2351_init,
+MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
new file mode 100644 (file)
index 0000000..5330ad7
--- /dev/null
@@ -0,0 +1,275 @@
+/*
+ * arch/arm/mach-ixp23xx/pci.c
+ *
+ * PCI routines for IXP23XX based systems
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ *
+ * based on original code:
+ *
+ * Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Copyright 2002-2005 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/sizes.h>
+#include <asm/system.h>
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+
+extern int (*external_fault) (unsigned long, struct pt_regs *);
+
+static int pci_master_aborts = 0;
+
+#ifdef DEBUG
+#define DBG(x...)      printk(x)
+#else
+#define DBG(x...)
+#endif
+
+int clear_master_aborts(void);
+
+static u32
+*ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
+{
+       u32 *paddress;
+
+       /*
+        * Must be dword aligned
+        */
+       where &= ~3;
+
+       /*
+        * For top bus, generate type 0, else type 1
+        */
+       if (!bus_nr) {
+               if (PCI_SLOT(devfn) >= 8)
+                       return 0;
+
+               paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
+                                   | (1 << (PCI_SLOT(devfn) + 16))
+                                   | (PCI_FUNC(devfn) << 8) | where);
+       } else {
+               paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
+                                   | (bus_nr << 16)
+                                   | (PCI_SLOT(devfn) << 11)
+                                   | (PCI_FUNC(devfn) << 8) | where);
+       }
+
+       return paddress;
+}
+
+/*
+ * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
+ * 0 and 3 are not valid indexes...
+ */
+static u32 bytemask[] = {
+       /*0*/   0,
+       /*1*/   0xff,
+       /*2*/   0xffff,
+       /*3*/   0,
+       /*4*/   0xffffffff,
+};
+
+static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+                               int where, int size, u32 *value)
+{
+       u32 n;
+       u32 *addr;
+
+       n = where % 4;
+
+       DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
+               bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
+
+       addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
+       if (!addr)
+               return PCIBIOS_DEVICE_NOT_FOUND;
+
+       pci_master_aborts = 0;
+       *value = (*addr >> (8*n)) & bytemask[size];
+       if (pci_master_aborts) {
+                       pci_master_aborts = 0;
+                       *value = 0xffffffff;
+                       return PCIBIOS_DEVICE_NOT_FOUND;
+               }
+
+       return PCIBIOS_SUCCESSFUL;
+}
+
+/*
+ * We don't do error checking on the address for writes.
+ * It's assumed that the user checked for the device existing first
+ * by doing a read first.
+ */
+static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+                                       int where, int size, u32 value)
+{
+       u32 mask;
+       u32 *addr;
+       u32 temp;
+
+       mask = ~(bytemask[size] << ((where % 0x4) * 8));
+       addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
+       if (!addr)
+               return PCIBIOS_DEVICE_NOT_FOUND;
+       temp = (u32) (value) << ((where % 0x4) * 8);
+       *addr = (*addr & mask) | temp;
+
+       clear_master_aborts();
+
+       return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops ixp23xx_pci_ops = {
+       .read   = ixp23xx_pci_read_config,
+       .write  = ixp23xx_pci_write_config,
+};
+
+struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
+{
+       return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata);
+}
+
+int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
+{
+       volatile unsigned long temp;
+       unsigned long flags;
+
+       pci_master_aborts = 1;
+
+       local_irq_save(flags);
+       temp = *IXP23XX_PCI_CONTROL;
+
+       /*
+        * master abort and cmd tgt err
+        */
+       if (temp & ((1 << 8) | (1 << 5)))
+               *IXP23XX_PCI_CONTROL = temp;
+
+       temp = *IXP23XX_PCI_CMDSTAT;
+
+       if (temp & (1 << 29))
+               *IXP23XX_PCI_CMDSTAT = temp;
+       local_irq_restore(flags);
+
+       /*
+        * If it was an imprecise abort, then we need to correct the
+        * return address to be _after_ the instruction.
+        */
+       if (fsr & (1 << 10))
+               regs->ARM_pc += 4;
+
+       return 0;
+}
+
+int clear_master_aborts(void)
+{
+       volatile u32 temp;
+
+       temp = *IXP23XX_PCI_CONTROL;
+
+       /*
+        * master abort and cmd tgt err
+        */
+       if (temp & ((1 << 8) | (1 << 5)))
+               *IXP23XX_PCI_CONTROL = temp;
+
+       temp = *IXP23XX_PCI_CMDSTAT;
+
+       if (temp & (1 << 29))
+               *IXP23XX_PCI_CMDSTAT = temp;
+
+       return 0;
+}
+
+void __init ixp23xx_pci_preinit(void)
+{
+#ifdef __ARMEB__
+       *IXP23XX_PCI_CONTROL |= 0x20000;        /* set I/O swapping */
+#endif
+       /*
+        * ADDR_31 needs to be clear for PCI memory access to CPP memory
+        */
+       *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
+       *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
+
+       /*
+        * Select correct memory for PCI inbound transactions
+        */
+       if (ixp23xx_cpp_boot()) {
+               *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
+       } else {
+               *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
+       }
+
+       hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS,
+                       "PCI config cycle to non-existent device");
+
+       *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
+}
+
+/*
+ * Prevent PCI layer from seeing the inbound host-bridge resources
+ */
+static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
+{
+       int i;
+
+       dev->class &= 0xff;
+       dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
+       for (i = 0; i < PCI_NUM_RESOURCES; i++) {
+               dev->resource[i].start = 0;
+               dev->resource[i].end   = 0;
+               dev->resource[i].flags = 0;
+       }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
+
+/*
+ * IXP2300 systems often have large resource requirements, so we just
+ * use our own resource space.
+ */
+static struct resource ixp23xx_pci_mem_space = {
+       .start  = IXP23XX_PCI_MEM_START,
+       .end    = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
+       .flags  = IORESOURCE_MEM,
+       .name   = "PCI Mem Space"
+};
+
+static struct resource ixp23xx_pci_io_space = {
+       .start  = 0x00000100,
+       .end    = 0x01ffffff,
+       .flags  = IORESOURCE_IO,
+       .name   = "PCI I/O Space"
+};
+
+int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
+{
+       if (nr >= 1)
+               return 0;
+
+       sys->resource[0] = &ixp23xx_pci_io_space;
+       sys->resource[1] = &ixp23xx_pci_mem_space;
+       sys->resource[2] = NULL;
+
+       return 1;
+}
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
new file mode 100644 (file)
index 0000000..43c14e7
--- /dev/null
@@ -0,0 +1,164 @@
+/*
+ * arch/arm/mach-ixp23xx/roadrunner.c
+ *
+ * RoadRunner board-specific routines
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2005 (c) MontaVista Software, Inc.
+ *
+ * Based on 2.4 code Copyright 2005 (c) ADI Engineering Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/bitops.h>
+#include <linux/ioport.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_core.h>
+#include <linux/device.h>
+#include <linux/mm.h>
+#include <linux/pci.h>
+#include <linux/mtd/physmap.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/tlbflush.h>
+#include <asm/pgtable.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/pci.h>
+
+/*
+ * Interrupt mapping
+ */
+#define INTA           IRQ_ROADRUNNER_PCI_INTA
+#define INTB           IRQ_ROADRUNNER_PCI_INTB
+#define INTC           IRQ_ROADRUNNER_PCI_INTC
+#define INTD           IRQ_ROADRUNNER_PCI_INTD
+
+#define INTC_PIN       IXP23XX_GPIO_PIN_11
+#define INTD_PIN       IXP23XX_GPIO_PIN_12
+
+static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
+{
+       static int pci_card_slot_irq[] = {INTB, INTC, INTD, INTA};
+       static int pmc_card_slot_irq[] = {INTA, INTB, INTC, INTD};
+       static int usb_irq[] = {INTB, INTC, INTD, -1};
+       static int mini_pci_1_irq[] = {INTB, INTC, -1, -1};
+       static int mini_pci_2_irq[] = {INTC, INTD, -1, -1};
+
+       switch(dev->bus->number) {
+               case 0:
+                       switch(dev->devfn) {
+                       case 0x0: // PCI-PCI bridge
+                               break;
+                       case 0x8: // PCI Card Slot
+                               return pci_card_slot_irq[pin - 1];
+                       case 0x10: // PMC Slot
+                               return pmc_card_slot_irq[pin - 1];
+                       case 0x18: // PMC Slot Secondary Agent
+                               break;
+                       case 0x20: // IXP Processor
+                               break;
+                       default:
+                               return NO_IRQ;
+                       }
+                       break;
+
+               case 1:
+                       switch(dev->devfn) {
+                       case 0x0: // IDE Controller
+                               return (pin == 1) ? INTC : -1;
+                       case 0x8: // USB fun 0
+                       case 0x9: // USB fun 1
+                       case 0xa: // USB fun 2
+                               return usb_irq[pin - 1];
+                       case 0x10: // Mini PCI 1
+                               return mini_pci_1_irq[pin-1];
+                       case 0x18: // Mini PCI 2
+                               return mini_pci_2_irq[pin-1];
+                       case 0x20: // MEM slot
+                               return (pin == 1) ? INTA : -1;
+                       default:
+                               return NO_IRQ;
+                       }
+                       break;
+
+               default:
+                       return NO_IRQ;
+       }
+
+       return NO_IRQ;
+}
+
+static void roadrunner_pci_preinit(void)
+{
+       set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQT_LOW);
+       set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQT_LOW);
+
+       ixp23xx_pci_preinit();
+}
+
+static struct hw_pci roadrunner_pci __initdata = {
+       .nr_controllers = 1,
+       .preinit        = roadrunner_pci_preinit,
+       .setup          = ixp23xx_pci_setup,
+       .scan           = ixp23xx_pci_scan_bus,
+       .map_irq        = roadrunner_map_irq,
+};
+
+static int __init roadrunner_pci_init(void)
+{
+       if (machine_is_roadrunner())
+               pci_common_init(&roadrunner_pci);
+
+       return 0;
+};
+
+subsys_initcall(roadrunner_pci_init);
+
+static void __init roadrunner_init(void)
+{
+       physmap_configure(0x90000000, 0x04000000, 2, NULL);
+
+       /*
+        * Mark flash as writeable
+        */
+       IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
+       IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
+       IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
+       IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
+
+       ixp23xx_sys_init();
+}
+
+MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform")
+       /* Maintainer: Deepak Saxena */
+       .phys_io        = IXP23XX_PERIPHERAL_PHYS,
+       .io_pg_offst    = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
+       .map_io         = ixp23xx_map_io,
+       .init_irq       = ixp23xx_init_irq,
+       .timer          = &ixp23xx_timer,
+       .boot_params    = 0x00000100,
+       .init_machine   = roadrunner_init,
+MACHINE_END
diff --git a/include/asm-arm/arch-ixp23xx/debug-macro.S b/include/asm-arm/arch-ixp23xx/debug-macro.S
new file mode 100644 (file)
index 0000000..eb99fd6
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * include/asm-arm/arch-ixp23xx/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/arch/ixp23xx.h>
+
+               .macro  addruart,rx
+               mrc     p15, 0, \rx, c1, c0
+               tst     \rx, #1                         @ mmu enabled?
+               ldreq   \rx, =IXP23XX_PERIPHERAL_PHYS   @ physical
+               ldrne   \rx, =IXP23XX_PERIPHERAL_VIRT   @ virtual
+               .endm
+
+#define UART_SHIFT     2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-ixp23xx/dma.h b/include/asm-arm/arch-ixp23xx/dma.h
new file mode 100644 (file)
index 0000000..2f4335e
--- /dev/null
@@ -0,0 +1,3 @@
+/*
+ * include/asm-arm/arch-ixp23xx/dma.h
+ */
diff --git a/include/asm-arm/arch-ixp23xx/entry-macro.S b/include/asm-arm/arch-ixp23xx/entry-macro.S
new file mode 100644 (file)
index 0000000..0ef4e60
--- /dev/null
@@ -0,0 +1,31 @@
+/*
+ * include/asm-arm/arch-ixp23xx/entry-macro.S
+ */
+
+               .macro  disable_fiq
+               .endm
+
+               .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+               ldr     \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
+               ldr     \irqnr, [\irqnr]        @ get interrupt number
+               cmp     \irqnr, #0x0            @ suprious interrupt ?
+               movne   \irqnr, \irqnr, lsr #2  @ skip unwanted low order bits
+               subne   \irqnr, \irqnr, #1      @ convert to 0 based
+
+#if 0
+               cmp     \irqnr, #IRQ_IXP23XX_PCI_INT_RPH
+               bne     1001f
+               mov     \irqnr, #IRQ_IXP23XX_INTA
+
+               ldr     \irqnr, =0xf5000030
+
+               mov     \tmp, #(1<<26)
+               tst     \irqnr, \tmp
+               movne   \irqnr, #IRQ_IXP23XX_INTB
+
+               mov     \tmp, #(1<<27)
+               tst     \irqnr, \tmp
+               movne   \irqnr, #IRQ_IXP23XX_INTA
+1001:
+#endif
+               .endm
diff --git a/include/asm-arm/arch-ixp23xx/hardware.h b/include/asm-arm/arch-ixp23xx/hardware.h
new file mode 100644 (file)
index 0000000..c0010d2
--- /dev/null
@@ -0,0 +1,37 @@
+/*
+ * include/asm-arm/arch-ixp23xx/hardware.h
+ *
+ * Copyright (C) 2002-2004 Intel Corporation.
+ * Copyricht (C) 2005 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Hardware definitions for IXP23XX based systems
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* PCI IO info */
+#define PCIO_BASE              IXP23XX_PCI_IO_VIRT
+#define PCIBIOS_MIN_IO         0x00000000
+#define PCIBIOS_MIN_MEM                0xe0000000
+
+#include "ixp23xx.h"
+
+#define pcibios_assign_all_busses()    0
+
+/*
+ * Platform helper functions
+ */
+#include "platform.h"
+
+/*
+ * Platform-specific headers
+ */
+#include "ixdp2351.h"
+
+
+#endif
diff --git a/include/asm-arm/arch-ixp23xx/io.h b/include/asm-arm/arch-ixp23xx/io.h
new file mode 100644 (file)
index 0000000..18415a8
--- /dev/null
@@ -0,0 +1,54 @@
+/*
+ * include/asm-arm/arch-ixp23xx/io.h
+ *
+ * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2003-2005 Intel Corp.
+ * Copyright (C) 2005 MontaVista Software, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(p)                ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
+#define __mem_pci(a)   (a)
+
+#include <linux/kernel.h>      /* For BUG */
+
+static inline void __iomem *
+ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned long flags)
+{
+       if (addr >= IXP23XX_PCI_MEM_START &&
+               addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) {
+               if (addr + size > IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE)
+                       return NULL;
+
+               return (void __iomem *)
+                       ((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT);
+       }
+
+       return __ioremap(addr, size, flags);
+}
+
+static inline void
+ixp23xx_iounmap(void __iomem *addr)
+{
+       if ((((u32)addr) >= IXP23XX_PCI_MEM_VIRT) &&
+           (((u32)addr) < IXP23XX_PCI_MEM_VIRT + IXP23XX_PCI_MEM_SIZE))
+               return;
+
+       __iounmap(addr);
+}
+
+#define __arch_ioremap(a,s,f)  ixp23xx_ioremap(a,s,f)
+#define __arch_iounmap(a)      ixp23xx_iounmap(a)
+
+
+#endif
diff --git a/include/asm-arm/arch-ixp23xx/irqs.h b/include/asm-arm/arch-ixp23xx/irqs.h
new file mode 100644 (file)
index 0000000..e696395
--- /dev/null
@@ -0,0 +1,223 @@
+/*
+ * include/asm-arm/arch-ixp23xx/irqs.h
+ *
+ * IRQ definitions for IXP23XX based systems
+ *
+ * Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ *
+ * Copyright (C) 2003-2004 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#define NR_IXP23XX_IRQS                        IRQ_IXP23XX_INTB+1
+#define IRQ_IXP23XX_EXTIRQS            NR_IXP23XX_IRQS
+
+
+#define IRQ_IXP23XX_DBG0               0       /* Debug/Execution/MBox */
+#define IRQ_IXP23XX_DBG1               1       /* Debug/Execution/MBox */
+#define IRQ_IXP23XX_NPE_TRG            2       /* npe_trigger */
+#define IRQ_IXP23XX_TIMER1             3       /* Timer[0] */
+#define IRQ_IXP23XX_TIMER2             4       /* Timer[1] */
+#define IRQ_IXP23XX_TIMESTAMP          5       /* Timer[2], Time-stamp */
+#define IRQ_IXP23XX_WDOG               6       /* Time[3], Watchdog Timer */
+#define IRQ_IXP23XX_PCI_DBELL          7       /* PCI Doorbell */
+#define IRQ_IXP23XX_PCI_DMA1           8       /* PCI DMA Channel 1 */
+#define IRQ_IXP23XX_PCI_DMA2           9       /* PCI DMA Channel 2 */
+#define IRQ_IXP23XX_PCI_DMA3           10      /* PCI DMA Channel 3 */
+#define IRQ_IXP23XX_PCI_INT_RPH                11      /* pcxg_pci_int_rph */
+#define IRQ_IXP23XX_CPP_PMU            12      /* xpxg_pm_int_rpl */
+#define IRQ_IXP23XX_SWINT0             13      /* S/W Interrupt0 */
+#define IRQ_IXP23XX_SWINT1             14      /* S/W Interrupt1 */
+#define IRQ_IXP23XX_UART2              15      /* UART1 Interrupt */
+#define IRQ_IXP23XX_UART1              16      /* UART0 Interrupt */
+#define IRQ_IXP23XX_XSI_PMU_ROLLOVER   17      /* AHB Performance M. Unit counter rollover */
+#define IRQ_IXP23XX_XSI_AHB_PM0                18      /* intr_pm_o */
+#define IRQ_IXP23XX_XSI_AHB_ECE0       19      /* intr_ece_o */
+#define IRQ_IXP23XX_XSI_AHB_GASKET     20      /* gas_intr_o */
+#define IRQ_IXP23XX_XSI_CPP            21      /* xsi2cpp_int */
+#define IRQ_IXP23XX_CPP_XSI            22      /* cpp2xsi_int */
+#define IRQ_IXP23XX_ME_ATTN0           23      /* ME_ATTN */
+#define IRQ_IXP23XX_ME_ATTN1           24      /* ME_ATTN */
+#define IRQ_IXP23XX_ME_ATTN2           25      /* ME_ATTN */
+#define IRQ_IXP23XX_ME_ATTN3           26      /* ME_ATTN */
+#define IRQ_IXP23XX_PCI_ERR_RPH                27      /* PCXG_PCI_ERR_RPH */
+#define IRQ_IXP23XX_D0XG_ECC_CORR      28      /* D0XG_DRAM_ECC_CORR */
+#define IRQ_IXP23XX_D0XG_ECC_UNCORR    29      /* D0XG_DRAM_ECC_UNCORR */
+#define IRQ_IXP23XX_SRAM_ERR1          30      /* SRAM1_ERR */
+#define IRQ_IXP23XX_SRAM_ERR0          31      /* SRAM0_ERR */
+#define IRQ_IXP23XX_MEDIA_ERR          32      /* MEDIA_ERR */
+#define IRQ_IXP23XX_STH_DRAM_ECC_MAJ   33      /* STH_DRAM0_ECC_MAJ */
+#define IRQ_IXP23XX_GPIO6              34      /* GPIO0 interrupts */
+#define IRQ_IXP23XX_GPIO7              35      /* GPIO1 interrupts */
+#define IRQ_IXP23XX_GPIO8              36      /* GPIO2 interrupts */
+#define IRQ_IXP23XX_GPIO9              37      /* GPIO3 interrupts */
+#define IRQ_IXP23XX_GPIO10             38      /* GPIO4 interrupts */
+#define IRQ_IXP23XX_GPIO11             39      /* GPIO5 interrupts */
+#define IRQ_IXP23XX_GPIO12             40      /* GPIO6 interrupts */
+#define IRQ_IXP23XX_GPIO13             41      /* GPIO7 interrupts */
+#define IRQ_IXP23XX_GPIO14             42      /* GPIO8 interrupts */
+#define IRQ_IXP23XX_GPIO15             43      /* GPIO9 interrupts */
+#define IRQ_IXP23XX_SHAC_RING0         44      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING1         45      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING2         46      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING3         47      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING4         48      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING5         49      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING6         50      /* SHAC RING Full */
+#define IRQ_IXP23XX_SHAC_RING7         51      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING8         52      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING9         53      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING10                54      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING11                55      /* SHAC Ring Full */
+#define IRQ_IXP23XX_ME_THREAD_A0_ME0   56      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A1_ME0   57      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A2_ME0   58      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A3_ME0   59      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A4_ME0   60      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A5_ME0   61      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A6_ME0   62      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A7_ME0   63      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A8_ME1   64      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A9_ME1   65      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A10_ME1  66      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A11_ME1  67      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A12_ME1  68      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A13_ME1  69      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A14_ME1  70      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A15_ME1  71      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A16_ME2  72      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A17_ME2  73      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A18_ME2  74      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A19_ME2  75      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A20_ME2  76      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A21_ME2  77      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A22_ME2  78      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A23_ME2  79      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A24_ME3  80      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A25_ME3  81      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A26_ME3  82      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A27_ME3  83      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A28_ME3  84      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A29_ME3  85      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A30_ME3  86      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A31_ME3  87      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_B0_ME0   88      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B1_ME0   89      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B2_ME0   90      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B3_ME0   91      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B4_ME0   92      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B5_ME0   93      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B6_ME0   94      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B7_ME0   95      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B8_ME1   96      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B9_ME1   97      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B10_ME1  98      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B11_ME1  99      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B12_ME1  100     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B13_ME1  101     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B14_ME1  102     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B15_ME1  103     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B16_ME2  104     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B17_ME2  105     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B18_ME2  106     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B19_ME2  107     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B20_ME2  108     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B21_ME2  109     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B22_ME2  110     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B23_ME2  111     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B24_ME3  112     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B25_ME3  113     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B26_ME3  114     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B27_ME3  115     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B28_ME3  116     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B29_ME3  117     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B30_ME3  118     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B31_ME3  119     /* ME_THREAD_B */
+
+#define NUM_IXP23XX_RAW_IRQS           120
+
+#define IRQ_IXP23XX_INTA               120     /* Indirect pcxg_pci_int_rph */
+#define IRQ_IXP23XX_INTB               121     /* Indirect pcxg_pci_int_rph */
+
+#define NR_IXP23XX_IRQ                 (IRQ_IXP23XX_INTB + 1)
+
+/*
+ * We default to 32 per-board IRQs. Increase this number if you need
+ * more, but keep it realistic.
+ */
+#define NR_IXP23XX_MACH_IRQS           32
+
+#define NR_IRQS                                NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS
+
+#define IXP23XX_MACH_IRQ(irq)          (NR_IXP23XX_IRQ + (irq))
+
+
+/*
+ * IXDP2351-specific interrupts
+ */
+
+/*
+ * External PCI interrupts signaled through INTB
+ *
+ */
+#define IXDP2351_INTB_IRQ_BASE                 0
+#define IRQ_IXDP2351_INTA_82546                IXP23XX_MACH_IRQ(0)
+#define IRQ_IXDP2351_INTB_82546                IXP23XX_MACH_IRQ(1)
+#define IRQ_IXDP2351_SPCI_DB_0         IXP23XX_MACH_IRQ(2)
+#define IRQ_IXDP2351_SPCI_DB_1         IXP23XX_MACH_IRQ(3)
+#define IRQ_IXDP2351_SPCI_PMC_INTA     IXP23XX_MACH_IRQ(4)
+#define IRQ_IXDP2351_SPCI_PMC_INTB     IXP23XX_MACH_IRQ(5)
+#define IRQ_IXDP2351_SPCI_PMC_INTC     IXP23XX_MACH_IRQ(6)
+#define IRQ_IXDP2351_SPCI_PMC_INTD     IXP23XX_MACH_IRQ(7)
+#define IRQ_IXDP2351_SPCI_FIC          IXP23XX_MACH_IRQ(8)
+
+#define IXDP2351_INTB_IRQ_BIT(irq)     (irq - IXP23XX_MACH_IRQ(0))
+#define IXDP2351_INTB_IRQ_MASK(irq)    (1 << IXDP2351_INTB_IRQ_BIT(irq))
+#define IXDP2351_INTB_IRQ_VALID                0x01FF
+#define IXDP2351_INTB_IRQ_NUM          16
+
+/*
+ * Other external interrupts signaled through INTA
+ */
+#define IXDP2351_INTA_IRQ_BASE                 16
+#define IRQ_IXDP2351_IPMI_FROM         IXP23XX_MACH_IRQ(16)
+#define IRQ_IXDP2351_125US             IXP23XX_MACH_IRQ(17)
+#define IRQ_IXDP2351_DB_0_ADD          IXP23XX_MACH_IRQ(18)
+#define IRQ_IXDP2351_DB_1_ADD          IXP23XX_MACH_IRQ(19)
+#define IRQ_IXDP2351_DEBUG1            IXP23XX_MACH_IRQ(20)
+#define IRQ_IXDP2351_ADD_UART          IXP23XX_MACH_IRQ(21)
+#define IRQ_IXDP2351_FIC_ADD           IXP23XX_MACH_IRQ(24)
+#define IRQ_IXDP2351_CS8900            IXP23XX_MACH_IRQ(25)
+#define IRQ_IXDP2351_BBSRAM            IXP23XX_MACH_IRQ(26)
+#define IRQ_IXDP2351_CONFIG_MEDIA      IXP23XX_MACH_IRQ(27)
+#define IRQ_IXDP2351_CLOCK_REF         IXP23XX_MACH_IRQ(28)
+#define IRQ_IXDP2351_A10_NP            IXP23XX_MACH_IRQ(29)
+#define IRQ_IXDP2351_A11_NP            IXP23XX_MACH_IRQ(30)
+#define IRQ_IXDP2351_DEBUG_NP          IXP23XX_MACH_IRQ(31)
+
+#define IXDP2351_INTA_IRQ_BIT(irq)     (irq - IXP23XX_MACH_IRQ(16))
+#define IXDP2351_INTA_IRQ_MASK(irq)    (1 << IXDP2351_INTA_IRQ_BIT(irq))
+#define IXDP2351_INTA_IRQ_VALID        0xFF3F
+#define IXDP2351_INTA_IRQ_NUM          16
+
+
+/*
+ * ADI RoadRunner IRQs
+ */
+#define IRQ_ROADRUNNER_PCI_INTA        IRQ_IXP23XX_INTA
+#define IRQ_ROADRUNNER_PCI_INTB        IRQ_IXP23XX_INTB
+#define IRQ_ROADRUNNER_PCI_INTC        IRQ_IXP23XX_GPIO11
+#define IRQ_ROADRUNNER_PCI_INTD        IRQ_IXP23XX_GPIO12
+
+/*
+ * Put new board definitions here
+ */
+
+
+#endif
diff --git a/include/asm-arm/arch-ixp23xx/ixdp2351.h b/include/asm-arm/arch-ixp23xx/ixdp2351.h
new file mode 100644 (file)
index 0000000..4a24f8f
--- /dev/null
@@ -0,0 +1,89 @@
+/*
+ * include/asm-arm/arch-ixp23xx/ixdp2351.h
+ *
+ * Register and other defines for IXDP2351
+ *
+ * Copyright (c) 2002-2004 Intel Corp.
+ * Copytight (c) 2005 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_ARCH_IXDP2351_H
+#define __ASM_ARCH_IXDP2351_H
+
+/*
+ * NP module memory map
+ */
+#define IXDP2351_NP_PHYS_BASE          (IXP23XX_EXP_BUS_CS4_BASE)
+#define IXDP2351_NP_PHYS_SIZE          0x00100000
+#define IXDP2351_NP_VIRT_BASE          0xeff00000
+
+#define IXDP2351_VIRT_CS8900_BASE      (IXDP2351_NP_VIRT_BASE)
+#define IXDP2351_VIRT_CS8900_END       (IXDP2351_VIRT_CS8900_BASE + 16)
+
+#define IXDP2351_VIRT_NP_CPLD_BASE     (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000)
+
+#define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg))
+
+#define IXDP2351_NP_CPLD_RESET1_REG    IXDP2351_NP_CPLD_REG(0x00)
+#define IXDP2351_NP_CPLD_LED_REG       IXDP2351_NP_CPLD_REG(0x02)
+#define IXDP2351_NP_CPLD_VERSION_REG   IXDP2351_NP_CPLD_REG(0x04)
+
+/*
+ * Base board module memory map
+ */
+
+#define IXDP2351_BB_BASE_PHYS          (IXP23XX_EXP_BUS_CS5_BASE)
+#define IXDP2351_BB_SIZE               0x01000000
+#define IXDP2351_BB_BASE_VIRT          (0xee000000)
+
+#define IXDP2351_BB_AREA_BASE(offset)  (IXDP2351_BB_BASE_VIRT + offset)
+
+#define IXDP2351_VIRT_NVRAM_BASE       IXDP2351_BB_AREA_BASE(0x0)
+#define IXDP2351_NVRAM_SIZE            (0x20000)
+
+#define IXDP2351_VIRT_MB_IXF1104_BASE  IXDP3251_BB_AREA_BASE(0x00020000)
+#define IXDP2351_VIRT_ADD_UART_BASE    IXDP2351_BB_AREA_BASE(0x000240C0)
+#define IXDP2351_VIRT_FIC_BASE         IXDP2351_BB_AREA_BASE(0x00200000)
+#define IXDP2351_VIRT_DB0_BASE         IXDP2351_BB_AREA_BASE(0x00400000)
+#define IXDP2351_VIRT_DB1_BASE         IXDP2351_BB_AREA_BASE(0x00600000)
+#define IXDP2351_VIRT_CPLD_BASE                IXDP2351_BB_AREA_BASE(0x00024000)
+
+/*
+ * On board CPLD registers
+ */
+#define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg))
+
+#define IXDP2351_CPLD_RESET0_REG       IXDP2351_CPLD_BB_REG(0x00)
+#define IXDP2351_CPLD_RESET1_REG       IXDP2351_CPLD_BB_REG(0x04)
+
+#define IXDP2351_CPLD_RESET1_MAGIC     0x55AA
+#define IXDP2351_CPLD_RESET1_ENABLE    0x8000
+
+#define IXDP2351_CPLD_FPGA_CONFIG_REG  IXDP2351_CPLD_BB_REG(0x08)
+#define IXDP2351_CPLD_INTB_MASK_SET_REG        IXDP2351_CPLD_BB_REG(0x10)
+#define IXDP2351_CPLD_INTA_MASK_SET_REG        IXDP2351_CPLD_BB_REG(0x14)
+#define IXDP2351_CPLD_INTB_STAT_REG    IXDP2351_CPLD_BB_REG(0x18)
+#define IXDP2351_CPLD_INTA_STAT_REG    IXDP2351_CPLD_BB_REG(0x1C)
+#define IXDP2351_CPLD_INTB_RAW_REG     IXDP2351_CPLD_BB_REG(0x20)      /* read */
+#define IXDP2351_CPLD_INTA_RAW_REG     IXDP2351_CPLD_BB_REG(0x24)      /* read */
+#define IXDP2351_CPLD_INTB_MASK_CLR_REG        IXDP2351_CPLD_INTB_RAW_REG      /* write */
+#define IXDP2351_CPLD_INTA_MASK_CLR_REG        IXDP2351_CPLD_INTA_RAW_REG      /* write */
+#define IXDP2351_CPLD_INTB_SIM_REG     IXDP2351_CPLD_BB_REG(0x28)
+#define IXDP2351_CPLD_INTA_SIM_REG     IXDP2351_CPLD_BB_REG(0x2C)
+       /* Interrupt bits are defined in irqs.h */
+#define IXDP2351_CPLD_BB_GBE0_REG      IXDP2351_CPLD_BB_REG(0x30)
+#define IXDP2351_CPLD_BB_GBE1_REG      IXDP2351_CPLD_BB_REG(0x34)
+
+/* #define IXDP2351_CPLD_BB_MISC_REG   IXDP2351_CPLD_REG(0x1C) */
+/* #define IXDP2351_CPLD_BB_MISC_REV_MASK      0xFF            */
+/* #define IXDP2351_CPLD_BB_GDXCS0_REG IXDP2351_CPLD_REG(0x24) */
+/* #define IXDP2351_CPLD_BB_GDXCS1_REG IXDP2351_CPLD_REG(0x28) */
+/* #define IXDP2351_CPLD_BB_CLOCK_REG  IXDP2351_CPLD_REG(0x04) */
+
+
+#endif
diff --git a/include/asm-arm/arch-ixp23xx/ixp23xx.h b/include/asm-arm/arch-ixp23xx/ixp23xx.h
new file mode 100644 (file)
index 0000000..e49e1ca
--- /dev/null
@@ -0,0 +1,306 @@
+/*
+ * include/asm-arm/arch-ixp23xx/ixp23xx.h
+ *
+ * Register definitions for IXP23XX
+ *
+ * Copyright (C) 2003-2005 Intel Corporation.
+ * Copyright (C) 2005 MontaVista Software, Inc.
+ *
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_IXP23XX_H
+#define __ASM_ARCH_IXP23XX_H
+
+/*
+ * IXP2300 linux memory map:
+ *
+ * virt                phys            size
+ * fffd0000    a0000000        64K             XSI2CPP_CSR
+ * fffc0000    c4000000        4K              EXP_CFG
+ * fff00000    c8000000        64K             PERIPHERAL
+ * fe000000    1c0000000       16M             CAP_CSR
+ * fd000000    1c8000000       16M             MSF_CSR
+ * fb000000                    16M             ---
+ * fa000000    1d8000000       32M             PCI_IO
+ * f8000000    1da000000       32M             PCI_CFG
+ * f6000000    1de000000       32M             PCI_CREG
+ * f4000000                    32M             ---
+ * f0000000    1e0000000       64M             PCI_MEM
+ * e[c-f]000000                                        per-platform mappings
+ */
+
+
+/****************************************************************************
+ * Static mappings.
+ ****************************************************************************/
+#define IXP23XX_XSI2CPP_CSR_PHYS       0xa0000000
+#define IXP23XX_XSI2CPP_CSR_VIRT       0xfffd0000
+#define IXP23XX_XSI2CPP_CSR_SIZE       0x00010000
+
+#define IXP23XX_EXP_CFG_PHYS           0xc4000000
+#define IXP23XX_EXP_CFG_VIRT           0xfffc0000
+#define IXP23XX_EXP_CFG_SIZE           0x00001000
+
+#define IXP23XX_PERIPHERAL_PHYS                0xc8000000
+#define IXP23XX_PERIPHERAL_VIRT                0xfff00000
+#define IXP23XX_PERIPHERAL_SIZE                0x00010000
+
+#define IXP23XX_CAP_CSR_PHYS           0x1c0000000ULL
+#define IXP23XX_CAP_CSR_VIRT           0xfe000000
+#define IXP23XX_CAP_CSR_SIZE           0x01000000
+
+#define IXP23XX_MSF_CSR_PHYS           0x1c8000000ULL
+#define IXP23XX_MSF_CSR_VIRT           0xfd000000
+#define IXP23XX_MSF_CSR_SIZE           0x01000000
+
+#define IXP23XX_PCI_IO_PHYS            0x1d8000000ULL
+#define IXP23XX_PCI_IO_VIRT            0xfa000000
+#define IXP23XX_PCI_IO_SIZE            0x02000000
+
+#define IXP23XX_PCI_CFG_PHYS           0x1da000000ULL
+#define IXP23XX_PCI_CFG_VIRT           0xf8000000
+#define IXP23XX_PCI_CFG_SIZE           0x02000000
+#define IXP23XX_PCI_CFG0_VIRT          IXP23XX_PCI_CFG_VIRT
+#define IXP23XX_PCI_CFG1_VIRT          (IXP23XX_PCI_CFG_VIRT + 0x01000000)
+
+#define IXP23XX_PCI_CREG_PHYS          0x1de000000ULL
+#define IXP23XX_PCI_CREG_VIRT          0xf6000000
+#define IXP23XX_PCI_CREG_SIZE          0x02000000
+#define IXP23XX_PCI_CSR_VIRT           (IXP23XX_PCI_CREG_VIRT + 0x01000000)
+
+#define IXP23XX_PCI_MEM_START          0xe0000000
+#define IXP23XX_PCI_MEM_PHYS           0x1e0000000ULL
+#define IXP23XX_PCI_MEM_VIRT           0xf0000000
+#define IXP23XX_PCI_MEM_SIZE           0x04000000
+
+
+/****************************************************************************
+ * XSI2CPP CSRs.
+ ****************************************************************************/
+#define IXP23XX_XSI2CPP_REG(x)         ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x)))
+#define IXP23XX_CPP2XSI_CURR_XFER_REG3 IXP23XX_XSI2CPP_REG(0xf8)
+#define IXP23XX_CPP2XSI_ADDR_31                (1 << 19)
+#define IXP23XX_CPP2XSI_PSH_OFF                (1 << 20)
+#define IXP23XX_CPP2XSI_COH_OFF                (1 << 21)
+
+
+/****************************************************************************
+ * Expansion Bus Config.
+ ****************************************************************************/
+#define IXP23XX_EXP_CFG_REG(x)         ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x)))
+#define IXP23XX_EXP_CS0                        IXP23XX_EXP_CFG_REG(0x00)
+#define IXP23XX_EXP_CS1                        IXP23XX_EXP_CFG_REG(0x04)
+#define IXP23XX_EXP_CS2                        IXP23XX_EXP_CFG_REG(0x08)
+#define IXP23XX_EXP_CS3                        IXP23XX_EXP_CFG_REG(0x0c)
+#define IXP23XX_EXP_CS4                        IXP23XX_EXP_CFG_REG(0x10)
+#define IXP23XX_EXP_CS5                        IXP23XX_EXP_CFG_REG(0x14)
+#define IXP23XX_EXP_CS6                        IXP23XX_EXP_CFG_REG(0x18)
+#define IXP23XX_EXP_CS7                        IXP23XX_EXP_CFG_REG(0x1c)
+#define IXP23XX_FLASH_WRITABLE         (0x2)
+#define IXP23XX_FLASH_BUS8             (0x1)
+
+#define IXP23XX_EXP_CFG0               IXP23XX_EXP_CFG_REG(0x20)
+#define IXP23XX_EXP_CFG1               IXP23XX_EXP_CFG_REG(0x24)
+#define IXP23XX_EXP_CFG0_MEM_MAP               (1 << 31)
+#define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL      (3 << 22)
+#define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN       (1 << 21)
+#define IXP23XX_EXP_CFG0_CPP_SPEED_SEL         (3 << 19)
+#define IXP23XX_EXP_CFG0_CPP_SPEED_EN          (1 << 18)
+#define IXP23XX_EXP_CFG0_PCI_SWIN              (3 << 16)
+#define IXP23XX_EXP_CFG0_PCI_DWIN              (3 << 14)
+#define IXP23XX_EXP_CFG0_PCI33_MODE            (1 << 13)
+#define IXP23XX_EXP_CFG0_QDR_SPEED_SEL         (1 << 12)
+#define IXP23XX_EXP_CFG0_CPP_DIV_SEL           (1 << 5)
+#define IXP23XX_EXP_CFG0_XSI_NOT_PRES          (1 << 4)
+#define IXP23XX_EXP_CFG0_PROM_BOOT             (1 << 3)
+#define IXP23XX_EXP_CFG0_PCI_ARB               (1 << 2)
+#define IXP23XX_EXP_CFG0_PCI_HOST              (1 << 1)
+#define IXP23XX_EXP_CFG0_FLASH_WIDTH           (1 << 0)
+
+#define IXP23XX_EXP_UNIT_FUSE          IXP23XX_EXP_CFG_REG(0x28)
+#define IXP23XX_EXP_MSF_MUX            IXP23XX_EXP_CFG_REG(0x30)
+
+#define IXP23XX_EXP_BUS_PHYS           0x90000000
+#define IXP23XX_EXP_BUS_WINDOW_SIZE    0x01000000
+
+#define IXP23XX_EXP_BUS_CS0_BASE       (IXP23XX_EXP_BUS_PHYS + 0x00000000)
+#define IXP23XX_EXP_BUS_CS1_BASE       (IXP23XX_EXP_BUS_PHYS + 0x01000000)
+#define IXP23XX_EXP_BUS_CS2_BASE       (IXP23XX_EXP_BUS_PHYS + 0x02000000)
+#define IXP23XX_EXP_BUS_CS3_BASE       (IXP23XX_EXP_BUS_PHYS + 0x03000000)
+#define IXP23XX_EXP_BUS_CS4_BASE       (IXP23XX_EXP_BUS_PHYS + 0x04000000)
+#define IXP23XX_EXP_BUS_CS5_BASE       (IXP23XX_EXP_BUS_PHYS + 0x05000000)
+#define IXP23XX_EXP_BUS_CS6_BASE       (IXP23XX_EXP_BUS_PHYS + 0x06000000)
+#define IXP23XX_EXP_BUS_CS7_BASE       (IXP23XX_EXP_BUS_PHYS + 0x07000000)
+
+
+/****************************************************************************
+ * Peripherals.
+ ****************************************************************************/
+#define IXP23XX_UART1_VIRT             (IXP23XX_PERIPHERAL_VIRT + 0x0000)
+#define IXP23XX_UART2_VIRT             (IXP23XX_PERIPHERAL_VIRT + 0x1000)
+#define IXP23XX_PMU_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x2000)
+#define IXP23XX_INTC_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x3000)
+#define IXP23XX_GPIO_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x4000)
+#define IXP23XX_TIMER_VIRT             (IXP23XX_PERIPHERAL_VIRT + 0x5000)
+#define IXP23XX_NPE0_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x6000)
+#define IXP23XX_DSR_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x7000)
+#define IXP23XX_NPE1_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x8000)
+#define IXP23XX_ETH0_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x9000)
+#define IXP23XX_ETH1_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0xA000)
+#define IXP23XX_GIG0_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0xB000)
+#define IXP23XX_GIG1_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0xC000)
+#define IXP23XX_DDRS_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0xD000)
+
+#define IXP23XX_UART1_PHYS             (IXP23XX_PERIPHERAL_PHYS + 0x0000)
+#define IXP23XX_UART2_PHYS             (IXP23XX_PERIPHERAL_PHYS + 0x1000)
+#define IXP23XX_PMU_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x2000)
+#define IXP23XX_INTC_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x3000)
+#define IXP23XX_GPIO_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x4000)
+#define IXP23XX_TIMER_PHYS             (IXP23XX_PERIPHERAL_PHYS + 0x5000)
+#define IXP23XX_NPE0_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x6000)
+#define IXP23XX_DSR_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x7000)
+#define IXP23XX_NPE1_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x8000)
+#define IXP23XX_ETH0_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x9000)
+#define IXP23XX_ETH1_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0xA000)
+#define IXP23XX_GIG0_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0xB000)
+#define IXP23XX_GIG1_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0xC000)
+#define IXP23XX_DDRS_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0xD000)
+
+
+/****************************************************************************
+ * Interrupt controller.
+ ****************************************************************************/
+#define IXP23XX_INTC_REG(x)             ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x)))
+#define IXP23XX_INTR_ST1               IXP23XX_INTC_REG(0x00)
+#define IXP23XX_INTR_ST2               IXP23XX_INTC_REG(0x04)
+#define IXP23XX_INTR_ST3               IXP23XX_INTC_REG(0x08)
+#define IXP23XX_INTR_ST4               IXP23XX_INTC_REG(0x0c)
+#define IXP23XX_INTR_EN1               IXP23XX_INTC_REG(0x10)
+#define IXP23XX_INTR_EN2               IXP23XX_INTC_REG(0x14)
+#define IXP23XX_INTR_EN3               IXP23XX_INTC_REG(0x18)
+#define IXP23XX_INTR_EN4               IXP23XX_INTC_REG(0x1c)
+#define IXP23XX_INTR_SEL1              IXP23XX_INTC_REG(0x20)
+#define IXP23XX_INTR_SEL2              IXP23XX_INTC_REG(0x24)
+#define IXP23XX_INTR_SEL3              IXP23XX_INTC_REG(0x28)
+#define IXP23XX_INTR_SEL4              IXP23XX_INTC_REG(0x2c)
+#define IXP23XX_INTR_IRQ_ST1           IXP23XX_INTC_REG(0x30)
+#define IXP23XX_INTR_IRQ_ST2           IXP23XX_INTC_REG(0x34)
+#define IXP23XX_INTR_IRQ_ST3           IXP23XX_INTC_REG(0x38)
+#define IXP23XX_INTR_IRQ_ST4           IXP23XX_INTC_REG(0x3c)
+#define IXP23XX_INTR_IRQ_ENC_ST_OFFSET 0x54
+
+
+/****************************************************************************
+ * GPIO.
+ ****************************************************************************/
+#define IXP23XX_GPIO_REG(x)            ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x)))
+#define IXP23XX_GPIO_GPOUTR            IXP23XX_GPIO_REG(0x00)
+#define IXP23XX_GPIO_GPOER             IXP23XX_GPIO_REG(0x04)
+#define IXP23XX_GPIO_GPINR             IXP23XX_GPIO_REG(0x08)
+#define IXP23XX_GPIO_GPISR             IXP23XX_GPIO_REG(0x0c)
+#define IXP23XX_GPIO_GPIT1R            IXP23XX_GPIO_REG(0x10)
+#define IXP23XX_GPIO_GPIT2R            IXP23XX_GPIO_REG(0x14)
+#define IXP23XX_GPIO_GPCLKR            IXP23XX_GPIO_REG(0x18)
+#define IXP23XX_GPIO_GPDBSELR          IXP23XX_GPIO_REG(0x1c)
+
+#define IXP23XX_GPIO_STYLE_MASK                0x7
+#define IXP23XX_GPIO_STYLE_ACTIVE_HIGH 0x0
+#define IXP23XX_GPIO_STYLE_ACTIVE_LOW  0x1
+#define IXP23XX_GPIO_STYLE_RISING_EDGE 0x2
+#define IXP23XX_GPIO_STYLE_FALLING_EDGE        0x3
+#define IXP23XX_GPIO_STYLE_TRANSITIONAL        0x4
+
+#define IXP23XX_GPIO_STYLE_SIZE                3
+
+
+/****************************************************************************
+ * Timer.
+ ****************************************************************************/
+#define IXP23XX_TIMER_REG(x)           ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x)))
+#define IXP23XX_TIMER_CONT             IXP23XX_TIMER_REG(0x00)
+#define IXP23XX_TIMER1_TIMESTAMP       IXP23XX_TIMER_REG(0x04)
+#define IXP23XX_TIMER1_RELOAD          IXP23XX_TIMER_REG(0x08)
+#define IXP23XX_TIMER2_TIMESTAMP       IXP23XX_TIMER_REG(0x0c)
+#define IXP23XX_TIMER2_RELOAD          IXP23XX_TIMER_REG(0x10)
+#define IXP23XX_TIMER_WDOG             IXP23XX_TIMER_REG(0x14)
+#define IXP23XX_TIMER_WDOG_EN          IXP23XX_TIMER_REG(0x18)
+#define IXP23XX_TIMER_WDOG_KEY         IXP23XX_TIMER_REG(0x1c)
+#define IXP23XX_TIMER_WDOG_KEY_MAGIC   0x482e
+#define IXP23XX_TIMER_STATUS           IXP23XX_TIMER_REG(0x20)
+#define IXP23XX_TIMER_SOFT_RESET       IXP23XX_TIMER_REG(0x24)
+#define IXP23XX_TIMER_SOFT_RESET_EN    IXP23XX_TIMER_REG(0x28)
+
+#define IXP23XX_TIMER_ENABLE           (1 << 0)
+#define IXP23XX_TIMER_ONE_SHOT         (1 << 1)
+/* Low order bits of reload value ignored */
+#define IXP23XX_TIMER_RELOAD_MASK      (0x3)
+#define IXP23XX_TIMER_DISABLED         (0x0)
+#define IXP23XX_TIMER1_INT_PEND                (1 << 0)
+#define IXP23XX_TIMER2_INT_PEND                (1 << 1)
+#define IXP23XX_TIMER_STATUS_TS_PEND   (1 << 2)
+#define IXP23XX_TIMER_STATUS_WDOG_PEND (1 << 3)
+#define IXP23XX_TIMER_STATUS_WARM_RESET        (1 << 4)
+
+
+/****************************************************************************
+ * CAP CSRs.
+ ****************************************************************************/
+#define IXP23XX_GLOBAL_REG(x)          ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x)))
+#define IXP23XX_PROD_IDG               IXP23XX_GLOBAL_REG(0x00)
+#define IXP23XX_MISC_CONTROL           IXP23XX_GLOBAL_REG(0x04)
+#define IXP23XX_MSF_CLK_CNTRL          IXP23XX_GLOBAL_REG(0x08)
+#define IXP23XX_RESET0                 IXP23XX_GLOBAL_REG(0x0c)
+#define IXP23XX_RESET1                 IXP23XX_GLOBAL_REG(0x10)
+#define IXP23XX_STRAP_OPTIONS          IXP23XX_GLOBAL_REG(0x18)
+
+#define IXP23XX_ENABLE_WATCHDOG                (1 << 24)
+#define IXP23XX_SHPC_INIT_COMP         (1 << 21)
+#define IXP23XX_RST_ALL                        (1 << 16)
+#define IXP23XX_RESET_PCI              (1 << 2)
+#define IXP23XX_PCI_UNIT_RESET         (1 << 1)
+#define IXP23XX_XSCALE_RESET           (1 << 0)
+
+
+/****************************************************************************
+ * PCI CSRs.
+ ****************************************************************************/
+#define IXP23XX_PCI_CREG(x)            ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x)))
+#define IXP23XX_PCI_CMDSTAT            IXP23XX_PCI_CREG(0x04)
+#define IXP23XX_PCI_SRAM_BAR           IXP23XX_PCI_CREG(0x14)
+#define IXP23XX_PCI_SDRAM_BAR          IXP23XX_PCI_CREG(0x18)
+
+
+#define IXP23XX_PCI_CSR(x)             ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x)))
+#define IXP23XX_PCI_OUT_INT_STATUS     IXP23XX_PCI_CSR(0x0030)
+#define IXP23XX_PCI_OUT_INT_MASK       IXP23XX_PCI_CSR(0x0034)
+#define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc)
+#define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100)
+#define IXP23XX_PCI_CONTROL            IXP23XX_PCI_CSR(0x013c)
+#define IXP23XX_PCI_ADDR_EXT           IXP23XX_PCI_CSR(0x0140)
+#define IXP23XX_PCI_ME_PUSH_STATUS     IXP23XX_PCI_CSR(0x0148)
+#define IXP23XX_PCI_ME_PUSH_EN         IXP23XX_PCI_CSR(0x014c)
+#define IXP23XX_PCI_ERR_STATUS         IXP23XX_PCI_CSR(0x0150)
+#define IXP23XX_PCI_ERROR_STATUS       IXP23XX_PCI_CSR(0x0150)
+#define IXP23XX_PCI_ERR_ENABLE         IXP23XX_PCI_CSR(0x0154)
+#define IXP23XX_PCI_XSCALE_INT_STATUS  IXP23XX_PCI_CSR(0x0158)
+#define IXP23XX_PCI_XSCALE_INT_ENABLE  IXP23XX_PCI_CSR(0x015c)
+#define IXP23XX_PCI_CPP_ADDR_BITS      IXP23XX_PCI_CSR(0x0160)
+
+
+#ifndef __ASSEMBLY__
+/*
+ * Is system memory on the XSI or CPP bus?
+ */
+static inline unsigned ixp23xx_cpp_boot(void)
+{
+       return (*IXP23XX_EXP_CFG0 & IXP23XX_EXP_CFG0_XSI_NOT_PRES);
+}
+#endif
+
+
+#endif
diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h
new file mode 100644 (file)
index 0000000..bebcf0a
--- /dev/null
@@ -0,0 +1,46 @@
+/*
+ * include/asm-arm/arch-ixp23xx/memory.h
+ *
+ * Copyright (c) 2003-2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <asm/hardware.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET            (0x00000000)
+
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *             address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *             to an address that the kernel can use.
+ */
+#ifndef __ASSEMBLY__
+
+#define __virt_to_bus(v)                                               \
+       ({ unsigned int ret;                                            \
+       ret = ((__virt_to_phys(v) - 0x00000000) +                       \
+        (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0));      \
+       ret; })
+
+#define __bus_to_virt(b)                                               \
+       ({ unsigned int data;                                           \
+       data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR);                \
+        __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); })
+
+#endif
+
+
+#endif
diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h
new file mode 100644 (file)
index 0000000..f85b468
--- /dev/null
@@ -0,0 +1,31 @@
+/*
+ * include/asm-arm/arch-ixp23xx/platform.h
+ *
+ * Various bits of code used by platform-level code.
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2005 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASSEMBLY__
+
+struct pci_sys_data;
+
+void ixp23xx_map_io(void);
+void ixp23xx_init_irq(void);
+void ixp23xx_sys_init(void);
+int ixp23xx_pci_setup(int, struct pci_sys_data *);
+void ixp23xx_pci_preinit(void);
+struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*);
+
+extern struct sys_timer ixp23xx_timer;
+
+#define IXP23XX_UART_XTAL              14745600
+
+
+#endif
diff --git a/include/asm-arm/arch-ixp23xx/system.h b/include/asm-arm/arch-ixp23xx/system.h
new file mode 100644 (file)
index 0000000..925e6b0
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ * include/asm-arm/arch-ixp23xx/system.h
+ *
+ * Copyright (C) 2003 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+static inline void arch_idle(void)
+{
+#if 0
+       if (!hlt_counter)
+               cpu_do_idle();
+#endif
+}
+
+static inline void arch_reset(char mode)
+{
+       /* First try machine specific support */
+       if (machine_is_ixdp2351()) {
+               *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC;
+               (void) *IXDP2351_CPLD_RESET1_REG;
+               *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE;
+       }
+
+       /* Use on-chip reset capability */
+       *IXP23XX_RESET0 |= IXP23XX_RST_ALL;
+}
diff --git a/include/asm-arm/arch-ixp23xx/time.h b/include/asm-arm/arch-ixp23xx/time.h
new file mode 100644 (file)
index 0000000..f6828fd
--- /dev/null
@@ -0,0 +1,3 @@
+/*
+ * include/asm-arm/arch-ixp23xx/time.h
+ */
diff --git a/include/asm-arm/arch-ixp23xx/timex.h b/include/asm-arm/arch-ixp23xx/timex.h
new file mode 100644 (file)
index 0000000..516f72f
--- /dev/null
@@ -0,0 +1,7 @@
+/*
+ * include/asm-arm/arch-ixp23xx/timex.h
+ *
+ * XScale architecture timex specifications
+ */
+
+#define CLOCK_TICK_RATE 75000000
diff --git a/include/asm-arm/arch-ixp23xx/uncompress.h b/include/asm-arm/arch-ixp23xx/uncompress.h
new file mode 100644 (file)
index 0000000..62623fa
--- /dev/null
@@ -0,0 +1,45 @@
+/*
+ * include/asm-arm/arch-ixp23xx/uncompress.h
+ *
+ * Copyright (C) 2002-2004 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <asm/hardware.h>
+#include <linux/serial_reg.h>
+
+#define UART_BASE      ((volatile u32 *)IXP23XX_UART1_PHYS)
+
+static __inline__ void putc(char c)
+{
+       int j;
+
+       for (j = 0; j < 0x1000; j++) {
+               if (UART_BASE[UART_LSR] & UART_LSR_THRE)
+                       break;
+       }
+
+       UART_BASE[UART_TX] = c;
+}
+
+static void putstr(const char *s)
+{
+       while (*s) {
+               putc(*s);
+               if (*s == '\n')
+                       putc('\r');
+               s++;
+       }
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+
+#endif
diff --git a/include/asm-arm/arch-ixp23xx/vmalloc.h b/include/asm-arm/arch-ixp23xx/vmalloc.h
new file mode 100644 (file)
index 0000000..9f25666
--- /dev/null
@@ -0,0 +1,10 @@
+/*
+ * include/asm-arm/arch-ixp23xx/vmalloc.h
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ *
+ * NPU mappings end at 0xf0000000 and we allocate 64MB for board
+ * specific static I/O.
+ */
+
+#define VMALLOC_END    (0xec000000)