drm/radeon/kms: rs400/480 MC setup is different than r300.

Boot testing on my rs480 laptop found the MC idle never happened
on startup, a quick check with AMD found the idle bit is in a different
place on the rs4xx than r300.

Implement a new rs400 mc idle function to fix this.

Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index eeeb0d6d7a44a10e5036fb05f8bb9d302b2b2d82..287fcebfb4e67733ff27aef939380b5b92f3a742 100644 (file)
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -223,15 +223,31 @@ int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
        return 0;
 }
 
+int rs400_mc_wait_for_idle(struct radeon_device *rdev)
+{
+       unsigned i;
+       uint32_t tmp;
+
+       for (i = 0; i < rdev->usec_timeout; i++) {
+               /* read MC_STATUS */
+               tmp = RREG32(0x0150);
+               if (tmp & (1 << 2)) {
+                       return 0;
+               }
+               DRM_UDELAY(1);
+       }
+       return -1;
+}
+
 void rs400_gpu_init(struct radeon_device *rdev)
 {
        /* FIXME: HDP same place on rs400 ? */
        r100_hdp_reset(rdev);
        /* FIXME: is this correct ? */
        r420_pipes_init(rdev);
-       if (r300_mc_wait_for_idle(rdev)) {
-               printk(KERN_WARNING "Failed to wait MC idle while "
-                      "programming pipes. Bad things might happen.\n");
+       if (rs400_mc_wait_for_idle(rdev)) {
+               printk(KERN_WARNING "rs400: Failed to wait MC idle while "
+                      "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
        }
 }
 
@@ -370,8 +386,8 @@ void rs400_mc_program(struct radeon_device *rdev)
        r100_mc_stop(rdev, &save);
 
        /* Wait for mc idle */
-       if (r300_mc_wait_for_idle(rdev))
-               dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
+       if (rs400_mc_wait_for_idle(rdev))
+               dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
        WREG32(R_000148_MC_FB_LOCATION,
                S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
                S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));