};
#endif
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+static struct resource dtv_resource[] = {
+ [0] = {
+ .start = INT_DTV,
+ .end = INT_DTV,
+ .flags = IORESOURCE_IRQ,
+ },
+ [1] = {
+ .start = TEGRA_DTV_BASE,
+ .end = TEGRA_DTV_BASE + TEGRA_DTV_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .start = TEGRA_DMA_REQ_SEL_DTV,
+ .end = TEGRA_DMA_REQ_SEL_DTV,
+ .flags = IORESOURCE_DMA
+ },
+};
+#endif
+
+
struct platform_device tegra_spi_device1 = {
.name = "spi_tegra",
.id = 0,
},
};
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+struct platform_device tegra_dtv_device = {
+ .name = "tegra_dtv",
+ .id = -1,
+ .resource = dtv_resource,
+ .num_resources = ARRAY_SIZE(dtv_resource),
+ .dev = {
+ .init_name = "dtv",
+ .coherent_dma_mask = 0xffffffff,
+ },
+};
+#endif
+
static struct resource sdhci_resource1[] = {
[0] = {
.start = INT_SDMMC1,
extern struct platform_device tegra_spi_device6;
extern struct platform_device tegra_spi_slave_device5;
extern struct platform_device tegra_spi_slave_device6;
+extern struct platform_device tegra_dtv_device;
#endif
extern struct platform_device tegra_ehci1_device;
extern struct platform_device tegra_ehci2_device;
#define INT_UARTB (INT_SEC_BASE + 5)
#define INT_I2C (INT_SEC_BASE + 6)
#define INT_SPI (INT_SEC_BASE + 7)
+#define INT_DTV INT_SPI
#define INT_TWC (INT_SEC_BASE + 8)
#define INT_TMR3 (INT_SEC_BASE + 9)
#define INT_TMR4 (INT_SEC_BASE + 10)