Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelv...
Linus Torvalds [Wed, 25 May 2011 23:52:50 +0000 (16:52 -0700)]
* 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelvare/staging:
  hwmon: New driver for the SMSC EMC6W201
  hwmon: (abituguru) Depend on DMI
  hwmon: (it87) Use request_muxed_region
  hwmon: (sch5627) Trigger Vbat measurements
  hwmon: (sch5627) Add sch5627_send_cmd function
  i8k: Integrate with the hwmon subsystem
  hwmon: (max6650) Properly support the MAX6650
  hwmon: (max6650) Drop device detection
  Move ACPI power meter driver to hwmon
  hwmon: (f71882fg) Add support for F71808A
  hwmon: (f71882fg) Split has_beep in fan_has_beep and temp_has_beep
  hwmon: (asc7621) Drop duplicate dependency
  hwmon: (jc42) Change detection class
  hwmon: Add driver for AMD family 15h processor power information
  hwmon: (k10temp) Add support for Fam15h (Bulldozer)
  hwmon: Use helper functions to set and get driver data
  i8k: Avoid lahf in 64-bit code

640 files changed:
.mailmap
CREDITS
Documentation/ABI/testing/sysfs-block
Documentation/ABI/testing/sysfs-ptp [new file with mode: 0644]
Documentation/IRQ-affinity.txt
Documentation/blockdev/cciss.txt
Documentation/cachetlb.txt
Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
Documentation/filesystems/9p.txt
Documentation/filesystems/proc.txt
Documentation/kernel-parameters.txt
Documentation/lockstat.txt
Documentation/ptp/ptp.txt [new file with mode: 0644]
Documentation/ptp/testptp.c [new file with mode: 0644]
Documentation/ptp/testptp.mk [new file with mode: 0644]
Documentation/virtual/uml/UserModeLinux-HOWTO.txt
Documentation/vm/locking
MAINTAINERS
Makefile
arch/Kconfig
arch/alpha/Kconfig
arch/alpha/include/asm/gpio.h [new file with mode: 0644]
arch/alpha/include/asm/smp.h
arch/alpha/kernel/process.c
arch/alpha/kernel/setup.c
arch/alpha/kernel/smp.c
arch/alpha/kernel/sys_dp264.c
arch/alpha/kernel/sys_titan.c
arch/alpha/mm/init.c
arch/alpha/mm/numa.c
arch/arm/Kconfig.debug
arch/arm/include/asm/smp.h
arch/arm/include/asm/tlb.h
arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h [new file with mode: 0644]
arch/arm/mach-omap2/board-3430sdp.c
arch/arm/mach-omap2/board-4430sdp.c
arch/arm/mach-omap2/board-am3517evm.c
arch/arm/mach-omap2/board-cm-t35.c
arch/arm/mach-omap2/board-devkit8000.c
arch/arm/mach-omap2/board-igep0020.c
arch/arm/mach-omap2/board-omap3beagle.c
arch/arm/mach-omap2/board-omap3evm.c
arch/arm/mach-omap2/board-omap3pandora.c
arch/arm/mach-omap2/board-omap3stalker.c
arch/arm/mach-omap2/board-omap4panda.c
arch/arm/mach-omap2/board-overo.c
arch/arm/mach-omap2/board-rx51-video.c
arch/arm/mach-omap2/board-zoom-display.c
arch/arm/mach-omap2/display.c
arch/arm/mach-omap2/include/mach/board-zoom.h
arch/arm/mach-shmobile/Makefile
arch/arm/mach-shmobile/board-ag5evm.c
arch/arm/mach-shmobile/board-ap4evb.c
arch/arm/mach-shmobile/board-g4evm.c
arch/arm/mach-shmobile/board-mackerel.c
arch/arm/mach-shmobile/clock-sh7372.c
arch/arm/mach-shmobile/clock-sh73a0.c
arch/arm/mach-shmobile/cpuidle.c [new file with mode: 0644]
arch/arm/mach-shmobile/headsmp.S
arch/arm/mach-shmobile/include/mach/common.h
arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
arch/arm/mach-shmobile/include/mach/head-mackerel.txt
arch/arm/mach-shmobile/include/mach/sh7372.h
arch/arm/mach-shmobile/include/mach/sh73a0.h
arch/arm/mach-shmobile/intc-sh7372.c
arch/arm/mach-shmobile/pm-sh7372.c [new file with mode: 0644]
arch/arm/mach-shmobile/setup-sh7367.c
arch/arm/mach-shmobile/setup-sh7372.c
arch/arm/mach-shmobile/setup-sh7377.c
arch/arm/mach-shmobile/setup-sh73a0.c
arch/arm/mach-shmobile/sleep-sh7372.S [new file with mode: 0644]
arch/arm/mach-shmobile/smp-sh73a0.c
arch/arm/mach-shmobile/suspend.c [new file with mode: 0644]
arch/arm/mach-ux500/Kconfig
arch/arm/mach-ux500/Makefile
arch/arm/mach-ux500/cpu-db5500.c
arch/arm/mach-ux500/cpu-db8500.c
arch/arm/mach-ux500/cpu.c
arch/arm/mach-ux500/cpufreq.c [deleted file]
arch/arm/mach-ux500/include/mach/db5500-regs.h
arch/arm/mach-ux500/include/mach/db8500-regs.h
arch/arm/mach-ux500/include/mach/hardware.h
arch/arm/mach-ux500/include/mach/id.h
arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
arch/arm/mach-ux500/include/mach/irqs-board-u5500.h [new file with mode: 0644]
arch/arm/mach-ux500/include/mach/irqs-db5500.h
arch/arm/mach-ux500/include/mach/irqs-db8500.h
arch/arm/mach-ux500/include/mach/irqs.h
arch/arm/mach-ux500/include/mach/prcmu-defs.h [deleted file]
arch/arm/mach-ux500/include/mach/prcmu.h [deleted file]
arch/arm/mach-ux500/prcmu.c [deleted file]
arch/arm/mm/init.c
arch/arm/mm/mmu.c
arch/avr32/mm/init.c
arch/blackfin/Kconfig
arch/blackfin/Kconfig.debug
arch/blackfin/configs/BF527-EZKIT-V2_defconfig
arch/blackfin/configs/BF527-EZKIT_defconfig
arch/blackfin/configs/BF533-STAMP_defconfig
arch/blackfin/configs/BF537-STAMP_defconfig
arch/blackfin/include/asm/bfin-global.h
arch/blackfin/include/asm/bfin_pfmon.h [new file with mode: 0644]
arch/blackfin/include/asm/bfin_sport.h
arch/blackfin/include/asm/cacheflush.h
arch/blackfin/include/asm/cpu.h
arch/blackfin/include/asm/def_LPBlackfin.h
arch/blackfin/include/asm/irq_handler.h
arch/blackfin/include/asm/kgdb.h
arch/blackfin/include/asm/perf_event.h [new file with mode: 0644]
arch/blackfin/include/asm/ptrace.h
arch/blackfin/include/mach-common/irq.h [new file with mode: 0644]
arch/blackfin/kernel/Makefile
arch/blackfin/kernel/bfin_dma_5xx.c
arch/blackfin/kernel/bfin_gpio.c
arch/blackfin/kernel/bfin_ksyms.c
arch/blackfin/kernel/debug-mmrs.c [new file with mode: 0644]
arch/blackfin/kernel/ipipe.c
arch/blackfin/kernel/irqchip.c
arch/blackfin/kernel/nmi.c
arch/blackfin/kernel/perf_event.c [new file with mode: 0644]
arch/blackfin/kernel/process.c
arch/blackfin/kernel/reboot.c
arch/blackfin/kernel/setup.c
arch/blackfin/kernel/vmlinux.lds.S
arch/blackfin/mach-bf518/include/mach/anomaly.h
arch/blackfin/mach-bf518/include/mach/cdefBF512.h
arch/blackfin/mach-bf518/include/mach/defBF512.h
arch/blackfin/mach-bf518/include/mach/irq.h
arch/blackfin/mach-bf527/boards/ezkit.c
arch/blackfin/mach-bf527/include/mach/anomaly.h
arch/blackfin/mach-bf527/include/mach/cdefBF522.h
arch/blackfin/mach-bf527/include/mach/defBF522.h
arch/blackfin/mach-bf527/include/mach/irq.h
arch/blackfin/mach-bf533/include/mach/anomaly.h
arch/blackfin/mach-bf533/include/mach/irq.h
arch/blackfin/mach-bf537/boards/stamp.c
arch/blackfin/mach-bf537/include/mach/anomaly.h
arch/blackfin/mach-bf537/include/mach/irq.h
arch/blackfin/mach-bf537/ints-priority.c
arch/blackfin/mach-bf538/include/mach/anomaly.h
arch/blackfin/mach-bf538/include/mach/irq.h
arch/blackfin/mach-bf548/boards/ezkit.c
arch/blackfin/mach-bf548/include/mach/anomaly.h
arch/blackfin/mach-bf548/include/mach/irq.h
arch/blackfin/mach-bf561/boards/ezkit.c
arch/blackfin/mach-bf561/include/mach/anomaly.h
arch/blackfin/mach-bf561/include/mach/irq.h
arch/blackfin/mach-bf561/smp.c
arch/blackfin/mach-common/dpmc.c
arch/blackfin/mach-common/ints-priority.c
arch/blackfin/mach-common/smp.c
arch/blackfin/mm/sram-alloc.c
arch/cris/arch-v32/kernel/irq.c
arch/cris/arch-v32/kernel/smp.c
arch/cris/mm/init.c
arch/frv/mm/init.c
arch/ia64/include/asm/tlb.h
arch/ia64/mm/contig.c
arch/ia64/mm/discontig.c
arch/ia64/mm/init.c
arch/m32r/Kconfig.debug
arch/m32r/include/asm/smp.h
arch/m32r/mm/discontig.c
arch/m32r/mm/init.c
arch/m68k/mm/init_mm.c
arch/microblaze/mm/init.c
arch/mips/Kconfig.debug
arch/mips/mm/init.c
arch/mn10300/kernel/irq.c
arch/mn10300/kernel/smp.c
arch/mn10300/mm/cache-smp.c
arch/mn10300/mm/init.c
arch/mn10300/mm/tlb-smp.c
arch/parisc/include/asm/smp.h
arch/parisc/mm/init.c
arch/powerpc/Kconfig
arch/powerpc/Kconfig.debug
arch/powerpc/boot/dts/mpc8313erdb.dts
arch/powerpc/boot/dts/mpc8572ds.dts
arch/powerpc/boot/dts/p2020ds.dts
arch/powerpc/boot/dts/p2020rdb.dts
arch/powerpc/include/asm/pgalloc.h
arch/powerpc/include/asm/thread_info.h
arch/powerpc/kernel/process.c
arch/powerpc/mm/pgtable.c
arch/powerpc/mm/tlb_hash32.c
arch/powerpc/mm/tlb_hash64.c
arch/powerpc/mm/tlb_nohash.c
arch/s390/include/asm/tlb.h
arch/s390/mm/pgtable.c
arch/score/Kconfig.debug
arch/score/mm/init.c
arch/sh/Kconfig.debug
arch/sh/include/asm/tlb.h
arch/sh/mm/init.c
arch/sparc/Kconfig.debug
arch/sparc/include/asm/pgalloc_64.h
arch/sparc/include/asm/pgtable_64.h
arch/sparc/include/asm/tlb_64.h
arch/sparc/include/asm/tlbflush_64.h
arch/sparc/kernel/setup_32.c
arch/sparc/mm/init_32.c
arch/sparc/mm/tlb.c
arch/sparc/mm/tsb.c
arch/tile/Kconfig
arch/tile/Kconfig.debug
arch/tile/configs/tile_defconfig [deleted file]
arch/tile/configs/tilegx_defconfig [new file with mode: 0644]
arch/tile/configs/tilepro_defconfig [new file with mode: 0644]
arch/tile/include/arch/chip_tilegx.h [new file with mode: 0644]
arch/tile/include/arch/icache.h
arch/tile/include/arch/interrupts_64.h [new file with mode: 0644]
arch/tile/include/arch/spr_def.h
arch/tile/include/arch/spr_def_64.h [new file with mode: 0644]
arch/tile/include/asm/atomic.h
arch/tile/include/asm/atomic_32.h
arch/tile/include/asm/atomic_64.h [new file with mode: 0644]
arch/tile/include/asm/backtrace.h
arch/tile/include/asm/bitops.h
arch/tile/include/asm/bitops_32.h
arch/tile/include/asm/bitops_64.h [new file with mode: 0644]
arch/tile/include/asm/cacheflush.h
arch/tile/include/asm/compat.h
arch/tile/include/asm/dma-mapping.h
arch/tile/include/asm/fb.h [new file with mode: 0644]
arch/tile/include/asm/io.h
arch/tile/include/asm/irq.h
arch/tile/include/asm/mmu_context.h
arch/tile/include/asm/opcode-tile_32.h
arch/tile/include/asm/opcode-tile_64.h
arch/tile/include/asm/opcode_constants_64.h
arch/tile/include/asm/page.h
arch/tile/include/asm/parport.h [new file with mode: 0644]
arch/tile/include/asm/pci.h
arch/tile/include/asm/pgtable_64.h [new file with mode: 0644]
arch/tile/include/asm/processor.h
arch/tile/include/asm/serial.h [new file with mode: 0644]
arch/tile/include/asm/signal.h
arch/tile/include/asm/spinlock_64.h [new file with mode: 0644]
arch/tile/include/asm/stat.h
arch/tile/include/asm/swab.h
arch/tile/include/asm/thread_info.h
arch/tile/include/asm/topology.h
arch/tile/include/asm/traps.h
arch/tile/include/asm/unistd.h
arch/tile/include/asm/vga.h [moved from arch/tile/include/hv/pagesize.h with 52% similarity]
arch/tile/include/hv/hypervisor.h
arch/tile/kernel/backtrace.c
arch/tile/kernel/compat.c
arch/tile/kernel/compat_signal.c
arch/tile/kernel/futex_64.S [new file with mode: 0644]
arch/tile/kernel/hardwall.c
arch/tile/kernel/head_64.S [new file with mode: 0644]
arch/tile/kernel/intvec_32.S
arch/tile/kernel/intvec_64.S [new file with mode: 0644]
arch/tile/kernel/module.c
arch/tile/kernel/pci-dma.c
arch/tile/kernel/pci.c
arch/tile/kernel/process.c
arch/tile/kernel/regs_64.S [new file with mode: 0644]
arch/tile/kernel/setup.c
arch/tile/kernel/signal.c
arch/tile/kernel/single_step.c
arch/tile/kernel/stack.c
arch/tile/kernel/sys.c
arch/tile/kernel/tile-desc_32.c
arch/tile/kernel/tile-desc_64.c [new file with mode: 0644]
arch/tile/kernel/time.c
arch/tile/kernel/tlb.c
arch/tile/kernel/traps.c
arch/tile/lib/atomic_asm_32.S
arch/tile/lib/cacheflush.c
arch/tile/lib/memchr_64.c [new file with mode: 0644]
arch/tile/lib/memcpy_64.c [new file with mode: 0644]
arch/tile/lib/memcpy_user_64.c [new file with mode: 0644]
arch/tile/lib/memset_64.c [new file with mode: 0644]
arch/tile/lib/spinlock_64.c [new file with mode: 0644]
arch/tile/lib/strchr_64.c [new file with mode: 0644]
arch/tile/lib/strlen_64.c [new file with mode: 0644]
arch/tile/lib/usercopy_64.S [new file with mode: 0644]
arch/tile/mm/fault.c
arch/tile/mm/init.c
arch/tile/mm/migrate_64.S [new file with mode: 0644]
arch/um/Kconfig.debug
arch/um/drivers/Makefile
arch/um/drivers/mcast.h [deleted file]
arch/um/drivers/mcast_kern.c [deleted file]
arch/um/drivers/mcast_user.c [deleted file]
arch/um/drivers/umcast.h [new file with mode: 0644]
arch/um/drivers/umcast_kern.c [new file with mode: 0644]
arch/um/drivers/umcast_user.c [new file with mode: 0644]
arch/um/drivers/xterm.c
arch/um/include/asm/processor-generic.h
arch/um/include/asm/smp.h
arch/um/include/asm/tlb.h
arch/um/include/shared/os.h
arch/um/kernel/Makefile
arch/um/kernel/early_printk.c [new file with mode: 0644]
arch/um/kernel/smp.c
arch/um/kernel/trap.c
arch/um/os-Linux/main.c
arch/um/os-Linux/process.c
arch/um/os-Linux/util.c
arch/unicore32/Kconfig.debug
arch/unicore32/mm/init.c
arch/unicore32/mm/mmu.c
arch/x86/Kconfig
arch/x86/Kconfig.debug
arch/x86/include/asm/io.h
arch/x86/kernel/setup.c
arch/x86/kernel/tboot.c
arch/x86/kvm/mmu.c
arch/x86/mm/fault.c
arch/x86/mm/hugetlbpage.c
arch/x86/mm/init.c
arch/xtensa/include/asm/page.h
arch/xtensa/mm/mmu.c
arch/xtensa/mm/pgtable.c [deleted file]
block/blk-cgroup.c
block/blk-cgroup.h
block/blk-core.c
block/blk-exec.c
block/blk-flush.c
block/blk-ioc.c
block/blk-lib.c
block/blk-settings.c
block/blk-sysfs.c
block/blk-throttle.c
block/blk.h
block/cfq-iosched.c
block/elevator.c
drivers/Kconfig
drivers/Makefile
drivers/acpi/apei/einj.c
drivers/acpi/atomicio.c
drivers/ata/libata-scsi.c
drivers/base/node.c
drivers/block/Kconfig
drivers/block/Makefile
drivers/block/cciss.c
drivers/block/cciss.h
drivers/block/cciss_cmd.h
drivers/block/cciss_scsi.c
drivers/block/cciss_scsi.h
drivers/block/drbd/drbd_actlog.c
drivers/block/drbd/drbd_bitmap.c
drivers/block/drbd/drbd_int.h
drivers/block/drbd/drbd_main.c
drivers/block/drbd/drbd_nl.c
drivers/block/drbd/drbd_receiver.c
drivers/block/drbd/drbd_req.c
drivers/block/drbd/drbd_req.h
drivers/block/drbd/drbd_worker.c
drivers/block/loop.c
drivers/block/paride/pcd.c
drivers/block/rbd.c
drivers/block/xen-blkback/Makefile [new file with mode: 0644]
drivers/block/xen-blkback/blkback.c [new file with mode: 0644]
drivers/block/xen-blkback/common.h [new file with mode: 0644]
drivers/block/xen-blkback/xenbus.c [new file with mode: 0644]
drivers/block/xen-blkfront.c
drivers/cdrom/viocd.c
drivers/cpufreq/Makefile
drivers/cpufreq/db8500-cpufreq.c [new file with mode: 0644]
drivers/dma/shdma.c
drivers/dma/shdma.h
drivers/edac/i3200_edac.c
drivers/gpio/ml_ioh_gpio.c
drivers/gpio/vx855_gpio.c
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/ttm/ttm_page_alloc.c
drivers/ide/ide-cd.c
drivers/input/input-compat.h
drivers/leds/Kconfig
drivers/leds/Makefile
drivers/leds/led-class.c
drivers/leds/leds-gpio-register.c [new file with mode: 0644]
drivers/leds/leds-h1940.c [deleted file]
drivers/leds/leds-lm3530.c
drivers/leds/leds-pca9532.c
drivers/leds/leds.h
drivers/leds/ledtrig-timer.c
drivers/media/video/omap/omap_vout.c
drivers/media/video/omap/omap_voutdef.h
drivers/mfd/Kconfig
drivers/mfd/Makefile
drivers/mfd/ab8500-i2c.c
drivers/mfd/db5500-prcmu-regs.h [moved from arch/arm/mach-ux500/include/mach/prcmu-regs.h with 80% similarity]
drivers/mfd/db5500-prcmu.c [new file with mode: 0644]
drivers/mfd/db8500-prcmu-regs.h [new file with mode: 0644]
drivers/mfd/db8500-prcmu.c [new file with mode: 0644]
drivers/net/Makefile
drivers/net/arm/ixp4xx_eth.c
drivers/net/gianfar_ptp.c [new file with mode: 0644]
drivers/net/ioc3-eth.c
drivers/net/phy/Makefile
drivers/net/phy/dp83640.c [new file with mode: 0644]
drivers/net/phy/dp83640_reg.h [new file with mode: 0644]
drivers/net/tile/tilepro.c
drivers/platform/x86/ibm_rtl.c
drivers/platform/x86/intel_ips.c
drivers/ptp/Kconfig [new file with mode: 0644]
drivers/ptp/Makefile [new file with mode: 0644]
drivers/ptp/ptp_chardev.c [new file with mode: 0644]
drivers/ptp/ptp_clock.c [new file with mode: 0644]
drivers/ptp/ptp_ixp46x.c [new file with mode: 0644]
drivers/ptp/ptp_private.h [new file with mode: 0644]
drivers/ptp/ptp_sysfs.c [new file with mode: 0644]
drivers/regulator/Kconfig
drivers/regulator/Makefile
drivers/regulator/db8500-prcmu.c [new file with mode: 0644]
drivers/rtc/Kconfig
drivers/rtc/Makefile
drivers/rtc/rtc-tile.c [new file with mode: 0644]
drivers/scsi/qla4xxx/ql4_nx.c
drivers/scsi/sr.c
drivers/staging/zcache/zcache.c
drivers/tty/serial/68328serial.c
drivers/tty/serial/pch_uart.c
drivers/video/Kconfig
drivers/video/Makefile
drivers/video/amifb.c
drivers/video/backlight/adp5520_bl.c
drivers/video/da8xx-fb.c
drivers/video/efifb.c
drivers/video/mb862xx/Makefile
drivers/video/mb862xx/mb862xx-i2c.c [new file with mode: 0644]
drivers/video/mb862xx/mb862xx_reg.h
drivers/video/mb862xx/mb862xxfb.h
drivers/video/mb862xx/mb862xxfbdrv.c [moved from drivers/video/mb862xx/mb862xxfb.c with 86% similarity]
drivers/video/omap/dispc.c
drivers/video/omap/omapfb_main.c
drivers/video/omap/rfbi.c
drivers/video/omap2/Makefile
drivers/video/omap2/displays/Kconfig
drivers/video/omap2/displays/panel-acx565akm.c
drivers/video/omap2/displays/panel-generic-dpi.c
drivers/video/omap2/displays/panel-lgphilips-lb035q02.c
drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c
drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
drivers/video/omap2/displays/panel-taal.c
drivers/video/omap2/displays/panel-tpo-td043mtea1.c
drivers/video/omap2/dss/Kconfig
drivers/video/omap2/dss/core.c
drivers/video/omap2/dss/dispc.c
drivers/video/omap2/dss/dispc.h [new file with mode: 0644]
drivers/video/omap2/dss/display.c
drivers/video/omap2/dss/dpi.c
drivers/video/omap2/dss/dsi.c
drivers/video/omap2/dss/dss.c
drivers/video/omap2/dss/dss.h
drivers/video/omap2/dss/dss_features.c
drivers/video/omap2/dss/dss_features.h
drivers/video/omap2/dss/hdmi.c
drivers/video/omap2/dss/hdmi.h
drivers/video/omap2/dss/hdmi_omap4_panel.c
drivers/video/omap2/dss/manager.c
drivers/video/omap2/dss/overlay.c
drivers/video/omap2/dss/rfbi.c
drivers/video/omap2/dss/sdi.c
drivers/video/omap2/dss/venc.c
drivers/video/omap2/omapfb/omapfb-ioctl.c
drivers/video/omap2/omapfb/omapfb-main.c
drivers/video/omap2/omapfb/omapfb-sysfs.c
drivers/video/omap2/omapfb/omapfb.h
drivers/video/s3c-fb.c
drivers/video/s3c2410fb.c
drivers/video/s3fb.c
drivers/video/savage/savagefb-i2c.c
drivers/video/savage/savagefb.h
drivers/video/savage/savagefb_driver.c
drivers/video/sh7760fb.c
drivers/video/sh_mobile_hdmi.c
drivers/video/sh_mobile_lcdcfb.c
drivers/video/sh_mobile_lcdcfb.h
drivers/video/sh_mobile_meram.c [new file with mode: 0644]
drivers/video/sh_mobile_meram.h [new file with mode: 0644]
drivers/video/sm501fb.c
drivers/video/udlfb.c
fs/9p/Kconfig
fs/9p/vfs_inode_dotl.c
fs/Kconfig
fs/block_dev.c
fs/ceph/addr.c
fs/ceph/caps.c
fs/ceph/dir.c
fs/ceph/export.c
fs/ceph/mds_client.c
fs/ceph/mds_client.h
fs/dcache.c
fs/drop_caches.c
fs/exec.c
fs/fscache/operation.c
fs/fscache/page.c
fs/gfs2/glock.c
fs/gfs2/quota.c
fs/gfs2/quota.h
fs/hugetlbfs/inode.c
fs/inode.c
fs/mbcache.c
fs/ncpfs/inode.c
fs/nfs/dir.c
fs/nfs/internal.h
fs/partitions/check.c
fs/proc/internal.h
fs/proc/task_mmu.c
fs/quota/dquot.c
fs/splice.c
fs/xfs/linux-2.6/xfs_buf.c
fs/xfs/linux-2.6/xfs_sync.c
fs/xfs/quota/xfs_qm.c
include/asm-generic/audit_change_attr.h
include/asm-generic/audit_dir_write.h
include/asm-generic/audit_read.h
include/asm-generic/audit_write.h
include/asm-generic/cacheflush.h
include/asm-generic/resource.h
include/asm-generic/tlb.h
include/asm-generic/unistd.h
include/linux/Kbuild
include/linux/bitmap.h
include/linux/blk_types.h
include/linux/blkdev.h
include/linux/bootmem.h
include/linux/c2port.h
include/linux/ceph/ceph_fs.h
include/linux/compat.h
include/linux/compiler-gcc.h
include/linux/compiler-gcc4.h
include/linux/cpumask.h
include/linux/drbd.h
include/linux/drbd_tag_magic.h
include/linux/fs.h
include/linux/fscache-cache.h
include/linux/genalloc.h
include/linux/genhd.h
include/linux/gfp.h
include/linux/huge_mm.h
include/linux/kernel.h
include/linux/leds-pca9532.h
include/linux/leds.h
include/linux/lockdep.h
include/linux/lru_cache.h
include/linux/memblock.h
include/linux/mempolicy.h
include/linux/mfd/db5500-prcmu.h [new file with mode: 0644]
include/linux/mfd/db8500-prcmu.h [new file with mode: 0644]
include/linux/mm.h
include/linux/mm_types.h
include/linux/mmu_notifier.h
include/linux/mmzone.h
include/linux/mutex.h
include/linux/oom.h
include/linux/pagemap.h
include/linux/percpu_counter.h
include/linux/posix-timers.h
include/linux/printk.h
include/linux/proc_fs.h
include/linux/ptp_classify.h
include/linux/ptp_clock.h [new file with mode: 0644]
include/linux/ptp_clock_kernel.h [new file with mode: 0644]
include/linux/regulator/db8500-prcmu.h [new file with mode: 0644]
include/linux/rmap.h
include/linux/sched.h
include/linux/shmem_fs.h
include/linux/vmstat.h
include/linux/xattr.h
include/net/9p/9p.h
include/net/9p/client.h
include/net/9p/transport.h
include/video/omap-panel-generic-dpi.h [moved from arch/arm/plat-omap/include/plat/panel-generic-dpi.h with 86% similarity]
include/video/omap-panel-nokia-dsi.h [moved from arch/arm/plat-omap/include/plat/nokia-dsi-panel.h with 65% similarity]
include/video/omapdss.h [moved from arch/arm/plat-omap/include/plat/display.h with 85% similarity]
include/video/sh_mobile_lcdc.h
include/video/sh_mobile_meram.h [new file with mode: 0644]
include/xen/interface/io/blkif.h
init/calibrate.c
init/main.c
kernel/compat.c
kernel/fork.c
kernel/hrtimer.c
kernel/irq/proc.c
kernel/mutex.c
kernel/posix-timers.c
kernel/printk.c
kernel/sysctl.c
lib/Kconfig.debug
lib/audit.c
lib/bitmap.c
lib/genalloc.c
lib/kstrtox.c
lib/lru_cache.c
lib/show_mem.c
lib/vsprintf.c
mm/backing-dev.c
mm/filemap.c
mm/filemap_xip.c
mm/fremap.c
mm/huge_memory.c
mm/hugetlb.c
mm/init-mm.c
mm/internal.h
mm/ksm.c
mm/memcontrol.c
mm/memory-failure.c
mm/memory.c
mm/memory_hotplug.c
mm/mempolicy.c
mm/migrate.c
mm/mmap.c
mm/mremap.c
mm/nobootmem.c
mm/nommu.c
mm/oom_kill.c
mm/page_alloc.c
mm/readahead.c
mm/rmap.c
mm/shmem.c
mm/slub.c
mm/swap.c
mm/swapfile.c
mm/util.c
mm/vmalloc.c
mm/vmscan.c
mm/vmstat.c
net/9p/Kconfig
net/9p/client.c
net/9p/mod.c
net/9p/trans_fd.c
net/9p/util.c
net/ceph/messenger.c
net/ceph/osd_client.c
net/ceph/osdmap.c
net/sunrpc/auth.c
scripts/checkpatch.pl
scripts/checkversion.pl
scripts/export_report.pl
scripts/package/Makefile
scripts/package/mkspec
scripts/patch-kernel

index 5a6dd59..353ad56 100644 (file)
--- a/.mailmap
+++ b/.mailmap
@@ -32,6 +32,7 @@ Brian Avery <b.avery@hp.com>
 Brian King <brking@us.ibm.com>
 Christoph Hellwig <hch@lst.de>
 Corey Minyard <minyard@acm.org>
+Damian Hobson-Garcia <dhobsong@igel.co.jp>
 David Brownell <david-b@pacbell.net>
 David Woodhouse <dwmw2@shinybook.infradead.org>
 Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
diff --git a/CREDITS b/CREDITS
index 95c469c..58d2a02 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -2943,6 +2943,10 @@ S: Kasarmikatu 11 A4
 S: 70110 Kuopio
 S: Finland
 
+N: Tobias Ringström
+E: tori@unhappy.mine.nu
+D: Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver
+
 N: Luca Risolia
 E: luca.risolia@studio.unibo.it
 P: 1024D/FCE635A4 88E8 F32F 7244 68BA 3958  5D40 99DA 5D2A FCE6 35A4
index 4873c75..c1eb41c 100644 (file)
@@ -142,3 +142,67 @@ Description:
                with the previous I/O request are enabled. When set to 2,
                all merge tries are disabled. The default value is 0 -
                which enables all types of merge tries.
+
+What:          /sys/block/<disk>/discard_alignment
+Date:          May 2011
+Contact:       Martin K. Petersen <martin.petersen@oracle.com>
+Description:
+               Devices that support discard functionality may
+               internally allocate space in units that are bigger than
+               the exported logical block size. The discard_alignment
+               parameter indicates how many bytes the beginning of the
+               device is offset from the internal allocation unit's
+               natural alignment.
+
+What:          /sys/block/<disk>/<partition>/discard_alignment
+Date:          May 2011
+Contact:       Martin K. Petersen <martin.petersen@oracle.com>
+Description:
+               Devices that support discard functionality may
+               internally allocate space in units that are bigger than
+               the exported logical block size. The discard_alignment
+               parameter indicates how many bytes the beginning of the
+               partition is offset from the internal allocation unit's
+               natural alignment.
+
+What:          /sys/block/<disk>/queue/discard_granularity
+Date:          May 2011
+Contact:       Martin K. Petersen <martin.petersen@oracle.com>
+Description:
+               Devices that support discard functionality may
+               internally allocate space using units that are bigger
+               than the logical block size. The discard_granularity
+               parameter indicates the size of the internal allocation
+               unit in bytes if reported by the device. Otherwise the
+               discard_granularity will be set to match the device's
+               physical block size. A discard_granularity of 0 means
+               that the device does not support discard functionality.
+
+What:          /sys/block/<disk>/queue/discard_max_bytes
+Date:          May 2011
+Contact:       Martin K. Petersen <martin.petersen@oracle.com>
+Description:
+               Devices that support discard functionality may have
+               internal limits on the number of bytes that can be
+               trimmed or unmapped in a single operation. Some storage
+               protocols also have inherent limits on the number of
+               blocks that can be described in a single command. The
+               discard_max_bytes parameter is set by the device driver
+               to the maximum number of bytes that can be discarded in
+               a single operation. Discard requests issued to the
+               device must not exceed this limit. A discard_max_bytes
+               value of 0 means that the device does not support
+               discard functionality.
+
+What:          /sys/block/<disk>/queue/discard_zeroes_data
+Date:          May 2011
+Contact:       Martin K. Petersen <martin.petersen@oracle.com>
+Description:
+               Devices that support discard functionality may return
+               stale or random data when a previously discarded block
+               is read back. This can cause problems if the filesystem
+               expects discarded blocks to be explicitly cleared. If a
+               device reports that it deterministically returns zeroes
+               when a discarded area is read the discard_zeroes_data
+               parameter will be set to one. Otherwise it will be 0 and
+               the result of reading a discarded area is undefined.
diff --git a/Documentation/ABI/testing/sysfs-ptp b/Documentation/ABI/testing/sysfs-ptp
new file mode 100644 (file)
index 0000000..d40d2b5
--- /dev/null
@@ -0,0 +1,98 @@
+What:          /sys/class/ptp/
+Date:          September 2010
+Contact:       Richard Cochran <richardcochran@gmail.com>
+Description:
+               This directory contains files and directories
+               providing a standardized interface to the ancillary
+               features of PTP hardware clocks.
+
+What:          /sys/class/ptp/ptpN/
+Date:          September 2010
+Contact:       Richard Cochran <richardcochran@gmail.com>
+Description:
+               This directory contains the attributes of the Nth PTP
+               hardware clock registered into the PTP class driver
+               subsystem.
+
+What:          /sys/class/ptp/ptpN/clock_name
+Date:          September 2010
+Contact:       Richard Cochran <richardcochran@gmail.com>
+Description:
+               This file contains the name of the PTP hardware clock
+               as a human readable string.
+
+What:          /sys/class/ptp/ptpN/max_adjustment
+Date:          September 2010
+Contact:       Richard Cochran <richardcochran@gmail.com>
+Description:
+               This file contains the PTP hardware clock's maximum
+               frequency adjustment value (a positive integer) in
+               parts per billion.
+
+What:          /sys/class/ptp/ptpN/n_alarms
+Date:          September 2010
+Contact:       Richard Cochran <richardcochran@gmail.com>
+Description:
+               This file contains the number of periodic or one shot
+               alarms offer by the PTP hardware clock.
+
+What:          /sys/class/ptp/ptpN/n_external_timestamps
+Date:          September 2010
+Contact:       Richard Cochran <richardcochran@gmail.com>
+Description:
+               This file contains the number of external timestamp
+               channels offered by the PTP hardware clock.
+
+What:          /sys/class/ptp/ptpN/n_periodic_outputs
+Date:          September 2010
+Contact:       Richard Cochran <richardcochran@gmail.com>
+Description:
+               This file contains the number of programmable periodic
+               output channels offered by the PTP hardware clock.
+
+What:          /sys/class/ptp/ptpN/pps_avaiable
+Date:          September 2010
+Contact:       Richard Cochran <richardcochran@gmail.com>
+Description:
+               This file indicates whether the PTP hardware clock
+               supports a Pulse Per Second to the host CPU. Reading
+               "1" means that the PPS is supported, while "0" means
+               not supported.
+
+What:          /sys/class/ptp/ptpN/extts_enable
+Date:          September 2010
+Contact:       Richard Cochran <richardcochran@gmail.com>
+Description:
+               This write-only file enables or disables external
+               timestamps. To enable external timestamps, write the
+               channel index followed by a "1" into the file.
+               To disable external timestamps, write the channel
+               index followed by a "0" into the file.
+
+What:          /sys/class/ptp/ptpN/fifo
+Date:          September 2010
+Contact:       Richard Cochran <richardcochran@gmail.com>
+Description:
+               This file provides timestamps on external events, in
+               the form of three integers: channel index, seconds,
+               and nanoseconds.
+
+What:          /sys/class/ptp/ptpN/period
+Date:          September 2010
+Contact:       Richard Cochran <richardcochran@gmail.com>
+Description:
+               This write-only file enables or disables periodic
+               outputs. To enable a periodic output, write five
+               integers into the file: channel index, start time
+               seconds, start time nanoseconds, period seconds, and
+               period nanoseconds. To disable a periodic output, set
+               all the seconds and nanoseconds values to zero.
+
+What:          /sys/class/ptp/ptpN/pps_enable
+Date:          September 2010
+Contact:       Richard Cochran <richardcochran@gmail.com>
+Description:
+               This write-only file enables or disables delivery of
+               PPS events to the Linux PPS subsystem. To enable PPS
+               events, write a "1" into the file. To disable events,
+               write a "0" into the file.
index b4a615b..7890fae 100644 (file)
@@ -4,10 +4,11 @@ ChangeLog:
 
 SMP IRQ affinity
 
-/proc/irq/IRQ#/smp_affinity specifies which target CPUs are permitted
-for a given IRQ source. It's a bitmask of allowed CPUs. It's not allowed
-to turn off all CPUs, and if an IRQ controller does not support IRQ
-affinity then the value will not change from the default 0xffffffff.
+/proc/irq/IRQ#/smp_affinity and /proc/irq/IRQ#/smp_affinity_list specify
+which target CPUs are permitted for a given IRQ source.  It's a bitmask
+(smp_affinity) or cpu list (smp_affinity_list) of allowed CPUs.  It's not
+allowed to turn off all CPUs, and if an IRQ controller does not support
+IRQ affinity then the value will not change from the default of all cpus.
 
 /proc/irq/default_smp_affinity specifies default affinity mask that applies
 to all non-active IRQs. Once IRQ is allocated/activated its affinity bitmask
@@ -54,3 +55,11 @@ round-trip min/avg/max = 0.1/0.5/585.4 ms
 This time around IRQ44 was delivered only to the last four processors.
 i.e counters for the CPU0-3 did not change.
 
+Here is an example of limiting that same irq (44) to cpus 1024 to 1031:
+
+[root@moon 44]# echo 1024-1031 > smp_affinity
+[root@moon 44]# cat smp_affinity
+1024-1031
+
+Note that to do this with a bitmask would require 32 bitmasks of zero
+to follow the pertinent one.
index 89698e8..c00c6a5 100644 (file)
@@ -169,3 +169,18 @@ is issued which positions the tape to a known position.  Typically you
 must rewind the tape (by issuing "mt -f /dev/st0 rewind" for example)
 before i/o can proceed again to a tape drive which was reset.
 
+There is a cciss_tape_cmds module parameter which can be used to make cciss
+allocate more commands for use by tape drives.  Ordinarily only a few commands
+(6) are allocated for tape drives because tape drives are slow and
+infrequently used and the primary purpose of Smart Array controllers is to
+act as a RAID controller for disk drives, so the vast majority of commands
+are allocated for disk devices.  However, if you have more than a few tape
+drives attached to a smart array, the default number of commands may not be
+enought (for example, if you have 8 tape drives, you could only rewind 6
+at one time with the default number of commands.)  The cciss_tape_cmds module
+parameter allows more commands (up to 16 more) to be allocated for use by
+tape drives.  For example:
+
+        insmod cciss.ko cciss_tape_cmds=16
+
+Or, as a kernel boot parameter passed in via grub:  cciss.cciss_tape_cmds=8
index 9164ae3..9b728dc 100644 (file)
@@ -16,7 +16,7 @@ on all processors in the system.  Don't let this scare you into
 thinking SMP cache/tlb flushing must be so inefficient, this is in
 fact an area where many optimizations are possible.  For example,
 if it can be proven that a user address space has never executed
-on a cpu (see vma->cpu_vm_mask), one need not perform a flush
+on a cpu (see mm_cpumask()), one need not perform a flush
 for this address space on that cpu.
 
 First, the TLB flushing interfaces, since they are the simplest.  The
index edb7ae1..2c6be03 100644 (file)
@@ -74,3 +74,57 @@ Example:
                interrupt-parent = <&mpic>;
                phy-handle = <&phy0>
        };
+
+* Gianfar PTP clock nodes
+
+General Properties:
+
+  - compatible   Should be "fsl,etsec-ptp"
+  - reg          Offset and length of the register set for the device
+  - interrupts   There should be at least two interrupts. Some devices
+                 have as many as four PTP related interrupts.
+
+Clock Properties:
+
+  - fsl,tclk-period  Timer reference clock period in nanoseconds.
+  - fsl,tmr-prsc     Prescaler, divides the output clock.
+  - fsl,tmr-add      Frequency compensation value.
+  - fsl,tmr-fiper1   Fixed interval period pulse generator.
+  - fsl,tmr-fiper2   Fixed interval period pulse generator.
+  - fsl,max-adj      Maximum frequency adjustment in parts per billion.
+
+  These properties set the operational parameters for the PTP
+  clock. You must choose these carefully for the clock to work right.
+  Here is how to figure good values:
+
+  TimerOsc     = system clock               MHz
+  tclk_period  = desired clock period       nanoseconds
+  NominalFreq  = 1000 / tclk_period         MHz
+  FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)
+  tmr_add      = ceil(2^32 / FreqDivRatio)
+  OutputClock  = NominalFreq / tmr_prsc     MHz
+  PulseWidth   = 1 / OutputClock            microseconds
+  FiperFreq1   = desired frequency in Hz
+  FiperDiv1    = 1000000 * OutputClock / FiperFreq1
+  tmr_fiper1   = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
+  max_adj      = 1000000000 * (FreqDivRatio - 1.0) - 1
+
+  The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
+  driver expects that tmr_fiper1 will be correctly set to produce a 1
+  Pulse Per Second (PPS) signal, since this will be offered to the PPS
+  subsystem to synchronize the Linux clock.
+
+Example:
+
+       ptp_clock@24E00 {
+               compatible = "fsl,etsec-ptp";
+               reg = <0x24E00 0xB0>;
+               interrupts = <12 0x8 13 0x8>;
+               interrupt-parent = < &ipic >;
+               fsl,tclk-period = <10>;
+               fsl,tmr-prsc    = <100>;
+               fsl,tmr-add     = <0x999999A4>;
+               fsl,tmr-fiper1  = <0x3B9AC9F6>;
+               fsl,tmr-fiper2  = <0x00018696>;
+               fsl,max-adj     = <659999998>;
+       };
index b22abba..13de64c 100644 (file)
@@ -25,6 +25,8 @@ Other applications are described in the following papers:
                http://xcpu.org/papers/cellfs-talk.pdf
        * PROSE I/O: Using 9p to enable Application Partitions
                http://plan9.escet.urjc.es/iwp9/cready/PROSE_iwp9_2006.pdf
+       * VirtFS: A Virtualization Aware File System pass-through
+               http://goo.gl/3WPDg
 
 USAGE
 =====
@@ -130,31 +132,20 @@ OPTIONS
 RESOURCES
 =========
 
-Our current recommendation is to use Inferno (http://www.vitanuova.com/nferno/index.html)
-as the 9p server.  You can start a 9p server under Inferno by issuing the
-following command:
-   ; styxlisten -A tcp!*!564 export '#U*'
+Protocol specifications are maintained on github:
+http://ericvh.github.com/9p-rfc/
 
-The -A specifies an unauthenticated export.  The 564 is the port # (you may
-have to choose a higher port number if running as a normal user).  The '#U*'
-specifies exporting the root of the Linux name space.  You may specify a
-subset of the namespace by extending the path: '#U*'/tmp would just export
-/tmp.  For more information, see the Inferno manual pages covering styxlisten
-and export.
+9p client and server implementations are listed on
+http://9p.cat-v.org/implementations
 
-A Linux version of the 9p server is now maintained under the npfs project
-on sourceforge (http://sourceforge.net/projects/npfs).  The currently
-maintained version is the single-threaded version of the server (named spfs)
-available from the same SVN repository.
+A 9p2000.L server is being developed by LLNL and can be found
+at http://code.google.com/p/diod/
 
 There are user and developer mailing lists available through the v9fs project
 on sourceforge (http://sourceforge.net/projects/v9fs).
 
-A stand-alone version of the module (which should build for any 2.6 kernel)
-is available via (http://github.com/ericvh/9p-sac/tree/master)
-
-News and other information is maintained on SWiK (http://swik.net/v9fs)
-and the Wiki (http://sf.net/apps/mediawiki/v9fs/index.php).
+News and other information is maintained on a Wiki.
+(http://sf.net/apps/mediawiki/v9fs/index.php).
 
 Bug reports may be issued through the kernel.org bugzilla 
 (http://bugzilla.kernel.org)
index 60740e8..f481780 100644 (file)
@@ -574,6 +574,12 @@ The contents of each smp_affinity file is the same by default:
   > cat /proc/irq/0/smp_affinity
   ffffffff
 
+There is an alternate interface, smp_affinity_list which allows specifying
+a cpu range instead of a bitmask:
+
+  > cat /proc/irq/0/smp_affinity_list
+  1024-1031
+
 The default_smp_affinity mask applies to all non-active IRQs, which are the
 IRQs which have not yet been allocated/activated, and hence which lack a
 /proc/irq/[0-9]* directory.
@@ -583,12 +589,13 @@ reports itself as being attached. This hardware locality information does not
 include information about any possible driver locality preference.
 
 prof_cpu_mask specifies which CPUs are to be profiled by the system wide
-profiler. Default value is ffffffff (all cpus).
+profiler. Default value is ffffffff (all cpus if there are only 32 of them).
 
 The way IRQs are routed is handled by the IO-APIC, and it's Round Robin
 between all the CPUs which are allowed to handle it. As usual the kernel has
 more info than you and does a better job than you, so the defaults are the
-best choice for almost everyone.
+best choice for almost everyone.  [Note this applies only to those IO-APIC's
+that support "Round Robin" interrupt distribution.]
 
 There are  three  more  important subdirectories in /proc: net, scsi, and sys.
 The general  rule  is  that  the  contents,  or  even  the  existence of these
index 7c6624e..5438a2d 100644 (file)
@@ -1777,9 +1777,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 
        nosoftlockup    [KNL] Disable the soft-lockup detector.
 
-       noswapaccount   [KNL] Disable accounting of swap in memory resource
-                       controller. (See Documentation/cgroups/memory.txt)
-
        nosync          [HW,M68K] Disables sync negotiation for all devices.
 
        notsc           [BUGS=X86-32] Disable Time Stamp Counter
index 65f4c79..9c0a80d 100644 (file)
@@ -136,7 +136,7 @@ View the top contending locks:
                              dcache_lock:          1037           1161           0.38          45.32         774.51           6611         243371           0.15         306.48       77387.24
                          &inode->i_mutex:           161            286 18446744073709       62882.54     1244614.55           3653          20598 18446744073709       62318.60     1693822.74
                          &zone->lru_lock:            94             94           0.53           7.33          92.10           4366          32690           0.29          59.81       16350.06
-              &inode->i_data.i_mmap_lock:            79             79           0.40           3.77          53.03          11779          87755           0.28         116.93       29898.44
+              &inode->i_data.i_mmap_mutex:            79             79           0.40           3.77          53.03          11779          87755           0.28         116.93       29898.44
                         &q->__queue_lock:            48             50           0.52          31.62          86.31            774          13131           0.17         113.08       12277.52
                         &rq->rq_lock_key:            43             47           0.74          68.50         170.63           3706          33929           0.22         107.99       17460.62
                       &rq->rq_lock_key#2:            39             46           0.75           6.68          49.03           2979          32292           0.17         125.17       17137.63
diff --git a/Documentation/ptp/ptp.txt b/Documentation/ptp/ptp.txt
new file mode 100644 (file)
index 0000000..ae8fef8
--- /dev/null
@@ -0,0 +1,89 @@
+
+* PTP hardware clock infrastructure for Linux
+
+  This patch set introduces support for IEEE 1588 PTP clocks in
+  Linux. Together with the SO_TIMESTAMPING socket options, this
+  presents a standardized method for developing PTP user space
+  programs, synchronizing Linux with external clocks, and using the
+  ancillary features of PTP hardware clocks.
+
+  A new class driver exports a kernel interface for specific clock
+  drivers and a user space interface. The infrastructure supports a
+  complete set of PTP hardware clock functionality.
+
+  + Basic clock operations
+    - Set time
+    - Get time
+    - Shift the clock by a given offset atomically
+    - Adjust clock frequency
+
+  + Ancillary clock features
+    - One short or periodic alarms, with signal delivery to user program
+    - Time stamp external events
+    - Period output signals configurable from user space
+    - Synchronization of the Linux system time via the PPS subsystem
+
+** PTP hardware clock kernel API
+
+   A PTP clock driver registers itself with the class driver. The
+   class driver handles all of the dealings with user space. The
+   author of a clock driver need only implement the details of
+   programming the clock hardware. The clock driver notifies the class
+   driver of asynchronous events (alarms and external time stamps) via
+   a simple message passing interface.
+
+   The class driver supports multiple PTP clock drivers. In normal use
+   cases, only one PTP clock is needed. However, for testing and
+   development, it can be useful to have more than one clock in a
+   single system, in order to allow performance comparisons.
+
+** PTP hardware clock user space API
+
+   The class driver also creates a character device for each
+   registered clock. User space can use an open file descriptor from
+   the character device as a POSIX clock id and may call
+   clock_gettime, clock_settime, and clock_adjtime.  These calls
+   implement the basic clock operations.
+
+   User space programs may control the clock using standardized
+   ioctls. A program may query, enable, configure, and disable the
+   ancillary clock features. User space can receive time stamped
+   events via blocking read() and poll(). One shot and periodic
+   signals may be configured via the POSIX timer_settime() system
+   call.
+
+** Writing clock drivers
+
+   Clock drivers include include/linux/ptp_clock_kernel.h and register
+   themselves by presenting a 'struct ptp_clock_info' to the
+   registration method. Clock drivers must implement all of the
+   functions in the interface. If a clock does not offer a particular
+   ancillary feature, then the driver should just return -EOPNOTSUPP
+   from those functions.
+
+   Drivers must ensure that all of the methods in interface are
+   reentrant. Since most hardware implementations treat the time value
+   as a 64 bit integer accessed as two 32 bit registers, drivers
+   should use spin_lock_irqsave/spin_unlock_irqrestore to protect
+   against concurrent access. This locking cannot be accomplished in
+   class driver, since the lock may also be needed by the clock
+   driver's interrupt service routine.
+
+** Supported hardware
+
+   + Freescale eTSEC gianfar
+     - 2 Time stamp external triggers, programmable polarity (opt. interrupt)
+     - 2 Alarm registers (optional interrupt)
+     - 3 Periodic signals (optional interrupt)
+
+   + National DP83640
+     - 6 GPIOs programmable as inputs or outputs
+     - 6 GPIOs with dedicated functions (LED/JTAG/clock) can also be
+       used as general inputs or outputs
+     - GPIO inputs can time stamp external triggers
+     - GPIO outputs can produce periodic signals
+     - 1 interrupt pin
+
+   + Intel IXP465
+     - Auxiliary Slave/Master Mode Snapshot (optional interrupt)
+     - Target Time (optional interrupt)
diff --git a/Documentation/ptp/testptp.c b/Documentation/ptp/testptp.c
new file mode 100644 (file)
index 0000000..f59ded0
--- /dev/null
@@ -0,0 +1,381 @@
+/*
+ * PTP 1588 clock support - User space test program
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <errno.h>
+#include <fcntl.h>
+#include <math.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include <sys/timex.h>
+#include <sys/types.h>
+#include <time.h>
+#include <unistd.h>
+
+#include <linux/ptp_clock.h>
+
+#define DEVICE "/dev/ptp0"
+
+#ifndef ADJ_SETOFFSET
+#define ADJ_SETOFFSET 0x0100
+#endif
+
+#ifndef CLOCK_INVALID
+#define CLOCK_INVALID -1
+#endif
+
+/* When glibc offers the syscall, this will go away. */
+#include <sys/syscall.h>
+static int clock_adjtime(clockid_t id, struct timex *tx)
+{
+       return syscall(__NR_clock_adjtime, id, tx);
+}
+
+static clockid_t get_clockid(int fd)
+{
+#define CLOCKFD 3
+#define FD_TO_CLOCKID(fd)      ((~(clockid_t) (fd) << 3) | CLOCKFD)
+
+       return FD_TO_CLOCKID(fd);
+}
+
+static void handle_alarm(int s)
+{
+       printf("received signal %d\n", s);
+}
+
+static int install_handler(int signum, void (*handler)(int))
+{
+       struct sigaction action;
+       sigset_t mask;
+
+       /* Unblock the signal. */
+       sigemptyset(&mask);
+       sigaddset(&mask, signum);
+       sigprocmask(SIG_UNBLOCK, &mask, NULL);
+
+       /* Install the signal handler. */
+       action.sa_handler = handler;
+       action.sa_flags = 0;
+       sigemptyset(&action.sa_mask);
+       sigaction(signum, &action, NULL);
+
+       return 0;
+}
+
+static long ppb_to_scaled_ppm(int ppb)
+{
+       /*
+        * The 'freq' field in the 'struct timex' is in parts per
+        * million, but with a 16 bit binary fractional field.
+        * Instead of calculating either one of
+        *
+        *    scaled_ppm = (ppb / 1000) << 16  [1]
+        *    scaled_ppm = (ppb << 16) / 1000  [2]
+        *
+        * we simply use double precision math, in order to avoid the
+        * truncation in [1] and the possible overflow in [2].
+        */
+       return (long) (ppb * 65.536);
+}
+
+static void usage(char *progname)
+{
+       fprintf(stderr,
+               "usage: %s [options]\n"
+               " -a val     request a one-shot alarm after 'val' seconds\n"
+               " -A val     request a periodic alarm every 'val' seconds\n"
+               " -c         query the ptp clock's capabilities\n"
+               " -d name    device to open\n"
+               " -e val     read 'val' external time stamp events\n"
+               " -f val     adjust the ptp clock frequency by 'val' ppb\n"
+               " -g         get the ptp clock time\n"
+               " -h         prints this message\n"
+               " -p val     enable output with a period of 'val' nanoseconds\n"
+               " -P val     enable or disable (val=1|0) the system clock PPS\n"
+               " -s         set the ptp clock time from the system time\n"
+               " -S         set the system time from the ptp clock time\n"
+               " -t val     shift the ptp clock time by 'val' seconds\n",
+               progname);
+}
+
+int main(int argc, char *argv[])
+{
+       struct ptp_clock_caps caps;
+       struct ptp_extts_event event;
+       struct ptp_extts_request extts_request;
+       struct ptp_perout_request perout_request;
+       struct timespec ts;
+       struct timex tx;
+
+       static timer_t timerid;
+       struct itimerspec timeout;
+       struct sigevent sigevent;
+
+       char *progname;
+       int c, cnt, fd;
+
+       char *device = DEVICE;
+       clockid_t clkid;
+       int adjfreq = 0x7fffffff;
+       int adjtime = 0;
+       int capabilities = 0;
+       int extts = 0;
+       int gettime = 0;
+       int oneshot = 0;
+       int periodic = 0;
+       int perout = -1;
+       int pps = -1;
+       int settime = 0;
+
+       progname = strrchr(argv[0], '/');
+       progname = progname ? 1+progname : argv[0];
+       while (EOF != (c = getopt(argc, argv, "a:A:cd:e:f:ghp:P:sSt:v"))) {
+               switch (c) {
+               case 'a':
+                       oneshot = atoi(optarg);
+                       break;
+               case 'A':
+                       periodic = atoi(optarg);
+                       break;
+               case 'c':
+                       capabilities = 1;
+                       break;
+               case 'd':
+                       device = optarg;
+                       break;
+               case 'e':
+                       extts = atoi(optarg);
+                       break;
+               case 'f':
+                       adjfreq = atoi(optarg);
+                       break;
+               case 'g':
+                       gettime = 1;
+                       break;
+               case 'p':
+                       perout = atoi(optarg);
+                       break;
+               case 'P':
+                       pps = atoi(optarg);
+                       break;
+               case 's':
+                       settime = 1;
+                       break;
+               case 'S':
+                       settime = 2;
+                       break;
+               case 't':
+                       adjtime = atoi(optarg);
+                       break;
+               case 'h':
+                       usage(progname);
+                       return 0;
+               case '?':
+               default:
+                       usage(progname);
+                       return -1;
+               }
+       }
+
+       fd = open(device, O_RDWR);
+       if (fd < 0) {
+               fprintf(stderr, "opening %s: %s\n", device, strerror(errno));
+               return -1;
+       }
+
+       clkid = get_clockid(fd);
+       if (CLOCK_INVALID == clkid) {
+               fprintf(stderr, "failed to read clock id\n");
+               return -1;
+       }
+
+       if (capabilities) {
+               if (ioctl(fd, PTP_CLOCK_GETCAPS, &caps)) {
+                       perror("PTP_CLOCK_GETCAPS");
+               } else {
+                       printf("capabilities:\n"
+                              "  %d maximum frequency adjustment (ppb)\n"
+                              "  %d programmable alarms\n"
+                              "  %d external time stamp channels\n"
+                              "  %d programmable periodic signals\n"
+                              "  %d pulse per second\n",
+                              caps.max_adj,
+                              caps.n_alarm,
+                              caps.n_ext_ts,
+                              caps.n_per_out,
+                              caps.pps);
+               }
+       }
+
+       if (0x7fffffff != adjfreq) {
+               memset(&tx, 0, sizeof(tx));
+               tx.modes = ADJ_FREQUENCY;
+               tx.freq = ppb_to_scaled_ppm(adjfreq);
+               if (clock_adjtime(clkid, &tx)) {
+                       perror("clock_adjtime");
+               } else {
+                       puts("frequency adjustment okay");
+               }
+       }
+
+       if (adjtime) {
+               memset(&tx, 0, sizeof(tx));
+               tx.modes = ADJ_SETOFFSET;
+               tx.time.tv_sec = adjtime;
+               tx.time.tv_usec = 0;
+               if (clock_adjtime(clkid, &tx) < 0) {
+                       perror("clock_adjtime");
+               } else {
+                       puts("time shift okay");
+               }
+       }
+
+       if (gettime) {
+               if (clock_gettime(clkid, &ts)) {
+                       perror("clock_gettime");
+               } else {
+                       printf("clock time: %ld.%09ld or %s",
+                              ts.tv_sec, ts.tv_nsec, ctime(&ts.tv_sec));
+               }
+       }
+
+       if (settime == 1) {
+               clock_gettime(CLOCK_REALTIME, &ts);
+               if (clock_settime(clkid, &ts)) {
+                       perror("clock_settime");
+               } else {
+                       puts("set time okay");
+               }
+       }
+
+       if (settime == 2) {
+               clock_gettime(clkid, &ts);
+               if (clock_settime(CLOCK_REALTIME, &ts)) {
+                       perror("clock_settime");
+               } else {
+                       puts("set time okay");
+               }
+       }
+
+       if (extts) {
+               memset(&extts_request, 0, sizeof(extts_request));
+               extts_request.index = 0;
+               extts_request.flags = PTP_ENABLE_FEATURE;
+               if (ioctl(fd, PTP_EXTTS_REQUEST, &extts_request)) {
+                       perror("PTP_EXTTS_REQUEST");
+                       extts = 0;
+               } else {
+                       puts("external time stamp request okay");
+               }
+               for (; extts; extts--) {
+                       cnt = read(fd, &event, sizeof(event));
+                       if (cnt != sizeof(event)) {
+                               perror("read");
+                               break;
+                       }
+                       printf("event index %u at %lld.%09u\n", event.index,
+                              event.t.sec, event.t.nsec);
+                       fflush(stdout);
+               }
+               /* Disable the feature again. */
+               extts_request.flags = 0;
+               if (ioctl(fd, PTP_EXTTS_REQUEST, &extts_request)) {
+                       perror("PTP_EXTTS_REQUEST");
+               }
+       }
+
+       if (oneshot) {
+               install_handler(SIGALRM, handle_alarm);
+               /* Create a timer. */
+               sigevent.sigev_notify = SIGEV_SIGNAL;
+               sigevent.sigev_signo = SIGALRM;
+               if (timer_create(clkid, &sigevent, &timerid)) {
+                       perror("timer_create");
+                       return -1;
+               }
+               /* Start the timer. */
+               memset(&timeout, 0, sizeof(timeout));
+               timeout.it_value.tv_sec = oneshot;
+               if (timer_settime(timerid, 0, &timeout, NULL)) {
+                       perror("timer_settime");
+                       return -1;
+               }
+               pause();
+               timer_delete(timerid);
+       }
+
+       if (periodic) {
+               install_handler(SIGALRM, handle_alarm);
+               /* Create a timer. */
+               sigevent.sigev_notify = SIGEV_SIGNAL;
+               sigevent.sigev_signo = SIGALRM;
+               if (timer_create(clkid, &sigevent, &timerid)) {
+                       perror("timer_create");
+                       return -1;
+               }
+               /* Start the timer. */
+               memset(&timeout, 0, sizeof(timeout));
+               timeout.it_interval.tv_sec = periodic;
+               timeout.it_value.tv_sec = periodic;
+               if (timer_settime(timerid, 0, &timeout, NULL)) {
+                       perror("timer_settime");
+                       return -1;
+               }
+               while (1) {
+                       pause();
+               }
+               timer_delete(timerid);
+       }
+
+       if (perout >= 0) {
+               if (clock_gettime(clkid, &ts)) {
+                       perror("clock_gettime");
+                       return -1;
+               }
+               memset(&perout_request, 0, sizeof(perout_request));
+               perout_request.index = 0;
+               perout_request.start.sec = ts.tv_sec + 2;
+               perout_request.start.nsec = 0;
+               perout_request.period.sec = 0;
+               perout_request.period.nsec = perout;
+               if (ioctl(fd, PTP_PEROUT_REQUEST, &perout_request)) {
+                       perror("PTP_PEROUT_REQUEST");
+               } else {
+                       puts("periodic output request okay");
+               }
+       }
+
+       if (pps != -1) {
+               int enable = pps ? 1 : 0;
+               if (ioctl(fd, PTP_ENABLE_PPS, enable)) {
+                       perror("PTP_ENABLE_PPS");
+               } else {
+                       puts("pps for system time request okay");
+               }
+       }
+
+       close(fd);
+       return 0;
+}
diff --git a/Documentation/ptp/testptp.mk b/Documentation/ptp/testptp.mk
new file mode 100644 (file)
index 0000000..4ef2d97
--- /dev/null
@@ -0,0 +1,33 @@
+# PTP 1588 clock support - User space test program
+#
+# Copyright (C) 2010 OMICRON electronics GmbH
+#
+#  This program is free software; you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; either version 2 of the License, or
+#  (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+CC        = $(CROSS_COMPILE)gcc
+INC       = -I$(KBUILD_OUTPUT)/usr/include
+CFLAGS    = -Wall $(INC)
+LDLIBS    = -lrt
+PROGS     = testptp
+
+all: $(PROGS)
+
+testptp: testptp.o
+
+clean:
+       rm -f testptp.o
+
+distclean: clean
+       rm -f $(PROGS)
index 9b7e190..5d0fc8b 100644 (file)
   forge.net/>  and explains these in detail, as well as
   some other issues.
 
+  There is also a related point-to-point only "ucast" transport.
+  This is useful when your network does not support multicast, and
+  all network connections are simple point to point links.
+
+  The full set of command line options for this transport are
+
+
+       ethn=ucast,ethernet address,remote address,listen port,remote port
+
+
 
 
   6\b6.\b.6\b6.\b.  T\bTU\bUN\bN/\b/T\bTA\bAP\bP w\bwi\bit\bth\bh t\bth\bhe\be u\bum\bml\bl_\b_n\bne\bet\bt h\bhe\bel\blp\bpe\ber\br
index 25fadb4..f61228b 100644 (file)
@@ -66,7 +66,7 @@ in some cases it is not really needed. Eg, vm_start is modified by
 expand_stack(), it is hard to come up with a destructive scenario without 
 having the vmlist protection in this case.
 
-The page_table_lock nests with the inode i_mmap_lock and the kmem cache
+The page_table_lock nests with the inode i_mmap_mutex and the kmem cache
 c_spinlock spinlocks.  This is okay, since the kmem code asks for pages after
 dropping c_spinlock.  The page_table_lock also nests with pagecache_lock and
 pagemap_lru_lock spinlocks, and no code asks for memory with these locks
index 88a5bef..a26c9ee 100644 (file)
@@ -287,35 +287,35 @@ F:        sound/pci/ad1889.*
 
 AD525X ANALOG DEVICES DIGITAL POTENTIOMETERS DRIVER
 M:     Michael Hennerich <michael.hennerich@analog.com>
-L:     device-driver-devel@blackfin.uclinux.org
+L:     device-drivers-devel@blackfin.uclinux.org
 W:     http://wiki.analog.com/AD5254
 S:     Supported
 F:     drivers/misc/ad525x_dpot.c
 
 AD5398 CURRENT REGULATOR DRIVER (AD5398/AD5821)
 M:     Michael Hennerich <michael.hennerich@analog.com>
-L:     device-driver-devel@blackfin.uclinux.org
+L:     device-drivers-devel@blackfin.uclinux.org
 W:     http://wiki.analog.com/AD5398
 S:     Supported
 F:     drivers/regulator/ad5398.c
 
 AD714X CAPACITANCE TOUCH SENSOR DRIVER (AD7142/3/7/8/7A)
 M:     Michael Hennerich <michael.hennerich@analog.com>
-L:     device-driver-devel@blackfin.uclinux.org
+L:     device-drivers-devel@blackfin.uclinux.org
 W:     http://wiki.analog.com/AD7142
 S:     Supported
 F:     drivers/input/misc/ad714x.c
 
 AD7877 TOUCHSCREEN DRIVER
 M:     Michael Hennerich <michael.hennerich@analog.com>
-L:     device-driver-devel@blackfin.uclinux.org
+L:     device-drivers-devel@blackfin.uclinux.org
 W:     http://wiki.analog.com/AD7877
 S:     Supported
 F:     drivers/input/touchscreen/ad7877.c
 
 AD7879 TOUCHSCREEN DRIVER (AD7879/AD7889)
 M:     Michael Hennerich <michael.hennerich@analog.com>
-L:     device-driver-devel@blackfin.uclinux.org
+L:     device-drivers-devel@blackfin.uclinux.org
 W:     http://wiki.analog.com/AD7879
 S:     Supported
 F:     drivers/input/touchscreen/ad7879.c
@@ -341,7 +341,7 @@ F:  drivers/net/wireless/adm8211.*
 
 ADP5520 BACKLIGHT DRIVER WITH IO EXPANDER (ADP5520/ADP5501)
 M:     Michael Hennerich <michael.hennerich@analog.com>
-L:     device-driver-devel@blackfin.uclinux.org
+L:     device-drivers-devel@blackfin.uclinux.org
 W:     http://wiki.analog.com/ADP5520
 S:     Supported
 F:     drivers/mfd/adp5520.c
@@ -352,7 +352,7 @@ F:  drivers/input/keyboard/adp5520-keys.c
 
 ADP5588 QWERTY KEYPAD AND IO EXPANDER DRIVER (ADP5588/ADP5587)
 M:     Michael Hennerich <michael.hennerich@analog.com>
-L:     device-driver-devel@blackfin.uclinux.org
+L:     device-drivers-devel@blackfin.uclinux.org
 W:     http://wiki.analog.com/ADP5588
 S:     Supported
 F:     drivers/input/keyboard/adp5588-keys.c
@@ -360,7 +360,7 @@ F:  drivers/gpio/adp5588-gpio.c
 
 ADP8860 BACKLIGHT DRIVER (ADP8860/ADP8861/ADP8863)
 M:     Michael Hennerich <michael.hennerich@analog.com>
-L:     device-driver-devel@blackfin.uclinux.org
+L:     device-drivers-devel@blackfin.uclinux.org
 W:     http://wiki.analog.com/ADP8860
 S:     Supported
 F:     drivers/video/backlight/adp8860_bl.c
@@ -387,7 +387,7 @@ F:  drivers/hwmon/adt7475.c
 
 ADXL34X THREE-AXIS DIGITAL ACCELEROMETER DRIVER (ADXL345/ADXL346)
 M:     Michael Hennerich <michael.hennerich@analog.com>
-L:     device-driver-devel@blackfin.uclinux.org
+L:     device-drivers-devel@blackfin.uclinux.org
 W:     http://wiki.analog.com/ADXL345
 S:     Supported
 F:     drivers/input/misc/adxl34x.c
@@ -533,7 +533,7 @@ S:  Maintained
 F:     drivers/infiniband/hw/amso1100/
 
 ANALOG DEVICES INC ASOC CODEC DRIVERS
-L:     device-driver-devel@blackfin.uclinux.org
+L:     device-drivers-devel@blackfin.uclinux.org
 L:     alsa-devel@alsa-project.org (moderated for non-subscribers)
 W:     http://wiki.analog.com/
 S:     Supported
@@ -2041,9 +2041,8 @@ F:        net/ax25/ax25_timer.c
 F:     net/ax25/sysctl_net_ax25.c
 
 DAVICOM FAST ETHERNET (DMFE) NETWORK DRIVER
-M:     Tobias Ringstrom <tori@unhappy.mine.nu>
 L:     netdev@vger.kernel.org
-S:     Maintained
+S:     Orphan
 F:     Documentation/networking/dmfe.txt
 F:     drivers/net/tulip/dmfe.c
 
@@ -3905,7 +3904,6 @@ F:        drivers/*/*/*pasemi*
 LINUX SECURITY MODULE (LSM) FRAMEWORK
 M:     Chris Wright <chrisw@sous-sol.org>
 L:     linux-security-module@vger.kernel.org
-T:     git git://git.kernel.org/pub/scm/linux/kernel/git/chrisw/lsm-2.6.git
 S:     Supported
 
 LIS3LV02D ACCELEROMETER DRIVER
index 6b73d1e..529d93f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -220,6 +220,14 @@ ifeq ($(ARCH),sh64)
        SRCARCH := sh
 endif
 
+# Additional ARCH settings for tile
+ifeq ($(ARCH),tilepro)
+       SRCARCH := tile
+endif
+ifeq ($(ARCH),tilegx)
+       SRCARCH := tile
+endif
+
 # Where to locate arch specific headers
 hdr-arch  := $(SRCARCH)
 
@@ -1009,7 +1017,8 @@ include/generated/utsrelease.h: include/config/kernel.release FORCE
 
 PHONY += headerdep
 headerdep:
-       $(Q)find include/ -name '*.h' | xargs --max-args 1 scripts/headerdep.pl
+       $(Q)find $(srctree)/include/ -name '*.h' | xargs --max-args 1 \
+       $(srctree)/scripts/headerdep.pl -I$(srctree)/include
 
 # ---------------------------------------------------------------------------
 
@@ -1417,13 +1426,15 @@ tags TAGS cscope gtags: FORCE
 # Scripts to check various things for consistency
 # ---------------------------------------------------------------------------
 
+PHONY += includecheck versioncheck coccicheck namespacecheck export_report
+
 includecheck:
-       find * $(RCS_FIND_IGNORE) \
+       find $(srctree)/* $(RCS_FIND_IGNORE) \
                -name '*.[hcS]' -type f -print | sort \
                | xargs $(PERL) -w $(srctree)/scripts/checkincludes.pl
 
 versioncheck:
-       find * $(RCS_FIND_IGNORE) \
+       find $(srctree)/* $(RCS_FIND_IGNORE) \
                -name '*.[hcS]' -type f -print | sort \
                | xargs $(PERL) -w $(srctree)/scripts/checkversion.pl
 
index 8d24bac..26b0e23 100644 (file)
@@ -175,4 +175,7 @@ config HAVE_ARCH_JUMP_LABEL
 config HAVE_ARCH_MUTEX_CPU_RELAX
        bool
 
+config HAVE_RCU_TABLE_FREE
+       bool
+
 source "kernel/gcov/Kconfig"
index 9808998..e3a8277 100644 (file)
@@ -12,6 +12,7 @@ config ALPHA
        select GENERIC_IRQ_PROBE
        select AUTO_IRQ_AFFINITY if SMP
        select GENERIC_IRQ_SHOW
+       select ARCH_WANT_OPTIONAL_GPIOLIB
        help
          The Alpha is a 64-bit general-purpose processor designed and
          marketed by the Digital Equipment Corporation of blessed memory,
@@ -51,6 +52,9 @@ config GENERIC_CALIBRATE_DELAY
 config GENERIC_CMOS_UPDATE
         def_bool y
 
+config GENERIC_GPIO
+       def_bool y
+
 config ZONE_DMA
        bool
        default y
diff --git a/arch/alpha/include/asm/gpio.h b/arch/alpha/include/asm/gpio.h
new file mode 100644 (file)
index 0000000..7dc6a63
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ * Generic GPIO API implementation for Alpha.
+ *
+ * A stright copy of that for PowerPC which was:
+ *
+ * Copyright (c) 2007-2008  MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _ASM_ALPHA_GPIO_H
+#define _ASM_ALPHA_GPIO_H
+
+#include <linux/errno.h>
+#include <asm-generic/gpio.h>
+
+#ifdef CONFIG_GPIOLIB
+
+/*
+ * We don't (yet) implement inlined/rapid versions for on-chip gpios.
+ * Just call gpiolib.
+ */
+static inline int gpio_get_value(unsigned int gpio)
+{
+       return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int value)
+{
+       __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned int gpio)
+{
+       return __gpio_cansleep(gpio);
+}
+
+static inline int gpio_to_irq(unsigned int gpio)
+{
+       return __gpio_to_irq(gpio);
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+       return -EINVAL;
+}
+
+#endif /* CONFIG_GPIOLIB */
+
+#endif /* _ASM_ALPHA_GPIO_H */
index 3f390e8..c46e714 100644 (file)
@@ -39,8 +39,6 @@ struct cpuinfo_alpha {
 
 extern struct cpuinfo_alpha cpu_data[NR_CPUS];
 
-#define PROC_CHANGE_PENALTY     20
-
 #define hard_smp_processor_id()        __hard_smp_processor_id()
 #define raw_smp_processor_id() (current_thread_info()->cpu)
 
index 3ec3506..838eac1 100644 (file)
@@ -121,7 +121,7 @@ common_shutdown_1(void *generic_ptr)
        /* Wait for the secondaries to halt. */
        set_cpu_present(boot_cpuid, false);
        set_cpu_possible(boot_cpuid, false);
-       while (cpus_weight(cpu_present_map))
+       while (cpumask_weight(cpu_present_mask))
                barrier();
 #endif
 
index edbddcb..cc0fd86 100644 (file)
@@ -1257,7 +1257,7 @@ show_cpuinfo(struct seq_file *f, void *slot)
 #ifdef CONFIG_SMP
        seq_printf(f, "cpus active\t\t: %u\n"
                      "cpu active mask\t\t: %016lx\n",
-                      num_online_cpus(), cpus_addr(cpu_possible_map)[0]);
+                      num_online_cpus(), cpumask_bits(cpu_possible_mask)[0]);
 #endif
 
        show_cache_size (f, "L1 Icache", alpha_l1i_cacheshape);
index 5a621c6..d739703 100644 (file)
@@ -451,7 +451,7 @@ setup_smp(void)
        }
 
        printk(KERN_INFO "SMP: %d CPUs probed -- cpu_present_map = %lx\n",
-              smp_num_probed, cpu_present_map.bits[0]);
+              smp_num_probed, cpumask_bits(cpu_present_mask)[0]);
 }
 
 /*
@@ -629,8 +629,9 @@ smp_send_reschedule(int cpu)
 void
 smp_send_stop(void)
 {
-       cpumask_t to_whom = cpu_possible_map;
-       cpu_clear(smp_processor_id(), to_whom);
+       cpumask_t to_whom;
+       cpumask_copy(&to_whom, cpu_possible_mask);
+       cpumask_clear_cpu(smp_processor_id(), &to_whom);
 #ifdef DEBUG_IPI_MSG
        if (hard_smp_processor_id() != boot_cpu_id)
                printk(KERN_WARNING "smp_send_stop: Not on boot cpu.\n");
index 5ac00fd..f885682 100644 (file)
@@ -140,7 +140,7 @@ cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
 
        for (cpu = 0; cpu < 4; cpu++) {
                unsigned long aff = cpu_irq_affinity[cpu];
-               if (cpu_isset(cpu, affinity))
+               if (cpumask_test_cpu(cpu, &affinity))
                        aff |= 1UL << irq;
                else
                        aff &= ~(1UL << irq);
index fea0e46..6994407 100644 (file)
@@ -65,10 +65,11 @@ titan_update_irq_hw(unsigned long mask)
        register int bcpu = boot_cpuid;
 
 #ifdef CONFIG_SMP
-       cpumask_t cpm = cpu_present_map;
+       cpumask_t cpm;
        volatile unsigned long *dim0, *dim1, *dim2, *dim3;
        unsigned long mask0, mask1, mask2, mask3, dummy;
 
+       cpumask_copy(&cpm, cpu_present_mask);
        mask &= ~isa_enable;
        mask0 = mask & titan_cpu_irq_affinity[0];
        mask1 = mask & titan_cpu_irq_affinity[1];
@@ -84,10 +85,10 @@ titan_update_irq_hw(unsigned long mask)
        dim1 = &cchip->dim1.csr;
        dim2 = &cchip->dim2.csr;
        dim3 = &cchip->dim3.csr;
-       if (!cpu_isset(0, cpm)) dim0 = &dummy;
-       if (!cpu_isset(1, cpm)) dim1 = &dummy;
-       if (!cpu_isset(2, cpm)) dim2 = &dummy;
-       if (!cpu_isset(3, cpm)) dim3 = &dummy;
+       if (!cpumask_test_cpu(0, &cpm)) dim0 = &dummy;
+       if (!cpumask_test_cpu(1, &cpm)) dim1 = &dummy;
+       if (!cpumask_test_cpu(2, &cpm)) dim2 = &dummy;
+       if (!cpumask_test_cpu(3, &cpm)) dim3 = &dummy;
 
        *dim0 = mask0;
        *dim1 = mask1;
@@ -137,7 +138,7 @@ titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
        int cpu;
 
        for (cpu = 0; cpu < 4; cpu++) {
-               if (cpu_isset(cpu, affinity))
+               if (cpumask_test_cpu(cpu, &affinity))
                        titan_cpu_irq_affinity[cpu] |= 1UL << irq;
                else
                        titan_cpu_irq_affinity[cpu] &= ~(1UL << irq);
index 86425ab..69d0c57 100644 (file)
@@ -32,8 +32,6 @@
 #include <asm/console.h>
 #include <asm/tlb.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 extern void die_if_kernel(char *,struct pt_regs *,long);
 
 static struct pcb_struct original_pcb;
index 7b2c56d..3973ae3 100644 (file)
@@ -313,6 +313,7 @@ void __init paging_init(void)
                        zones_size[ZONE_DMA] = dma_local_pfn;
                        zones_size[ZONE_NORMAL] = (end_pfn - start_pfn) - dma_local_pfn;
                }
+               node_set_state(nid, N_NORMAL_MEMORY);
                free_area_init_node(nid, zones_size, start_pfn, NULL);
        }
 
index 03d01d7..81cbe40 100644 (file)
@@ -63,13 +63,6 @@ config DEBUG_USER
              8 - SIGSEGV faults
             16 - SIGBUS faults
 
-config DEBUG_STACK_USAGE
-       bool "Enable stack utilization instrumentation"
-       depends on DEBUG_KERNEL
-       help
-         Enables the display of the minimum amount of free stack which each
-         task has ever had available in the sysrq-T output.
-
 # These options are only for real kernel hackers who want to get their hands dirty.
 config DEBUG_LL
        bool "Kernel low-level debugging functions"
index a87664f..d2b514f 100644 (file)
 
 #define raw_smp_processor_id() (current_thread_info()->cpu)
 
-/*
- * at the moment, there's not a big penalty for changing CPUs
- * (the >big< penalty is running SMP in the first place)
- */
-#define PROC_CHANGE_PENALTY            15
-
 struct seq_file;
 
 /*
index 82dfe5d..265f908 100644 (file)
  */
 #if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7)
 #define tlb_fast_mode(tlb)     0
-#define FREE_PTE_NR            500
 #else
 #define tlb_fast_mode(tlb)     1
-#define FREE_PTE_NR            0
 #endif
 
+#define MMU_GATHER_BUNDLE      8
+
 /*
  * TLB handling.  This allows us to remove pages from the page
  * tables, and efficiently handle the TLB issues.
@@ -58,7 +58,9 @@ struct mmu_gather {
        unsigned long           range_start;
        unsigned long           range_end;
        unsigned int            nr;
-       struct page             *pages[FREE_PTE_NR];
+       unsigned int            max;
+       struct page             **pages;
+       struct page             *local[MMU_GATHER_BUNDLE];
 };
 
 DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
@@ -97,26 +99,37 @@ static inline void tlb_add_flush(struct mmu_gather *tlb, unsigned long addr)
        }
 }
 
+static inline void __tlb_alloc_page(struct mmu_gather *tlb)
+{
+       unsigned long addr = __get_free_pages(GFP_NOWAIT | __GFP_NOWARN, 0);
+
+       if (addr) {
+               tlb->pages = (void *)addr;
+               tlb->max = PAGE_SIZE / sizeof(struct page *);
+       }
+}
+
 static inline void tlb_flush_mmu(struct mmu_gather *tlb)
 {
        tlb_flush(tlb);
        if (!tlb_fast_mode(tlb)) {
                free_pages_and_swap_cache(tlb->pages, tlb->nr);
                tlb->nr = 0;
+               if (tlb->pages == tlb->local)
+                       __tlb_alloc_page(tlb);
        }
 }
 
-static inline struct mmu_gather *
-tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
+static inline void
+tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int fullmm)
 {
-       struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-
        tlb->mm = mm;
-       tlb->fullmm = full_mm_flush;
+       tlb->fullmm = fullmm;
        tlb->vma = NULL;
+       tlb->max = ARRAY_SIZE(tlb->local);
+       tlb->pages = tlb->local;
        tlb->nr = 0;
-
-       return tlb;
+       __tlb_alloc_page(tlb);
 }
 
 static inline void
@@ -127,7 +140,8 @@ tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
        /* keep the page table cache within bounds */
        check_pgt_cache();
 
-       put_cpu_var(mmu_gathers);
+       if (tlb->pages != tlb->local)
+               free_pages((unsigned long)tlb->pages, 0);
 }
 
 /*
@@ -162,15 +176,22 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
                tlb_flush(tlb);
 }
 
-static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
 {
        if (tlb_fast_mode(tlb)) {
                free_page_and_swap_cache(page);
-       } else {
-               tlb->pages[tlb->nr++] = page;
-               if (tlb->nr >= FREE_PTE_NR)
-                       tlb_flush_mmu(tlb);
+               return 1; /* avoid calling tlb_flush_mmu */
        }
+
+       tlb->pages[tlb->nr++] = page;
+       VM_BUG_ON(tlb->nr > tlb->max);
+       return tlb->max - tlb->nr;
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+       if (!__tlb_remove_page(tlb, page))
+               tlb_flush_mmu(tlb);
 }
 
 static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
new file mode 100644 (file)
index 0000000..292d55e
--- /dev/null
@@ -0,0 +1,78 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _IXP46X_TS_H_
+#define _IXP46X_TS_H_
+
+#define DEFAULT_ADDEND 0xF0000029
+#define TICKS_NS_SHIFT 4
+
+struct ixp46x_channel_ctl {
+       u32 ch_control;  /* 0x40 Time Synchronization Channel Control */
+       u32 ch_event;    /* 0x44 Time Synchronization Channel Event */
+       u32 tx_snap_lo;  /* 0x48 Transmit Snapshot Low Register */
+       u32 tx_snap_hi;  /* 0x4C Transmit Snapshot High Register */
+       u32 rx_snap_lo;  /* 0x50 Receive Snapshot Low Register */
+       u32 rx_snap_hi;  /* 0x54 Receive Snapshot High Register */
+       u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
+       u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
+};
+
+struct ixp46x_ts_regs {
+       u32 control;     /* 0x00 Time Sync Control Register */
+       u32 event;       /* 0x04 Time Sync Event Register */
+       u32 addend;      /* 0x08 Time Sync Addend Register */
+       u32 accum;       /* 0x0C Time Sync Accumulator Register */
+       u32 test;        /* 0x10 Time Sync Test Register */
+       u32 unused;      /* 0x14 */
+       u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
+       u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
+       u32 systime_lo;  /* 0x20 SystemTime_Low Register */
+       u32 systime_hi;  /* 0x24 SystemTime_High Register */
+       u32 trgt_lo;     /* 0x28 TargetTime_Low Register */
+       u32 trgt_hi;     /* 0x2C TargetTime_High Register */
+       u32 asms_lo;     /* 0x30 Auxiliary Slave Mode Snapshot Low  */
+       u32 asms_hi;     /* 0x34 Auxiliary Slave Mode Snapshot High */
+       u32 amms_lo;     /* 0x38 Auxiliary Master Mode Snapshot Low */
+       u32 amms_hi;     /* 0x3C Auxiliary Master Mode Snapshot High */
+
+       struct ixp46x_channel_ctl channel[3];
+};
+
+/* 0x00 Time Sync Control Register Bits */
+#define TSCR_AMM (1<<3)
+#define TSCR_ASM (1<<2)
+#define TSCR_TTM (1<<1)
+#define TSCR_RST (1<<0)
+
+/* 0x04 Time Sync Event Register Bits */
+#define TSER_SNM (1<<3)
+#define TSER_SNS (1<<2)
+#define TTIPEND  (1<<1)
+
+/* 0x40 Time Synchronization Channel Control Register Bits */
+#define MASTER_MODE   (1<<0)
+#define TIMESTAMP_ALL (1<<1)
+
+/* 0x44 Time Synchronization Channel Event Register Bits */
+#define TX_SNAPSHOT_LOCKED (1<<0)
+#define RX_SNAPSHOT_LOCKED (1<<1)
+
+#endif
index 9afd087..23244cd 100644 (file)
@@ -37,8 +37,8 @@
 #include <plat/common.h>
 #include <plat/dma.h>
 #include <plat/gpmc.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include <plat/gpmc-smc91x.h>
 
index 56702c5..93edd7f 100644 (file)
@@ -36,7 +36,7 @@
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include <plat/omap4-keypad.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
 
 #include "mux.h"
 #include "hsmmc.h"
@@ -680,6 +680,15 @@ static struct omap_dss_device sdp4430_hdmi_device = {
        .name = "hdmi",
        .driver_name = "hdmi_panel",
        .type = OMAP_DISPLAY_TYPE_HDMI,
+       .clocks = {
+               .dispc  = {
+                       .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
+               },
+               .hdmi   = {
+                       .regn   = 15,
+                       .regm2  = 1,
+               },
+       },
        .platform_enable = sdp4430_panel_enable_hdmi,
        .platform_disable = sdp4430_panel_disable_hdmi,
        .channel = OMAP_DSS_CHANNEL_DIGIT,
index ce7d5e6..ff8c59b 100644 (file)
@@ -34,8 +34,8 @@
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include "mux.h"
 #include "control.h"
index 02a12b4..9340f6a 100644 (file)
@@ -45,8 +45,8 @@
 #include <plat/nand.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 #include <plat/mcspi.h>
 
 #include <mach/hardware.h>
index 65f9fde..1d1b56a 100644 (file)
@@ -45,8 +45,8 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include <plat/mcspi.h>
 #include <linux/input/matrix_keypad.h>
index 34cf982..3da64d3 100644 (file)
@@ -31,8 +31,8 @@
 #include <plat/common.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 #include <plat/onenand.h>
 
 #include "mux.h"
index 33007fd..97750d4 100644 (file)
@@ -41,8 +41,8 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
index 5a1a916..7f94ccc 100644 (file)
@@ -44,8 +44,8 @@
 #include <plat/usb.h>
 #include <plat/common.h>
 #include <plat/mcspi.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
index 07dba88..1db1549 100644 (file)
@@ -46,7 +46,7 @@
 #include <mach/hardware.h>
 #include <plat/mcspi.h>
 #include <plat/usb.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
 #include <plat/nand.h>
 
 #include "mux.h"
index a6e0b91..a72c90a 100644 (file)
@@ -39,8 +39,8 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include <plat/mcspi.h>
 #include <linux/input/matrix_keypad.h>
index f3a7b10..e4973ac 100644 (file)
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
 
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/usb.h>
 #include <plat/mmc.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omap-panel-generic-dpi.h>
 #include "timer-gp.h"
 
 #include "hsmmc.h"
index 59ca333..9d192ff 100644 (file)
@@ -43,8 +43,8 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 #include <mach/gpio.h>
 #include <plat/gpmc.h>
 #include <mach/hardware.h>
index 89a66db..2df10b6 100644 (file)
@@ -15,7 +15,7 @@
 #include <linux/spi/spi.h>
 #include <linux/mm.h>
 #include <asm/mach-types.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
 #include <plat/vram.h>
 #include <plat/mcspi.h>
 
index 37b84c2..60e8645 100644 (file)
@@ -15,7 +15,7 @@
 #include <linux/i2c/twl.h>
 #include <linux/spi/spi.h>
 #include <plat/mcspi.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
 
 #define LCD_PANEL_RESET_GPIO_PROD      96
 #define LCD_PANEL_RESET_GPIO_PILOT     55
index 256d23f..543fcb8 100644 (file)
@@ -22,7 +22,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 
-#include <plat/display.h>
+#include <video/omapdss.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 
@@ -56,37 +56,58 @@ static bool opt_clock_available(const char *clk_role)
        return false;
 }
 
+struct omap_dss_hwmod_data {
+       const char *oh_name;
+       const char *dev_name;
+       const int id;
+};
+
+static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
+       { "dss_core", "omapdss_dss", -1 },
+       { "dss_dispc", "omapdss_dispc", -1 },
+       { "dss_rfbi", "omapdss_rfbi", -1 },
+       { "dss_venc", "omapdss_venc", -1 },
+};
+
+static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
+       { "dss_core", "omapdss_dss", -1 },
+       { "dss_dispc", "omapdss_dispc", -1 },
+       { "dss_rfbi", "omapdss_rfbi", -1 },
+       { "dss_venc", "omapdss_venc", -1 },
+       { "dss_dsi1", "omapdss_dsi1", -1 },
+};
+
+static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
+       { "dss_core", "omapdss_dss", -1 },
+       { "dss_dispc", "omapdss_dispc", -1 },
+       { "dss_rfbi", "omapdss_rfbi", -1 },
+       { "dss_venc", "omapdss_venc", -1 },
+       { "dss_dsi1", "omapdss_dsi1", -1 },
+       { "dss_dsi2", "omapdss_dsi2", -1 },
+       { "dss_hdmi", "omapdss_hdmi", -1 },
+};
+
 int __init omap_display_init(struct omap_dss_board_info *board_data)
 {
        int r = 0;
        struct omap_hwmod *oh;
        struct omap_device *od;
-       int i;
+       int i, oh_count;
        struct omap_display_platform_data pdata;
-
-       /*
-        * omap: valid DSS hwmod names
-        * omap2,3,4: dss_core, dss_dispc, dss_rfbi, dss_venc
-        * omap3,4: dss_dsi1
-        * omap4: dss_dsi2, dss_hdmi
-        */
-       char *oh_name[] = { "dss_core", "dss_dispc", "dss_rfbi", "dss_venc",
-               "dss_dsi1", "dss_dsi2", "dss_hdmi" };
-       char *dev_name[] = { "omapdss_dss", "omapdss_dispc", "omapdss_rfbi",
-               "omapdss_venc", "omapdss_dsi1", "omapdss_dsi2",
-               "omapdss_hdmi" };
-       int oh_count;
+       const struct omap_dss_hwmod_data *curr_dss_hwmod;
 
        memset(&pdata, 0, sizeof(pdata));
 
-       if (cpu_is_omap24xx())
-               oh_count = ARRAY_SIZE(oh_name) - 3;
-               /* last 3 hwmod dev in oh_name are not available for omap2 */
-       else if (cpu_is_omap44xx())
-               oh_count = ARRAY_SIZE(oh_name);
-       else
-               oh_count = ARRAY_SIZE(oh_name) - 2;
-               /* last 2 hwmod dev in oh_name are not available for omap3 */
+       if (cpu_is_omap24xx()) {
+               curr_dss_hwmod = omap2_dss_hwmod_data;
+               oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
+       } else if (cpu_is_omap34xx()) {
+               curr_dss_hwmod = omap3_dss_hwmod_data;
+               oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
+       } else {
+               curr_dss_hwmod = omap4_dss_hwmod_data;
+               oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
+       }
 
        /* opt_clks are always associated with dss hwmod */
        oh_core = omap_hwmod_lookup("dss_core");
@@ -100,19 +121,21 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
        pdata.opt_clock_available = opt_clock_available;
 
        for (i = 0; i < oh_count; i++) {
-               oh = omap_hwmod_lookup(oh_name[i]);
+               oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
                if (!oh) {
-                       pr_err("Could not look up %s\n", oh_name[i]);
+                       pr_err("Could not look up %s\n",
+                               curr_dss_hwmod[i].oh_name);
                        return -ENODEV;
                }
 
-               od = omap_device_build(dev_name[i], -1, oh, &pdata,
+               od = omap_device_build(curr_dss_hwmod[i].dev_name,
+                               curr_dss_hwmod[i].id, oh, &pdata,
                                sizeof(struct omap_display_platform_data),
                                omap_dss_latency,
                                ARRAY_SIZE(omap_dss_latency), 0);
 
                if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n",
-                               oh_name[i]))
+                               curr_dss_hwmod[i].oh_name))
                        return -ENODEV;
        }
        omap_display_device.dev.platform_data = board_data;
index d20bd9c..775fdc3 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * Defines for zoom boards
  */
-#include <plat/display.h>
+#include <video/omapdss.h>
 
 #define ZOOM_NAND_CS    0
 
index e2507f6..612b270 100644 (file)
@@ -30,6 +30,11 @@ obj-$(CONFIG_ARCH_SH7377)    += entry-intc.o
 obj-$(CONFIG_ARCH_SH7372)      += entry-intc.o
 obj-$(CONFIG_ARCH_SH73A0)      += entry-gic.o
 
+# PM objects
+obj-$(CONFIG_SUSPEND)          += suspend.o
+obj-$(CONFIG_CPU_IDLE)         += cpuidle.o
+obj-$(CONFIG_ARCH_SH7372)      += pm-sh7372.o sleep-sh7372.o
+
 # Board objects
 obj-$(CONFIG_MACH_G3EVM)       += board-g3evm.o
 obj-$(CONFIG_MACH_G4EVM)       += board-g4evm.o
index 3e6f0aa..c95258c 100644 (file)
@@ -34,6 +34,8 @@
 #include <linux/input/sh_keysc.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mfd/tmio.h>
 #include <linux/sh_clk.h>
 #include <video/sh_mobile_lcdc.h>
 #include <video/sh_mipi_dsi.h>
@@ -156,10 +158,19 @@ static struct resource sh_mmcif_resources[] = {
        },
 };
 
+static struct sh_mmcif_dma sh_mmcif_dma = {
+       .chan_priv_rx   = {
+               .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+       },
+       .chan_priv_tx   = {
+               .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+       },
+};
 static struct sh_mmcif_plat_data sh_mmcif_platdata = {
        .sup_pclk       = 0,
        .ocr            = MMC_VDD_165_195,
        .caps           = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
+       .dma            = &sh_mmcif_dma,
 };
 
 static struct platform_device mmc_device = {
@@ -296,11 +307,13 @@ static struct platform_device lcdc0_device = {
 /* MIPI-DSI */
 static struct resource mipidsi0_resources[] = {
        [0] = {
+               .name   = "DSI0",
                .start  = 0xfeab0000,
                .end    = 0xfeab3fff,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
+               .name   = "DSI0",
                .start  = 0xfeab4000,
                .end    = 0xfeab7fff,
                .flags  = IORESOURCE_MEM,
@@ -325,6 +338,89 @@ static struct platform_device mipidsi0_device = {
        },
 };
 
+static struct sh_mobile_sdhi_info sdhi0_info = {
+       .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
+       .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
+       .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
+       .tmio_ocr_mask  = MMC_VDD_27_28 | MMC_VDD_28_29,
+};
+
+static struct resource sdhi0_resources[] = {
+       [0] = {
+               .name   = "SDHI0",
+               .start  = 0xee100000,
+               .end    = 0xee1000ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = gic_spi(83),
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = gic_spi(84),
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = gic_spi(85),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device sdhi0_device = {
+       .name           = "sh_mobile_sdhi",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(sdhi0_resources),
+       .resource       = sdhi0_resources,
+       .dev    = {
+               .platform_data  = &sdhi0_info,
+       },
+};
+
+void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
+{
+       gpio_set_value(GPIO_PORT114, state);
+}
+
+static struct sh_mobile_sdhi_info sh_sdhi1_platdata = {
+       .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
+       .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
+       .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
+       .tmio_caps      = MMC_CAP_NONREMOVABLE,
+       .tmio_ocr_mask  = MMC_VDD_32_33 | MMC_VDD_33_34,
+       .set_pwr        = ag5evm_sdhi1_set_pwr,
+};
+
+static struct resource sdhi1_resources[] = {
+       [0] = {
+               .name   = "SDHI1",
+               .start  = 0xee120000,
+               .end    = 0xee1200ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = gic_spi(87),
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = gic_spi(88),
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = gic_spi(89),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device sdhi1_device = {
+       .name           = "sh_mobile_sdhi",
+       .id             = 1,
+       .dev            = {
+               .platform_data  = &sh_sdhi1_platdata,
+       },
+       .num_resources  = ARRAY_SIZE(sdhi1_resources),
+       .resource       = sdhi1_resources,
+};
+
 static struct platform_device *ag5evm_devices[] __initdata = {
        &eth_device,
        &keysc_device,
@@ -333,6 +429,8 @@ static struct platform_device *ag5evm_devices[] __initdata = {
        &irda_device,
        &lcdc0_device,
        &mipidsi0_device,
+       &sdhi0_device,
+       &sdhi1_device,
 };
 
 static struct map_desc ag5evm_io_desc[] __initdata = {
@@ -454,6 +552,26 @@ static void __init ag5evm_init(void)
        /* MIPI-DSI clock setup */
        __raw_writel(0x2a809010, DSI0PHYCR);
 
+       /* enable SDHI0 on CN15 [SD I/F] */
+       gpio_request(GPIO_FN_SDHICD0, NULL);
+       gpio_request(GPIO_FN_SDHIWP0, NULL);
+       gpio_request(GPIO_FN_SDHICMD0, NULL);
+       gpio_request(GPIO_FN_SDHICLK0, NULL);
+       gpio_request(GPIO_FN_SDHID0_3, NULL);
+       gpio_request(GPIO_FN_SDHID0_2, NULL);
+       gpio_request(GPIO_FN_SDHID0_1, NULL);
+       gpio_request(GPIO_FN_SDHID0_0, NULL);
+
+       /* enable SDHI1 on CN4 [WLAN I/F] */
+       gpio_request(GPIO_FN_SDHICLK1, NULL);
+       gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
+       gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
+       gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
+       gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
+       gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
+       gpio_request(GPIO_PORT114, "sdhi1_power");
+       gpio_direction_output(GPIO_PORT114, 0);
+
 #ifdef CONFIG_CACHE_L2X0
        /* Shared attribute override enable, 64K*8way */
        l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
index 1e35fa9..08acb6e 100644 (file)
@@ -316,8 +316,16 @@ static struct resource sdhi0_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = evt2irq(0x0e00) /* SDHI0 */,
-               .flags  = IORESOURCE_IRQ,
+               .start  = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
+               .flags  = IORESOURCE_IRQ,
        },
 };
 
@@ -349,8 +357,16 @@ static struct resource sdhi1_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = evt2irq(0x0e80),
-               .flags  = IORESOURCE_IRQ,
+               .start  = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
+               .flags  = IORESOURCE_IRQ,
        },
 };
 
@@ -980,11 +996,6 @@ static void __init hdmi_init_pm_clock(void)
                goto out;
        }
 
-       ret = clk_enable(&sh7372_pllc2_clk);
-       if (ret < 0) {
-               pr_err("Cannot enable pllc2 clock\n");
-               goto out;
-       }
        pr_debug("PLLC2 set frequency %lu\n", rate);
 
        ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
@@ -1343,6 +1354,7 @@ static void __init ap4evb_init(void)
 
        hdmi_init_pm_clock();
        fsi_init_pm_clock();
+       sh7372_pm_init();
 }
 
 static void __init ap4evb_timer_init(void)
index c87a7b7..8e3c555 100644 (file)
@@ -205,7 +205,7 @@ static struct resource sdhi0_resources[] = {
        [0] = {
                .name   = "SDHI0",
                .start  = 0xe6d50000,
-               .end    = 0xe6d50nff,
+               .end    = 0xe6d500ff,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
index 7da2ca2..448ddbe 100644 (file)
@@ -43,6 +43,7 @@
 #include <linux/sh_intc.h>
 #include <linux/tca6416_keypad.h>
 #include <linux/usb/r8a66597.h>
+#include <linux/usb/renesas_usbhs.h>
 
 #include <video/sh_mobile_hdmi.h>
 #include <video/sh_mobile_lcdc.h>
  * open      | external VBUS | Function
  *
  * *1
- * CN31 is used as Host in Linux.
+ * CN31 is used as
+ * CONFIG_USB_R8A66597_HCD     Host
+ * CONFIG_USB_RENESAS_USBHS    Function
+ *
+ * CAUTION
+ *
+ * renesas_usbhs driver can use external interrupt mode
+ * (which come from USB-PHY) or autonomy mode (it use own interrupt)
+ * for detecting connection/disconnection when Function.
+ * USB will be power OFF while it has been disconnecting
+ * if external interrupt mode, and it is always power ON if autonomy mode,
+ *
+ * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0",
+ * because Touchscreen is using IRQ7-PORT40.
+ * It is impossible to use IRQ7 demux on this board.
+ *
+ * We can use external interrupt mode USB-Function on "USB1".
+ * USB1 can become Host by r8a66597, and become Function by renesas_usbhs.
+ * But don't select both drivers in same time.
+ * These uses same IRQ number for request_irq(), and aren't supporting
+ * IRQF_SHARD / IORESOURCE_IRQ_SHAREABLE.
+ *
+ * Actually these are old/new version of USB driver.
+ * This mean its register will be broken if it supports SHARD IRQ,
  */
 
 /*
  * FIXME !!
  *
  * gpio_no_direction
+ * gpio_pull_down
  * are quick_hack.
  *
  * current gpio frame work doesn't have
@@ -196,6 +221,16 @@ static void __init gpio_no_direction(u32 addr)
        __raw_writeb(0x00, addr);
 }
 
+static void __init gpio_pull_down(u32 addr)
+{
+       u8 data = __raw_readb(addr);
+
+       data &= 0x0F;
+       data |= 0xA0;
+
+       __raw_writeb(data, addr);
+}
+
 /* MTD */
 static struct mtd_partition nor_flash_partitions[] = {
        {
@@ -458,12 +493,6 @@ static void __init hdmi_init_pm_clock(void)
                goto out;
        }
 
-       ret = clk_enable(&sh7372_pllc2_clk);
-       if (ret < 0) {
-               pr_err("Cannot enable pllc2 clock\n");
-               goto out;
-       }
-
        pr_debug("PLLC2 set frequency %lu\n", rate);
 
        ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
@@ -515,6 +544,157 @@ static struct platform_device usb1_host_device = {
        .resource       = usb1_host_resources,
 };
 
+/* USB1 (Function) */
+#define USB_PHY_MODE           (1 << 4)
+#define USB_PHY_INT_EN         ((1 << 3) | (1 << 2))
+#define USB_PHY_ON             (1 << 1)
+#define USB_PHY_OFF            (1 << 0)
+#define USB_PHY_INT_CLR                (USB_PHY_ON | USB_PHY_OFF)
+
+struct usbhs_private {
+       unsigned int irq;
+       unsigned int usbphyaddr;
+       unsigned int usbcrcaddr;
+       struct renesas_usbhs_platform_info info;
+};
+
+#define usbhs_get_priv(pdev)                           \
+       container_of(renesas_usbhs_get_info(pdev),      \
+                    struct usbhs_private, info)
+
+#define usbhs_is_connected(priv)                       \
+       (!((1 << 7) & __raw_readw(priv->usbcrcaddr)))
+
+static int usbhs1_get_id(struct platform_device *pdev)
+{
+       return USBHS_GADGET;
+}
+
+static int usbhs1_get_vbus(struct platform_device *pdev)
+{
+       return usbhs_is_connected(usbhs_get_priv(pdev));
+}
+
+static irqreturn_t usbhs1_interrupt(int irq, void *data)
+{
+       struct platform_device *pdev = data;
+       struct usbhs_private *priv = usbhs_get_priv(pdev);
+
+       dev_dbg(&pdev->dev, "%s\n", __func__);
+
+       renesas_usbhs_call_notify_hotplug(pdev);
+
+       /* clear status */
+       __raw_writew(__raw_readw(priv->usbphyaddr) | USB_PHY_INT_CLR,
+                    priv->usbphyaddr);
+
+       return IRQ_HANDLED;
+}
+
+static int usbhs1_hardware_init(struct platform_device *pdev)
+{
+       struct usbhs_private *priv = usbhs_get_priv(pdev);
+       int ret;
+
+       irq_set_irq_type(priv->irq, IRQ_TYPE_LEVEL_HIGH);
+
+       /* clear interrupt status */
+       __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
+
+       ret = request_irq(priv->irq, usbhs1_interrupt, 0,
+                         dev_name(&pdev->dev), pdev);
+       if (ret) {
+               dev_err(&pdev->dev, "request_irq err\n");
+               return ret;
+       }
+
+       /* enable USB phy interrupt */
+       __raw_writew(USB_PHY_MODE | USB_PHY_INT_EN, priv->usbphyaddr);
+
+       return 0;
+}
+
+static void usbhs1_hardware_exit(struct platform_device *pdev)
+{
+       struct usbhs_private *priv = usbhs_get_priv(pdev);
+
+       /* clear interrupt status */
+       __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
+
+       free_irq(priv->irq, pdev);
+}
+
+static void usbhs1_phy_reset(struct platform_device *pdev)
+{
+       struct usbhs_private *priv = usbhs_get_priv(pdev);
+
+       /* init phy */
+       __raw_writew(0x8a0a, priv->usbcrcaddr);
+}
+
+static u32 usbhs1_pipe_cfg[] = {
+       USB_ENDPOINT_XFER_CONTROL,
+       USB_ENDPOINT_XFER_ISOC,
+       USB_ENDPOINT_XFER_ISOC,
+       USB_ENDPOINT_XFER_BULK,
+       USB_ENDPOINT_XFER_BULK,
+       USB_ENDPOINT_XFER_BULK,
+       USB_ENDPOINT_XFER_INT,
+       USB_ENDPOINT_XFER_INT,
+       USB_ENDPOINT_XFER_INT,
+       USB_ENDPOINT_XFER_BULK,
+       USB_ENDPOINT_XFER_BULK,
+       USB_ENDPOINT_XFER_BULK,
+       USB_ENDPOINT_XFER_BULK,
+       USB_ENDPOINT_XFER_BULK,
+       USB_ENDPOINT_XFER_BULK,
+       USB_ENDPOINT_XFER_BULK,
+};
+
+static struct usbhs_private usbhs1_private = {
+       .irq            = evt2irq(0x0300),      /* IRQ8 */
+       .usbphyaddr     = 0xE60581E2,           /* USBPHY1INTAP */
+       .usbcrcaddr     = 0xE6058130,           /* USBCR4 */
+       .info = {
+               .platform_callback = {
+                       .hardware_init  = usbhs1_hardware_init,
+                       .hardware_exit  = usbhs1_hardware_exit,
+                       .phy_reset      = usbhs1_phy_reset,
+                       .get_id         = usbhs1_get_id,
+                       .get_vbus       = usbhs1_get_vbus,
+               },
+               .driver_param = {
+                       .buswait_bwait  = 4,
+                       .pipe_type      = usbhs1_pipe_cfg,
+                       .pipe_size      = ARRAY_SIZE(usbhs1_pipe_cfg),
+               },
+       },
+};
+
+static struct resource usbhs1_resources[] = {
+       [0] = {
+               .name   = "USBHS",
+               .start  = 0xE68B0000,
+               .end    = 0xE68B00E6 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = evt2irq(0x1ce0) /* USB1_USB1I0 */,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device usbhs1_device = {
+       .name   = "renesas_usbhs",
+       .id     = 1,
+       .dev = {
+               .platform_data          = &usbhs1_private.info,
+       },
+       .num_resources  = ARRAY_SIZE(usbhs1_resources),
+       .resource       = usbhs1_resources,
+};
+
+
 /* LED */
 static struct gpio_led mackerel_leds[] = {
        {
@@ -690,7 +870,15 @@ static struct resource sdhi0_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = evt2irq(0x0e00) /* SDHI0 */,
+               .start  = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -705,7 +893,7 @@ static struct platform_device sdhi0_device = {
        },
 };
 
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
 /* SDHI1 */
 static struct sh_mobile_sdhi_info sdhi1_info = {
        .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
@@ -725,7 +913,15 @@ static struct resource sdhi1_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = evt2irq(0x0e80),
+               .start  = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -768,7 +964,15 @@ static struct resource sdhi2_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = evt2irq(0x1200),
+               .start  = evt2irq(0x1200), /* SDHI2_SDHI2I0 */
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -803,6 +1007,15 @@ static struct resource sh_mmcif_resources[] = {
        },
 };
 
+static struct sh_mmcif_dma sh_mmcif_dma = {
+       .chan_priv_rx   = {
+               .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+       },
+       .chan_priv_tx   = {
+               .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+       },
+};
+
 static struct sh_mmcif_plat_data sh_mmcif_plat = {
        .sup_pclk       = 0,
        .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@@ -810,6 +1023,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
                          MMC_CAP_8_BIT_DATA |
                          MMC_CAP_NEEDS_POLL,
        .get_cd         = slot_cn7_get_cd,
+       .dma            = &sh_mmcif_dma,
 };
 
 static struct platform_device sh_mmcif_device = {
@@ -858,37 +1072,23 @@ static struct soc_camera_link camera_link = {
        .priv           = &camera_info,
 };
 
-static void dummy_release(struct device *dev)
+static struct platform_device *camera_device;
+
+static void mackerel_camera_release(struct device *dev)
 {
+       soc_camera_platform_release(&camera_device);
 }
 
-static struct platform_device camera_device = {
-       .name           = "soc_camera_platform",
-       .dev            = {
-               .platform_data  = &camera_info,
-               .release        = dummy_release,
-       },
-};
-
 static int mackerel_camera_add(struct soc_camera_link *icl,
                               struct device *dev)
 {
-       if (icl != &camera_link)
-               return -ENODEV;
-
-       camera_info.dev = dev;
-
-       return platform_device_register(&camera_device);
+       return soc_camera_platform_add(icl, dev, &camera_device, &camera_link,
+                                      mackerel_camera_release, 0);
 }
 
 static void mackerel_camera_del(struct soc_camera_link *icl)
 {
-       if (icl != &camera_link)
-               return;
-
-       platform_device_unregister(&camera_device);
-       memset(&camera_device.dev.kobj, 0,
-              sizeof(camera_device.dev.kobj));
+       soc_camera_platform_del(icl, camera_device, &camera_link);
 }
 
 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
@@ -935,12 +1135,13 @@ static struct platform_device *mackerel_devices[] __initdata = {
        &smc911x_device,
        &lcdc_device,
        &usb1_host_device,
+       &usbhs1_device,
        &leds_device,
        &fsi_device,
        &fsi_ak4643_device,
        &fsi_hdmi_device,
        &sdhi0_device,
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
        &sdhi1_device,
 #endif
        &sdhi2_device,
@@ -1030,6 +1231,7 @@ static void __init mackerel_map_io(void)
 
 #define GPIO_PORT9CR   0xE6051009
 #define GPIO_PORT10CR  0xE605100A
+#define GPIO_PORT168CR 0xE60520A8
 #define SRCR4          0xe61580bc
 #define USCCR1         0xE6058144
 static void __init mackerel_init(void)
@@ -1088,6 +1290,7 @@ static void __init mackerel_init(void)
        gpio_request(GPIO_FN_OVCN_1_114, NULL);
        gpio_request(GPIO_FN_EXTLP_1,    NULL);
        gpio_request(GPIO_FN_OVCN2_1,    NULL);
+       gpio_pull_down(GPIO_PORT168CR);
 
        /* setup USB phy */
        __raw_writew(0x8a0a, 0xE6058130);       /* USBCR4 */
@@ -1140,7 +1343,7 @@ static void __init mackerel_init(void)
        gpio_request(GPIO_FN_SDHID0_1, NULL);
        gpio_request(GPIO_FN_SDHID0_0, NULL);
 
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
        /* enable SDHI1 */
        gpio_request(GPIO_FN_SDHICMD1, NULL);
        gpio_request(GPIO_FN_SDHICLK1, NULL);
@@ -1216,6 +1419,7 @@ static void __init mackerel_init(void)
        platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
 
        hdmi_init_pm_clock();
+       sh7372_pm_init();
 }
 
 static void __init mackerel_timer_init(void)
index e9731b5..d17eb66 100644 (file)
 #define DSI1PCKCR      0xe6150098
 #define PLLC01CR       0xe6150028
 #define PLLC2CR                0xe615002c
+#define RMSTPCR0       0xe6150110
+#define RMSTPCR1       0xe6150114
+#define RMSTPCR2       0xe6150118
+#define RMSTPCR3       0xe615011c
+#define RMSTPCR4       0xe6150120
 #define SMSTPCR0       0xe6150130
 #define SMSTPCR1       0xe6150134
 #define SMSTPCR2       0xe6150138
@@ -421,9 +426,6 @@ static unsigned long fsidiv_recalc(struct clk *clk)
 
        value = __raw_readl(clk->mapping->base);
 
-       if ((value & 0x3) != 0x3)
-               return 0;
-
        value >>= 16;
        if (value < 2)
                return 0;
@@ -504,7 +506,7 @@ static struct clk *late_main_clks[] = {
 enum { MSTP001,
        MSTP131, MSTP130,
        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
-       MSTP118, MSTP117, MSTP116,
+       MSTP118, MSTP117, MSTP116, MSTP113,
        MSTP106, MSTP101, MSTP100,
        MSTP223,
        MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
@@ -527,6 +529,7 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
        [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
        [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
+       [MSTP113] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 13, 0), /* MERAM */
        [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
        [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
        [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
@@ -617,6 +620,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
+       CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[MSTP113]), /* MERAM */
        CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
        CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
@@ -634,6 +638,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
        CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
        CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
+       CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */
        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
@@ -644,6 +649,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
        CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
        CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
+       CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
 
        CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
@@ -655,6 +661,13 @@ void __init sh7372_clock_init(void)
 {
        int k, ret = 0;
 
+       /* make sure MSTP bits on the RT/SH4AL-DSP side are off */
+       __raw_writel(0xe4ef8087, RMSTPCR0);
+       __raw_writel(0xffffffff, RMSTPCR1);
+       __raw_writel(0x37c7f7ff, RMSTPCR2);
+       __raw_writel(0xffffffff, RMSTPCR3);
+       __raw_writel(0xffe0fffd, RMSTPCR4);
+
        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                ret = clk_register(main_clks[k]);
 
index 7e58904..bcacb1e 100644 (file)
@@ -266,7 +266,8 @@ enum { MSTP001,
        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
        MSTP219,
        MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
-       MSTP331, MSTP329, MSTP325, MSTP323, MSTP312,
+       MSTP331, MSTP329, MSTP325, MSTP323, MSTP318,
+       MSTP314, MSTP313, MSTP312, MSTP311,
        MSTP411, MSTP410, MSTP403,
        MSTP_NR };
 
@@ -295,7 +296,11 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
        [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
        [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
+       [MSTP318] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* SY-DMAC */
+       [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */
+       [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
        [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
+       [MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */
        [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
        [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
        [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
@@ -313,6 +318,9 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
        CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
        CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
+       CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]),
+       CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]),
+       CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]),
        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
        CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
@@ -341,7 +349,11 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
        CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
+       CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP318]), /* SY-DMAC */
+       CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+       CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
+       CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
        CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
        CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
@@ -351,6 +363,11 @@ void __init sh73a0_clock_init(void)
 {
        int k, ret = 0;
 
+       /* Set SDHI clocks to a known state */
+       __raw_writel(0x108, SD0CKCR);
+       __raw_writel(0x108, SD1CKCR);
+       __raw_writel(0x108, SD2CKCR);
+
        /* detect main clock parent */
        switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
        case 0:
diff --git a/arch/arm/mach-shmobile/cpuidle.c b/arch/arm/mach-shmobile/cpuidle.c
new file mode 100644 (file)
index 0000000..2e44f11
--- /dev/null
@@ -0,0 +1,92 @@
+/*
+ * CPUIdle support code for SH-Mobile ARM
+ *
+ *  Copyright (C) 2011 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/pm.h>
+#include <linux/cpuidle.h>
+#include <linux/suspend.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <asm/system.h>
+#include <asm/io.h>
+
+static void shmobile_enter_wfi(void)
+{
+       cpu_do_idle();
+}
+
+void (*shmobile_cpuidle_modes[CPUIDLE_STATE_MAX])(void) = {
+       shmobile_enter_wfi, /* regular sleep mode */
+};
+
+static int shmobile_cpuidle_enter(struct cpuidle_device *dev,
+                                 struct cpuidle_state *state)
+{
+       ktime_t before, after;
+       int requested_state = state - &dev->states[0];
+
+       dev->last_state = &dev->states[requested_state];
+       before = ktime_get();
+
+       local_irq_disable();
+       local_fiq_disable();
+
+       shmobile_cpuidle_modes[requested_state]();
+
+       local_irq_enable();
+       local_fiq_enable();
+
+       after = ktime_get();
+       return ktime_to_ns(ktime_sub(after, before)) >> 10;
+}
+
+static struct cpuidle_device shmobile_cpuidle_dev;
+static struct cpuidle_driver shmobile_cpuidle_driver = {
+       .name =         "shmobile_cpuidle",
+       .owner =        THIS_MODULE,
+};
+
+void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev);
+
+static int shmobile_cpuidle_init(void)
+{
+       struct cpuidle_device *dev = &shmobile_cpuidle_dev;
+       struct cpuidle_state *state;
+       int i;
+
+       cpuidle_register_driver(&shmobile_cpuidle_driver);
+
+       for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
+               dev->states[i].name[0] = '\0';
+               dev->states[i].desc[0] = '\0';
+               dev->states[i].enter = shmobile_cpuidle_enter;
+       }
+
+       i = CPUIDLE_DRIVER_STATE_START;
+
+       state = &dev->states[i++];
+       snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
+       strncpy(state->desc, "WFI", CPUIDLE_DESC_LEN);
+       state->exit_latency = 1;
+       state->target_residency = 1 * 2;
+       state->power_usage = 3;
+       state->flags = 0;
+       state->flags |= CPUIDLE_FLAG_TIME_VALID;
+
+       dev->safe_state = state;
+       dev->state_count = i;
+
+       if (shmobile_cpuidle_setup)
+               shmobile_cpuidle_setup(dev);
+
+       cpuidle_register_device(dev);
+
+       return 0;
+}
+late_initcall(shmobile_cpuidle_init);
index d4cec6b..26079d9 100644 (file)
@@ -24,4 +24,4 @@
        .align  12
 ENTRY(shmobile_secondary_vector)
        ldr     pc, 1f
-1:     .long   secondary_startup - PAGE_OFFSET + PHYS_OFFSET
+1:     .long   secondary_startup - PAGE_OFFSET + PLAT_PHYS_OFFSET
index 013ac0e..06aecb3 100644 (file)
@@ -8,6 +8,10 @@ struct clk;
 extern int clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
 extern void shmobile_handle_irq_gic(struct pt_regs *);
+extern struct platform_suspend_ops shmobile_suspend_ops;
+struct cpuidle_device;
+extern void (*shmobile_cpuidle_modes[])(void);
+extern void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev);
 
 extern void sh7367_init_irq(void);
 extern void sh7367_add_early_devices(void);
@@ -30,6 +34,9 @@ extern void sh7372_add_early_devices(void);
 extern void sh7372_add_standard_devices(void);
 extern void sh7372_clock_init(void);
 extern void sh7372_pinmux_init(void);
+extern void sh7372_pm_init(void);
+extern void sh7372_cpu_suspend(void);
+extern void sh7372_cpu_resume(void);
 extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
 
index 3029aba..9f134df 100644 (file)
@@ -87,8 +87,7 @@ WAIT 1, 0xFE40009C
 ED 0xFE400354, 0x01AD8002
 
 LIST "SCIF0 - Serial port for earlyprintk"
-EB 0xE6053098, 0x11
 EB 0xE6053098, 0xe1
 EW 0xE6C40000, 0x0000
 EB 0xE6C40004, 0x19
-EW 0xE6C40008, 0x3000
+EW 0xE6C40008, 0x0030
index 3029aba..9f134df 100644 (file)
@@ -87,8 +87,7 @@ WAIT 1, 0xFE40009C
 ED 0xFE400354, 0x01AD8002
 
 LIST "SCIF0 - Serial port for earlyprintk"
-EB 0xE6053098, 0x11
 EB 0xE6053098, 0xe1
 EW 0xE6C40000, 0x0000
 EB 0xE6C40004, 0x19
-EW 0xE6C40008, 0x3000
+EW 0xE6C40008, 0x0030
index 5736efc..df20d76 100644 (file)
@@ -435,6 +435,7 @@ enum {
 
 /* DMA slave IDs */
 enum {
+       SHDMA_SLAVE_INVALID,
        SHDMA_SLAVE_SCIF0_TX,
        SHDMA_SLAVE_SCIF0_RX,
        SHDMA_SLAVE_SCIF1_TX,
index ceb2cdc..216c3d6 100644 (file)
@@ -463,5 +463,35 @@ enum {
        GPIO_FN_FSIAIBT_PU,
        GPIO_FN_FSIAISLD_PU,
 };
+/* DMA slave IDs */
+enum {
+       SHDMA_SLAVE_INVALID,
+       SHDMA_SLAVE_SCIF0_TX,
+       SHDMA_SLAVE_SCIF0_RX,
+       SHDMA_SLAVE_SCIF1_TX,
+       SHDMA_SLAVE_SCIF1_RX,
+       SHDMA_SLAVE_SCIF2_TX,
+       SHDMA_SLAVE_SCIF2_RX,
+       SHDMA_SLAVE_SCIF3_TX,
+       SHDMA_SLAVE_SCIF3_RX,
+       SHDMA_SLAVE_SCIF4_TX,
+       SHDMA_SLAVE_SCIF4_RX,
+       SHDMA_SLAVE_SCIF5_TX,
+       SHDMA_SLAVE_SCIF5_RX,
+       SHDMA_SLAVE_SCIF6_TX,
+       SHDMA_SLAVE_SCIF6_RX,
+       SHDMA_SLAVE_SCIF7_TX,
+       SHDMA_SLAVE_SCIF7_RX,
+       SHDMA_SLAVE_SCIF8_TX,
+       SHDMA_SLAVE_SCIF8_RX,
+       SHDMA_SLAVE_SDHI0_TX,
+       SHDMA_SLAVE_SDHI0_RX,
+       SHDMA_SLAVE_SDHI1_TX,
+       SHDMA_SLAVE_SDHI1_RX,
+       SHDMA_SLAVE_SDHI2_TX,
+       SHDMA_SLAVE_SDHI2_RX,
+       SHDMA_SLAVE_MMCIF_TX,
+       SHDMA_SLAVE_MMCIF_RX,
+};
 
 #endif /* __ASM_SH73A0_H__ */
index 7a4960f..3b28743 100644 (file)
@@ -27,8 +27,6 @@
 
 enum {
        UNUSED_INTCA = 0,
-       ENABLED,
-       DISABLED,
 
        /* interrupt sources INTCA */
        IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
@@ -49,14 +47,14 @@ enum {
        MSIOF2, MSIOF1,
        SCIFA4, SCIFA5, SCIFB,
        FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
-       SDHI0,
-       SDHI1,
+       SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
+       SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
        IRREM,
        IRDA,
        TPU0,
        TTI20,
        DDM,
-       SDHI2,
+       SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
        RWDT0,
        DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
        DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
@@ -84,7 +82,7 @@ enum {
 
        /* interrupt groups INTCA */
        DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
-       AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1
+       AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
 };
 
 static struct intc_vect intca_vectors[] __initdata = {
@@ -125,17 +123,17 @@ static struct intc_vect intca_vectors[] __initdata = {
        INTC_VECT(SCIFB, 0x0d60),
        INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
        INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
-       INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
-       INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
-       INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
-       INTC_VECT(SDHI1, 0x0ec0),
+       INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
+       INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
+       INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
+       INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
        INTC_VECT(IRREM, 0x0f60),
        INTC_VECT(IRDA, 0x0480),
        INTC_VECT(TPU0, 0x04a0),
        INTC_VECT(TTI20, 0x1100),
        INTC_VECT(DDM, 0x1140),
-       INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
-       INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
+       INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
+       INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
        INTC_VECT(RWDT0, 0x1280),
        INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
        INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
@@ -195,6 +193,12 @@ static struct intc_group intca_groups[] __initdata = {
        INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
                   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
        INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
+       INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
+                  SDHI0_SDHI0I2, SDHI0_SDHI0I3),
+       INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
+                  SDHI1_SDHI1I2),
+       INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
+                  SDHI2_SDHI2I2, SDHI2_SDHI2I3),
        INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
 };
 
@@ -230,10 +234,10 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
          { SCIFB, SCIFA5, SCIFA4, MSIOF1,
            0, 0, MSIOF2, 0 } },
        { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
-         { DISABLED, ENABLED, ENABLED, ENABLED,
+         { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
            FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
        { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
-         { 0, ENABLED, ENABLED, ENABLED,
+         { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
            TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
        { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
          { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
@@ -248,7 +252,7 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
          { 0, 0, TPU0, 0,
            0, 0, 0, 0 } },
        { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
-         { DISABLED, DISABLED, ENABLED, ENABLED,
+         { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
            0, CMT3, 0, RWDT0 } },
        { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
          { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
@@ -354,14 +358,10 @@ static struct intc_mask_reg intca_ack_registers[] __initdata = {
          { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
 };
 
-static struct intc_desc intca_desc __initdata = {
-       .name = "sh7372-intca",
-       .force_enable = ENABLED,
-       .force_disable = DISABLED,
-       .hw = INTC_HW_DESC(intca_vectors, intca_groups,
-                          intca_mask_registers, intca_prio_registers,
-                          intca_sense_registers, intca_ack_registers),
-};
+static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca",
+                            intca_vectors, intca_groups,
+                            intca_mask_registers, intca_prio_registers,
+                            intca_sense_registers, intca_ack_registers);
 
 enum {
        UNUSED_INTCS = 0,
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
new file mode 100644 (file)
index 0000000..8e4aadf
--- /dev/null
@@ -0,0 +1,108 @@
+/*
+ * sh7372 Power management support
+ *
+ *  Copyright (C) 2011 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/pm.h>
+#include <linux/suspend.h>
+#include <linux/cpuidle.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/tlbflush.h>
+#include <mach/common.h>
+
+#define SMFRAM 0xe6a70000
+#define SYSTBCR 0xe6150024
+#define SBAR 0xe6180020
+#define APARMBAREA 0xe6f10020
+
+static void sh7372_enter_core_standby(void)
+{
+       void __iomem *smfram = (void __iomem *)SMFRAM;
+
+       __raw_writel(0, APARMBAREA); /* translate 4k */
+       __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
+       __raw_writel(0x10, SYSTBCR); /* enable core standby */
+
+       __raw_writel(0, smfram + 0x3c); /* clear page table address */
+
+       sh7372_cpu_suspend();
+       cpu_init();
+
+       /* if page table address is non-NULL then we have been powered down */
+       if (__raw_readl(smfram + 0x3c)) {
+               __raw_writel(__raw_readl(smfram + 0x40),
+                            __va(__raw_readl(smfram + 0x3c)));
+
+               flush_tlb_all();
+               set_cr(__raw_readl(smfram + 0x38));
+       }
+
+       __raw_writel(0, SYSTBCR); /* disable core standby */
+       __raw_writel(0, SBAR); /* disable reset vector translation */
+}
+
+#ifdef CONFIG_CPU_IDLE
+static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
+{
+       struct cpuidle_state *state;
+       int i = dev->state_count;
+
+       state = &dev->states[i];
+       snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
+       strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
+       state->exit_latency = 10;
+       state->target_residency = 20 + 10;
+       state->power_usage = 1; /* perhaps not */
+       state->flags = 0;
+       state->flags |= CPUIDLE_FLAG_TIME_VALID;
+       shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
+
+       dev->state_count = i + 1;
+}
+
+static void sh7372_cpuidle_init(void)
+{
+       shmobile_cpuidle_setup = sh7372_cpuidle_setup;
+}
+#else
+static void sh7372_cpuidle_init(void) {}
+#endif
+
+#ifdef CONFIG_SUSPEND
+static int sh7372_enter_suspend(suspend_state_t suspend_state)
+{
+       sh7372_enter_core_standby();
+       return 0;
+}
+
+static void sh7372_suspend_init(void)
+{
+       shmobile_suspend_ops.enter = sh7372_enter_suspend;
+}
+#else
+static void sh7372_suspend_init(void) {}
+#endif
+
+#define DBGREG1 0xe6100020
+#define DBGREG9 0xe6100040
+
+void __init sh7372_pm_init(void)
+{
+       /* enable DBG hardware block to kick SYSC */
+       __raw_writel(0x0000a500, DBGREG9);
+       __raw_writel(0x0000a501, DBGREG9);
+       __raw_writel(0x00000000, DBGREG1);
+
+       sh7372_suspend_init();
+       sh7372_cpuidle_init();
+}
index ce28141..2c10190 100644 (file)
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/uio_driver.h>
 #include <linux/delay.h>
 #include <linux/input.h>
 #include <linux/io.h>
@@ -195,6 +196,214 @@ static struct platform_device cmt10_device = {
        .num_resources  = ARRAY_SIZE(cmt10_resources),
 };
 
+/* VPU */
+static struct uio_info vpu_platform_data = {
+       .name = "VPU5",
+       .version = "0",
+       .irq = intcs_evt2irq(0x980),
+};
+
+static struct resource vpu_resources[] = {
+       [0] = {
+               .name   = "VPU",
+               .start  = 0xfe900000,
+               .end    = 0xfe902807,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device vpu_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 0,
+       .dev = {
+               .platform_data  = &vpu_platform_data,
+       },
+       .resource       = vpu_resources,
+       .num_resources  = ARRAY_SIZE(vpu_resources),
+};
+
+/* VEU0 */
+static struct uio_info veu0_platform_data = {
+       .name = "VEU0",
+       .version = "0",
+       .irq = intcs_evt2irq(0x700),
+};
+
+static struct resource veu0_resources[] = {
+       [0] = {
+               .name   = "VEU0",
+               .start  = 0xfe920000,
+               .end    = 0xfe9200b7,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device veu0_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 1,
+       .dev = {
+               .platform_data  = &veu0_platform_data,
+       },
+       .resource       = veu0_resources,
+       .num_resources  = ARRAY_SIZE(veu0_resources),
+};
+
+/* VEU1 */
+static struct uio_info veu1_platform_data = {
+       .name = "VEU1",
+       .version = "0",
+       .irq = intcs_evt2irq(0x720),
+};
+
+static struct resource veu1_resources[] = {
+       [0] = {
+               .name   = "VEU1",
+               .start  = 0xfe924000,
+               .end    = 0xfe9240b7,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device veu1_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 2,
+       .dev = {
+               .platform_data  = &veu1_platform_data,
+       },
+       .resource       = veu1_resources,
+       .num_resources  = ARRAY_SIZE(veu1_resources),
+};
+
+/* VEU2 */
+static struct uio_info veu2_platform_data = {
+       .name = "VEU2",
+       .version = "0",
+       .irq = intcs_evt2irq(0x740),
+};
+
+static struct resource veu2_resources[] = {
+       [0] = {
+               .name   = "VEU2",
+               .start  = 0xfe928000,
+               .end    = 0xfe9280b7,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device veu2_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 3,
+       .dev = {
+               .platform_data  = &veu2_platform_data,
+       },
+       .resource       = veu2_resources,
+       .num_resources  = ARRAY_SIZE(veu2_resources),
+};
+
+/* VEU3 */
+static struct uio_info veu3_platform_data = {
+       .name = "VEU3",
+       .version = "0",
+       .irq = intcs_evt2irq(0x760),
+};
+
+static struct resource veu3_resources[] = {
+       [0] = {
+               .name   = "VEU3",
+               .start  = 0xfe92c000,
+               .end    = 0xfe92c0b7,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device veu3_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 4,
+       .dev = {
+               .platform_data  = &veu3_platform_data,
+       },
+       .resource       = veu3_resources,
+       .num_resources  = ARRAY_SIZE(veu3_resources),
+};
+
+/* VEU2H */
+static struct uio_info veu2h_platform_data = {
+       .name = "VEU2H",
+       .version = "0",
+       .irq = intcs_evt2irq(0x520),
+};
+
+static struct resource veu2h_resources[] = {
+       [0] = {
+               .name   = "VEU2H",
+               .start  = 0xfe93c000,
+               .end    = 0xfe93c27b,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device veu2h_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 5,
+       .dev = {
+               .platform_data  = &veu2h_platform_data,
+       },
+       .resource       = veu2h_resources,
+       .num_resources  = ARRAY_SIZE(veu2h_resources),
+};
+
+/* JPU */
+static struct uio_info jpu_platform_data = {
+       .name = "JPU",
+       .version = "0",
+       .irq = intcs_evt2irq(0x560),
+};
+
+static struct resource jpu_resources[] = {
+       [0] = {
+               .name   = "JPU",
+               .start  = 0xfe980000,
+               .end    = 0xfe9902d3,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device jpu_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 6,
+       .dev = {
+               .platform_data  = &jpu_platform_data,
+       },
+       .resource       = jpu_resources,
+       .num_resources  = ARRAY_SIZE(jpu_resources),
+};
+
+/* SPU1 */
+static struct uio_info spu1_platform_data = {
+       .name = "SPU1",
+       .version = "0",
+       .irq = evt2irq(0xfc0),
+};
+
+static struct resource spu1_resources[] = {
+       [0] = {
+               .name   = "SPU1",
+               .start  = 0xfe300000,
+               .end    = 0xfe3fffff,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device spu1_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 7,
+       .dev = {
+               .platform_data  = &spu1_platform_data,
+       },
+       .resource       = spu1_resources,
+       .num_resources  = ARRAY_SIZE(spu1_resources),
+};
+
 static struct platform_device *sh7367_early_devices[] __initdata = {
        &scif0_device,
        &scif1_device,
@@ -206,10 +415,24 @@ static struct platform_device *sh7367_early_devices[] __initdata = {
        &cmt10_device,
 };
 
+static struct platform_device *sh7367_devices[] __initdata = {
+       &vpu_device,
+       &veu0_device,
+       &veu1_device,
+       &veu2_device,
+       &veu3_device,
+       &veu2h_device,
+       &jpu_device,
+       &spu1_device,
+};
+
 void __init sh7367_add_standard_devices(void)
 {
        platform_add_devices(sh7367_early_devices,
                             ARRAY_SIZE(sh7367_early_devices));
+
+       platform_add_devices(sh7367_devices,
+                           ARRAY_SIZE(sh7367_devices));
 }
 
 #define SYMSTPCR2 0xe6158048
index ff0494f..cd807ee 100644 (file)
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/uio_driver.h>
 #include <linux/delay.h>
 #include <linux/input.h>
 #include <linux/io.h>
@@ -601,6 +602,214 @@ static struct platform_device dma2_device = {
        },
 };
 
+/* VPU */
+static struct uio_info vpu_platform_data = {
+       .name = "VPU5HG",
+       .version = "0",
+       .irq = intcs_evt2irq(0x980),
+};
+
+static struct resource vpu_resources[] = {
+       [0] = {
+               .name   = "VPU",
+               .start  = 0xfe900000,
+               .end    = 0xfe900157,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device vpu_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 0,
+       .dev = {
+               .platform_data  = &vpu_platform_data,
+       },
+       .resource       = vpu_resources,
+       .num_resources  = ARRAY_SIZE(vpu_resources),
+};
+
+/* VEU0 */
+static struct uio_info veu0_platform_data = {
+       .name = "VEU0",
+       .version = "0",
+       .irq = intcs_evt2irq(0x700),
+};
+
+static struct resource veu0_resources[] = {
+       [0] = {
+               .name   = "VEU0",
+               .start  = 0xfe920000,
+               .end    = 0xfe9200cb,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device veu0_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 1,
+       .dev = {
+               .platform_data  = &veu0_platform_data,
+       },
+       .resource       = veu0_resources,
+       .num_resources  = ARRAY_SIZE(veu0_resources),
+};
+
+/* VEU1 */
+static struct uio_info veu1_platform_data = {
+       .name = "VEU1",
+       .version = "0",
+       .irq = intcs_evt2irq(0x720),
+};
+
+static struct resource veu1_resources[] = {
+       [0] = {
+               .name   = "VEU1",
+               .start  = 0xfe924000,
+               .end    = 0xfe9240cb,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device veu1_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 2,
+       .dev = {
+               .platform_data  = &veu1_platform_data,
+       },
+       .resource       = veu1_resources,
+       .num_resources  = ARRAY_SIZE(veu1_resources),
+};
+
+/* VEU2 */
+static struct uio_info veu2_platform_data = {
+       .name = "VEU2",
+       .version = "0",
+       .irq = intcs_evt2irq(0x740),
+};
+
+static struct resource veu2_resources[] = {
+       [0] = {
+               .name   = "VEU2",
+               .start  = 0xfe928000,
+               .end    = 0xfe928307,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device veu2_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 3,
+       .dev = {
+               .platform_data  = &veu2_platform_data,
+       },
+       .resource       = veu2_resources,
+       .num_resources  = ARRAY_SIZE(veu2_resources),
+};
+
+/* VEU3 */
+static struct uio_info veu3_platform_data = {
+       .name = "VEU3",
+       .version = "0",
+       .irq = intcs_evt2irq(0x760),
+};
+
+static struct resource veu3_resources[] = {
+       [0] = {
+               .name   = "VEU3",
+               .start  = 0xfe92c000,
+               .end    = 0xfe92c307,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device veu3_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 4,
+       .dev = {
+               .platform_data  = &veu3_platform_data,
+       },
+       .resource       = veu3_resources,
+       .num_resources  = ARRAY_SIZE(veu3_resources),
+};
+
+/* JPU */
+static struct uio_info jpu_platform_data = {
+       .name = "JPU",
+       .version = "0",
+       .irq = intcs_evt2irq(0x560),
+};
+
+static struct resource jpu_resources[] = {
+       [0] = {
+               .name   = "JPU",
+               .start  = 0xfe980000,
+               .end    = 0xfe9902d3,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device jpu_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 5,
+       .dev = {
+               .platform_data  = &jpu_platform_data,
+       },
+       .resource       = jpu_resources,
+       .num_resources  = ARRAY_SIZE(jpu_resources),
+};
+
+/* SPU2DSP0 */
+static struct uio_info spu0_platform_data = {
+       .name = "SPU2DSP0",
+       .version = "0",
+       .irq = evt2irq(0x1800),
+};
+
+static struct resource spu0_resources[] = {
+       [0] = {
+               .name   = "SPU2DSP0",
+               .start  = 0xfe200000,
+               .end    = 0xfe2fffff,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device spu0_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 6,
+       .dev = {
+               .platform_data  = &spu0_platform_data,
+       },
+       .resource       = spu0_resources,
+       .num_resources  = ARRAY_SIZE(spu0_resources),
+};
+
+/* SPU2DSP1 */
+static struct uio_info spu1_platform_data = {
+       .name = "SPU2DSP1",
+       .version = "0",
+       .irq = evt2irq(0x1820),
+};
+
+static struct resource spu1_resources[] = {
+       [0] = {
+               .name   = "SPU2DSP1",
+               .start  = 0xfe300000,
+               .end    = 0xfe3fffff,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device spu1_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 7,
+       .dev = {
+               .platform_data  = &spu1_platform_data,
+       },
+       .resource       = spu1_resources,
+       .num_resources  = ARRAY_SIZE(spu1_resources),
+};
+
 static struct platform_device *sh7372_early_devices[] __initdata = {
        &scif0_device,
        &scif1_device,
@@ -620,6 +829,14 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
        &dma0_device,
        &dma1_device,
        &dma2_device,
+       &vpu_device,
+       &veu0_device,
+       &veu1_device,
+       &veu2_device,
+       &veu3_device,
+       &jpu_device,
+       &spu0_device,
+       &spu1_device,
 };
 
 void __init sh7372_add_standard_devices(void)
index 8099b0b..bb405b8 100644 (file)
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/uio_driver.h>
 #include <linux/delay.h>
 #include <linux/input.h>
 #include <linux/io.h>
@@ -38,7 +39,7 @@ static struct plat_sci_port scif0_platform_data = {
        .flags          = UPF_BOOT_AUTOCONF,
        .scscr          = SCSCR_RE | SCSCR_TE,
        .scbrr_algo_id  = SCBRR_ALGO_4,
-       .type           = PORT_SCIF,
+       .type           = PORT_SCIFA,
        .irqs           = { evt2irq(0xc00), evt2irq(0xc00),
                            evt2irq(0xc00), evt2irq(0xc00) },
 };
@@ -57,7 +58,7 @@ static struct plat_sci_port scif1_platform_data = {
        .flags          = UPF_BOOT_AUTOCONF,
        .scscr          = SCSCR_RE | SCSCR_TE,
        .scbrr_algo_id  = SCBRR_ALGO_4,
-       .type           = PORT_SCIF,
+       .type           = PORT_SCIFA,
        .irqs           = { evt2irq(0xc20), evt2irq(0xc20),
                            evt2irq(0xc20), evt2irq(0xc20) },
 };
@@ -76,7 +77,7 @@ static struct plat_sci_port scif2_platform_data = {
        .flags          = UPF_BOOT_AUTOCONF,
        .scscr          = SCSCR_RE | SCSCR_TE,
        .scbrr_algo_id  = SCBRR_ALGO_4,
-       .type           = PORT_SCIF,
+       .type           = PORT_SCIFA,
        .irqs           = { evt2irq(0xc40), evt2irq(0xc40),
                            evt2irq(0xc40), evt2irq(0xc40) },
 };
@@ -95,7 +96,7 @@ static struct plat_sci_port scif3_platform_data = {
        .flags          = UPF_BOOT_AUTOCONF,
        .scscr          = SCSCR_RE | SCSCR_TE,
        .scbrr_algo_id  = SCBRR_ALGO_4,
-       .type           = PORT_SCIF,
+       .type           = PORT_SCIFA,
        .irqs           = { evt2irq(0xc60), evt2irq(0xc60),
                            evt2irq(0xc60), evt2irq(0xc60) },
 };
@@ -114,7 +115,7 @@ static struct plat_sci_port scif4_platform_data = {
        .flags          = UPF_BOOT_AUTOCONF,
        .scscr          = SCSCR_RE | SCSCR_TE,
        .scbrr_algo_id  = SCBRR_ALGO_4,
-       .type           = PORT_SCIF,
+       .type           = PORT_SCIFA,
        .irqs           = { evt2irq(0xd20), evt2irq(0xd20),
                            evt2irq(0xd20), evt2irq(0xd20) },
 };
@@ -133,7 +134,7 @@ static struct plat_sci_port scif5_platform_data = {
        .flags          = UPF_BOOT_AUTOCONF,
        .scscr          = SCSCR_RE | SCSCR_TE,
        .scbrr_algo_id  = SCBRR_ALGO_4,
-       .type           = PORT_SCIF,
+       .type           = PORT_SCIFA,
        .irqs           = { evt2irq(0xd40), evt2irq(0xd40),
                            evt2irq(0xd40), evt2irq(0xd40) },
 };
@@ -152,7 +153,7 @@ static struct plat_sci_port scif6_platform_data = {
        .flags          = UPF_BOOT_AUTOCONF,
        .scscr          = SCSCR_RE | SCSCR_TE,
        .scbrr_algo_id  = SCBRR_ALGO_4,
-       .type           = PORT_SCIF,
+       .type           = PORT_SCIFA,
        .irqs           = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
                            intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
 };
@@ -171,7 +172,7 @@ static struct plat_sci_port scif7_platform_data = {
        .flags          = UPF_BOOT_AUTOCONF,
        .scscr          = SCSCR_RE | SCSCR_TE,
        .scbrr_algo_id  = SCBRR_ALGO_4,
-       .type           = PORT_SCIF,
+       .type           = PORT_SCIFB,
        .irqs           = { evt2irq(0xd60), evt2irq(0xd60),
                            evt2irq(0xd60), evt2irq(0xd60) },
 };
@@ -215,6 +216,214 @@ static struct platform_device cmt10_device = {
        .num_resources  = ARRAY_SIZE(cmt10_resources),
 };
 
+/* VPU */
+static struct uio_info vpu_platform_data = {
+       .name = "VPU5HG",
+       .version = "0",
+       .irq = intcs_evt2irq(0x980),
+};
+
+static struct resource vpu_resources[] = {
+       [0] = {
+               .name   = "VPU",
+               .start  = 0xfe900000,
+               .end    = 0xfe900157,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device vpu_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 0,
+       .dev = {
+               .platform_data  = &vpu_platform_data,
+       },
+       .resource       = vpu_resources,
+       .num_resources  = ARRAY_SIZE(vpu_resources),
+};
+
+/* VEU0 */
+static struct uio_info veu0_platform_data = {
+       .name = "VEU0",
+       .version = "0",
+       .irq = intcs_evt2irq(0x700),
+};
+
+static struct resource veu0_resources[] = {
+       [0] = {
+               .name   = "VEU0",
+               .start  = 0xfe920000,
+               .end    = 0xfe9200cb,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device veu0_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 1,
+       .dev = {
+               .platform_data  = &veu0_platform_data,
+       },
+       .resource       = veu0_resources,
+       .num_resources  = ARRAY_SIZE(veu0_resources),
+};
+
+/* VEU1 */
+static struct uio_info veu1_platform_data = {
+       .name = "VEU1",
+       .version = "0",
+       .irq = intcs_evt2irq(0x720),
+};
+
+static struct resource veu1_resources[] = {
+       [0] = {
+               .name   = "VEU1",
+               .start  = 0xfe924000,
+               .end    = 0xfe9240cb,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device veu1_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 2,
+       .dev = {
+               .platform_data  = &veu1_platform_data,
+       },
+       .resource       = veu1_resources,
+       .num_resources  = ARRAY_SIZE(veu1_resources),
+};
+
+/* VEU2 */
+static struct uio_info veu2_platform_data = {
+       .name = "VEU2",
+       .version = "0",
+       .irq = intcs_evt2irq(0x740),
+};
+
+static struct resource veu2_resources[] = {
+       [0] = {
+               .name   = "VEU2",
+               .start  = 0xfe928000,
+               .end    = 0xfe928307,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device veu2_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 3,
+       .dev = {
+               .platform_data  = &veu2_platform_data,
+       },
+       .resource       = veu2_resources,
+       .num_resources  = ARRAY_SIZE(veu2_resources),
+};
+
+/* VEU3 */
+static struct uio_info veu3_platform_data = {
+       .name = "VEU3",
+       .version = "0",
+       .irq = intcs_evt2irq(0x760),
+};
+
+static struct resource veu3_resources[] = {
+       [0] = {
+               .name   = "VEU3",
+               .start  = 0xfe92c000,
+               .end    = 0xfe92c307,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device veu3_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 4,
+       .dev = {
+               .platform_data  = &veu3_platform_data,
+       },
+       .resource       = veu3_resources,
+       .num_resources  = ARRAY_SIZE(veu3_resources),
+};
+
+/* JPU */
+static struct uio_info jpu_platform_data = {
+       .name = "JPU",
+       .version = "0",
+       .irq = intcs_evt2irq(0x560),
+};
+
+static struct resource jpu_resources[] = {
+       [0] = {
+               .name   = "JPU",
+               .start  = 0xfe980000,
+               .end    = 0xfe9902d3,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device jpu_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 5,
+       .dev = {
+               .platform_data  = &jpu_platform_data,
+       },
+       .resource       = jpu_resources,
+       .num_resources  = ARRAY_SIZE(jpu_resources),
+};
+
+/* SPU2DSP0 */
+static struct uio_info spu0_platform_data = {
+       .name = "SPU2DSP0",
+       .version = "0",
+       .irq = evt2irq(0x1800),
+};
+
+static struct resource spu0_resources[] = {
+       [0] = {
+               .name   = "SPU2DSP0",
+               .start  = 0xfe200000,
+               .end    = 0xfe2fffff,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device spu0_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 6,
+       .dev = {
+               .platform_data  = &spu0_platform_data,
+       },
+       .resource       = spu0_resources,
+       .num_resources  = ARRAY_SIZE(spu0_resources),
+};
+
+/* SPU2DSP1 */
+static struct uio_info spu1_platform_data = {
+       .name = "SPU2DSP1",
+       .version = "0",
+       .irq = evt2irq(0x1820),
+};
+
+static struct resource spu1_resources[] = {
+       [0] = {
+               .name   = "SPU2DSP1",
+               .start  = 0xfe300000,
+               .end    = 0xfe3fffff,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device spu1_device = {
+       .name           = "uio_pdrv_genirq",
+       .id             = 7,
+       .dev = {
+               .platform_data  = &spu1_platform_data,
+       },
+       .resource       = spu1_resources,
+       .num_resources  = ARRAY_SIZE(spu1_resources),
+};
+
 static struct platform_device *sh7377_early_devices[] __initdata = {
        &scif0_device,
        &scif1_device,
@@ -227,10 +436,24 @@ static struct platform_device *sh7377_early_devices[] __initdata = {
        &cmt10_device,
 };
 
+static struct platform_device *sh7377_devices[] __initdata = {
+       &vpu_device,
+       &veu0_device,
+       &veu1_device,
+       &veu2_device,
+       &veu3_device,
+       &jpu_device,
+       &spu0_device,
+       &spu1_device,
+};
+
 void __init sh7377_add_standard_devices(void)
 {
        platform_add_devices(sh7377_early_devices,
                            ARRAY_SIZE(sh7377_early_devices));
+
+       platform_add_devices(sh7377_devices,
+                           ARRAY_SIZE(sh7377_devices));
 }
 
 #define SMSTPCR3 0xe615013c
index 685c40a..e46821c 100644 (file)
 #include <linux/input.h>
 #include <linux/io.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <mach/hardware.h>
+#include <mach/sh73a0.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
@@ -392,6 +394,242 @@ static struct platform_device i2c4_device = {
        .num_resources  = ARRAY_SIZE(i2c4_resources),
 };
 
+/* Transmit sizes and respective CHCR register values */
+enum {
+       XMIT_SZ_8BIT            = 0,
+       XMIT_SZ_16BIT           = 1,
+       XMIT_SZ_32BIT           = 2,
+       XMIT_SZ_64BIT           = 7,
+       XMIT_SZ_128BIT          = 3,
+       XMIT_SZ_256BIT          = 4,
+       XMIT_SZ_512BIT          = 5,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+#define TS_SHIFT {                     \
+       [XMIT_SZ_8BIT]          = 0,    \
+       [XMIT_SZ_16BIT]         = 1,    \
+       [XMIT_SZ_32BIT]         = 2,    \
+       [XMIT_SZ_64BIT]         = 3,    \
+       [XMIT_SZ_128BIT]        = 4,    \
+       [XMIT_SZ_256BIT]        = 5,    \
+       [XMIT_SZ_512BIT]        = 6,    \
+}
+
+#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
+#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
+#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
+
+static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
+       {
+               .slave_id       = SHDMA_SLAVE_SCIF0_TX,
+               .addr           = 0xe6c40020,
+               .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x21,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF0_RX,
+               .addr           = 0xe6c40024,
+               .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x22,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF1_TX,
+               .addr           = 0xe6c50020,
+               .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x25,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF1_RX,
+               .addr           = 0xe6c50024,
+               .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x26,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF2_TX,
+               .addr           = 0xe6c60020,
+               .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x29,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF2_RX,
+               .addr           = 0xe6c60024,
+               .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x2a,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF3_TX,
+               .addr           = 0xe6c70020,
+               .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x2d,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF3_RX,
+               .addr           = 0xe6c70024,
+               .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x2e,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF4_TX,
+               .addr           = 0xe6c80020,
+               .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x39,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF4_RX,
+               .addr           = 0xe6c80024,
+               .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x3a,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF5_TX,
+               .addr           = 0xe6cb0020,
+               .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x35,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF5_RX,
+               .addr           = 0xe6cb0024,
+               .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x36,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF6_TX,
+               .addr           = 0xe6cc0020,
+               .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x1d,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF6_RX,
+               .addr           = 0xe6cc0024,
+               .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x1e,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF7_TX,
+               .addr           = 0xe6cd0020,
+               .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x19,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF7_RX,
+               .addr           = 0xe6cd0024,
+               .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x1a,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF8_TX,
+               .addr           = 0xe6c30040,
+               .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x3d,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF8_RX,
+               .addr           = 0xe6c30060,
+               .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+               .mid_rid        = 0x3e,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SDHI0_TX,
+               .addr           = 0xee100030,
+               .chcr           = CHCR_TX(XMIT_SZ_16BIT),
+               .mid_rid        = 0xc1,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SDHI0_RX,
+               .addr           = 0xee100030,
+               .chcr           = CHCR_RX(XMIT_SZ_16BIT),
+               .mid_rid        = 0xc2,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SDHI1_TX,
+               .addr           = 0xee120030,
+               .chcr           = CHCR_TX(XMIT_SZ_16BIT),
+               .mid_rid        = 0xc9,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SDHI1_RX,
+               .addr           = 0xee120030,
+               .chcr           = CHCR_RX(XMIT_SZ_16BIT),
+               .mid_rid        = 0xca,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SDHI2_TX,
+               .addr           = 0xee140030,
+               .chcr           = CHCR_TX(XMIT_SZ_16BIT),
+               .mid_rid        = 0xcd,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SDHI2_RX,
+               .addr           = 0xee140030,
+               .chcr           = CHCR_RX(XMIT_SZ_16BIT),
+               .mid_rid        = 0xce,
+       }, {
+               .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+               .addr           = 0xe6bd0034,
+               .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+               .mid_rid        = 0xd1,
+       }, {
+               .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+               .addr           = 0xe6bd0034,
+               .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+               .mid_rid        = 0xd2,
+       },
+};
+
+#define DMAE_CHANNEL(_offset)                                  \
+       {                                                       \
+               .offset         = _offset - 0x20,               \
+               .dmars          = _offset - 0x20 + 0x40,        \
+       }
+
+static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
+       DMAE_CHANNEL(0x8000),
+       DMAE_CHANNEL(0x8080),
+       DMAE_CHANNEL(0x8100),
+       DMAE_CHANNEL(0x8180),
+       DMAE_CHANNEL(0x8200),
+       DMAE_CHANNEL(0x8280),
+       DMAE_CHANNEL(0x8300),
+       DMAE_CHANNEL(0x8380),
+       DMAE_CHANNEL(0x8400),
+       DMAE_CHANNEL(0x8480),
+       DMAE_CHANNEL(0x8500),
+       DMAE_CHANNEL(0x8580),
+       DMAE_CHANNEL(0x8600),
+       DMAE_CHANNEL(0x8680),
+       DMAE_CHANNEL(0x8700),
+       DMAE_CHANNEL(0x8780),
+       DMAE_CHANNEL(0x8800),
+       DMAE_CHANNEL(0x8880),
+       DMAE_CHANNEL(0x8900),
+       DMAE_CHANNEL(0x8980),
+};
+
+static const unsigned int ts_shift[] = TS_SHIFT;
+
+static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
+       .slave          = sh73a0_dmae_slaves,
+       .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
+       .channel        = sh73a0_dmae_channels,
+       .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
+       .ts_low_shift   = 3,
+       .ts_low_mask    = 0x18,
+       .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
+       .ts_high_mask   = 0x00300000,
+       .ts_shift       = ts_shift,
+       .ts_shift_num   = ARRAY_SIZE(ts_shift),
+       .dmaor_init     = DMAOR_DME,
+};
+
+static struct resource sh73a0_dmae_resources[] = {
+       {
+               /* Registers including DMAOR and channels including DMARSx */
+               .start  = 0xfe000020,
+               .end    = 0xfe008a00 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               /* DMA error IRQ */
+               .start  = gic_spi(129),
+               .end    = gic_spi(129),
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               /* IRQ for channels 0-19 */
+               .start  = gic_spi(109),
+               .end    = gic_spi(128),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device dma0_device = {
+       .name           = "sh-dma-engine",
+       .id             = 0,
+       .resource       = sh73a0_dmae_resources,
+       .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
+       .dev            = {
+               .platform_data  = &sh73a0_dmae_platform_data,
+       },
+};
+
 static struct platform_device *sh73a0_early_devices[] __initdata = {
        &scif0_device,
        &scif1_device,
@@ -413,10 +651,16 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
        &i2c2_device,
        &i2c3_device,
        &i2c4_device,
+       &dma0_device,
 };
 
+#define SRCR2          0xe61580b0
+
 void __init sh73a0_add_standard_devices(void)
 {
+       /* Clear software reset bit on SY-DMAC module */
+       __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
+
        platform_add_devices(sh73a0_early_devices,
                            ARRAY_SIZE(sh73a0_early_devices));
        platform_add_devices(sh73a0_late_devices,
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
new file mode 100644 (file)
index 0000000..d37d3ca
--- /dev/null
@@ -0,0 +1,260 @@
+/*
+ * sh7372 lowlevel sleep code for "Core Standby Mode"
+ *
+ * Copyright (C) 2011 Magnus Damm
+ *
+ * In "Core Standby Mode" the ARM core is off, but L2 cache is still on
+ *
+ * Based on mach-omap2/sleep34xx.S
+ *
+ * (C) Copyright 2007 Texas Instruments
+ * Karthik Dasu <karthik-dp@ti.com>
+ *
+ * (C) Copyright 2004 Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#define SMFRAM 0xe6a70000
+
+       .align
+kernel_flush:
+       .word   v7_flush_dcache_all
+
+       .align  3
+ENTRY(sh7372_cpu_suspend)
+       stmfd   sp!, {r0-r12, lr}       @ save registers on stack
+
+       ldr     r8, =SMFRAM
+
+       mov     r4, sp                  @ Store sp
+       mrs     r5, spsr                @ Store spsr
+       mov     r6, lr                  @ Store lr
+       stmia   r8!, {r4-r6}
+
+       mrc     p15, 0, r4, c1, c0, 2   @ Coprocessor access control register
+       mrc     p15, 0, r5, c2, c0, 0   @ TTBR0
+       mrc     p15, 0, r6, c2, c0, 1   @ TTBR1
+       mrc     p15, 0, r7, c2, c0, 2   @ TTBCR
+       stmia   r8!, {r4-r7}
+
+       mrc     p15, 0, r4, c3, c0, 0   @ Domain access Control Register
+       mrc     p15, 0, r5, c10, c2, 0  @ PRRR
+       mrc     p15, 0, r6, c10, c2, 1  @ NMRR
+       stmia   r8!,{r4-r6}
+
+       mrc     p15, 0, r4, c13, c0, 1  @ Context ID
+       mrc     p15, 0, r5, c13, c0, 2  @ User r/w thread and process ID
+       mrc     p15, 0, r6, c12, c0, 0  @ Secure or NS vector base address
+       mrs     r7, cpsr                @ Store current cpsr
+       stmia   r8!, {r4-r7}
+
+       mrc     p15, 0, r4, c1, c0, 0   @ save control register
+       stmia   r8!, {r4}
+
+       /*
+        * jump out to kernel flush routine
+        *  - reuse that code is better
+        *  - it executes in a cached space so is faster than refetch per-block
+        *  - should be faster and will change with kernel
+        *  - 'might' have to copy address, load and jump to it
+        * Flush all data from the L1 data cache before disabling
+        * SCTLR.C bit.
+        */
+       ldr     r1, kernel_flush
+       mov     lr, pc
+       bx      r1
+
+       /*
+        * Clear the SCTLR.C bit to prevent further data cache
+        * allocation. Clearing SCTLR.C would make all the data accesses
+        * strongly ordered and would not hit the cache.
+        */
+       mrc     p15, 0, r0, c1, c0, 0
+       bic     r0, r0, #(1 << 2)       @ Disable the C bit
+       mcr     p15, 0, r0, c1, c0, 0
+       isb
+
+       /*
+        * Invalidate L1 data cache. Even though only invalidate is
+        * necessary exported flush API is used here. Doing clean
+        * on already clean cache would be almost NOP.
+        */
+       ldr     r1, kernel_flush
+       blx     r1
+       /*
+        * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
+        * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
+        * This sequence switches back to ARM.  Note that .align may insert a
+        * nop: bx pc needs to be word-aligned in order to work.
+        */
+ THUMB(        .thumb          )
+ THUMB(        .align          )
+ THUMB(        bx      pc      )
+ THUMB(        nop             )
+       .arm
+
+       /* Data memory barrier and Data sync barrier */
+       dsb
+       dmb
+
+/*
+ * ===================================
+ * == WFI instruction => Enter idle ==
+ * ===================================
+ */
+       wfi                             @ wait for interrupt
+
+/*
+ * ===================================
+ * == Resume path for non-OFF modes ==
+ * ===================================
+ */
+       mrc     p15, 0, r0, c1, c0, 0
+       tst     r0, #(1 << 2)           @ Check C bit enabled?
+       orreq   r0, r0, #(1 << 2)       @ Enable the C bit if cleared
+       mcreq   p15, 0, r0, c1, c0, 0
+       isb
+
+/*
+ * ===================================
+ * == Exit point from non-OFF modes ==
+ * ===================================
+ */
+       ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
+
+       .pool
+
+       .align  12
+       .text
+       .global sh7372_cpu_resume
+sh7372_cpu_resume:
+
+       mov     r1, #0
+       /*
+        * Invalidate all instruction caches to PoU
+        * and flush branch target cache
+        */
+       mcr     p15, 0, r1, c7, c5, 0
+
+       ldr     r3, =SMFRAM
+
+       ldmia   r3!, {r4-r6}
+       mov     sp, r4                  @ Restore sp
+       msr     spsr_cxsf, r5           @ Restore spsr
+       mov     lr, r6                  @ Restore lr
+
+       ldmia   r3!, {r4-r7}
+       mcr     p15, 0, r4, c1, c0, 2   @ Coprocessor access Control Register
+       mcr     p15, 0, r5, c2, c0, 0   @ TTBR0
+       mcr     p15, 0, r6, c2, c0, 1   @ TTBR1
+       mcr     p15, 0, r7, c2, c0, 2   @ TTBCR
+
+       ldmia   r3!,{r4-r6}
+       mcr     p15, 0, r4, c3, c0, 0   @ Domain access Control Register
+       mcr     p15, 0, r5, c10, c2, 0  @ PRRR
+       mcr     p15, 0, r6, c10, c2, 1  @ NMRR
+
+       ldmia   r3!,{r4-r7}
+       mcr     p15, 0, r4, c13, c0, 1  @ Context ID
+       mcr     p15, 0, r5, c13, c0, 2  @ User r/w thread and process ID
+       mrc     p15, 0, r6, c12, c0, 0  @ Secure or NS vector base address
+       msr     cpsr, r7                @ store cpsr
+
+       /* Starting to enable MMU here */
+       mrc     p15, 0, r7, c2, c0, 2   @ Read TTBRControl
+       /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
+       and     r7, #0x7
+       cmp     r7, #0x0
+       beq     usettbr0
+ttbr_error:
+       /*
+        * More work needs to be done to support N[0:2] value other than 0
+        * So looping here so that the error can be detected
+        */
+       b       ttbr_error
+
+       .align
+cache_pred_disable_mask:
+       .word   0xFFFFE7FB
+ttbrbit_mask:
+       .word   0xFFFFC000
+table_index_mask:
+       .word   0xFFF00000
+table_entry:
+       .word   0x00000C02
+usettbr0:
+
+       mrc     p15, 0, r2, c2, c0, 0
+       ldr     r5, ttbrbit_mask
+       and     r2, r5
+       mov     r4, pc
+       ldr     r5, table_index_mask
+       and     r4, r5                  @ r4 = 31 to 20 bits of pc
+       /* Extract the value to be written to table entry */
+       ldr     r6, table_entry
+       /* r6 has the value to be written to table entry */
+       add     r6, r6, r4
+       /* Getting the address of table entry to modify */
+       lsr     r4, #18
+       /* r2 has the location which needs to be modified */
+       add     r2, r4
+       ldr     r4, [r2]
+       str     r6, [r2] /* modify the table entry */
+
+       mov     r7, r6
+       mov     r5, r2
+       mov     r6, r4
+       /* r5 = original page table address */
+       /* r6 = original page table data */
+
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c5, 4   @ Flush prefetch buffer
+       mcr     p15, 0, r0, c7, c5, 6   @ Invalidate branch predictor array
+       mcr     p15, 0, r0, c8, c5, 0   @ Invalidate instruction TLB
+       mcr     p15, 0, r0, c8, c6, 0   @ Invalidate data TLB
+
+       /*
+        * Restore control register. This enables the MMU.
+        * The caches and prediction are not enabled here, they
+        * will be enabled after restoring the MMU table entry.
+        */
+       ldmia   r3!, {r4}
+       stmia   r3!, {r5} /* save original page table address */
+       stmia   r3!, {r6} /* save original page table data */
+       stmia   r3!, {r7} /* save modified page table data */
+
+       ldr     r2, cache_pred_disable_mask
+       and     r4, r2
+       mcr     p15, 0, r4, c1, c0, 0
+       dsb
+       isb
+
+       ldr     r0, =restoremmu_on
+       bx      r0
+
+/*
+ * ==============================
+ * == Exit point from OFF mode ==
+ * ==============================
+ */
+restoremmu_on:
+
+       ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
index a156d21..3ffdbc9 100644 (file)
@@ -59,6 +59,11 @@ unsigned int __init sh73a0_get_core_count(void)
 {
        void __iomem *scu_base = scu_base_addr();
 
+#ifdef CONFIG_HAVE_ARM_TWD
+       /* twd_base needs to be initialized before percpu_timer_setup() */
+       twd_base = (void __iomem *)0xf0000600;
+#endif
+
        return scu_get_core_count(scu_base);
 }
 
@@ -82,10 +87,6 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
 
 void __init sh73a0_smp_prepare_cpus(void)
 {
-#ifdef CONFIG_HAVE_ARM_TWD
-       twd_base = (void __iomem *)0xf0000600;
-#endif
-
        scu_enable(scu_base_addr());
 
        /* Map the reset vector (in headsmp.S) */
diff --git a/arch/arm/mach-shmobile/suspend.c b/arch/arm/mach-shmobile/suspend.c
new file mode 100644 (file)
index 0000000..c1febe1
--- /dev/null
@@ -0,0 +1,47 @@
+/*
+ * Suspend-to-RAM support code for SH-Mobile ARM
+ *
+ *  Copyright (C) 2011 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/pm.h>
+#include <linux/suspend.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <asm/system.h>
+#include <asm/io.h>
+
+static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
+{
+       cpu_do_idle();
+       return 0;
+}
+
+static int shmobile_suspend_begin(suspend_state_t state)
+{
+       disable_hlt();
+       return 0;
+}
+
+static void shmobile_suspend_end(void)
+{
+       enable_hlt();
+}
+
+struct platform_suspend_ops shmobile_suspend_ops = {
+       .begin          = shmobile_suspend_begin,
+       .end            = shmobile_suspend_end,
+       .enter          = shmobile_suspend_default_enter,
+       .valid          = suspend_valid_only_mem,
+};
+
+static int __init shmobile_suspend_init(void)
+{
+       suspend_set_ops(&shmobile_suspend_ops);
+       return 0;
+}
+late_initcall(shmobile_suspend_init);
index 5862601..54429d0 100644 (file)
@@ -12,9 +12,12 @@ menu "Ux500 SoC"
 
 config UX500_SOC_DB5500
        bool "DB5500"
+       select MFD_DB5500_PRCMU
 
 config UX500_SOC_DB8500
        bool "DB8500"
+       select MFD_DB8500_PRCMU
+       select REGULATOR_DB8500_PRCMU
 
 endmenu