#include <linux/interrupt.h>
#include <linux/bootmem.h>
#include <linux/sh_intc.h>
+#include <linux/sysdev.h>
+#include <linux/list.h>
#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
};
struct intc_desc_int {
+ struct list_head list;
+ struct sys_device sysdev;
+ pm_message_t state;
unsigned long *reg;
#ifdef CONFIG_SMP
unsigned long *smp;
struct irq_chip chip;
};
+static LIST_HEAD(intc_list);
+
#ifdef CONFIG_SMP
#define IS_SMP(x) x.smp
#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
}
}
+static int intc_set_wake(unsigned int irq, unsigned int on)
+{
+ return 0; /* allow wakeup, but setup hardware in intc_suspend() */
+}
+
#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
static void intc_mask_ack(unsigned int irq)
{
if (!data[0] && data[1])
primary = 1;
+ if (!data[0] && !data[1])
+ pr_warning("intc: missing unique irq mask for "
+ "irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
+
data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
return 0;
}
+static unsigned char *intc_evt2irq_table;
+
+unsigned int intc_evt2irq(unsigned int vector)
+{
+ unsigned int irq = evt2irq(vector);
+
+ if (intc_evt2irq_table && intc_evt2irq_table[irq])
+ irq = intc_evt2irq_table[irq];
+
+ return irq;
+}
void __init register_intc_controller(struct intc_desc *desc)
{
- unsigned int i, k, smp;
+ unsigned int i, k, smp, cpu = smp_processor_id();
struct intc_desc_int *d;
d = alloc_bootmem(sizeof(*d));
+ INIT_LIST_HEAD(&d->list);
+ list_add(&d->list, &intc_list);
+
d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
d->chip.mask = intc_disable;
d->chip.unmask = intc_enable;
d->chip.mask_ack = intc_disable;
+ d->chip.enable = intc_enable;
+ d->chip.disable = intc_disable;
+ d->chip.shutdown = intc_disable;
d->chip.set_type = intc_set_sense;
+ d->chip.set_wake = intc_set_wake;
#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
if (desc->ack_regs) {
BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
+ /* keep the first vector only if same enum is used multiple times */
for (i = 0; i < desc->nr_vectors; i++) {
struct intc_vect *vect = desc->vectors + i;
+ int first_irq = evt2irq(vect->vect);
+
+ if (!vect->enum_id)
+ continue;
+
+ for (k = i + 1; k < desc->nr_vectors; k++) {
+ struct intc_vect *vect2 = desc->vectors + k;
+
+ if (vect->enum_id != vect2->enum_id)
+ continue;
+
+ vect2->enum_id = 0;
+
+ if (!intc_evt2irq_table)
+ intc_evt2irq_table = alloc_bootmem(NR_IRQS);
+
+ if (!intc_evt2irq_table) {
+ pr_warning("intc: cannot allocate evt2irq!\n");
+ continue;
+ }
- intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
+ intc_evt2irq_table[evt2irq(vect2->vect)] = first_irq;
+ }
}
+
+ /* register the vectors one by one */
+ for (i = 0; i < desc->nr_vectors; i++) {
+ struct intc_vect *vect = desc->vectors + i;
+ unsigned int irq = evt2irq(vect->vect);
+ struct irq_desc *irq_desc;
+
+ if (!vect->enum_id)
+ continue;
+
+ irq_desc = irq_to_desc_alloc_cpu(irq, cpu);
+ if (unlikely(!irq_desc)) {
+ printk(KERN_INFO "can not get irq_desc for %d\n", irq);
+ continue;
+ }
+
+ intc_register_irq(desc, d, vect->enum_id, irq);
+ }
+}
+
+static int intc_suspend(struct sys_device *dev, pm_message_t state)
+{
+ struct intc_desc_int *d;
+ struct irq_desc *desc;
+ int irq;
+
+ /* get intc controller associated with this sysdev */
+ d = container_of(dev, struct intc_desc_int, sysdev);
+
+ switch (state.event) {
+ case PM_EVENT_ON:
+ if (d->state.event != PM_EVENT_FREEZE)
+ break;
+ for_each_irq_desc(irq, desc) {
+ if (desc->chip != &d->chip)
+ continue;
+ if (desc->status & IRQ_DISABLED)
+ intc_disable(irq);
+ else
+ intc_enable(irq);
+ }
+ break;
+ case PM_EVENT_FREEZE:
+ /* nothing has to be done */
+ break;
+ case PM_EVENT_SUSPEND:
+ /* enable wakeup irqs belonging to this intc controller */
+ for_each_irq_desc(irq, desc) {
+ if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
+ intc_enable(irq);
+ }
+ break;
+ }
+ d->state = state;
+
+ return 0;
}
+
+static int intc_resume(struct sys_device *dev)
+{
+ return intc_suspend(dev, PMSG_ON);
+}
+
+static struct sysdev_class intc_sysdev_class = {
+ .name = "intc",
+ .suspend = intc_suspend,
+ .resume = intc_resume,
+};
+
+/* register this intc as sysdev to allow suspend/resume */
+static int __init register_intc_sysdevs(void)
+{
+ struct intc_desc_int *d;
+ int error;
+ int id = 0;
+
+ error = sysdev_class_register(&intc_sysdev_class);
+ if (!error) {
+ list_for_each_entry(d, &intc_list, list) {
+ d->sysdev.id = id;
+ d->sysdev.cls = &intc_sysdev_class;
+ error = sysdev_register(&d->sysdev);
+ if (error)
+ break;
+ id++;
+ }
+ }
+
+ if (error)
+ pr_warning("intc: sysdev registration error\n");
+
+ return error;
+}
+
+device_initcall(register_intc_sysdevs);