x86, mce: fix reporting of Thermal Monitoring mechanism enabled
[linux-2.6.git] / arch / x86 / kernel / cpu / mcheck / therm_throt.c
index 7a508aa..15f2bc0 100644 (file)
@@ -24,7 +24,6 @@
 #include <linux/smp.h>
 #include <linux/cpu.h>
 
-#include <asm/therm_throt.h>
 #include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/apic.h>
@@ -38,7 +37,7 @@
 static DEFINE_PER_CPU(__u64, next_check) = INITIAL_JIFFIES;
 static DEFINE_PER_CPU(unsigned long, thermal_throttle_count);
 
-atomic_t therm_throt_en                = ATOMIC_INIT(0);
+static atomic_t therm_throt_en         = ATOMIC_INIT(0);
 
 #ifdef CONFIG_SYSFS
 #define define_therm_throt_sysdev_one_ro(_name)                                \
@@ -93,7 +92,7 @@ static struct attribute_group thermal_throttle_attr_group = {
  *          1 : Event should be logged further, and a message has been
  *              printed to the syslog.
  */
-int therm_throt_process(int curr)
+static int therm_throt_process(int curr)
 {
        unsigned int cpu = smp_processor_id();
        __u64 tmp_jiffs = get_jiffies_64();
@@ -202,7 +201,7 @@ device_initcall(thermal_throttle_init_device);
 #endif /* CONFIG_SYSFS */
 
 /* Thermal transition interrupt handler */
-void intel_thermal_interrupt(void)
+static void intel_thermal_interrupt(void)
 {
        __u64 msr_val;
 
@@ -231,11 +230,6 @@ asmlinkage void smp_thermal_interrupt(struct pt_regs *regs)
        ack_APIC_irq();
 }
 
-void intel_set_thermal_handler(void)
-{
-       smp_thermal_vector = intel_thermal_interrupt;
-}
-
 void intel_init_thermal(struct cpuinfo_x86 *c)
 {
        unsigned int cpu = smp_processor_id();
@@ -259,9 +253,6 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
                return;
        }
 
-       if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))
-               tm2 = 1;
-
        /* Check whether a vector already exists */
        if (h & APIC_VECTOR_MASK) {
                printk(KERN_DEBUG
@@ -270,6 +261,16 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
                return;
        }
 
+       /* early Pentium M models use different method for enabling TM2 */
+       if (cpu_has(c, X86_FEATURE_TM2)) {
+               if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
+                       rdmsr(MSR_THERM2_CTL, l, h);
+                       if (l & MSR_THERM2_CTL_TM_SELECT)
+                               tm2 = 1;
+               } else if (l & MSR_IA32_MISC_ENABLE_TM2)
+                       tm2 = 1;
+       }
+
        /* We'll mask the thermal vector in the lapic till we're ready: */
        h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
        apic_write(APIC_LVTTHMR, h);
@@ -278,7 +279,7 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
        wrmsr(MSR_IA32_THERM_INTERRUPT,
                l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);
 
-       intel_set_thermal_handler();
+       smp_thermal_vector = intel_thermal_interrupt;
 
        rdmsr(MSR_IA32_MISC_ENABLE, l, h);
        wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);