[PATCH] ppc32 8xx: Added setbitsXX/clrbitsXX macro for read-modify-write operations

[linux-2.6.git] / arch / ppc / syslib / m8xx_setup.c

diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c
index a192719929d37dadf8770cbc0c305606ebede756..ff0282479a781f93712ee87be57aa68b8be01c56 100644 (file)
--- a/arch/ppc/syslib/m8xx_setup.c
+++ b/arch/ppc/syslib/m8xx_setup.c
@@ -45,6 +45,7 @@
 #include <asm/bootinfo.h>
 #include <asm/time.h>
 #include <asm/xmon.h>
+#include <asm/ppc_sys.h>
 
 #include "ppc8xx_pic.h"
 
@@ -134,6 +135,18 @@ static struct irqaction tbint_irqaction = {
        .name = "tbint",
 };
 
+/* per-board overridable init_internal_rtc() function. */
+void __init __attribute__ ((weak))
+init_internal_rtc(void)
+{
+       /* Disable the RTC one second and alarm interrupts. */
+       clrbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
+
+       /* Enable the RTC */
+       setbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
+
+}
+
 /* The decrementer counts at the system (internal) clock frequency divided by
  * sixteen, or external oscillator divided by four.  We force the processor
  * to use system clock divided by sixteen.
@@ -148,8 +161,7 @@ void __init m8xx_calibrate_decr(void)
        out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY);
 
        /* Force all 8xx processors to use divide by 16 processor clock. */
-       out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr,
-               in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr)|0x02000000);
+       setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr, 0x02000000);
        /* Processor frequency is MHz.
         * The value 'fp' is the number of decrementer ticks per second.
         */
@@ -182,10 +194,7 @@ void __init m8xx_calibrate_decr(void)
        out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, KAPWR_KEY);
        out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, KAPWR_KEY);
 
-       /* Disable the RTC one second and alarm interrupts. */
-       out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) & ~(RTCSC_SIE | RTCSC_ALE));
-       /* Enable the RTC */
-       out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) | (RTCSC_RTF | RTCSC_RTE));
+       init_internal_rtc();
 
        /* Enabling the decrementer also enables the timebase interrupts
         * (or from the other point of view, to get decrementer interrupts
@@ -231,8 +240,8 @@ m8xx_restart(char *cmd)
        __volatile__ unsigned char dummy;
 
        local_irq_disable();
-       out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr) | 0x00000080);
 
+       setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, 0x00000080);
        /* Clear the ME bit in MSR to cause checkstop on machine check
        */
        mtmsr(mfmsr() & ~0x1000);
@@ -302,8 +311,8 @@ m8xx_init_IRQ(void)
        i8259_init(0);
 
        /* The i8259 cascade interrupt must be level sensitive. */
-       out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, in_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel & ~(0x80000000 >> ISA_BRIDGE_INT)));
 
+       clrbits32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, (0x80000000 >> ISA_BRIDGE_INT));
        if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction))
                enable_irq(ISA_BRIDGE_INT);
 #endif /* CONFIG_PCI */
@@ -399,6 +408,8 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
                strcpy(cmd_line, (char *)(r6+KERNELBASE));
        }
 
+       identify_ppc_sys_by_name(BOARD_CHIP_NAME);
+
        ppc_md.setup_arch               = m8xx_setup_arch;
        ppc_md.show_percpuinfo          = m8xx_show_percpuinfo;
        ppc_md.init_IRQ                 = m8xx_init_IRQ;