[PATCH] RapidIO support: ppc32
[linux-2.6.git] / arch / ppc / platforms / 85xx / stx_gp3.c
index bc95836..15ce9d0 100644 (file)
@@ -30,7 +30,6 @@
 #include <linux/blkdev.h>
 #include <linux/console.h>
 #include <linux/delay.h>
-#include <linux/irq.h>
 #include <linux/root_dev.h>
 #include <linux/seq_file.h>
 #include <linux/serial.h>
@@ -38,6 +37,7 @@
 #include <linux/module.h>
 #include <linux/fsl_devices.h>
 #include <linux/interrupt.h>
+#include <linux/rio.h>
 
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/time.h>
 #include <asm/io.h>
 #include <asm/machdep.h>
-#include <asm/prom.h>
 #include <asm/open_pic.h>
 #include <asm/bootinfo.h>
 #include <asm/pci-bridge.h>
 #include <asm/mpc85xx.h>
 #include <asm/irq.h>
 #include <asm/immap_85xx.h>
-#include <asm/immap_cpm2.h>
+#include <asm/cpm2.h>
 #include <asm/mpc85xx.h>
 #include <asm/ppc_sys.h>
 
 #include <syslib/cpm2_pic.h>
 #include <syslib/ppc85xx_common.h>
+#include <syslib/ppc85xx_rio.h>
 
-extern void cpm2_reset(void);
 
 unsigned char __res[sizeof(bd_t)];
 
@@ -72,38 +71,7 @@ unsigned long pci_dram_offset = 0;
 
 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
 static u8 gp3_openpic_initsenses[] __initdata = {
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  0: L2 Cache */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  1: ECM */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  2: DDR DRAM */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  3: LBIU */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  4: DMA 0 */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  5: DMA 1 */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  6: DMA 2 */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  7: DMA 3 */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  8: PCI/PCI-X */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  9: RIO Inbound Port Write Error */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 10: RIO Doorbell Inbound */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 11: RIO Outbound Message */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 12: RIO Inbound Message */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 13: TSEC 0 Transmit */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 14: TSEC 0 Receive */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 15: Unused */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 16: Unused */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 17: Unused */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 18: TSEC 0 Receive/Transmit Error */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 19: TSEC 1 Transmit */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 20: TSEC 1 Receive */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 21: Unused */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 22: Unused */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 23: Unused */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 24: TSEC 1 Receive/Transmit Error */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 25: Fast Ethernet */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 26: DUART */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 27: I2C */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 28: Performance Monitor */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 29: Unused */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 30: CPM */
-       (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 31: Unused */
+       MPC85XX_INTERNAL_IRQ_SENSES,
        0x0,                                            /* External  0: */
 #if defined(CONFIG_PCI)
        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 1: PCI slot 0 */
@@ -125,6 +93,9 @@ static u8 gp3_openpic_initsenses[] __initdata = {
        0x0,                            /* External 11: */
 };
 
+static const char *GFAR_PHY_2 = "phy0:2";
+static const char *GFAR_PHY_4 = "phy0:4";
+
 /*
  * Setup the architecture
  */
@@ -134,6 +105,7 @@ gp3_setup_arch(void)
        bd_t *binfo = (bd_t *) __res;
        unsigned int freq;
        struct gianfar_platform_data *pdata;
+       struct gianfar_mdio_data *mdata;
 
        cpm2_reset();
 
@@ -152,21 +124,28 @@ gp3_setup_arch(void)
        mpc85xx_setup_hose();
 #endif
 
+       /* setup the board related info for the MDIO bus */
+       mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
+
+       mdata->irq[2] = MPC85xx_IRQ_EXT5;
+       mdata->irq[4] = MPC85xx_IRQ_EXT5;
+       mdata->irq[31] = -1;
+       mdata->paddr += binfo->bi_immr_base;
+
        /* setup the board related information for the enet controllers */
        pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
-/*     pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
-       pdata->interruptPHY = MPC85xx_IRQ_EXT5;
-       pdata->phyid = 2;
-       pdata->phy_reg_addr += binfo->bi_immr_base;
-       memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
+       if (pdata) {
+       /*      pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
+               pdata->bus_id = GFAR_PHY_2;
+               memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
+       }
 
        pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
-/*     pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
-       pdata->interruptPHY = MPC85xx_IRQ_EXT5;
-       pdata->phyid = 4;
-       /* fixup phy address */
-       pdata->phy_reg_addr += binfo->bi_immr_base;
-       memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
+       if (pdata) {
+       /*      pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
+               pdata->bus_id = GFAR_PHY_4;
+               memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
+       }
 
 #ifdef CONFIG_BLK_DEV_INITRD
        if (initrd_start)
@@ -200,7 +179,6 @@ static struct irqaction cpm2_irqaction = {
 static void __init
 gp3_init_IRQ(void)
 {
-       int i;
        bd_t *binfo = (bd_t *) __res;
 
        /*
@@ -218,7 +196,7 @@ gp3_init_IRQ(void)
        openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
 
        /* Map PIC IRQs 0-11 */
-       openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
+       openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
 
        /*
         * Let openpic interrupts starting from an offset, to
@@ -297,6 +275,18 @@ int mpc85xx_exclude_device(u_char bus, u_char devfn)
 }
 #endif /* CONFIG_PCI */
 
+#ifdef CONFIG_RAPIDIO
+void
+platform_rio_init(void)
+{
+       /*
+        * The STx firmware configures the RapidIO Local Access Window
+        * at 0xc0000000 with a size of 512MB.
+        */
+       mpc85xx_rio_setup(0xc0000000, 0x20000000);
+}
+#endif /* CONFIG_RAPIDIO */
+
 void __init
 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
              unsigned long r6, unsigned long r7)