[MIPS] Sibyte: Finish conversion to modern time APIs.
[linux-2.6.git] / arch / mips / sibyte / sb1250 / time.c
index 2efffe1..9ef5462 100644 (file)
@@ -25,6 +25,7 @@
  * code to do general bookkeeping (e.g. update jiffies, run
  * bottom halves, etc.)
  */
+#include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/sched.h>
 #include <linux/spinlock.h>
@@ -71,16 +72,87 @@ void __init sb1250_hpt_setup(void)
        }
 }
 
+/*
+ * The general purpose timer ticks at 1 Mhz independent if
+ * the rest of the system
+ */
+static void sibyte_set_mode(enum clock_event_mode mode,
+                           struct clock_event_device *evt)
+{
+       unsigned int cpu = smp_processor_id();
+       void __iomem *timer_cfg, *timer_init;
 
-void sb1250_time_init(void)
+       timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
+       timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
+
+       switch(mode) {
+       case CLOCK_EVT_MODE_PERIODIC:
+               __raw_writeq(0, timer_cfg);
+               __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
+               __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
+                            timer_cfg);
+               break;
+
+       case CLOCK_EVT_MODE_ONESHOT:
+               /* Stop the timer until we actually program a shot */
+       case CLOCK_EVT_MODE_SHUTDOWN:
+               __raw_writeq(0, timer_cfg);
+               break;
+
+       case CLOCK_EVT_MODE_UNUSED:     /* shuddup gcc */
+       case CLOCK_EVT_MODE_RESUME:
+               ;
+       }
+}
+
+static int
+sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
 {
-       int cpu = smp_processor_id();
-       int irq = K_INT_TIMER_0+cpu;
+       unsigned int cpu = smp_processor_id();
+       void __iomem *timer_cfg, *timer_init;
+
+       timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
+       timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
+
+       __raw_writeq(0, timer_cfg);
+       __raw_writeq(delta, timer_init);
+       __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);
+
+       return 0;
+}
+
+struct clock_event_device sibyte_hpt_clockevent = {
+       .name           = "sb1250-counter",
+       .features       = CLOCK_EVT_FEAT_PERIODIC,
+       .set_mode       = sibyte_set_mode,
+       .set_next_event = sibyte_next_event,
+       .shift          = 32,
+       .irq            = 0,
+};
+
+static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
+{
+       struct clock_event_device *cd = &sibyte_hpt_clockevent;
+
+       cd->event_handler(cd);
+
+       return IRQ_HANDLED;
+}
+
+static struct irqaction sibyte_irqaction = {
+       .handler        = sibyte_counter_handler,
+       .flags          = IRQF_DISABLED | IRQF_PERCPU,
+       .name           = "timer",
+};
+
+void __cpuinit sb1250_clockevent_init(void)
+{
+       struct clock_event_device *cd = &sibyte_hpt_clockevent;
+       unsigned int cpu = smp_processor_id();
+       int irq = K_INT_TIMER_0 + cpu;
 
        /* Only have 4 general purpose timers, and we use last one as hpt */
-       if (cpu > 2) {
-               BUG();
-       }
+       BUG_ON(cpu > 2);
 
        sb1250_mask_irq(cpu, irq);
 
@@ -88,24 +160,11 @@ void sb1250_time_init(void)
        __raw_writeq(IMR_IP4_VAL,
                     IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
                            (irq << 3)));
-
-       /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
-       /* Disable the timer and set up the count */
-       __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
-#ifdef CONFIG_SIMULATION
-       __raw_writeq((50000 / HZ) - 1,
-                    IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
-#else
-       __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
-                    IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
-#endif
-
-       /* Set the timer running */
-       __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
-                    IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
+       cd->cpumask = cpumask_of_cpu(0);
 
        sb1250_unmask_irq(cpu, irq);
        sb1250_steal_irq(irq);
+
        /*
         * This interrupt is "special" in that it doesn't use the request_irq
         * way to hook the irq line.  The timer interrupt is initialized early
@@ -114,29 +173,9 @@ void sb1250_time_init(void)
         * called directly from irq_handler.S when IP[4] is set during an
         * interrupt
         */
-}
-
-void sb1250_timer_interrupt(void)
-{
-       int cpu = smp_processor_id();
-       int irq = K_INT_TIMER_0 + cpu;
-
-       /* ACK interrupt */
-       ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
-                      IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
+       setup_irq(irq, &sibyte_irqaction);
 
-       if (cpu == 0) {
-               /*
-                * CPU 0 handles the global timer interrupt job
-                */
-               ll_timer_interrupt(irq);
-       }
-       else {
-               /*
-                * other CPUs should just do profiling and process accounting
-                */
-               ll_local_timer_interrupt(irq);
-       }
+       clockevents_register_device(cd);
 }
 
 /*
@@ -151,3 +190,26 @@ static cycle_t sb1250_hpt_read(void)
 
        return SB1250_HPT_VALUE - count;
 }
+
+struct clocksource bcm1250_clocksource = {
+       .name   = "MIPS",
+       .rating = 200,
+       .read   = sb1250_hpt_read,
+       .mask   = CLOCKSOURCE_MASK(32),
+       .shift  = 32,
+       .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+void __init sb1250_clocksource_init(void)
+{
+       struct clocksource *cs = &bcm1250_clocksource;
+
+       clocksource_set_clock(cs, V_SCD_TIMER_FREQ);
+       clocksource_register(cs);
+}
+
+void __init plat_time_init(void)
+{
+       sb1250_clocksource_init();
+       sb1250_clockevent_init();
+}