MIPS: Octeon: Workaround link failures with gcc-4.4.x 32-bits toolchains
[linux-2.6.git] / arch / mips / cavium-octeon / csrc-octeon.c
index 70fd92c..36400d2 100644 (file)
@@ -38,7 +38,7 @@ void octeon_init_cvmcount(void)
        local_irq_restore(flags);
 }
 
-static cycle_t octeon_cvmcount_read(void)
+static cycle_t octeon_cvmcount_read(struct clocksource *cs)
 {
        return read_c0_cvmcount();
 }
@@ -50,6 +50,30 @@ static struct clocksource clocksource_mips = {
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+unsigned long long notrace sched_clock(void)
+{
+       /* 64-bit arithmatic can overflow, so use 128-bit.  */
+       u64 t1, t2, t3;
+       unsigned long long rv;
+       u64 mult = clocksource_mips.mult;
+       u64 shift = clocksource_mips.shift;
+       u64 cnt = read_c0_cvmcount();
+
+       asm (
+               "dmultu\t%[cnt],%[mult]\n\t"
+               "nor\t%[t1],$0,%[shift]\n\t"
+               "mfhi\t%[t2]\n\t"
+               "mflo\t%[t3]\n\t"
+               "dsll\t%[t2],%[t2],1\n\t"
+               "dsrlv\t%[rv],%[t3],%[shift]\n\t"
+               "dsllv\t%[t1],%[t2],%[t1]\n\t"
+               "or\t%[rv],%[t1],%[rv]\n\t"
+               : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3)
+               : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
+               : "hi", "lo");
+       return rv;
+}
+
 void __init plat_time_init(void)
 {
        clocksource_mips.rating = 300;