* use agp op-combining
* use GET semantics to fetch memory
* participate in coherency domain
- * prefetch TLB entries
+ * DISABLE GART PREFETCHING due to hw bug tracked in SGI PV930029
*/
ca_base->ca_control1 |= CA_AGPDMA_OP_ENB_COMBDELAY; /* PV895469 ? */
ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM);
ca_base->ca_control2 |= (0x2ull << CA_GART_MEM_PARAM_SHFT);
tioca_kern->ca_gart_iscoherent = 1;
- ca_base->ca_control2 |=
- (CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB);
+ ca_base->ca_control2 &=
+ ~(CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB);
/*
* Unmask GART fetch error interrupts. Clear residual errors first.
if (!ct_addr)
return 0;
- bus_addr = (dma_addr_t) (ct_addr & 0xffffffffffff);
+ bus_addr = (dma_addr_t) (ct_addr & 0xffffffffffffUL);
node_upper = ct_addr >> 48;
if (node_upper > 64) {
ca_dmamap->cad_dma_addr = bus_addr;
ca_dmamap->cad_gart_size = entries;
ca_dmamap->cad_gart_entry = entry;
- list_add(&ca_dmamap->cad_list, &tioca_kern->ca_list);
+ list_add(&ca_dmamap->cad_list, &tioca_kern->ca_dmamaps);
if (xio_addr % ps) {
tioca_kern->ca_pcigart[entry] = tioca_paddr_to_gart(xio_addr);
* For mappings created using the direct modes (64 or 48) there are no
* resources to release.
*/
-void
+static void
tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
{
int i, entry;
* The mapping mode used is based on the devices dma_mask. As a last resort
* use the GART mapped mode.
*/
-uint64_t
+static uint64_t
tioca_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count)
{
uint64_t mapaddr;
* On successful setup, returns the kernel version of tioca_common back to
* the caller.
*/
-void *
+static void *
tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft)
{
struct tioca_common *tioca_common;