arm, cris, mips, sparc, powerpc, um, xtensa: fix build with bash 4.0
[linux-2.6.git] / arch / blackfin / mach-common / dpmc_modes.S
index 5e3f1d8..8009a51 100644 (file)
@@ -6,7 +6,7 @@
 
 #include <linux/linkage.h>
 #include <asm/blackfin.h>
-#include <asm/mach/irq.h>
+#include <mach/irq.h>
 #include <asm/dpmc.h>
 
 .section .l1.text
@@ -78,62 +78,6 @@ ENTRY(_hibernate_mode)
        jump .Lforever;
 ENDPROC(_hibernate_mode)
 
-ENTRY(_deep_sleep)
-       [--SP] = ( R7:0, P5:0 );
-       [--SP] =  RETS;
-
-       CLI R4;
-
-       R0 = IWR_ENABLE(0);
-       R1 = IWR_DISABLE_ALL;
-       R2 = IWR_DISABLE_ALL;
-
-       call _set_sic_iwr;
-
-       call _set_dram_srfs;
-
-       /* Clear all the interrupts,bits sticky */
-       R0 = 0xFFFF (Z);
-       call _set_rtc_istat
-
-       P0.H = hi(PLL_CTL);
-       P0.L = lo(PLL_CTL);
-       R0 = W[P0](z);
-       BITSET (R0, 5);
-       W[P0] = R0.L;
-
-       call _test_pll_locked;
-
-       SSYNC;
-       IDLE;
-
-       call _unset_dram_srfs;
-
-       call _test_pll_locked;
-
-       R0 = IWR_ENABLE(0);
-       R1 = IWR_DISABLE_ALL;
-       R2 = IWR_DISABLE_ALL;
-
-       call _set_sic_iwr;
-
-       P0.H = hi(PLL_CTL);
-       P0.L = lo(PLL_CTL);
-       R0 = w[p0](z);
-       BITCLR (R0, 3);
-       BITCLR (R0, 5);
-       BITCLR (R0, 8);
-       w[p0] = R0;
-       IDLE;
-       call _test_pll_locked;
-
-       STI R4;
-
-       RETS = [SP++];
-       ( R7:0, P5:0 ) = [SP++];
-       RTS;
-ENDPROC(_deep_sleep)
-
 ENTRY(_sleep_deeper)
        [--SP] = ( R7:0, P5:0 );
        [--SP] =  RETS;
@@ -303,7 +247,8 @@ ENTRY(_unset_dram_srfs)
 ENDPROC(_unset_dram_srfs)
 
 ENTRY(_set_sic_iwr)
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
+       defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
        P0.H = hi(SIC_IWR0);
        P0.L = lo(SIC_IWR0);
        P1.H = hi(SIC_IWR1);
@@ -431,10 +376,22 @@ ENTRY(_do_hibernate)
 #endif
 
 #ifdef PINT0_ASSIGN
+       PM_SYS_PUSH(PINT0_MASK_SET)
+       PM_SYS_PUSH(PINT1_MASK_SET)
+       PM_SYS_PUSH(PINT2_MASK_SET)
+       PM_SYS_PUSH(PINT3_MASK_SET)
        PM_SYS_PUSH(PINT0_ASSIGN)
        PM_SYS_PUSH(PINT1_ASSIGN)
        PM_SYS_PUSH(PINT2_ASSIGN)
        PM_SYS_PUSH(PINT3_ASSIGN)
+       PM_SYS_PUSH(PINT0_INVERT_SET)
+       PM_SYS_PUSH(PINT1_INVERT_SET)
+       PM_SYS_PUSH(PINT2_INVERT_SET)
+       PM_SYS_PUSH(PINT3_INVERT_SET)
+       PM_SYS_PUSH(PINT0_EDGE_SET)
+       PM_SYS_PUSH(PINT1_EDGE_SET)
+       PM_SYS_PUSH(PINT2_EDGE_SET)
+       PM_SYS_PUSH(PINT3_EDGE_SET)
 #endif
 
        PM_SYS_PUSH(EBIU_AMBCTL0)
@@ -769,10 +726,22 @@ ENTRY(_do_hibernate)
        PM_SYS_POP(EBIU_AMBCTL0)
 
 #ifdef PINT0_ASSIGN
+       PM_SYS_POP(PINT3_EDGE_SET)
+       PM_SYS_POP(PINT2_EDGE_SET)
+       PM_SYS_POP(PINT1_EDGE_SET)
+       PM_SYS_POP(PINT0_EDGE_SET)
+       PM_SYS_POP(PINT3_INVERT_SET)
+       PM_SYS_POP(PINT2_INVERT_SET)
+       PM_SYS_POP(PINT1_INVERT_SET)
+       PM_SYS_POP(PINT0_INVERT_SET)
        PM_SYS_POP(PINT3_ASSIGN)
        PM_SYS_POP(PINT2_ASSIGN)
        PM_SYS_POP(PINT1_ASSIGN)
        PM_SYS_POP(PINT0_ASSIGN)
+       PM_SYS_POP(PINT3_MASK_SET)
+       PM_SYS_POP(PINT2_MASK_SET)
+       PM_SYS_POP(PINT1_MASK_SET)
+       PM_SYS_POP(PINT0_MASK_SET)
 #endif
 
 #ifdef SICA_IWR1