arm, cris, mips, sparc, powerpc, um, xtensa: fix build with bash 4.0
[linux-2.6.git] / arch / blackfin / mach-common / dpmc_modes.S
index 46ee77a..8009a51 100644 (file)
@@ -6,7 +6,7 @@
 
 #include <linux/linkage.h>
 #include <asm/blackfin.h>
-#include <asm/mach/irq.h>
+#include <mach/irq.h>
 #include <asm/dpmc.h>
 
 .section .l1.text
@@ -51,6 +51,7 @@ ENTRY(_sleep_mode)
        RETS = [SP++];
        ( R7:0, P5:0 ) = [SP++];
        RTS;
+ENDPROC(_sleep_mode)
 
 ENTRY(_hibernate_mode)
        [--SP] = ( R7:0, P5:0 );
@@ -75,61 +76,7 @@ ENTRY(_hibernate_mode)
        IDLE;
 .Lforever:
        jump .Lforever;
-
-ENTRY(_deep_sleep)
-       [--SP] = ( R7:0, P5:0 );
-       [--SP] =  RETS;
-
-       CLI R4;
-
-       R0 = IWR_ENABLE(0);
-       R1 = IWR_DISABLE_ALL;
-       R2 = IWR_DISABLE_ALL;
-
-       call _set_sic_iwr;
-
-       call _set_dram_srfs;
-
-       /* Clear all the interrupts,bits sticky */
-       R0 = 0xFFFF (Z);
-       call _set_rtc_istat
-
-       P0.H = hi(PLL_CTL);
-       P0.L = lo(PLL_CTL);
-       R0 = W[P0](z);
-       BITSET (R0, 5);
-       W[P0] = R0.L;
-
-       call _test_pll_locked;
-
-       SSYNC;
-       IDLE;
-
-       call _unset_dram_srfs;
-
-       call _test_pll_locked;
-
-       R0 = IWR_ENABLE(0);
-       R1 = IWR_DISABLE_ALL;
-       R2 = IWR_DISABLE_ALL;
-
-       call _set_sic_iwr;
-
-       P0.H = hi(PLL_CTL);
-       P0.L = lo(PLL_CTL);
-       R0 = w[p0](z);
-       BITCLR (R0, 3);
-       BITCLR (R0, 5);
-       BITCLR (R0, 8);
-       w[p0] = R0;
-       IDLE;
-       call _test_pll_locked;
-
-       STI R4;
-
-       RETS = [SP++];
-       ( R7:0, P5:0 ) = [SP++];
-       RTS;
+ENDPROC(_hibernate_mode)
 
 ENTRY(_sleep_deeper)
        [--SP] = ( R7:0, P5:0 );
@@ -231,7 +178,7 @@ ENTRY(_sleep_deeper)
        RETS = [SP++];
        ( R7:0, P5:0 ) = [SP++];
        RTS;
-
+ENDPROC(_sleep_deeper)
 
 ENTRY(_set_dram_srfs)
        /*  set the dram to self refresh mode */
@@ -270,7 +217,7 @@ ENTRY(_set_dram_srfs)
        [P0] = R2;
 #endif
        RTS;
-
+ENDPROC(_set_dram_srfs)
 
 ENTRY(_unset_dram_srfs)
        /*  set the dram out of self refresh mode */
@@ -297,9 +244,11 @@ ENTRY(_unset_dram_srfs)
 #endif
        SSYNC;
        RTS;
+ENDPROC(_unset_dram_srfs)
 
 ENTRY(_set_sic_iwr)
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
+       defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
        P0.H = hi(SIC_IWR0);
        P0.L = lo(SIC_IWR0);
        P1.H = hi(SIC_IWR1);
@@ -318,6 +267,7 @@ ENTRY(_set_sic_iwr)
 
        SSYNC;
        RTS;
+ENDPROC(_set_sic_iwr)
 
 ENTRY(_set_rtc_istat)
 #ifndef CONFIG_BF561
@@ -332,6 +282,7 @@ ENTRY(_set_rtc_istat)
        nop;
 #endif
        RTS;
+ENDPROC(_set_rtc_istat)
 
 ENTRY(_test_pll_locked)
        P0.H = hi(PLL_STAT);
@@ -341,10 +292,10 @@ ENTRY(_test_pll_locked)
        CC = BITTST(R0,5);
        IF !CC JUMP 1b;
        RTS;
+ENDPROC(_test_pll_locked)
 
 .section .text
 
-
 ENTRY(_do_hibernate)
        [--SP] = ( R7:0, P5:0 );
        [--SP] =  RETS;
@@ -425,10 +376,22 @@ ENTRY(_do_hibernate)
 #endif
 
 #ifdef PINT0_ASSIGN
+       PM_SYS_PUSH(PINT0_MASK_SET)
+       PM_SYS_PUSH(PINT1_MASK_SET)
+       PM_SYS_PUSH(PINT2_MASK_SET)
+       PM_SYS_PUSH(PINT3_MASK_SET)
        PM_SYS_PUSH(PINT0_ASSIGN)
        PM_SYS_PUSH(PINT1_ASSIGN)
        PM_SYS_PUSH(PINT2_ASSIGN)
        PM_SYS_PUSH(PINT3_ASSIGN)
+       PM_SYS_PUSH(PINT0_INVERT_SET)
+       PM_SYS_PUSH(PINT1_INVERT_SET)
+       PM_SYS_PUSH(PINT2_INVERT_SET)
+       PM_SYS_PUSH(PINT3_INVERT_SET)
+       PM_SYS_PUSH(PINT0_EDGE_SET)
+       PM_SYS_PUSH(PINT1_EDGE_SET)
+       PM_SYS_PUSH(PINT2_EDGE_SET)
+       PM_SYS_PUSH(PINT3_EDGE_SET)
 #endif
 
        PM_SYS_PUSH(EBIU_AMBCTL0)
@@ -593,8 +556,8 @@ ENTRY(_do_hibernate)
        R0.H = 0xDEAD;  /* Hibernate Magic */
        R0.L = 0xBEEF;
        [P0++] = R0;    /* Store Hibernate Magic */
-       R0.H = pm_resume_here;
-       R0.L = pm_resume_here;
+       R0.H = .Lpm_resume_here;
+       R0.L = .Lpm_resume_here;
        [P0++] = R0;    /* Save Return Address */
        [P0++] = SP;    /* Save Stack Pointer */
        P0.H = _hibernate_mode;
@@ -602,7 +565,7 @@ ENTRY(_do_hibernate)
        R0 = R2;
        call (P0); /* Goodbye */
 
-pm_resume_here:
+.Lpm_resume_here:
 
        /* Restore Core Registers */
        SEQSTAT = [sp++];
@@ -763,10 +726,22 @@ pm_resume_here:
        PM_SYS_POP(EBIU_AMBCTL0)
 
 #ifdef PINT0_ASSIGN
+       PM_SYS_POP(PINT3_EDGE_SET)
+       PM_SYS_POP(PINT2_EDGE_SET)
+       PM_SYS_POP(PINT1_EDGE_SET)
+       PM_SYS_POP(PINT0_EDGE_SET)
+       PM_SYS_POP(PINT3_INVERT_SET)
+       PM_SYS_POP(PINT2_INVERT_SET)
+       PM_SYS_POP(PINT1_INVERT_SET)
+       PM_SYS_POP(PINT0_INVERT_SET)
        PM_SYS_POP(PINT3_ASSIGN)
        PM_SYS_POP(PINT2_ASSIGN)
        PM_SYS_POP(PINT1_ASSIGN)
        PM_SYS_POP(PINT0_ASSIGN)
+       PM_SYS_POP(PINT3_MASK_SET)
+       PM_SYS_POP(PINT2_MASK_SET)
+       PM_SYS_POP(PINT1_MASK_SET)
+       PM_SYS_POP(PINT0_MASK_SET)
 #endif
 
 #ifdef SICA_IWR1
@@ -846,3 +821,4 @@ pm_resume_here:
        RETS = [SP++];
        ( R7:0, P5:0 ) = [SP++];
        RTS;
+ENDPROC(_do_hibernate)