Blackfin arch: rewrite our reboot code in C
[linux-2.6.git] / arch / blackfin / mach-bf533 / head.S
index 7cb8258..6e1b5f6 100644 (file)
  */
 
 #include <linux/linkage.h>
+#include <linux/init.h>
 #include <asm/blackfin.h>
+#include <asm/trace.h>
 #if CONFIG_BFIN_KERNEL_CLOCK
+#include <asm/mach-common/clocks.h>
 #include <asm/mach/mem_init.h>
 #endif
 #if CONFIG_DEBUG_KERNEL_START
 
 #define INITIAL_STACK  0xFFB01000
 
-.text
+__INIT
 
 ENTRY(__start)
-ENTRY(__stext)
        /* R0: argument of command line string, passed from uboot, save it */
        R7 = R0;
-       /* Set the SYSCFG register */
-       R0 = 0x36;
-       /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
+       /* Enable Cycle Counter and Nesting Of Interrupts */
+#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
+       R0 = SYSCFG_SNEN;
+#else
+       R0 = SYSCFG_SNEN | SYSCFG_CCEN;
+#endif
        SYSCFG = R0;
        R0 = 0;
 
-       /*Clear Out All the data and pointer  Registers*/
+       /* Clear Out All the data and pointer Registers */
        R1 = R0;
        R2 = R0;
        R3 = R0;
@@ -79,7 +84,7 @@ ENTRY(__stext)
        L2 = r0;
        L3 = r0;
 
-       /* Clear Out All the DAG Registers*/
+       /* Clear Out All the DAG Registers */
        B0 = r0;
        B1 = r0;
        B2 = r0;
@@ -95,6 +100,10 @@ ENTRY(__stext)
        M2 = r0;
        M3 = r0;
 
+       trace_buffer_init(p0,r0);
+       P0 = R1;
+       R0 = R1;
+
 #if CONFIG_DEBUG_KERNEL_START
 
 /*
@@ -138,42 +147,43 @@ ENTRY(__stext)
        ssync;
 
        /* Turn off the icache */
-       p0.l = (IMEM_CONTROL & 0xFFFF);
-       p0.h = (IMEM_CONTROL >> 16);
+       p0.l = LO(IMEM_CONTROL);
+       p0.h = HI(IMEM_CONTROL);
        R1 = [p0];
        R0 = ~ENICPLB;
        R0 = R0 & R1;
 
        /* Anomaly 05000125 */
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        CLI R2;
        SSYNC;
 #endif
        [p0] = R0;
        SSYNC;
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        STI R2;
 #endif
 
        /* Turn off the dcache */
-       p0.l = (DMEM_CONTROL & 0xFFFF);
-       p0.h = (DMEM_CONTROL >> 16);
+       p0.l = LO(DMEM_CONTROL);
+       p0.h = HI(DMEM_CONTROL);
        R1 = [p0];
        R0 = ~ENDCPLB;
        R0 = R0 & R1;
 
        /* Anomaly 05000125 */
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        CLI R2;
        SSYNC;
 #endif
        [p0] = R0;
        SSYNC;
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        STI R2;
 #endif
 
-       /* Initialise UART */
+       /* Initialise UART - when booting from u-boot, the UART is not disabled
+        * so if we dont initalize here, our serial console gets hosed */
        p0.h = hi(UART_LCR);
        p0.l = lo(UART_LCR);
        r0 = 0x0(Z);
@@ -257,13 +267,14 @@ ENTRY(__stext)
        p0.l = .LWAIT_HERE;
        p0.h = .LWAIT_HERE;
        reti = p0;
-#if defined(ANOMALY_05000281)
+#if ANOMALY_05000281
        nop; nop; nop;
 #endif
        rti;
 
 .LWAIT_HERE:
        jump .LWAIT_HERE;
+ENDPROC(__start)
 
 ENTRY(_real_start)
        [ -- sp ] = reti;
@@ -302,7 +313,7 @@ ENTRY(_real_start)
 .L_clear_zero:
        W[p1++] = r0;
 
-/* pass the uboot arguments to the global value command line */
+       /* pass the uboot arguments to the global value command line */
        R0 = R7;
        call _cmdline_init;
 
@@ -321,7 +332,7 @@ ENTRY(_real_start)
        [p1] = r1;
 
        /*
-        *  load the current thread pointer and stack
+        * load the current thread pointer and stack
         */
        r1.l = _init_thread_union;
        r1.h = _init_thread_union;
@@ -332,9 +343,10 @@ ENTRY(_real_start)
        sp = r1;
        usp = sp;
        fp = sp;
-       call _start_kernel;
-.L_exit:
-       jump.s  .L_exit;
+       jump.l _start_kernel;
+ENDPROC(_real_start)
+
+__FINIT
 
 .section .l1.text
 #if CONFIG_BFIN_KERNEL_CLOCK
@@ -408,8 +420,8 @@ ENTRY(_start_dma_code)
        w[p0] = r0.l;
        ssync;
 
-       p0.l = (EBIU_SDBCTL & 0xFFFF);
-       p0.h = (EBIU_SDBCTL >> 16);     /* SDRAM Memory Bank Control Register */
+       p0.l = LO(EBIU_SDBCTL);
+       p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */
        r0 = mem_SDBCTL;
        w[p0] = r0.l;
        ssync;
@@ -438,110 +450,15 @@ ENTRY(_start_dma_code)
 
        p0.h = hi(SIC_IWR);
        p0.l = lo(SIC_IWR);
-       r0.l = lo(IWR_ENABLE_ALL)
-       r0.h = hi(IWR_ENABLE_ALL)
+       r0.l = lo(IWR_ENABLE_ALL);
+       r0.h = hi(IWR_ENABLE_ALL);
        [p0] = r0;
        SSYNC;
 
        RTS;
+ENDPROC(_start_dma_code)
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
 
-ENTRY(_bfin_reset)
-       /* No more interrupts to be handled*/
-       CLI R6;
-       SSYNC;
-
-#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
-       p0.h = hi(FIO_INEN);
-       p0.l = lo(FIO_INEN);
-       r0.l = ~(1 << CONFIG_ENET_FLASH_PIN);
-       w[p0] = r0.l;
-
-       p0.h = hi(FIO_DIR);
-       p0.l = lo(FIO_DIR);
-       r0.l = (1 << CONFIG_ENET_FLASH_PIN);
-       w[p0] = r0.l;
-
-       p0.h = hi(FIO_FLAG_C);
-       p0.l = lo(FIO_FLAG_C);
-       r0.l = (1 << CONFIG_ENET_FLASH_PIN);
-       w[p0] = r0.l;
-#endif
-
-       /* Clear the IMASK register */
-       p0.h = hi(IMASK);
-       p0.l = lo(IMASK);
-       r0 = 0x0;
-       [p0] = r0;
-
-       /* Clear the ILAT register */
-       p0.h = hi(ILAT);
-       p0.l = lo(ILAT);
-       r0 = [p0];
-       [p0] = r0;
-       SSYNC;
-
-       /* Disable the WDOG TIMER */
-       p0.h = hi(WDOG_CTL);
-       p0.l = lo(WDOG_CTL);
-       r0.l = 0xAD6;
-       w[p0] = r0.l;
-       SSYNC;
-
-       /* Clear the sticky bit incase it is already set */
-       p0.h = hi(WDOG_CTL);
-       p0.l = lo(WDOG_CTL);
-       r0.l = 0x8AD6;
-       w[p0] = r0.l;
-       SSYNC;
-
-       /* Program the count value */
-       R0.l = 0x100;
-       R0.h = 0x0;
-       P0.h = hi(WDOG_CNT);
-       P0.l = lo(WDOG_CNT);
-       [P0] = R0;
-       SSYNC;
-
-       /* Program WDOG_STAT if necessary */
-       P0.h = hi(WDOG_CTL);
-       P0.l = lo(WDOG_CTL);
-       R0 = W[P0](Z);
-       CC = BITTST(R0,1);
-       if !CC JUMP .LWRITESTAT;
-       CC = BITTST(R0,2);
-       if !CC JUMP .LWRITESTAT;
-       JUMP .LSKIP_WRITE;
-
-.LWRITESTAT:
-       /* When watch dog timer is enabled, a write to STAT will load the contents of CNT to STAT */
-       R0 = 0x0000(z);
-       P0.h = hi(WDOG_STAT);
-       P0.l = lo(WDOG_STAT)
-       [P0] = R0;
-       SSYNC;
-
-.LSKIP_WRITE:
-       /* Enable the reset event */
-       P0.h = hi(WDOG_CTL);
-       P0.l = lo(WDOG_CTL);
-       R0 = W[P0](Z);
-       BITCLR(R0,1);
-       BITCLR(R0,2);
-       W[P0] = R0.L;
-       SSYNC;
-       NOP;
-
-       /* Enable the wdog counter */
-       R0 = W[P0](Z);
-       BITCLR(R0,4);
-       W[P0] = R0.L;
-       SSYNC;
-
-       IDLE;
-
-       RTS;
-
 #if CONFIG_DEBUG_KERNEL_START
 debug_kernel_start_trap:
        /* Set up a temp stack in L1 - SDRAM might not be working  */