KVM: Merge kvm_ioapic_get_delivery_bitmask into kvm_get_intr_delivery_bitmask
[linux-2.6.git] / virt / kvm / ioapic.c
1 /*
2  *  Copyright (C) 2001  MandrakeSoft S.A.
3  *
4  *    MandrakeSoft S.A.
5  *    43, rue d'Aboukir
6  *    75002 Paris - France
7  *    http://www.linux-mandrake.com/
8  *    http://www.mandrakesoft.com/
9  *
10  *  This library is free software; you can redistribute it and/or
11  *  modify it under the terms of the GNU Lesser General Public
12  *  License as published by the Free Software Foundation; either
13  *  version 2 of the License, or (at your option) any later version.
14  *
15  *  This library is distributed in the hope that it will be useful,
16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  *  Lesser General Public License for more details.
19  *
20  *  You should have received a copy of the GNU Lesser General Public
21  *  License along with this library; if not, write to the Free Software
22  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  *
24  *  Yunhong Jiang <yunhong.jiang@intel.com>
25  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
26  *  Based on Xen 3.1 code.
27  */
28
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
31 #include <linux/mm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
35 #include <linux/io.h>
36 #include <asm/processor.h>
37 #include <asm/page.h>
38 #include <asm/current.h>
39
40 #include "ioapic.h"
41 #include "lapic.h"
42 #include "irq.h"
43
44 #if 0
45 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
46 #else
47 #define ioapic_debug(fmt, arg...)
48 #endif
49 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
50
51 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
52                                           unsigned long addr,
53                                           unsigned long length)
54 {
55         unsigned long result = 0;
56
57         switch (ioapic->ioregsel) {
58         case IOAPIC_REG_VERSION:
59                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
60                           | (IOAPIC_VERSION_ID & 0xff));
61                 break;
62
63         case IOAPIC_REG_APIC_ID:
64         case IOAPIC_REG_ARB_ID:
65                 result = ((ioapic->id & 0xf) << 24);
66                 break;
67
68         default:
69                 {
70                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
71                         u64 redir_content;
72
73                         ASSERT(redir_index < IOAPIC_NUM_PINS);
74
75                         redir_content = ioapic->redirtbl[redir_index].bits;
76                         result = (ioapic->ioregsel & 0x1) ?
77                             (redir_content >> 32) & 0xffffffff :
78                             redir_content & 0xffffffff;
79                         break;
80                 }
81         }
82
83         return result;
84 }
85
86 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
87 {
88         union kvm_ioapic_redirect_entry *pent;
89         int injected = -1;
90
91         pent = &ioapic->redirtbl[idx];
92
93         if (!pent->fields.mask) {
94                 injected = ioapic_deliver(ioapic, idx);
95                 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
96                         pent->fields.remote_irr = 1;
97         }
98         if (!pent->fields.trig_mode)
99                 ioapic->irr &= ~(1 << idx);
100
101         return injected;
102 }
103
104 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
105 {
106         unsigned index;
107         bool mask_before, mask_after;
108
109         switch (ioapic->ioregsel) {
110         case IOAPIC_REG_VERSION:
111                 /* Writes are ignored. */
112                 break;
113
114         case IOAPIC_REG_APIC_ID:
115                 ioapic->id = (val >> 24) & 0xf;
116                 break;
117
118         case IOAPIC_REG_ARB_ID:
119                 break;
120
121         default:
122                 index = (ioapic->ioregsel - 0x10) >> 1;
123
124                 ioapic_debug("change redir index %x val %x\n", index, val);
125                 if (index >= IOAPIC_NUM_PINS)
126                         return;
127                 mask_before = ioapic->redirtbl[index].fields.mask;
128                 if (ioapic->ioregsel & 1) {
129                         ioapic->redirtbl[index].bits &= 0xffffffff;
130                         ioapic->redirtbl[index].bits |= (u64) val << 32;
131                 } else {
132                         ioapic->redirtbl[index].bits &= ~0xffffffffULL;
133                         ioapic->redirtbl[index].bits |= (u32) val;
134                         ioapic->redirtbl[index].fields.remote_irr = 0;
135                 }
136                 mask_after = ioapic->redirtbl[index].fields.mask;
137                 if (mask_before != mask_after)
138                         kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
139                 if (ioapic->irr & (1 << index))
140                         ioapic_service(ioapic, index);
141                 break;
142         }
143 }
144
145 static int ioapic_inj_irq(struct kvm_ioapic *ioapic,
146                            struct kvm_vcpu *vcpu,
147                            u8 vector, u8 trig_mode, u8 delivery_mode)
148 {
149         ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode,
150                      delivery_mode);
151
152         ASSERT((delivery_mode == IOAPIC_FIXED) ||
153                (delivery_mode == IOAPIC_LOWEST_PRIORITY));
154
155         return kvm_apic_set_irq(vcpu, vector, trig_mode);
156 }
157
158 static void ioapic_inj_nmi(struct kvm_vcpu *vcpu)
159 {
160         kvm_inject_nmi(vcpu);
161         kvm_vcpu_kick(vcpu);
162 }
163
164 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
165 {
166         union kvm_ioapic_redirect_entry entry = ioapic->redirtbl[irq];
167         DECLARE_BITMAP(deliver_bitmask, KVM_MAX_VCPUS);
168         struct kvm_vcpu *vcpu;
169         int vcpu_id, r = -1;
170
171         ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
172                      "vector=%x trig_mode=%x\n",
173                      entry.fields.dest, entry.fields.dest_mode,
174                      entry.fields.delivery_mode, entry.fields.vector,
175                      entry.fields.trig_mode);
176
177         /* Always delivery PIT interrupt to vcpu 0 */
178 #ifdef CONFIG_X86
179         if (irq == 0) {
180                 bitmap_zero(deliver_bitmask, KVM_MAX_VCPUS);
181                 __set_bit(0, deliver_bitmask);
182         } else
183 #endif
184                 kvm_get_intr_delivery_bitmask(ioapic, &entry, deliver_bitmask);
185
186         if (find_first_bit(deliver_bitmask, KVM_MAX_VCPUS) >= KVM_MAX_VCPUS) {
187                 ioapic_debug("no target on destination\n");
188                 return 0;
189         }
190
191         while ((vcpu_id = find_first_bit(deliver_bitmask, KVM_MAX_VCPUS))
192                         < KVM_MAX_VCPUS) {
193                 __clear_bit(vcpu_id, deliver_bitmask);
194                 vcpu = ioapic->kvm->vcpus[vcpu_id];
195                 if (vcpu) {
196                         if (entry.fields.delivery_mode ==
197                                         IOAPIC_LOWEST_PRIORITY ||
198                             entry.fields.delivery_mode == IOAPIC_FIXED) {
199                                 if (r < 0)
200                                         r = 0;
201                                 r += ioapic_inj_irq(ioapic, vcpu,
202                                                     entry.fields.vector,
203                                                     entry.fields.trig_mode,
204                                                     entry.fields.delivery_mode);
205                         } else if (entry.fields.delivery_mode == IOAPIC_NMI) {
206                                 r = 1;
207                                 ioapic_inj_nmi(vcpu);
208                         } else
209                                 ioapic_debug("unsupported delivery mode %x!\n",
210                                              entry.fields.delivery_mode);
211                 } else
212                         ioapic_debug("null destination vcpu: "
213                                      "mask=%x vector=%x delivery_mode=%x\n",
214                                      entry.fields.deliver_bitmask,
215                                      entry.fields.vector,
216                                      entry.fields.delivery_mode);
217         }
218         return r;
219 }
220
221 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
222 {
223         u32 old_irr = ioapic->irr;
224         u32 mask = 1 << irq;
225         union kvm_ioapic_redirect_entry entry;
226         int ret = 1;
227
228         if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
229                 entry = ioapic->redirtbl[irq];
230                 level ^= entry.fields.polarity;
231                 if (!level)
232                         ioapic->irr &= ~mask;
233                 else {
234                         ioapic->irr |= mask;
235                         if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
236                             || !entry.fields.remote_irr)
237                                 ret = ioapic_service(ioapic, irq);
238                 }
239         }
240         return ret;
241 }
242
243 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
244                                     int trigger_mode)
245 {
246         union kvm_ioapic_redirect_entry *ent;
247
248         ent = &ioapic->redirtbl[pin];
249
250         kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
251
252         if (trigger_mode == IOAPIC_LEVEL_TRIG) {
253                 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
254                 ent->fields.remote_irr = 0;
255                 if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
256                         ioapic_service(ioapic, pin);
257         }
258 }
259
260 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
261 {
262         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
263         int i;
264
265         for (i = 0; i < IOAPIC_NUM_PINS; i++)
266                 if (ioapic->redirtbl[i].fields.vector == vector)
267                         __kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
268 }
269
270 static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
271                            int len, int is_write)
272 {
273         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
274
275         return ((addr >= ioapic->base_address &&
276                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
277 }
278
279 static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
280                              void *val)
281 {
282         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
283         u32 result;
284
285         ioapic_debug("addr %lx\n", (unsigned long)addr);
286         ASSERT(!(addr & 0xf));  /* check alignment */
287
288         addr &= 0xff;
289         switch (addr) {
290         case IOAPIC_REG_SELECT:
291                 result = ioapic->ioregsel;
292                 break;
293
294         case IOAPIC_REG_WINDOW:
295                 result = ioapic_read_indirect(ioapic, addr, len);
296                 break;
297
298         default:
299                 result = 0;
300                 break;
301         }
302         switch (len) {
303         case 8:
304                 *(u64 *) val = result;
305                 break;
306         case 1:
307         case 2:
308         case 4:
309                 memcpy(val, (char *)&result, len);
310                 break;
311         default:
312                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
313         }
314 }
315
316 static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
317                               const void *val)
318 {
319         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
320         u32 data;
321
322         ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
323                      (void*)addr, len, val);
324         ASSERT(!(addr & 0xf));  /* check alignment */
325         if (len == 4 || len == 8)
326                 data = *(u32 *) val;
327         else {
328                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
329                 return;
330         }
331
332         addr &= 0xff;
333         switch (addr) {
334         case IOAPIC_REG_SELECT:
335                 ioapic->ioregsel = data;
336                 break;
337
338         case IOAPIC_REG_WINDOW:
339                 ioapic_write_indirect(ioapic, data);
340                 break;
341 #ifdef  CONFIG_IA64
342         case IOAPIC_REG_EOI:
343                 kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
344                 break;
345 #endif
346
347         default:
348                 break;
349         }
350 }
351
352 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
353 {
354         int i;
355
356         for (i = 0; i < IOAPIC_NUM_PINS; i++)
357                 ioapic->redirtbl[i].fields.mask = 1;
358         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
359         ioapic->ioregsel = 0;
360         ioapic->irr = 0;
361         ioapic->id = 0;
362 }
363
364 int kvm_ioapic_init(struct kvm *kvm)
365 {
366         struct kvm_ioapic *ioapic;
367
368         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
369         if (!ioapic)
370                 return -ENOMEM;
371         kvm->arch.vioapic = ioapic;
372         kvm_ioapic_reset(ioapic);
373         ioapic->dev.read = ioapic_mmio_read;
374         ioapic->dev.write = ioapic_mmio_write;
375         ioapic->dev.in_range = ioapic_in_range;
376         ioapic->dev.private = ioapic;
377         ioapic->kvm = kvm;
378         kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
379         return 0;
380 }
381