b71c0442cecf64b17f0d3f2c2034236a27782e7e
[linux-2.6.git] / virt / kvm / ioapic.c
1 /*
2  *  Copyright (C) 2001  MandrakeSoft S.A.
3  *
4  *    MandrakeSoft S.A.
5  *    43, rue d'Aboukir
6  *    75002 Paris - France
7  *    http://www.linux-mandrake.com/
8  *    http://www.mandrakesoft.com/
9  *
10  *  This library is free software; you can redistribute it and/or
11  *  modify it under the terms of the GNU Lesser General Public
12  *  License as published by the Free Software Foundation; either
13  *  version 2 of the License, or (at your option) any later version.
14  *
15  *  This library is distributed in the hope that it will be useful,
16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  *  Lesser General Public License for more details.
19  *
20  *  You should have received a copy of the GNU Lesser General Public
21  *  License along with this library; if not, write to the Free Software
22  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  *
24  *  Yunhong Jiang <yunhong.jiang@intel.com>
25  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
26  *  Based on Xen 3.1 code.
27  */
28
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
31 #include <linux/mm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
35 #include <linux/io.h>
36 #include <asm/processor.h>
37 #include <asm/page.h>
38 #include <asm/current.h>
39
40 #include "ioapic.h"
41 #include "lapic.h"
42 #include "irq.h"
43
44 #if 0
45 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
46 #else
47 #define ioapic_debug(fmt, arg...)
48 #endif
49 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
50
51 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
52                                           unsigned long addr,
53                                           unsigned long length)
54 {
55         unsigned long result = 0;
56
57         switch (ioapic->ioregsel) {
58         case IOAPIC_REG_VERSION:
59                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
60                           | (IOAPIC_VERSION_ID & 0xff));
61                 break;
62
63         case IOAPIC_REG_APIC_ID:
64         case IOAPIC_REG_ARB_ID:
65                 result = ((ioapic->id & 0xf) << 24);
66                 break;
67
68         default:
69                 {
70                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
71                         u64 redir_content;
72
73                         ASSERT(redir_index < IOAPIC_NUM_PINS);
74
75                         redir_content = ioapic->redirtbl[redir_index].bits;
76                         result = (ioapic->ioregsel & 0x1) ?
77                             (redir_content >> 32) & 0xffffffff :
78                             redir_content & 0xffffffff;
79                         break;
80                 }
81         }
82
83         return result;
84 }
85
86 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
87 {
88         union kvm_ioapic_redirect_entry *pent;
89         int injected = -1;
90
91         pent = &ioapic->redirtbl[idx];
92
93         if (!pent->fields.mask) {
94                 injected = ioapic_deliver(ioapic, idx);
95                 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
96                         pent->fields.remote_irr = 1;
97         }
98         if (!pent->fields.trig_mode)
99                 ioapic->irr &= ~(1 << idx);
100
101         return injected;
102 }
103
104 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
105 {
106         unsigned index;
107         bool mask_before, mask_after;
108
109         switch (ioapic->ioregsel) {
110         case IOAPIC_REG_VERSION:
111                 /* Writes are ignored. */
112                 break;
113
114         case IOAPIC_REG_APIC_ID:
115                 ioapic->id = (val >> 24) & 0xf;
116                 break;
117
118         case IOAPIC_REG_ARB_ID:
119                 break;
120
121         default:
122                 index = (ioapic->ioregsel - 0x10) >> 1;
123
124                 ioapic_debug("change redir index %x val %x\n", index, val);
125                 if (index >= IOAPIC_NUM_PINS)
126                         return;
127                 mask_before = ioapic->redirtbl[index].fields.mask;
128                 if (ioapic->ioregsel & 1) {
129                         ioapic->redirtbl[index].bits &= 0xffffffff;
130                         ioapic->redirtbl[index].bits |= (u64) val << 32;
131                 } else {
132                         ioapic->redirtbl[index].bits &= ~0xffffffffULL;
133                         ioapic->redirtbl[index].bits |= (u32) val;
134                         ioapic->redirtbl[index].fields.remote_irr = 0;
135                 }
136                 mask_after = ioapic->redirtbl[index].fields.mask;
137                 if (mask_before != mask_after)
138                         kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
139                 if (ioapic->irr & (1 << index))
140                         ioapic_service(ioapic, index);
141                 break;
142         }
143 }
144
145 int ioapic_deliver_entry(struct kvm *kvm, union kvm_ioapic_redirect_entry *e)
146 {
147         DECLARE_BITMAP(deliver_bitmask, KVM_MAX_VCPUS);
148         int i, r = -1;
149
150         kvm_get_intr_delivery_bitmask(kvm, e, deliver_bitmask);
151
152         if (find_first_bit(deliver_bitmask, KVM_MAX_VCPUS) >= KVM_MAX_VCPUS) {
153                 ioapic_debug("no target on destination\n");
154                 return r;
155         }
156
157         while ((i = find_first_bit(deliver_bitmask, KVM_MAX_VCPUS))
158                         < KVM_MAX_VCPUS) {
159                 struct kvm_vcpu *vcpu = kvm->vcpus[i];
160                 __clear_bit(i, deliver_bitmask);
161                 if (vcpu) {
162                         if (r < 0)
163                                 r = 0;
164                         r += kvm_apic_set_irq(vcpu, e->fields.vector,
165                                         e->fields.delivery_mode,
166                                         e->fields.trig_mode);
167                 } else
168                         ioapic_debug("null destination vcpu: "
169                                      "mask=%x vector=%x delivery_mode=%x\n",
170                                      e->fields.deliver_bitmask,
171                                      e->fields.vector, e->fields.delivery_mode);
172         }
173         return r;
174 }
175
176 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
177 {
178         union kvm_ioapic_redirect_entry entry = ioapic->redirtbl[irq];
179
180         ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
181                      "vector=%x trig_mode=%x\n",
182                      entry.fields.dest, entry.fields.dest_mode,
183                      entry.fields.delivery_mode, entry.fields.vector,
184                      entry.fields.trig_mode);
185
186 #ifdef CONFIG_X86
187         /* Always delivery PIT interrupt to vcpu 0 */
188         if (irq == 0) {
189                 entry.fields.dest_mode = 0; /* Physical mode. */
190                 entry.fields.dest_id = ioapic->kvm->vcpus[0]->vcpu_id;
191         }
192 #endif
193         return ioapic_deliver_entry(ioapic->kvm, &entry);
194 }
195
196 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
197 {
198         u32 old_irr = ioapic->irr;
199         u32 mask = 1 << irq;
200         union kvm_ioapic_redirect_entry entry;
201         int ret = 1;
202
203         if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
204                 entry = ioapic->redirtbl[irq];
205                 level ^= entry.fields.polarity;
206                 if (!level)
207                         ioapic->irr &= ~mask;
208                 else {
209                         ioapic->irr |= mask;
210                         if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
211                             || !entry.fields.remote_irr)
212                                 ret = ioapic_service(ioapic, irq);
213                 }
214         }
215         return ret;
216 }
217
218 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
219                                     int trigger_mode)
220 {
221         union kvm_ioapic_redirect_entry *ent;
222
223         ent = &ioapic->redirtbl[pin];
224
225         kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
226
227         if (trigger_mode == IOAPIC_LEVEL_TRIG) {
228                 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
229                 ent->fields.remote_irr = 0;
230                 if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
231                         ioapic_service(ioapic, pin);
232         }
233 }
234
235 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
236 {
237         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
238         int i;
239
240         for (i = 0; i < IOAPIC_NUM_PINS; i++)
241                 if (ioapic->redirtbl[i].fields.vector == vector)
242                         __kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
243 }
244
245 static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
246                            int len, int is_write)
247 {
248         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
249
250         return ((addr >= ioapic->base_address &&
251                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
252 }
253
254 static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
255                              void *val)
256 {
257         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
258         u32 result;
259
260         ioapic_debug("addr %lx\n", (unsigned long)addr);
261         ASSERT(!(addr & 0xf));  /* check alignment */
262
263         addr &= 0xff;
264         switch (addr) {
265         case IOAPIC_REG_SELECT:
266                 result = ioapic->ioregsel;
267                 break;
268
269         case IOAPIC_REG_WINDOW:
270                 result = ioapic_read_indirect(ioapic, addr, len);
271                 break;
272
273         default:
274                 result = 0;
275                 break;
276         }
277         switch (len) {
278         case 8:
279                 *(u64 *) val = result;
280                 break;
281         case 1:
282         case 2:
283         case 4:
284                 memcpy(val, (char *)&result, len);
285                 break;
286         default:
287                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
288         }
289 }
290
291 static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
292                               const void *val)
293 {
294         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
295         u32 data;
296
297         ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
298                      (void*)addr, len, val);
299         ASSERT(!(addr & 0xf));  /* check alignment */
300         if (len == 4 || len == 8)
301                 data = *(u32 *) val;
302         else {
303                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
304                 return;
305         }
306
307         addr &= 0xff;
308         switch (addr) {
309         case IOAPIC_REG_SELECT:
310                 ioapic->ioregsel = data;
311                 break;
312
313         case IOAPIC_REG_WINDOW:
314                 ioapic_write_indirect(ioapic, data);
315                 break;
316 #ifdef  CONFIG_IA64
317         case IOAPIC_REG_EOI:
318                 kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
319                 break;
320 #endif
321
322         default:
323                 break;
324         }
325 }
326
327 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
328 {
329         int i;
330
331         for (i = 0; i < IOAPIC_NUM_PINS; i++)
332                 ioapic->redirtbl[i].fields.mask = 1;
333         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
334         ioapic->ioregsel = 0;
335         ioapic->irr = 0;
336         ioapic->id = 0;
337 }
338
339 int kvm_ioapic_init(struct kvm *kvm)
340 {
341         struct kvm_ioapic *ioapic;
342
343         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
344         if (!ioapic)
345                 return -ENOMEM;
346         kvm->arch.vioapic = ioapic;
347         kvm_ioapic_reset(ioapic);
348         ioapic->dev.read = ioapic_mmio_read;
349         ioapic->dev.write = ioapic_mmio_write;
350         ioapic->dev.in_range = ioapic_in_range;
351         ioapic->dev.private = ioapic;
352         ioapic->kvm = kvm;
353         kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
354         return 0;
355 }
356