ASoC: OMAP-McBSP: ASoC interface for McBSP sidetone
[linux-2.6.git] / sound / soc / omap / omap-mcbsp.c
1 /*
2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
3  *
4  * Copyright (C) 2008 Nokia Corporation
5  *
6  * Contact: Jarkko Nikula <jhnikula@gmail.com>
7  *          Peter Ujfalusi <peter.ujfalusi@nokia.com>
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * version 2 as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16  * General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21  * 02110-1301 USA
22  *
23  */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/initval.h>
32 #include <sound/soc.h>
33
34 #include <plat/control.h>
35 #include <plat/dma.h>
36 #include <plat/mcbsp.h>
37 #include "omap-mcbsp.h"
38 #include "omap-pcm.h"
39
40 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
41
42 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
43         xhandler_get, xhandler_put) \
44 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
45         .info = omap_mcbsp_st_info_volsw, \
46         .get = xhandler_get, .put = xhandler_put, \
47         .private_value = (unsigned long) &(struct soc_mixer_control) \
48         {.min = xmin, .max = xmax} }
49
50 struct omap_mcbsp_data {
51         unsigned int                    bus_id;
52         struct omap_mcbsp_reg_cfg       regs;
53         unsigned int                    fmt;
54         /*
55          * Flags indicating is the bus already activated and configured by
56          * another substream
57          */
58         int                             active;
59         int                             configured;
60         unsigned int                    in_freq;
61         int                             clk_div;
62 };
63
64 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
65
66 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
67
68 /*
69  * Stream DMA parameters. DMA request line and port address are set runtime
70  * since they are different between OMAP1 and later OMAPs
71  */
72 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
73
74 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
75 static const int omap1_dma_reqs[][2] = {
76         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
77         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
78         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
79 };
80 static const unsigned long omap1_mcbsp_port[][2] = {
81         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
82           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
83         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
84           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
85         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
86           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
87 };
88 #else
89 static const int omap1_dma_reqs[][2] = {};
90 static const unsigned long omap1_mcbsp_port[][2] = {};
91 #endif
92
93 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
94 static const int omap24xx_dma_reqs[][2] = {
95         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
96         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
97 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
98         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
99         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
100         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
101 #endif
102 };
103 #else
104 static const int omap24xx_dma_reqs[][2] = {};
105 #endif
106
107 #if defined(CONFIG_ARCH_OMAP2420)
108 static const unsigned long omap2420_mcbsp_port[][2] = {
109         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
110           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
111         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
112           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
113 };
114 #else
115 static const unsigned long omap2420_mcbsp_port[][2] = {};
116 #endif
117
118 #if defined(CONFIG_ARCH_OMAP2430)
119 static const unsigned long omap2430_mcbsp_port[][2] = {
120         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
121           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
122         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
123           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
124         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
125           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
126         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
127           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
128         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
129           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
130 };
131 #else
132 static const unsigned long omap2430_mcbsp_port[][2] = {};
133 #endif
134
135 #if defined(CONFIG_ARCH_OMAP3)
136 static const unsigned long omap34xx_mcbsp_port[][2] = {
137         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
138           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
139         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
140           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
141         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
142           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
143         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
144           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
145         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
146           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
147 };
148 #else
149 static const unsigned long omap34xx_mcbsp_port[][2] = {};
150 #endif
151
152 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
153 {
154         struct snd_soc_pcm_runtime *rtd = substream->private_data;
155         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
156         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
157         int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
158         int samples;
159
160         /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
161         if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
162                 samples = snd_pcm_lib_period_bytes(substream) >> 1;
163         else
164                 samples = 1;
165
166         /* Configure McBSP internal buffer usage */
167         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
168                 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, samples - 1);
169         else
170                 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, samples - 1);
171 }
172
173 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
174                                   struct snd_soc_dai *dai)
175 {
176         struct snd_soc_pcm_runtime *rtd = substream->private_data;
177         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
178         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
179         int bus_id = mcbsp_data->bus_id;
180         int err = 0;
181
182         if (!cpu_dai->active)
183                 err = omap_mcbsp_request(bus_id);
184
185         if (cpu_is_omap343x()) {
186                 int dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id);
187                 int max_period;
188
189                 /*
190                  * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
191                  * Set constraint for minimum buffer size to the same than FIFO
192                  * size in order to avoid underruns in playback startup because
193                  * HW is keeping the DMA request active until FIFO is filled.
194                  */
195                 if (bus_id == 1)
196                         snd_pcm_hw_constraint_minmax(substream->runtime,
197                                         SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
198                                         4096, UINT_MAX);
199
200                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
201                         max_period = omap_mcbsp_get_max_tx_threshold(bus_id);
202                 else
203                         max_period = omap_mcbsp_get_max_rx_threshold(bus_id);
204
205                 max_period++;
206                 max_period <<= 1;
207
208                 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
209                         snd_pcm_hw_constraint_minmax(substream->runtime,
210                                                 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
211                                                 32, max_period);
212         }
213
214         return err;
215 }
216
217 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
218                                     struct snd_soc_dai *dai)
219 {
220         struct snd_soc_pcm_runtime *rtd = substream->private_data;
221         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
222         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
223
224         if (!cpu_dai->active) {
225                 omap_mcbsp_free(mcbsp_data->bus_id);
226                 mcbsp_data->configured = 0;
227         }
228 }
229
230 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
231                                   struct snd_soc_dai *dai)
232 {
233         struct snd_soc_pcm_runtime *rtd = substream->private_data;
234         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
235         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
236         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
237
238         switch (cmd) {
239         case SNDRV_PCM_TRIGGER_START:
240         case SNDRV_PCM_TRIGGER_RESUME:
241         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
242                 mcbsp_data->active++;
243                 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
244                 break;
245
246         case SNDRV_PCM_TRIGGER_STOP:
247         case SNDRV_PCM_TRIGGER_SUSPEND:
248         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
249                 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
250                 mcbsp_data->active--;
251                 break;
252         default:
253                 err = -EINVAL;
254         }
255
256         return err;
257 }
258
259 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
260                                     struct snd_pcm_hw_params *params,
261                                     struct snd_soc_dai *dai)
262 {
263         struct snd_soc_pcm_runtime *rtd = substream->private_data;
264         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
265         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
266         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
267         int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
268         int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
269         unsigned long port;
270         unsigned int format, div, framesize, master;
271
272         if (cpu_class_is_omap1()) {
273                 dma = omap1_dma_reqs[bus_id][substream->stream];
274                 port = omap1_mcbsp_port[bus_id][substream->stream];
275         } else if (cpu_is_omap2420()) {
276                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
277                 port = omap2420_mcbsp_port[bus_id][substream->stream];
278         } else if (cpu_is_omap2430()) {
279                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
280                 port = omap2430_mcbsp_port[bus_id][substream->stream];
281         } else if (cpu_is_omap343x()) {
282                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
283                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
284                 omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold =
285                                                 omap_mcbsp_set_threshold;
286                 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
287                 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
288                                                 MCBSP_DMA_MODE_THRESHOLD)
289                         sync_mode = OMAP_DMA_SYNC_FRAME;
290         } else {
291                 return -ENODEV;
292         }
293         omap_mcbsp_dai_dma_params[id][substream->stream].name =
294                 substream->stream ? "Audio Capture" : "Audio Playback";
295         omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
296         omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
297         omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
298         cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
299
300         if (mcbsp_data->configured) {
301                 /* McBSP already configured by another stream */
302                 return 0;
303         }
304
305         format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
306         wpf = channels = params_channels(params);
307         if (channels == 2 && format == SND_SOC_DAIFMT_I2S) {
308                 /* Use dual-phase frames */
309                 regs->rcr2      |= RPHASE;
310                 regs->xcr2      |= XPHASE;
311                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
312                 wpf--;
313                 regs->rcr2      |= RFRLEN2(wpf - 1);
314                 regs->xcr2      |= XFRLEN2(wpf - 1);
315         }
316
317         regs->rcr1      |= RFRLEN1(wpf - 1);
318         regs->xcr1      |= XFRLEN1(wpf - 1);
319
320         switch (params_format(params)) {
321         case SNDRV_PCM_FORMAT_S16_LE:
322                 /* Set word lengths */
323                 wlen = 16;
324                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
325                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
326                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
327                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
328                 break;
329         default:
330                 /* Unsupported PCM format */
331                 return -EINVAL;
332         }
333
334         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
335          * by _counting_ BCLKs. Calculate frame size in BCLKs */
336         master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
337         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
338                 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
339                 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
340
341                 if (framesize < wlen * channels) {
342                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
343                                         "channels\n", __func__);
344                         return -EINVAL;
345                 }
346         } else
347                 framesize = wlen * channels;
348
349         /* Set FS period and length in terms of bit clock periods */
350         switch (format) {
351         case SND_SOC_DAIFMT_I2S:
352                 regs->srgr2     |= FPER(framesize - 1);
353                 regs->srgr1     |= FWID((framesize >> 1) - 1);
354                 break;
355         case SND_SOC_DAIFMT_DSP_A:
356         case SND_SOC_DAIFMT_DSP_B:
357                 regs->srgr2     |= FPER(framesize - 1);
358                 regs->srgr1     |= FWID(0);
359                 break;
360         }
361
362         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
363         mcbsp_data->configured = 1;
364
365         return 0;
366 }
367
368 /*
369  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
370  * cache is initialized here
371  */
372 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
373                                       unsigned int fmt)
374 {
375         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
376         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
377         unsigned int temp_fmt = fmt;
378
379         if (mcbsp_data->configured)
380                 return 0;
381
382         mcbsp_data->fmt = fmt;
383         memset(regs, 0, sizeof(*regs));
384         /* Generic McBSP register settings */
385         regs->spcr2     |= XINTM(3) | FREE;
386         regs->spcr1     |= RINTM(3);
387         /* RFIG and XFIG are not defined in 34xx */
388         if (!cpu_is_omap34xx()) {
389                 regs->rcr2      |= RFIG;
390                 regs->xcr2      |= XFIG;
391         }
392         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
393                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
394                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
395         }
396
397         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
398         case SND_SOC_DAIFMT_I2S:
399                 /* 1-bit data delay */
400                 regs->rcr2      |= RDATDLY(1);
401                 regs->xcr2      |= XDATDLY(1);
402                 break;
403         case SND_SOC_DAIFMT_DSP_A:
404                 /* 1-bit data delay */
405                 regs->rcr2      |= RDATDLY(1);
406                 regs->xcr2      |= XDATDLY(1);
407                 /* Invert FS polarity configuration */
408                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
409                 break;
410         case SND_SOC_DAIFMT_DSP_B:
411                 /* 0-bit data delay */
412                 regs->rcr2      |= RDATDLY(0);
413                 regs->xcr2      |= XDATDLY(0);
414                 /* Invert FS polarity configuration */
415                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
416                 break;
417         default:
418                 /* Unsupported data format */
419                 return -EINVAL;
420         }
421
422         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
423         case SND_SOC_DAIFMT_CBS_CFS:
424                 /* McBSP master. Set FS and bit clocks as outputs */
425                 regs->pcr0      |= FSXM | FSRM |
426                                    CLKXM | CLKRM;
427                 /* Sample rate generator drives the FS */
428                 regs->srgr2     |= FSGM;
429                 break;
430         case SND_SOC_DAIFMT_CBM_CFM:
431                 /* McBSP slave */
432                 break;
433         default:
434                 /* Unsupported master/slave configuration */
435                 return -EINVAL;
436         }
437
438         /* Set bit clock (CLKX/CLKR) and FS polarities */
439         switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
440         case SND_SOC_DAIFMT_NB_NF:
441                 /*
442                  * Normal BCLK + FS.
443                  * FS active low. TX data driven on falling edge of bit clock
444                  * and RX data sampled on rising edge of bit clock.
445                  */
446                 regs->pcr0      |= FSXP | FSRP |
447                                    CLKXP | CLKRP;
448                 break;
449         case SND_SOC_DAIFMT_NB_IF:
450                 regs->pcr0      |= CLKXP | CLKRP;
451                 break;
452         case SND_SOC_DAIFMT_IB_NF:
453                 regs->pcr0      |= FSXP | FSRP;
454                 break;
455         case SND_SOC_DAIFMT_IB_IF:
456                 break;
457         default:
458                 return -EINVAL;
459         }
460
461         return 0;
462 }
463
464 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
465                                      int div_id, int div)
466 {
467         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
468         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
469
470         if (div_id != OMAP_MCBSP_CLKGDV)
471                 return -ENODEV;
472
473         mcbsp_data->clk_div = div;
474         regs->srgr1     |= CLKGDV(div - 1);
475
476         return 0;
477 }
478
479 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
480                                        int clk_id)
481 {
482         int sel_bit;
483         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
484
485         if (cpu_class_is_omap1()) {
486                 /* OMAP1's can use only external source clock */
487                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
488                         return -EINVAL;
489                 else
490                         return 0;
491         }
492
493         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
494                 return -EINVAL;
495
496         if (cpu_is_omap343x())
497                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
498
499         switch (mcbsp_data->bus_id) {
500         case 0:
501                 reg = OMAP2_CONTROL_DEVCONF0;
502                 sel_bit = 2;
503                 break;
504         case 1:
505                 reg = OMAP2_CONTROL_DEVCONF0;
506                 sel_bit = 6;
507                 break;
508         case 2:
509                 reg = reg_devconf1;
510                 sel_bit = 0;
511                 break;
512         case 3:
513                 reg = reg_devconf1;
514                 sel_bit = 2;
515                 break;
516         case 4:
517                 reg = reg_devconf1;
518                 sel_bit = 4;
519                 break;
520         default:
521                 return -EINVAL;
522         }
523
524         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
525                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
526         else
527                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
528
529         return 0;
530 }
531
532 static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,
533                                        int clk_id)
534 {
535         int sel_bit, set = 0;
536         u16 reg = OMAP2_CONTROL_DEVCONF0;
537
538         if (cpu_class_is_omap1())
539                 return -EINVAL; /* TODO: Can this be implemented for OMAP1? */
540         if (mcbsp_data->bus_id != 0)
541                 return -EINVAL;
542
543         switch (clk_id) {
544         case OMAP_MCBSP_CLKR_SRC_CLKX:
545                 set = 1;
546         case OMAP_MCBSP_CLKR_SRC_CLKR:
547                 sel_bit = 3;
548                 break;
549         case OMAP_MCBSP_FSR_SRC_FSX:
550                 set = 1;
551         case OMAP_MCBSP_FSR_SRC_FSR:
552                 sel_bit = 4;
553                 break;
554         default:
555                 return -EINVAL;
556         }
557
558         if (set)
559                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
560         else
561                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
562
563         return 0;
564 }
565
566 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
567                                          int clk_id, unsigned int freq,
568                                          int dir)
569 {
570         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
571         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
572         int err = 0;
573
574         mcbsp_data->in_freq = freq;
575
576         switch (clk_id) {
577         case OMAP_MCBSP_SYSCLK_CLK:
578                 regs->srgr2     |= CLKSM;
579                 break;
580         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
581         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
582                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
583                 break;
584
585         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
586                 regs->srgr2     |= CLKSM;
587         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
588                 regs->pcr0      |= SCLKME;
589                 break;
590
591         case OMAP_MCBSP_CLKR_SRC_CLKR:
592         case OMAP_MCBSP_CLKR_SRC_CLKX:
593         case OMAP_MCBSP_FSR_SRC_FSR:
594         case OMAP_MCBSP_FSR_SRC_FSX:
595                 err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id);
596                 break;
597         default:
598                 err = -ENODEV;
599         }
600
601         return err;
602 }
603
604 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
605         .startup        = omap_mcbsp_dai_startup,
606         .shutdown       = omap_mcbsp_dai_shutdown,
607         .trigger        = omap_mcbsp_dai_trigger,
608         .hw_params      = omap_mcbsp_dai_hw_params,
609         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
610         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
611         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
612 };
613
614 #define OMAP_MCBSP_DAI_BUILDER(link_id)                         \
615 {                                                               \
616         .name = "omap-mcbsp-dai-"#link_id,                      \
617         .id = (link_id),                                        \
618         .playback = {                                           \
619                 .channels_min = 1,                              \
620                 .channels_max = 16,                             \
621                 .rates = OMAP_MCBSP_RATES,                      \
622                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
623         },                                                      \
624         .capture = {                                            \
625                 .channels_min = 1,                              \
626                 .channels_max = 16,                             \
627                 .rates = OMAP_MCBSP_RATES,                      \
628                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
629         },                                                      \
630         .ops = &omap_mcbsp_dai_ops,                             \
631         .private_data = &mcbsp_data[(link_id)].bus_id,          \
632 }
633
634 struct snd_soc_dai omap_mcbsp_dai[] = {
635         OMAP_MCBSP_DAI_BUILDER(0),
636         OMAP_MCBSP_DAI_BUILDER(1),
637 #if NUM_LINKS >= 3
638         OMAP_MCBSP_DAI_BUILDER(2),
639 #endif
640 #if NUM_LINKS == 5
641         OMAP_MCBSP_DAI_BUILDER(3),
642         OMAP_MCBSP_DAI_BUILDER(4),
643 #endif
644 };
645
646 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
647
648 int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
649                         struct snd_ctl_elem_info *uinfo)
650 {
651         struct soc_mixer_control *mc =
652                 (struct soc_mixer_control *)kcontrol->private_value;
653         int max = mc->max;
654         int min = mc->min;
655
656         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
657         uinfo->count = 1;
658         uinfo->value.integer.min = min;
659         uinfo->value.integer.max = max;
660         return 0;
661 }
662
663 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel)                   \
664 static int                                                              \
665 omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc,   \
666                                         struct snd_ctl_elem_value *uc)  \
667 {                                                                       \
668         struct soc_mixer_control *mc =                                  \
669                 (struct soc_mixer_control *)kc->private_value;          \
670         int max = mc->max;                                              \
671         int min = mc->min;                                              \
672         int val = uc->value.integer.value[0];                           \
673                                                                         \
674         if (val < min || val > max)                                     \
675                 return -EINVAL;                                         \
676                                                                         \
677         /* OMAP McBSP implementation uses index values 0..4 */          \
678         return omap_st_set_chgain((id)-1, channel, val);                \
679 }
680
681 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel)                   \
682 static int                                                              \
683 omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc,   \
684                                         struct snd_ctl_elem_value *uc)  \
685 {                                                                       \
686         s16 chgain;                                                     \
687                                                                         \
688         if (omap_st_get_chgain((id)-1, channel, &chgain))               \
689                 return -EAGAIN;                                         \
690                                                                         \
691         uc->value.integer.value[0] = chgain;                            \
692         return 0;                                                       \
693 }
694
695 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
696 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
697 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
698 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
699 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
700 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
701 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
702 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
703
704 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
705                                 struct snd_ctl_elem_value *ucontrol)
706 {
707         struct soc_mixer_control *mc =
708                 (struct soc_mixer_control *)kcontrol->private_value;
709         u8 value = ucontrol->value.integer.value[0];
710
711         if (value == omap_st_is_enabled(mc->reg))
712                 return 0;
713
714         if (value)
715                 omap_st_enable(mc->reg);
716         else
717                 omap_st_disable(mc->reg);
718
719         return 1;
720 }
721
722 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
723                                 struct snd_ctl_elem_value *ucontrol)
724 {
725         struct soc_mixer_control *mc =
726                 (struct soc_mixer_control *)kcontrol->private_value;
727
728         ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
729         return 0;
730 }
731
732 static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
733         SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
734                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
735         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
736                                       -32768, 32767,
737                                       omap_mcbsp2_get_st_ch0_volume,
738                                       omap_mcbsp2_set_st_ch0_volume),
739         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
740                                       -32768, 32767,
741                                       omap_mcbsp2_get_st_ch1_volume,
742                                       omap_mcbsp2_set_st_ch1_volume),
743 };
744
745 static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
746         SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
747                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
748         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
749                                       -32768, 32767,
750                                       omap_mcbsp3_get_st_ch0_volume,
751                                       omap_mcbsp3_set_st_ch0_volume),
752         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
753                                       -32768, 32767,
754                                       omap_mcbsp3_get_st_ch1_volume,
755                                       omap_mcbsp3_set_st_ch1_volume),
756 };
757
758 int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
759 {
760         if (!cpu_is_omap34xx())
761                 return -ENODEV;
762
763         switch (mcbsp_id) {
764         case 1: /* McBSP 2 */
765                 return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
766                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
767         case 2: /* McBSP 3 */
768                 return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
769                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
770         default:
771                 break;
772         }
773
774         return -EINVAL;
775 }
776 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
777
778 static int __init snd_omap_mcbsp_init(void)
779 {
780         return snd_soc_register_dais(omap_mcbsp_dai,
781                                      ARRAY_SIZE(omap_mcbsp_dai));
782 }
783 module_init(snd_omap_mcbsp_init);
784
785 static void __exit snd_omap_mcbsp_exit(void)
786 {
787         snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
788 }
789 module_exit(snd_omap_mcbsp_exit);
790
791 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
792 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
793 MODULE_LICENSE("GPL");