e845c4b9066e94be1f664e2574d9bad1744d358e
[linux-2.6.git] / sound / soc / codecs / tlv320dac33.c
1 /*
2  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3  *
4  * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
5  *
6  * Copyright:   (C) 2009 Nokia Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  */
23
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/pm.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/soc.h>
38 #include <sound/soc-dapm.h>
39 #include <sound/initval.h>
40 #include <sound/tlv.h>
41
42 #include <sound/tlv320dac33-plat.h>
43 #include "tlv320dac33.h"
44
45 #define DAC33_BUFFER_SIZE_BYTES         24576   /* bytes, 12288 16 bit words,
46                                                  * 6144 stereo */
47 #define DAC33_BUFFER_SIZE_SAMPLES       6144
48
49 #define NSAMPLE_MAX             5700
50
51 #define LATENCY_TIME_MS         20
52
53 static struct snd_soc_codec *tlv320dac33_codec;
54
55 enum dac33_state {
56         DAC33_IDLE = 0,
57         DAC33_PREFILL,
58         DAC33_PLAYBACK,
59         DAC33_FLUSH,
60 };
61
62 enum dac33_fifo_modes {
63         DAC33_FIFO_BYPASS = 0,
64         DAC33_FIFO_MODE1,
65         DAC33_FIFO_MODE7,
66         DAC33_FIFO_LAST_MODE,
67 };
68
69 #define DAC33_NUM_SUPPLIES 3
70 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
71         "AVDD",
72         "DVDD",
73         "IOVDD",
74 };
75
76 struct tlv320dac33_priv {
77         struct mutex mutex;
78         struct workqueue_struct *dac33_wq;
79         struct work_struct work;
80         struct snd_soc_codec codec;
81         struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
82         int power_gpio;
83         int chip_power;
84         int irq;
85         unsigned int refclk;
86
87         unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
88         unsigned int nsample_min;       /* nsample should not be lower than
89                                          * this */
90         unsigned int nsample_max;       /* nsample should not be higher than
91                                          * this */
92         enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
93         unsigned int nsample;           /* burst read amount from host */
94         u8 burst_bclkdiv;               /* BCLK divider value in burst mode */
95
96         enum dac33_state state;
97 };
98
99 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
100 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
101 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
102 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
103 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
104 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
105 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
106 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
107 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
108 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
109 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
110 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
111 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
112 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
113 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
114 0x00, 0x00,             /* 0x38 - 0x39 */
115 /* Registers 0x3a - 0x3f are reserved  */
116             0x00, 0x00, /* 0x3a - 0x3b */
117 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
118
119 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
120 0x00, 0x80,             /* 0x44 - 0x45 */
121 /* Registers 0x46 - 0x47 are reserved  */
122             0x80, 0x80, /* 0x46 - 0x47 */
123
124 0x80, 0x00, 0x00,       /* 0x48 - 0x4a */
125 /* Registers 0x4b - 0x7c are reserved  */
126                   0x00, /* 0x4b        */
127 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
128 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
129 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
130 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
131 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
132 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
133 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
134 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
135 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
136 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
137 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
138 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
139 0x00,                   /* 0x7c        */
140
141       0xda, 0x33, 0x03, /* 0x7d - 0x7f */
142 };
143
144 /* Register read and write */
145 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
146                                                 unsigned reg)
147 {
148         u8 *cache = codec->reg_cache;
149         if (reg >= DAC33_CACHEREGNUM)
150                 return 0;
151
152         return cache[reg];
153 }
154
155 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
156                                          u8 reg, u8 value)
157 {
158         u8 *cache = codec->reg_cache;
159         if (reg >= DAC33_CACHEREGNUM)
160                 return;
161
162         cache[reg] = value;
163 }
164
165 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
166                       u8 *value)
167 {
168         struct tlv320dac33_priv *dac33 = codec->private_data;
169         int val;
170
171         *value = reg & 0xff;
172
173         /* If powered off, return the cached value */
174         if (dac33->chip_power) {
175                 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
176                 if (val < 0) {
177                         dev_err(codec->dev, "Read failed (%d)\n", val);
178                         value[0] = dac33_read_reg_cache(codec, reg);
179                 } else {
180                         value[0] = val;
181                         dac33_write_reg_cache(codec, reg, val);
182                 }
183         } else {
184                 value[0] = dac33_read_reg_cache(codec, reg);
185         }
186
187         return 0;
188 }
189
190 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
191                        unsigned int value)
192 {
193         struct tlv320dac33_priv *dac33 = codec->private_data;
194         u8 data[2];
195         int ret = 0;
196
197         /*
198          * data is
199          *   D15..D8 dac33 register offset
200          *   D7...D0 register data
201          */
202         data[0] = reg & 0xff;
203         data[1] = value & 0xff;
204
205         dac33_write_reg_cache(codec, data[0], data[1]);
206         if (dac33->chip_power) {
207                 ret = codec->hw_write(codec->control_data, data, 2);
208                 if (ret != 2)
209                         dev_err(codec->dev, "Write failed (%d)\n", ret);
210                 else
211                         ret = 0;
212         }
213
214         return ret;
215 }
216
217 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
218                        unsigned int value)
219 {
220         struct tlv320dac33_priv *dac33 = codec->private_data;
221         int ret;
222
223         mutex_lock(&dac33->mutex);
224         ret = dac33_write(codec, reg, value);
225         mutex_unlock(&dac33->mutex);
226
227         return ret;
228 }
229
230 #define DAC33_I2C_ADDR_AUTOINC  0x80
231 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
232                        unsigned int value)
233 {
234         struct tlv320dac33_priv *dac33 = codec->private_data;
235         u8 data[3];
236         int ret = 0;
237
238         /*
239          * data is
240          *   D23..D16 dac33 register offset
241          *   D15..D8  register data MSB
242          *   D7...D0  register data LSB
243          */
244         data[0] = reg & 0xff;
245         data[1] = (value >> 8) & 0xff;
246         data[2] = value & 0xff;
247
248         dac33_write_reg_cache(codec, data[0], data[1]);
249         dac33_write_reg_cache(codec, data[0] + 1, data[2]);
250
251         if (dac33->chip_power) {
252                 /* We need to set autoincrement mode for 16 bit writes */
253                 data[0] |= DAC33_I2C_ADDR_AUTOINC;
254                 ret = codec->hw_write(codec->control_data, data, 3);
255                 if (ret != 3)
256                         dev_err(codec->dev, "Write failed (%d)\n", ret);
257                 else
258                         ret = 0;
259         }
260
261         return ret;
262 }
263
264 static void dac33_restore_regs(struct snd_soc_codec *codec)
265 {
266         struct tlv320dac33_priv *dac33 = codec->private_data;
267         u8 *cache = codec->reg_cache;
268         u8 data[2];
269         int i, ret;
270
271         if (!dac33->chip_power)
272                 return;
273
274         for (i = DAC33_PWR_CTRL; i <= DAC33_INTP_CTRL_B; i++) {
275                 data[0] = i;
276                 data[1] = cache[i];
277                 /* Skip the read only registers */
278                 if ((i >= DAC33_INT_OSC_STATUS &&
279                                 i <= DAC33_INT_OSC_FREQ_RAT_READ_B) ||
280                     (i >= DAC33_FIFO_WPTR_MSB && i <= DAC33_FIFO_IRQ_FLAG) ||
281                     i == DAC33_DAC_STATUS_FLAGS ||
282                     i == DAC33_SRC_EST_REF_CLK_RATIO_A ||
283                     i == DAC33_SRC_EST_REF_CLK_RATIO_B)
284                         continue;
285                 ret = codec->hw_write(codec->control_data, data, 2);
286                 if (ret != 2)
287                         dev_err(codec->dev, "Write failed (%d)\n", ret);
288         }
289         for (i = DAC33_LDAC_PWR_CTRL; i <= DAC33_LINEL_TO_LLO_VOL; i++) {
290                 data[0] = i;
291                 data[1] = cache[i];
292                 ret = codec->hw_write(codec->control_data, data, 2);
293                 if (ret != 2)
294                         dev_err(codec->dev, "Write failed (%d)\n", ret);
295         }
296         for (i = DAC33_LINER_TO_RLO_VOL; i <= DAC33_OSC_TRIM; i++) {
297                 data[0] = i;
298                 data[1] = cache[i];
299                 ret = codec->hw_write(codec->control_data, data, 2);
300                 if (ret != 2)
301                         dev_err(codec->dev, "Write failed (%d)\n", ret);
302         }
303 }
304
305 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
306 {
307         u8 reg;
308
309         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
310         if (power)
311                 reg |= DAC33_PDNALLB;
312         else
313                 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
314                          DAC33_DACRPDNB | DAC33_DACLPDNB);
315         dac33_write(codec, DAC33_PWR_CTRL, reg);
316 }
317
318 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
319 {
320         struct tlv320dac33_priv *dac33 = codec->private_data;
321         int ret;
322
323         mutex_lock(&dac33->mutex);
324         if (power) {
325                 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
326                                           dac33->supplies);
327                 if (ret != 0) {
328                         dev_err(codec->dev,
329                                 "Failed to enable supplies: %d\n", ret);
330                                 goto exit;
331                 }
332
333                 if (dac33->power_gpio >= 0)
334                         gpio_set_value(dac33->power_gpio, 1);
335
336                 dac33->chip_power = 1;
337
338                 /* Restore registers */
339                 dac33_restore_regs(codec);
340
341                 dac33_soft_power(codec, 1);
342         } else {
343                 dac33_soft_power(codec, 0);
344                 if (dac33->power_gpio >= 0)
345                         gpio_set_value(dac33->power_gpio, 0);
346
347                 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
348                                              dac33->supplies);
349                 if (ret != 0) {
350                         dev_err(codec->dev,
351                                 "Failed to disable supplies: %d\n", ret);
352                         goto exit;
353                 }
354
355                 dac33->chip_power = 0;
356         }
357
358 exit:
359         mutex_unlock(&dac33->mutex);
360         return ret;
361 }
362
363 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
364                          struct snd_ctl_elem_value *ucontrol)
365 {
366         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
367         struct tlv320dac33_priv *dac33 = codec->private_data;
368
369         ucontrol->value.integer.value[0] = dac33->nsample;
370
371         return 0;
372 }
373
374 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
375                          struct snd_ctl_elem_value *ucontrol)
376 {
377         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
378         struct tlv320dac33_priv *dac33 = codec->private_data;
379         int ret = 0;
380
381         if (dac33->nsample == ucontrol->value.integer.value[0])
382                 return 0;
383
384         if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
385             ucontrol->value.integer.value[0] > dac33->nsample_max)
386                 ret = -EINVAL;
387         else
388                 dac33->nsample = ucontrol->value.integer.value[0];
389
390         return ret;
391 }
392
393 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
394                          struct snd_ctl_elem_value *ucontrol)
395 {
396         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
397         struct tlv320dac33_priv *dac33 = codec->private_data;
398
399         ucontrol->value.integer.value[0] = dac33->fifo_mode;
400
401         return 0;
402 }
403
404 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
405                          struct snd_ctl_elem_value *ucontrol)
406 {
407         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
408         struct tlv320dac33_priv *dac33 = codec->private_data;
409         int ret = 0;
410
411         if (dac33->fifo_mode == ucontrol->value.integer.value[0])
412                 return 0;
413         /* Do not allow changes while stream is running*/
414         if (codec->active)
415                 return -EPERM;
416
417         if (ucontrol->value.integer.value[0] < 0 ||
418             ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
419                 ret = -EINVAL;
420         else
421                 dac33->fifo_mode = ucontrol->value.integer.value[0];
422
423         return ret;
424 }
425
426 /* Codec operation modes */
427 static const char *dac33_fifo_mode_texts[] = {
428         "Bypass", "Mode 1", "Mode 7"
429 };
430
431 static const struct soc_enum dac33_fifo_mode_enum =
432         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
433                             dac33_fifo_mode_texts);
434
435 /*
436  * DACL/R digital volume control:
437  * from 0 dB to -63.5 in 0.5 dB steps
438  * Need to be inverted later on:
439  * 0x00 == 0 dB
440  * 0x7f == -63.5 dB
441  */
442 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
443
444 static const struct snd_kcontrol_new dac33_snd_controls[] = {
445         SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
446                 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
447                 0, 0x7f, 1, dac_digivol_tlv),
448         SOC_DOUBLE_R("DAC Digital Playback Switch",
449                  DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
450         SOC_DOUBLE_R("Line to Line Out Volume",
451                  DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
452 };
453
454 static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
455         SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
456                  dac33_get_nsample, dac33_set_nsample),
457         SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
458                  dac33_get_fifo_mode, dac33_set_fifo_mode),
459 };
460
461 /* Analog bypass */
462 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
463         SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
464
465 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
466         SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
467
468 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
469         SND_SOC_DAPM_OUTPUT("LEFT_LO"),
470         SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
471
472         SND_SOC_DAPM_INPUT("LINEL"),
473         SND_SOC_DAPM_INPUT("LINER"),
474
475         SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
476         SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
477
478         /* Analog bypass */
479         SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
480                                 &dac33_dapm_abypassl_control),
481         SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
482                                 &dac33_dapm_abypassr_control),
483
484         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
485                          DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
486         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
487                          DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
488 };
489
490 static const struct snd_soc_dapm_route audio_map[] = {
491         /* Analog bypass */
492         {"Analog Left Bypass", "Switch", "LINEL"},
493         {"Analog Right Bypass", "Switch", "LINER"},
494
495         {"Output Left Amp Power", NULL, "DACL"},
496         {"Output Right Amp Power", NULL, "DACR"},
497
498         {"Output Left Amp Power", NULL, "Analog Left Bypass"},
499         {"Output Right Amp Power", NULL, "Analog Right Bypass"},
500
501         /* output */
502         {"LEFT_LO", NULL, "Output Left Amp Power"},
503         {"RIGHT_LO", NULL, "Output Right Amp Power"},
504 };
505
506 static int dac33_add_widgets(struct snd_soc_codec *codec)
507 {
508         snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
509                                   ARRAY_SIZE(dac33_dapm_widgets));
510
511         /* set up audio path interconnects */
512         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
513
514         return 0;
515 }
516
517 static int dac33_set_bias_level(struct snd_soc_codec *codec,
518                                 enum snd_soc_bias_level level)
519 {
520         int ret;
521
522         switch (level) {
523         case SND_SOC_BIAS_ON:
524                 dac33_soft_power(codec, 1);
525                 break;
526         case SND_SOC_BIAS_PREPARE:
527                 break;
528         case SND_SOC_BIAS_STANDBY:
529                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
530                         ret = dac33_hard_power(codec, 1);
531                         if (ret != 0)
532                                 return ret;
533                 }
534
535                 dac33_soft_power(codec, 0);
536                 break;
537         case SND_SOC_BIAS_OFF:
538                 ret = dac33_hard_power(codec, 0);
539                 if (ret != 0)
540                         return ret;
541
542                 break;
543         }
544         codec->bias_level = level;
545
546         return 0;
547 }
548
549 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
550 {
551         struct snd_soc_codec *codec;
552
553         codec = &dac33->codec;
554
555         switch (dac33->fifo_mode) {
556         case DAC33_FIFO_MODE1:
557                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
558                                 DAC33_THRREG(dac33->nsample));
559                 dac33_write16(codec, DAC33_PREFILL_MSB,
560                                 DAC33_THRREG(dac33->alarm_threshold));
561                 break;
562         case DAC33_FIFO_MODE7:
563                 dac33_write16(codec, DAC33_PREFILL_MSB,
564                                 DAC33_THRREG(10));
565                 break;
566         default:
567                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
568                                                         dac33->fifo_mode);
569                 break;
570         }
571 }
572
573 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
574 {
575         struct snd_soc_codec *codec;
576
577         codec = &dac33->codec;
578
579         switch (dac33->fifo_mode) {
580         case DAC33_FIFO_MODE1:
581                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
582                                 DAC33_THRREG(dac33->nsample));
583                 break;
584         case DAC33_FIFO_MODE7:
585                 /* At the moment we are not using interrupts in mode7 */
586                 break;
587         default:
588                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
589                                                         dac33->fifo_mode);
590                 break;
591         }
592 }
593
594 static void dac33_work(struct work_struct *work)
595 {
596         struct snd_soc_codec *codec;
597         struct tlv320dac33_priv *dac33;
598         u8 reg;
599
600         dac33 = container_of(work, struct tlv320dac33_priv, work);
601         codec = &dac33->codec;
602
603         mutex_lock(&dac33->mutex);
604         switch (dac33->state) {
605         case DAC33_PREFILL:
606                 dac33->state = DAC33_PLAYBACK;
607                 dac33_prefill_handler(dac33);
608                 break;
609         case DAC33_PLAYBACK:
610                 dac33_playback_handler(dac33);
611                 break;
612         case DAC33_IDLE:
613                 break;
614         case DAC33_FLUSH:
615                 dac33->state = DAC33_IDLE;
616                 /* Mask all interrupts from dac33 */
617                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
618
619                 /* flush fifo */
620                 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
621                 reg |= DAC33_FIFOFLUSH;
622                 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
623                 break;
624         }
625         mutex_unlock(&dac33->mutex);
626 }
627
628 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
629 {
630         struct snd_soc_codec *codec = dev;
631         struct tlv320dac33_priv *dac33 = codec->private_data;
632
633         queue_work(dac33->dac33_wq, &dac33->work);
634
635         return IRQ_HANDLED;
636 }
637
638 static void dac33_oscwait(struct snd_soc_codec *codec)
639 {
640         int timeout = 20;
641         u8 reg;
642
643         do {
644                 msleep(1);
645                 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
646         } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
647         if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
648                 dev_err(codec->dev,
649                         "internal oscillator calibration failed\n");
650 }
651
652 static int dac33_hw_params(struct snd_pcm_substream *substream,
653                            struct snd_pcm_hw_params *params,
654                            struct snd_soc_dai *dai)
655 {
656         struct snd_soc_pcm_runtime *rtd = substream->private_data;
657         struct snd_soc_device *socdev = rtd->socdev;
658         struct snd_soc_codec *codec = socdev->card->codec;
659
660         /* Check parameters for validity */
661         switch (params_rate(params)) {
662         case 44100:
663         case 48000:
664                 break;
665         default:
666                 dev_err(codec->dev, "unsupported rate %d\n",
667                         params_rate(params));
668                 return -EINVAL;
669         }
670
671         switch (params_format(params)) {
672         case SNDRV_PCM_FORMAT_S16_LE:
673                 break;
674         default:
675                 dev_err(codec->dev, "unsupported format %d\n",
676                         params_format(params));
677                 return -EINVAL;
678         }
679
680         return 0;
681 }
682
683 #define CALC_OSCSET(rate, refclk) ( \
684         ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
685 #define CALC_RATIOSET(rate, refclk) ( \
686         ((((refclk  * 100000) / rate) * 16384) + 50000) / 100000)
687
688 /*
689  * tlv320dac33 is strict on the sequence of the register writes, if the register
690  * writes happens in different order, than dac33 might end up in unknown state.
691  * Use the known, working sequence of register writes to initialize the dac33.
692  */
693 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
694 {
695         struct snd_soc_pcm_runtime *rtd = substream->private_data;
696         struct snd_soc_device *socdev = rtd->socdev;
697         struct snd_soc_codec *codec = socdev->card->codec;
698         struct tlv320dac33_priv *dac33 = codec->private_data;
699         unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
700         u8 aictrl_a, aictrl_b, fifoctrl_a;
701
702         switch (substream->runtime->rate) {
703         case 44100:
704         case 48000:
705                 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
706                 ratioset = CALC_RATIOSET(substream->runtime->rate,
707                                          dac33->refclk);
708                 break;
709         default:
710                 dev_err(codec->dev, "unsupported rate %d\n",
711                         substream->runtime->rate);
712                 return -EINVAL;
713         }
714
715
716         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
717         aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
718         /* Read FIFO control A, and clear FIFO flush bit */
719         fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
720         fifoctrl_a &= ~DAC33_FIFOFLUSH;
721
722         fifoctrl_a &= ~DAC33_WIDTH;
723         switch (substream->runtime->format) {
724         case SNDRV_PCM_FORMAT_S16_LE:
725                 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
726                 fifoctrl_a |= DAC33_WIDTH;
727                 break;
728         default:
729                 dev_err(codec->dev, "unsupported format %d\n",
730                         substream->runtime->format);
731                 return -EINVAL;
732         }
733
734         mutex_lock(&dac33->mutex);
735         dac33_soft_power(codec, 0);
736         dac33_soft_power(codec, 1);
737
738         reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
739         dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
740
741         /* Write registers 0x08 and 0x09 (MSB, LSB) */
742         dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
743
744         /* calib time: 128 is a nice number ;) */
745         dac33_write(codec, DAC33_CALIB_TIME, 128);
746
747         /* adjustment treshold & step */
748         dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
749                                                  DAC33_ADJSTEP(1));
750
751         /* div=4 / gain=1 / div */
752         dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
753
754         pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
755         pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
756         dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
757
758         dac33_oscwait(codec);
759
760         if (dac33->fifo_mode) {
761                 /* Generic for all FIFO modes */
762                 /* 50-51 : ASRC Control registers */
763                 dac33_write(codec, DAC33_ASRC_CTRL_A, (1 << 4)); /* div=2 */
764                 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
765
766                 /* Write registers 0x34 and 0x35 (MSB, LSB) */
767                 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
768
769                 /* Set interrupts to high active */
770                 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
771         } else {
772                 /* FIFO bypass mode */
773                 /* 50-51 : ASRC Control registers */
774                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
775                 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
776         }
777
778         /* Interrupt behaviour configuration */
779         switch (dac33->fifo_mode) {
780         case DAC33_FIFO_MODE1:
781                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
782                             DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
783                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
784                 break;
785         case DAC33_FIFO_MODE7:
786                 /* Disable all interrupts */
787                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
788                 break;
789         default:
790                 /* in FIFO bypass mode, the interrupts are not used */
791                 break;
792         }
793
794         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
795
796         switch (dac33->fifo_mode) {
797         case DAC33_FIFO_MODE1:
798                 /*
799                  * For mode1:
800                  * Disable the FIFO bypass (Enable the use of FIFO)
801                  * Select nSample mode
802                  * BCLK is only running when data is needed by DAC33
803                  */
804                 fifoctrl_a &= ~DAC33_FBYPAS;
805                 fifoctrl_a &= ~DAC33_FAUTO;
806                 aictrl_b &= ~DAC33_BCLKON;
807                 break;
808         case DAC33_FIFO_MODE7:
809                 /*
810                  * For mode1:
811                  * Disable the FIFO bypass (Enable the use of FIFO)
812                  * Select Threshold mode
813                  * BCLK is only running when data is needed by DAC33
814                  */
815                 fifoctrl_a &= ~DAC33_FBYPAS;
816                 fifoctrl_a |= DAC33_FAUTO;
817                 aictrl_b &= ~DAC33_BCLKON;
818                 break;
819         default:
820                 /*
821                  * For FIFO bypass mode:
822                  * Enable the FIFO bypass (Disable the FIFO use)
823                  * Set the BCLK as continous
824                  */
825                 fifoctrl_a |= DAC33_FBYPAS;
826                 aictrl_b |= DAC33_BCLKON;
827                 break;
828         }
829
830         dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
831         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
832         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
833
834         /*
835          * BCLK divide ratio
836          * 0: 1.5
837          * 1: 1
838          * 2: 2
839          * ...
840          * 254: 254
841          * 255: 255
842          */
843         if (dac33->fifo_mode)
844                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
845                                                         dac33->burst_bclkdiv);
846         else
847                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
848
849         switch (dac33->fifo_mode) {
850         case DAC33_FIFO_MODE1:
851                 dac33_write16(codec, DAC33_ATHR_MSB,
852                               DAC33_THRREG(dac33->alarm_threshold));
853                 break;
854         case DAC33_FIFO_MODE7:
855                 /*
856                  * Configure the threshold levels, and leave 10 sample space
857                  * at the bottom, and also at the top of the FIFO
858                  */
859                 dac33_write16(codec, DAC33_UTHR_MSB,
860                         DAC33_THRREG(DAC33_BUFFER_SIZE_SAMPLES - 10));
861                 dac33_write16(codec, DAC33_LTHR_MSB,
862                         DAC33_THRREG(10));
863                 break;
864         default:
865                 break;
866         }
867
868         mutex_unlock(&dac33->mutex);
869
870         return 0;
871 }
872
873 static void dac33_calculate_times(struct snd_pcm_substream *substream)
874 {
875         struct snd_soc_pcm_runtime *rtd = substream->private_data;
876         struct snd_soc_device *socdev = rtd->socdev;
877         struct snd_soc_codec *codec = socdev->card->codec;
878         struct tlv320dac33_priv *dac33 = codec->private_data;
879         unsigned int nsample_limit;
880
881         /* Number of samples (16bit, stereo) in one period */
882         dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
883
884         /* Number of samples (16bit, stereo) in ALSA buffer */
885         dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
886         /* Subtract one period from the total */
887         dac33->nsample_max -= dac33->nsample_min;
888
889         /* Number of samples for LATENCY_TIME_MS / 2 */
890         dac33->alarm_threshold = substream->runtime->rate /
891                                  (1000 / (LATENCY_TIME_MS / 2));
892
893         /* Find and fix up the lowest nsmaple limit */
894         nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
895
896         if (dac33->nsample_min < nsample_limit)
897                 dac33->nsample_min = nsample_limit;
898
899         if (dac33->nsample < dac33->nsample_min)
900                 dac33->nsample = dac33->nsample_min;
901
902         /*
903          * Find and fix up the highest nsmaple limit
904          * In order to not overflow the DAC33 buffer substract the
905          * alarm_threshold value from the size of the DAC33 buffer
906          */
907         nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
908
909         if (dac33->nsample_max > nsample_limit)
910                 dac33->nsample_max = nsample_limit;
911
912         if (dac33->nsample > dac33->nsample_max)
913                 dac33->nsample = dac33->nsample_max;
914 }
915
916 static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
917                              struct snd_soc_dai *dai)
918 {
919         dac33_calculate_times(substream);
920         dac33_prepare_chip(substream);
921
922         return 0;
923 }
924
925 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
926                              struct snd_soc_dai *dai)
927 {
928         struct snd_soc_pcm_runtime *rtd = substream->private_data;
929         struct snd_soc_device *socdev = rtd->socdev;
930         struct snd_soc_codec *codec = socdev->card->codec;
931         struct tlv320dac33_priv *dac33 = codec->private_data;
932         int ret = 0;
933
934         switch (cmd) {
935         case SNDRV_PCM_TRIGGER_START:
936         case SNDRV_PCM_TRIGGER_RESUME:
937         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
938                 if (dac33->fifo_mode) {
939                         dac33->state = DAC33_PREFILL;
940                         queue_work(dac33->dac33_wq, &dac33->work);
941                 }
942                 break;
943         case SNDRV_PCM_TRIGGER_STOP:
944         case SNDRV_PCM_TRIGGER_SUSPEND:
945         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
946                 if (dac33->fifo_mode) {
947                         dac33->state = DAC33_FLUSH;
948                         queue_work(dac33->dac33_wq, &dac33->work);
949                 }
950                 break;
951         default:
952                 ret = -EINVAL;
953         }
954
955         return ret;
956 }
957
958 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
959                 int clk_id, unsigned int freq, int dir)
960 {
961         struct snd_soc_codec *codec = codec_dai->codec;
962         struct tlv320dac33_priv *dac33 = codec->private_data;
963         u8 ioc_reg, asrcb_reg;
964
965         ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
966         asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
967         switch (clk_id) {
968         case TLV320DAC33_MCLK:
969                 ioc_reg |= DAC33_REFSEL;
970                 asrcb_reg |= DAC33_SRCREFSEL;
971                 break;
972         case TLV320DAC33_SLEEPCLK:
973                 ioc_reg &= ~DAC33_REFSEL;
974                 asrcb_reg &= ~DAC33_SRCREFSEL;
975                 break;
976         default:
977                 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
978                 break;
979         }
980         dac33->refclk = freq;
981
982         dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
983         dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
984
985         return 0;
986 }
987
988 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
989                              unsigned int fmt)
990 {
991         struct snd_soc_codec *codec = codec_dai->codec;
992         struct tlv320dac33_priv *dac33 = codec->private_data;
993         u8 aictrl_a, aictrl_b;
994
995         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
996         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
997         /* set master/slave audio interface */
998         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
999         case SND_SOC_DAIFMT_CBM_CFM:
1000                 /* Codec Master */
1001                 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1002                 break;
1003         case SND_SOC_DAIFMT_CBS_CFS:
1004                 /* Codec Slave */
1005                 if (dac33->fifo_mode) {
1006                         dev_err(codec->dev, "FIFO mode requires master mode\n");
1007                         return -EINVAL;
1008                 } else
1009                         aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1010                 break;
1011         default:
1012                 return -EINVAL;
1013         }
1014
1015         aictrl_a &= ~DAC33_AFMT_MASK;
1016         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1017         case SND_SOC_DAIFMT_I2S:
1018                 aictrl_a |= DAC33_AFMT_I2S;
1019                 break;
1020         case SND_SOC_DAIFMT_DSP_A:
1021                 aictrl_a |= DAC33_AFMT_DSP;
1022                 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1023                 aictrl_b |= DAC33_DATA_DELAY(1); /* 1 bit delay */
1024                 break;
1025         case SND_SOC_DAIFMT_DSP_B:
1026                 aictrl_a |= DAC33_AFMT_DSP;
1027                 aictrl_b &= ~DAC33_DATA_DELAY_MASK; /* No delay */
1028                 break;
1029         case SND_SOC_DAIFMT_RIGHT_J:
1030                 aictrl_a |= DAC33_AFMT_RIGHT_J;
1031                 break;
1032         case SND_SOC_DAIFMT_LEFT_J:
1033                 aictrl_a |= DAC33_AFMT_LEFT_J;
1034                 break;
1035         default:
1036                 dev_err(codec->dev, "Unsupported format (%u)\n",
1037                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1038                 return -EINVAL;
1039         }
1040
1041         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1042         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1043
1044         return 0;
1045 }
1046
1047 static void dac33_init_chip(struct snd_soc_codec *codec)
1048 {
1049         /* 44-46: DAC Control Registers */
1050         /* A : DAC sample rate Fsref/1.5 */
1051         dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(1));
1052         /* B : DAC src=normal, not muted */
1053         dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
1054                                              DAC33_DACSRCL_LEFT);
1055         /* C : (defaults) */
1056         dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
1057
1058         /* 64-65 : L&R DAC power control
1059          Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
1060         dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1061         dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1062
1063         /* 73 : volume soft stepping control,
1064          clock source = internal osc (?) */
1065         dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
1066
1067         /* 66 : LOP/LOM Modes */
1068         dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
1069
1070         /* 68 : LOM inverted from LOP */
1071         dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
1072
1073         dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
1074 }
1075
1076 static int dac33_soc_probe(struct platform_device *pdev)
1077 {
1078         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1079         struct snd_soc_codec *codec;
1080         struct tlv320dac33_priv *dac33;
1081         int ret = 0;
1082
1083         BUG_ON(!tlv320dac33_codec);
1084
1085         codec = tlv320dac33_codec;
1086         socdev->card->codec = codec;
1087         dac33 = codec->private_data;
1088
1089         /* Power up the codec */
1090         dac33_hard_power(codec, 1);
1091         /* Set default configuration */
1092         dac33_init_chip(codec);
1093
1094         /* register pcms */
1095         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1096         if (ret < 0) {
1097                 dev_err(codec->dev, "failed to create pcms\n");
1098                 goto pcm_err;
1099         }
1100
1101         snd_soc_add_controls(codec, dac33_snd_controls,
1102                              ARRAY_SIZE(dac33_snd_controls));
1103         /* Only add the nSample controls, if we have valid IRQ number */
1104         if (dac33->irq >= 0)
1105                 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1106                                      ARRAY_SIZE(dac33_nsample_snd_controls));
1107
1108         dac33_add_widgets(codec);
1109
1110         /* power on device */
1111         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1112
1113         /* Bias level configuration has enabled regulator an extra time */
1114         regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1115
1116         return 0;
1117
1118 pcm_err:
1119         dac33_hard_power(codec, 0);
1120         return ret;
1121 }
1122
1123 static int dac33_soc_remove(struct platform_device *pdev)
1124 {
1125         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1126         struct snd_soc_codec *codec = socdev->card->codec;
1127
1128         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1129
1130         snd_soc_free_pcms(socdev);
1131         snd_soc_dapm_free(socdev);
1132
1133         return 0;
1134 }
1135
1136 static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1137 {
1138         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1139         struct snd_soc_codec *codec = socdev->card->codec;
1140
1141         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1142
1143         return 0;
1144 }
1145
1146 static int dac33_soc_resume(struct platform_device *pdev)
1147 {
1148         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1149         struct snd_soc_codec *codec = socdev->card->codec;
1150
1151         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1152         dac33_set_bias_level(codec, codec->suspend_bias_level);
1153
1154         return 0;
1155 }
1156
1157 struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1158         .probe = dac33_soc_probe,
1159         .remove = dac33_soc_remove,
1160         .suspend = dac33_soc_suspend,
1161         .resume = dac33_soc_resume,
1162 };
1163 EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1164
1165 #define DAC33_RATES     (SNDRV_PCM_RATE_44100 | \
1166                          SNDRV_PCM_RATE_48000)
1167 #define DAC33_FORMATS   SNDRV_PCM_FMTBIT_S16_LE
1168
1169 static struct snd_soc_dai_ops dac33_dai_ops = {
1170         .hw_params      = dac33_hw_params,
1171         .prepare        = dac33_pcm_prepare,
1172         .trigger        = dac33_pcm_trigger,
1173         .set_sysclk     = dac33_set_dai_sysclk,
1174         .set_fmt        = dac33_set_dai_fmt,
1175 };
1176
1177 struct snd_soc_dai dac33_dai = {
1178         .name = "tlv320dac33",
1179         .playback = {
1180                 .stream_name = "Playback",
1181                 .channels_min = 2,
1182                 .channels_max = 2,
1183                 .rates = DAC33_RATES,
1184                 .formats = DAC33_FORMATS,},
1185         .ops = &dac33_dai_ops,
1186 };
1187 EXPORT_SYMBOL_GPL(dac33_dai);
1188
1189 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1190                                      const struct i2c_device_id *id)
1191 {
1192         struct tlv320dac33_platform_data *pdata;
1193         struct tlv320dac33_priv *dac33;
1194         struct snd_soc_codec *codec;
1195         int ret, i;
1196
1197         if (client->dev.platform_data == NULL) {
1198                 dev_err(&client->dev, "Platform data not set\n");
1199                 return -ENODEV;
1200         }
1201         pdata = client->dev.platform_data;
1202
1203         dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1204         if (dac33 == NULL)
1205                 return -ENOMEM;
1206
1207         codec = &dac33->codec;
1208         codec->private_data = dac33;
1209         codec->control_data = client;
1210
1211         mutex_init(&codec->mutex);
1212         mutex_init(&dac33->mutex);
1213         INIT_LIST_HEAD(&codec->dapm_widgets);
1214         INIT_LIST_HEAD(&codec->dapm_paths);
1215
1216         codec->name = "tlv320dac33";
1217         codec->owner = THIS_MODULE;
1218         codec->read = dac33_read_reg_cache;
1219         codec->write = dac33_write_locked;
1220         codec->hw_write = (hw_write_t) i2c_master_send;
1221         codec->bias_level = SND_SOC_BIAS_OFF;
1222         codec->set_bias_level = dac33_set_bias_level;
1223         codec->dai = &dac33_dai;
1224         codec->num_dai = 1;
1225         codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1226         codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1227                                    GFP_KERNEL);
1228         if (codec->reg_cache == NULL) {
1229                 ret = -ENOMEM;
1230                 goto error_reg;
1231         }
1232
1233         i2c_set_clientdata(client, dac33);
1234
1235         dac33->power_gpio = pdata->power_gpio;
1236         dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1237         dac33->irq = client->irq;
1238         dac33->nsample = NSAMPLE_MAX;
1239         /* Disable FIFO use by default */
1240         dac33->fifo_mode = DAC33_FIFO_BYPASS;
1241
1242         tlv320dac33_codec = codec;
1243
1244         codec->dev = &client->dev;
1245         dac33_dai.dev = codec->dev;
1246
1247         /* Check if the reset GPIO number is valid and request it */
1248         if (dac33->power_gpio >= 0) {
1249                 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1250                 if (ret < 0) {
1251                         dev_err(codec->dev,
1252                                 "Failed to request reset GPIO (%d)\n",
1253                                 dac33->power_gpio);
1254                         snd_soc_unregister_dai(&dac33_dai);
1255                         snd_soc_unregister_codec(codec);
1256                         goto error_gpio;
1257                 }
1258                 gpio_direction_output(dac33->power_gpio, 0);
1259         } else {
1260                 dac33->chip_power = 1;
1261         }
1262
1263         /* Check if the IRQ number is valid and request it */
1264         if (dac33->irq >= 0) {
1265                 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1266                                   IRQF_TRIGGER_RISING | IRQF_DISABLED,
1267                                   codec->name, codec);
1268                 if (ret < 0) {
1269                         dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1270                                                 dac33->irq, ret);
1271                         dac33->irq = -1;
1272                 }
1273                 if (dac33->irq != -1) {
1274                         /* Setup work queue */
1275                         dac33->dac33_wq =
1276                                 create_singlethread_workqueue("tlv320dac33");
1277                         if (dac33->dac33_wq == NULL) {
1278                                 free_irq(dac33->irq, &dac33->codec);
1279                                 ret = -ENOMEM;
1280                                 goto error_wq;
1281                         }
1282
1283                         INIT_WORK(&dac33->work, dac33_work);
1284                 }
1285         }
1286
1287         for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1288                 dac33->supplies[i].supply = dac33_supply_names[i];
1289
1290         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1291                                  dac33->supplies);
1292
1293         if (ret != 0) {
1294                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1295                 goto err_get;
1296         }
1297
1298         ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
1299                                     dac33->supplies);
1300         if (ret != 0) {
1301                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1302                 goto err_enable;
1303         }
1304
1305         ret = snd_soc_register_codec(codec);
1306         if (ret != 0) {
1307                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1308                 goto error_codec;
1309         }
1310
1311         ret = snd_soc_register_dai(&dac33_dai);
1312         if (ret != 0) {
1313                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1314                 snd_soc_unregister_codec(codec);
1315                 goto error_codec;
1316         }
1317
1318         /* Shut down the codec for now */
1319         dac33_hard_power(codec, 0);
1320
1321         return ret;
1322
1323 error_codec:
1324         regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1325 err_enable:
1326         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1327 err_get:
1328         if (dac33->irq >= 0) {
1329                 free_irq(dac33->irq, &dac33->codec);
1330                 destroy_workqueue(dac33->dac33_wq);
1331         }
1332 error_wq:
1333         if (dac33->power_gpio >= 0)
1334                 gpio_free(dac33->power_gpio);
1335 error_gpio:
1336         kfree(codec->reg_cache);
1337 error_reg:
1338         tlv320dac33_codec = NULL;
1339         kfree(dac33);
1340
1341         return ret;
1342 }
1343
1344 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1345 {
1346         struct tlv320dac33_priv *dac33;
1347
1348         dac33 = i2c_get_clientdata(client);
1349         dac33_hard_power(&dac33->codec, 0);
1350
1351         if (dac33->power_gpio >= 0)
1352                 gpio_free(dac33->power_gpio);
1353         if (dac33->irq >= 0)
1354                 free_irq(dac33->irq, &dac33->codec);
1355
1356         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1357
1358         destroy_workqueue(dac33->dac33_wq);
1359         snd_soc_unregister_dai(&dac33_dai);
1360         snd_soc_unregister_codec(&dac33->codec);
1361         kfree(dac33->codec.reg_cache);
1362         kfree(dac33);
1363         tlv320dac33_codec = NULL;
1364
1365         return 0;
1366 }
1367
1368 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1369         {
1370                 .name = "tlv320dac33",
1371                 .driver_data = 0,
1372         },
1373         { },
1374 };
1375
1376 static struct i2c_driver tlv320dac33_i2c_driver = {
1377         .driver = {
1378                 .name = "tlv320dac33",
1379                 .owner = THIS_MODULE,
1380         },
1381         .probe          = dac33_i2c_probe,
1382         .remove         = __devexit_p(dac33_i2c_remove),
1383         .id_table       = tlv320dac33_i2c_id,
1384 };
1385
1386 static int __init dac33_module_init(void)
1387 {
1388         int r;
1389         r = i2c_add_driver(&tlv320dac33_i2c_driver);
1390         if (r < 0) {
1391                 printk(KERN_ERR "DAC33: driver registration failed\n");
1392                 return r;
1393         }
1394         return 0;
1395 }
1396 module_init(dac33_module_init);
1397
1398 static void __exit dac33_module_exit(void)
1399 {
1400         i2c_del_driver(&tlv320dac33_i2c_driver);
1401 }
1402 module_exit(dac33_module_exit);
1403
1404
1405 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1406 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1407 MODULE_LICENSE("GPL");