[ALSA] Various fixes for suspend/resume of ALSA PCI drivers
[linux-2.6.git] / sound / pci / intel8x0.c
1 /*
2  *   ALSA driver for Intel ICH (i8x0) chipsets
3  *
4  *      Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5  *
6  *
7  *   This code also contains alpha support for SiS 735 chipsets provided
8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9  *   for SiS735, so the code is not fully functional.
10  *
11  *
12  *   This program is free software; you can redistribute it and/or modify
13  *   it under the terms of the GNU General Public License as published by
14  *   the Free Software Foundation; either version 2 of the License, or
15  *   (at your option) any later version.
16  *
17  *   This program is distributed in the hope that it will be useful,
18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  *   GNU General Public License for more details.
21  *
22  *   You should have received a copy of the GNU General Public License
23  *   along with this program; if not, write to the Free Software
24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
25
26  *
27  */      
28
29 #include <sound/driver.h>
30 #include <asm/io.h>
31 #include <linux/delay.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/slab.h>
36 #include <linux/moduleparam.h>
37 #include <sound/core.h>
38 #include <sound/pcm.h>
39 #include <sound/ac97_codec.h>
40 #include <sound/info.h>
41 #include <sound/initval.h>
42 /* for 440MX workaround */
43 #include <asm/pgtable.h>
44 #include <asm/cacheflush.h>
45
46 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48 MODULE_LICENSE("GPL");
49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
50                 "{Intel,82901AB-ICH0},"
51                 "{Intel,82801BA-ICH2},"
52                 "{Intel,82801CA-ICH3},"
53                 "{Intel,82801DB-ICH4},"
54                 "{Intel,ICH5},"
55                 "{Intel,ICH6},"
56                 "{Intel,ICH7},"
57                 "{Intel,6300ESB},"
58                 "{Intel,ESB2},"
59                 "{Intel,MX440},"
60                 "{SiS,SI7012},"
61                 "{NVidia,nForce Audio},"
62                 "{NVidia,nForce2 Audio},"
63                 "{AMD,AMD768},"
64                 "{AMD,AMD8111},"
65                 "{ALI,M5455}}");
66
67 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
68 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
69 static int ac97_clock;
70 static char *ac97_quirk;
71 static int buggy_semaphore;
72 static int buggy_irq = -1; /* auto-check */
73 static int xbox;
74
75 module_param(index, int, 0444);
76 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
77 module_param(id, charp, 0444);
78 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
79 module_param(ac97_clock, int, 0444);
80 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
81 module_param(ac97_quirk, charp, 0444);
82 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
83 module_param(buggy_semaphore, bool, 0444);
84 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
85 module_param(buggy_irq, bool, 0444);
86 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
87 module_param(xbox, bool, 0444);
88 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
89
90 /* just for backward compatibility */
91 static int enable;
92 module_param(enable, bool, 0444);
93 static int joystick;
94 module_param(joystick, int, 0444);
95
96 /*
97  *  Direct registers
98  */
99 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
100
101 #define ICHREG(x) ICH_REG_##x
102
103 #define DEFINE_REGSET(name,base) \
104 enum { \
105         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
106         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
107         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
108         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
109         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
110         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
111         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
112 };
113
114 /* busmaster blocks */
115 DEFINE_REGSET(OFF, 0);          /* offset */
116 DEFINE_REGSET(PI, 0x00);        /* PCM in */
117 DEFINE_REGSET(PO, 0x10);        /* PCM out */
118 DEFINE_REGSET(MC, 0x20);        /* Mic in */
119
120 /* ICH4 busmaster blocks */
121 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
122 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
123 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
124
125 /* values for each busmaster block */
126
127 /* LVI */
128 #define ICH_REG_LVI_MASK                0x1f
129
130 /* SR */
131 #define ICH_FIFOE                       0x10    /* FIFO error */
132 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
133 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
134 #define ICH_CELV                        0x02    /* current equals last valid */
135 #define ICH_DCH                         0x01    /* DMA controller halted */
136
137 /* PIV */
138 #define ICH_REG_PIV_MASK                0x1f    /* mask */
139
140 /* CR */
141 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
142 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
143 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
144 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
145 #define ICH_STARTBM                     0x01    /* start busmaster operation */
146
147
148 /* global block */
149 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
150 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
151 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
152 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
153 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
154 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
155 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
156 #define   ICH_PCM_246_MASK      0x00300000      /* 6 channels (not all chips) */
157 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
158 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
159 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
160 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
161 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
162 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
163 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
164 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
165 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
166 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
167 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
168 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
169 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
170 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
171 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
172 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
173 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
174 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
175 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
176 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
177 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
178 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
179 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
180 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
181 #define   ICH_SIS_TRI           0x00080000      /* SIS: tertiary resume irq */
182 #define   ICH_SIS_TCR           0x00040000      /* SIS: tertiary codec ready */
183 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
184 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
185 #define   ICH_RCS               0x00008000      /* read completion status */
186 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
187 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
188 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
189 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
190 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
191 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
192 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
193 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
194 #define   ICH_POINT             0x00000040      /* playback interrupt */
195 #define   ICH_PIINT             0x00000020      /* capture interrupt */
196 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
197 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
198 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
199 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
200 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
201 #define   ICH_CAS               0x01            /* codec access semaphore */
202 #define ICH_REG_SDM             0x80
203 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
204 #define   ICH_DI2L_SHIFT        6
205 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
206 #define   ICH_DI1L_SHIFT        4
207 #define   ICH_SE                0x00000008      /* steer enable */
208 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
209
210 #define ICH_MAX_FRAGS           32              /* max hw frags */
211
212
213 /*
214  * registers for Ali5455
215  */
216
217 /* ALi 5455 busmaster blocks */
218 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
219 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
220 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
221 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
222 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
223 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
224 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
225 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
226 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
227 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
228 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
229
230 enum {
231         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
232         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
233         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
234         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
235         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
236         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
237         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
238         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
239         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
240         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
241         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
242         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
243         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
244         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
245         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
246         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
247         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
248         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
249         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
250         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
251         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
252 };
253
254 #define ALI_CAS_SEM_BUSY        0x80000000
255 #define ALI_CPR_ADDR_SECONDARY  0x100
256 #define ALI_CPR_ADDR_READ       0x80
257 #define ALI_CSPSR_CODEC_READY   0x08
258 #define ALI_CSPSR_READ_OK       0x02
259 #define ALI_CSPSR_WRITE_OK      0x01
260
261 /* interrupts for the whole chip by interrupt status register finish */
262  
263 #define ALI_INT_MICIN2          (1<<26)
264 #define ALI_INT_PCMIN2          (1<<25)
265 #define ALI_INT_I2SIN           (1<<24)
266 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
267 #define ALI_INT_SPDIFIN         (1<<22)
268 #define ALI_INT_LFEOUT          (1<<21)
269 #define ALI_INT_CENTEROUT       (1<<20)
270 #define ALI_INT_CODECSPDIFOUT   (1<<19)
271 #define ALI_INT_MICIN           (1<<18)
272 #define ALI_INT_PCMOUT          (1<<17)
273 #define ALI_INT_PCMIN           (1<<16)
274 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
275 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
276 #define ALI_INT_GPIO            (1<<1)
277 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
278                                  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
279
280 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
281 #define ICH_ALI_SC_AC97_DBL     (1<<30)
282 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
283 #define ICH_ALI_SC_IN_BITS      (3<<18)
284 #define ICH_ALI_SC_OUT_BITS     (3<<16)
285 #define ICH_ALI_SC_6CH_CFG      (3<<14)
286 #define ICH_ALI_SC_PCM_4        (1<<8)
287 #define ICH_ALI_SC_PCM_6        (2<<8)
288 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
289
290 #define ICH_ALI_SS_SEC_ID       (3<<5)
291 #define ICH_ALI_SS_PRI_ID       (3<<3)
292
293 #define ICH_ALI_IF_AC97SP       (1<<21)
294 #define ICH_ALI_IF_MC           (1<<20)
295 #define ICH_ALI_IF_PI           (1<<19)
296 #define ICH_ALI_IF_MC2          (1<<18)
297 #define ICH_ALI_IF_PI2          (1<<17)
298 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
299 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
300 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
301 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
302 #define ICH_ALI_IF_PO_SPDF      (1<<3)
303 #define ICH_ALI_IF_PO           (1<<1)
304
305 /*
306  *  
307  */
308
309 enum {
310         ICHD_PCMIN,
311         ICHD_PCMOUT,
312         ICHD_MIC,
313         ICHD_MIC2,
314         ICHD_PCM2IN,
315         ICHD_SPBAR,
316         ICHD_LAST = ICHD_SPBAR
317 };
318 enum {
319         NVD_PCMIN,
320         NVD_PCMOUT,
321         NVD_MIC,
322         NVD_SPBAR,
323         NVD_LAST = NVD_SPBAR
324 };
325 enum {
326         ALID_PCMIN,
327         ALID_PCMOUT,
328         ALID_MIC,
329         ALID_AC97SPDIFOUT,
330         ALID_SPDIFIN,
331         ALID_SPDIFOUT,
332         ALID_LAST = ALID_SPDIFOUT
333 };
334
335 #define get_ichdev(substream) (substream->runtime->private_data)
336
337 struct ichdev {
338         unsigned int ichd;                      /* ich device number */
339         unsigned long reg_offset;               /* offset to bmaddr */
340         u32 *bdbar;                             /* CPU address (32bit) */
341         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
342         struct snd_pcm_substream *substream;
343         unsigned int physbuf;                   /* physical address (32bit) */
344         unsigned int size;
345         unsigned int fragsize;
346         unsigned int fragsize1;
347         unsigned int position;
348         unsigned int pos_shift;
349         int frags;
350         int lvi;
351         int lvi_frag;
352         int civ;
353         int ack;
354         int ack_reload;
355         unsigned int ack_bit;
356         unsigned int roff_sr;
357         unsigned int roff_picb;
358         unsigned int int_sta_mask;              /* interrupt status mask */
359         unsigned int ali_slot;                  /* ALI DMA slot */
360         struct ac97_pcm *pcm;
361         int pcm_open_flag;
362         unsigned int page_attr_changed: 1;
363         unsigned int suspended: 1;
364 };
365
366 struct intel8x0 {
367         unsigned int device_type;
368
369         int irq;
370
371         unsigned int mmio;
372         unsigned long addr;
373         void __iomem *remap_addr;
374         unsigned int bm_mmio;
375         unsigned long bmaddr;
376         void __iomem *remap_bmaddr;
377
378         struct pci_dev *pci;
379         struct snd_card *card;
380
381         int pcm_devs;
382         struct snd_pcm *pcm[6];
383         struct ichdev ichd[6];
384
385         unsigned multi4: 1,
386                  multi6: 1,
387                  dra: 1,
388                  smp20bit: 1;
389         unsigned in_ac97_init: 1,
390                  in_sdin_init: 1;
391         unsigned in_measurement: 1;     /* during ac97 clock measurement */
392         unsigned fix_nocache: 1;        /* workaround for 440MX */
393         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
394         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
395         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
396
397         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
398         unsigned int sdm_saved; /* SDM reg value */
399
400         struct snd_ac97_bus *ac97_bus;
401         struct snd_ac97 *ac97[3];
402         unsigned int ac97_sdin[3];
403         unsigned int max_codecs, ncodecs;
404         unsigned int *codec_bit;
405         unsigned int codec_isr_bits;
406         unsigned int codec_ready_bits;
407
408         spinlock_t reg_lock;
409         
410         u32 bdbars_count;
411         struct snd_dma_buffer bdbars;
412         u32 int_sta_reg;                /* interrupt status register */
413         u32 int_sta_mask;               /* interrupt status mask */
414 };
415
416 static struct pci_device_id snd_intel8x0_ids[] = {
417         { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
418         { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
419         { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
420         { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
421         { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
422         { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
423         { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
424         { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
425         { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
426         { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
427         { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
428         { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7012 */
429         { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE */
430         { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP04 */
431         { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE2 */
432         { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK804 */
433         { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8 */
434         { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE3 */
435         { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8S */
436         { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP51 */
437         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
438         { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
439         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
440         { 0, }
441 };
442
443 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
444
445 /*
446  *  Lowlevel I/O - busmaster
447  */
448
449 static u8 igetbyte(struct intel8x0 *chip, u32 offset)
450 {
451         if (chip->bm_mmio)
452                 return readb(chip->remap_bmaddr + offset);
453         else
454                 return inb(chip->bmaddr + offset);
455 }
456
457 static u16 igetword(struct intel8x0 *chip, u32 offset)
458 {
459         if (chip->bm_mmio)
460                 return readw(chip->remap_bmaddr + offset);
461         else
462                 return inw(chip->bmaddr + offset);
463 }
464
465 static u32 igetdword(struct intel8x0 *chip, u32 offset)
466 {
467         if (chip->bm_mmio)
468                 return readl(chip->remap_bmaddr + offset);
469         else
470                 return inl(chip->bmaddr + offset);
471 }
472
473 static void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
474 {
475         if (chip->bm_mmio)
476                 writeb(val, chip->remap_bmaddr + offset);
477         else
478                 outb(val, chip->bmaddr + offset);
479 }
480
481 static void iputword(struct intel8x0 *chip, u32 offset, u16 val)
482 {
483         if (chip->bm_mmio)
484                 writew(val, chip->remap_bmaddr + offset);
485         else
486                 outw(val, chip->bmaddr + offset);
487 }
488
489 static void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
490 {
491         if (chip->bm_mmio)
492                 writel(val, chip->remap_bmaddr + offset);
493         else
494                 outl(val, chip->bmaddr + offset);
495 }
496
497 /*
498  *  Lowlevel I/O - AC'97 registers
499  */
500
501 static u16 iagetword(struct intel8x0 *chip, u32 offset)
502 {
503         if (chip->mmio)
504                 return readw(chip->remap_addr + offset);
505         else
506                 return inw(chip->addr + offset);
507 }
508
509 static void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
510 {
511         if (chip->mmio)
512                 writew(val, chip->remap_addr + offset);
513         else
514                 outw(val, chip->addr + offset);
515 }
516
517 /*
518  *  Basic I/O
519  */
520
521 /*
522  * access to AC97 codec via normal i/o (for ICH and SIS7012)
523  */
524
525 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
526 {
527         int time;
528         
529         if (codec > 2)
530                 return -EIO;
531         if (chip->in_sdin_init) {
532                 /* we don't know the ready bit assignment at the moment */
533                 /* so we check any */
534                 codec = chip->codec_isr_bits;
535         } else {
536                 codec = chip->codec_bit[chip->ac97_sdin[codec]];
537         }
538
539         /* codec ready ? */
540         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
541                 return -EIO;
542
543         if (chip->buggy_semaphore)
544                 return 0; /* just ignore ... */
545
546         /* Anyone holding a semaphore for 1 msec should be shot... */
547         time = 100;
548         do {
549                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
550                         return 0;
551                 udelay(10);
552         } while (time--);
553
554         /* access to some forbidden (non existant) ac97 registers will not
555          * reset the semaphore. So even if you don't get the semaphore, still
556          * continue the access. We don't need the semaphore anyway. */
557         snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
558                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
559         iagetword(chip, 0);     /* clear semaphore flag */
560         /* I don't care about the semaphore */
561         return -EBUSY;
562 }
563  
564 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
565                                      unsigned short reg,
566                                      unsigned short val)
567 {
568         struct intel8x0 *chip = ac97->private_data;
569         
570         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
571                 if (! chip->in_ac97_init)
572                         snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
573         }
574         iaputword(chip, reg + ac97->num * 0x80, val);
575 }
576
577 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
578                                               unsigned short reg)
579 {
580         struct intel8x0 *chip = ac97->private_data;
581         unsigned short res;
582         unsigned int tmp;
583
584         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
585                 if (! chip->in_ac97_init)
586                         snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
587                 res = 0xffff;
588         } else {
589                 res = iagetword(chip, reg + ac97->num * 0x80);
590                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
591                         /* reset RCS and preserve other R/WC bits */
592                         iputdword(chip, ICHREG(GLOB_STA), tmp &
593                                   ~(chip->codec_ready_bits | ICH_GSCI));
594                         if (! chip->in_ac97_init)
595                                 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
596                         res = 0xffff;
597                 }
598         }
599         return res;
600 }
601
602 static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
603                                                    unsigned int codec)
604 {
605         unsigned int tmp;
606
607         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
608                 iagetword(chip, codec * 0x80);
609                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
610                         /* reset RCS and preserve other R/WC bits */
611                         iputdword(chip, ICHREG(GLOB_STA), tmp &
612                                   ~(chip->codec_ready_bits | ICH_GSCI));
613                 }
614         }
615 }
616
617 /*
618  * access to AC97 for Ali5455
619  */
620 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
621 {
622         int count = 0;
623         for (count = 0; count < 0x7f; count++) {
624                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
625                 if (val & mask)
626                         return 0;
627         }
628         if (! chip->in_ac97_init)
629                 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
630         return -EBUSY;
631 }
632
633 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
634 {
635         int time = 100;
636         if (chip->buggy_semaphore)
637                 return 0; /* just ignore ... */
638         while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
639                 udelay(1);
640         if (! time && ! chip->in_ac97_init)
641                 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
642         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
643 }
644
645 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
646 {
647         struct intel8x0 *chip = ac97->private_data;
648         unsigned short data = 0xffff;
649
650         if (snd_intel8x0_ali_codec_semaphore(chip))
651                 goto __err;
652         reg |= ALI_CPR_ADDR_READ;
653         if (ac97->num)
654                 reg |= ALI_CPR_ADDR_SECONDARY;
655         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
656         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
657                 goto __err;
658         data = igetword(chip, ICHREG(ALI_SPR));
659  __err:
660         return data;
661 }
662
663 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
664                                          unsigned short val)
665 {
666         struct intel8x0 *chip = ac97->private_data;
667
668         if (snd_intel8x0_ali_codec_semaphore(chip))
669                 return;
670         iputword(chip, ICHREG(ALI_CPR), val);
671         if (ac97->num)
672                 reg |= ALI_CPR_ADDR_SECONDARY;
673         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
674         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
675 }
676
677
678 /*
679  * DMA I/O
680  */
681 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 
682 {
683         int idx;
684         u32 *bdbar = ichdev->bdbar;
685         unsigned long port = ichdev->reg_offset;
686
687         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
688         if (ichdev->size == ichdev->fragsize) {
689                 ichdev->ack_reload = ichdev->ack = 2;
690                 ichdev->fragsize1 = ichdev->fragsize >> 1;
691                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
692                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
693                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
694                                                      ichdev->fragsize1 >> ichdev->pos_shift);
695                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
696                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
697                                                      ichdev->fragsize1 >> ichdev->pos_shift);
698                 }
699                 ichdev->frags = 2;
700         } else {
701                 ichdev->ack_reload = ichdev->ack = 1;
702                 ichdev->fragsize1 = ichdev->fragsize;
703                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
704                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
705                                                      (((idx >> 1) * ichdev->fragsize) %
706                                                       ichdev->size));
707                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
708                                                      ichdev->fragsize >> ichdev->pos_shift);
709 #if 0
710                         printk("bdbar[%i] = 0x%x [0x%x]\n",
711                                idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
712 #endif
713                 }
714                 ichdev->frags = ichdev->size / ichdev->fragsize;
715         }
716         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
717         ichdev->civ = 0;
718         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
719         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
720         ichdev->position = 0;
721 #if 0
722         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
723                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
724 #endif
725         /* clear interrupts */
726         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
727 }
728
729 #ifdef __i386__
730 /*
731  * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
732  * which aborts PCI busmaster for audio transfer.  A workaround is to set
733  * the pages as non-cached.  For details, see the errata in
734  *      http://www.intel.com/design/chipsets/specupdt/245051.htm
735  */
736 static void fill_nocache(void *buf, int size, int nocache)
737 {
738         size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
739         change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
740         global_flush_tlb();
741 }
742 #else
743 #define fill_nocache(buf,size,nocache)
744 #endif
745
746 /*
747  *  Interrupt handler
748  */
749
750 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
751 {
752         unsigned long port = ichdev->reg_offset;
753         int status, civ, i, step;
754         int ack = 0;
755
756         spin_lock(&chip->reg_lock);
757         status = igetbyte(chip, port + ichdev->roff_sr);
758         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
759         if (!(status & ICH_BCIS)) {
760                 step = 0;
761         } else if (civ == ichdev->civ) {
762                 // snd_printd("civ same %d\n", civ);
763                 step = 1;
764                 ichdev->civ++;
765                 ichdev->civ &= ICH_REG_LVI_MASK;
766         } else {
767                 step = civ - ichdev->civ;
768                 if (step < 0)
769                         step += ICH_REG_LVI_MASK + 1;
770                 // if (step != 1)
771                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
772                 ichdev->civ = civ;
773         }
774
775         ichdev->position += step * ichdev->fragsize1;
776         if (! chip->in_measurement)
777                 ichdev->position %= ichdev->size;
778         ichdev->lvi += step;
779         ichdev->lvi &= ICH_REG_LVI_MASK;
780         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
781         for (i = 0; i < step; i++) {
782                 ichdev->lvi_frag++;
783                 ichdev->lvi_frag %= ichdev->frags;
784                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
785 #if 0
786         printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
787                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
788                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
789                inl(port + 4), inb(port + ICH_REG_OFF_CR));
790 #endif
791                 if (--ichdev->ack == 0) {
792                         ichdev->ack = ichdev->ack_reload;
793                         ack = 1;
794                 }
795         }
796         spin_unlock(&chip->reg_lock);
797         if (ack && ichdev->substream) {
798                 snd_pcm_period_elapsed(ichdev->substream);
799         }
800         iputbyte(chip, port + ichdev->roff_sr,
801                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
802 }
803
804 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
805 {
806         struct intel8x0 *chip = dev_id;
807         struct ichdev *ichdev;
808         unsigned int status;
809         unsigned int i;
810
811         status = igetdword(chip, chip->int_sta_reg);
812         if (status == 0xffffffff)       /* we are not yet resumed */
813                 return IRQ_NONE;
814
815         if ((status & chip->int_sta_mask) == 0) {
816                 if (status) {
817                         /* ack */
818                         iputdword(chip, chip->int_sta_reg, status);
819                         if (! chip->buggy_irq)
820                                 status = 0;
821                 }
822                 return IRQ_RETVAL(status);
823         }
824
825         for (i = 0; i < chip->bdbars_count; i++) {
826                 ichdev = &chip->ichd[i];
827                 if (status & ichdev->int_sta_mask)
828                         snd_intel8x0_update(chip, ichdev);
829         }
830
831         /* ack them */
832         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
833         
834         return IRQ_HANDLED;
835 }
836
837 /*
838  *  PCM part
839  */
840
841 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
842 {
843         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
844         struct ichdev *ichdev = get_ichdev(substream);
845         unsigned char val = 0;
846         unsigned long port = ichdev->reg_offset;
847
848         switch (cmd) {
849         case SNDRV_PCM_TRIGGER_RESUME:
850                 ichdev->suspended = 0;
851                 /* fallthru */
852         case SNDRV_PCM_TRIGGER_START:
853                 val = ICH_IOCE | ICH_STARTBM;
854                 break;
855         case SNDRV_PCM_TRIGGER_SUSPEND:
856                 ichdev->suspended = 1;
857                 /* fallthru */
858         case SNDRV_PCM_TRIGGER_STOP:
859                 val = 0;
860                 break;
861         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
862                 val = ICH_IOCE;
863                 break;
864         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
865                 val = ICH_IOCE | ICH_STARTBM;
866                 break;
867         default:
868                 return -EINVAL;
869         }
870         iputbyte(chip, port + ICH_REG_OFF_CR, val);
871         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
872                 /* wait until DMA stopped */
873                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
874                 /* reset whole DMA things */
875                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
876         }
877         return 0;
878 }
879
880 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
881 {
882         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
883         struct ichdev *ichdev = get_ichdev(substream);
884         unsigned long port = ichdev->reg_offset;
885         static int fiforeg[] = {
886                 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
887         };
888         unsigned int val, fifo;
889
890         val = igetdword(chip, ICHREG(ALI_DMACR));
891         switch (cmd) {
892         case SNDRV_PCM_TRIGGER_RESUME:
893                 ichdev->suspended = 0;
894                 /* fallthru */
895         case SNDRV_PCM_TRIGGER_START:
896         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
897                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
898                         /* clear FIFO for synchronization of channels */
899                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
900                         fifo &= ~(0xff << (ichdev->ali_slot % 4));  
901                         fifo |= 0x83 << (ichdev->ali_slot % 4); 
902                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
903                 }
904                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
905                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
906                 /* start DMA */
907                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
908                 break;
909         case SNDRV_PCM_TRIGGER_SUSPEND:
910                 ichdev->suspended = 1;
911                 /* fallthru */
912         case SNDRV_PCM_TRIGGER_STOP:
913         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
914                 /* pause */
915                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
916                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
917                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
918                         ;
919                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
920                         break;
921                 /* reset whole DMA things */
922                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
923                 /* clear interrupts */
924                 iputbyte(chip, port + ICH_REG_OFF_SR,
925                          igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
926                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
927                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
928                 break;
929         default:
930                 return -EINVAL;
931         }
932         return 0;
933 }
934
935 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
936                                   struct snd_pcm_hw_params *hw_params)
937 {
938         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
939         struct ichdev *ichdev = get_ichdev(substream);
940         struct snd_pcm_runtime *runtime = substream->runtime;
941         int dbl = params_rate(hw_params) > 48000;
942         int err;
943
944         if (chip->fix_nocache && ichdev->page_attr_changed) {
945                 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
946                 ichdev->page_attr_changed = 0;
947         }
948         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
949         if (err < 0)
950                 return err;
951         if (chip->fix_nocache) {
952                 if (runtime->dma_area && ! ichdev->page_attr_changed) {
953                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
954                         ichdev->page_attr_changed = 1;
955                 }
956         }
957         if (ichdev->pcm_open_flag) {
958                 snd_ac97_pcm_close(ichdev->pcm);
959                 ichdev->pcm_open_flag = 0;
960         }
961         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
962                                 params_channels(hw_params),
963                                 ichdev->pcm->r[dbl].slots);
964         if (err >= 0) {
965                 ichdev->pcm_open_flag = 1;
966                 /* Force SPDIF setting */
967                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
968                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
969                                           params_rate(hw_params));
970         }
971         return err;
972 }
973
974 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
975 {
976         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
977         struct ichdev *ichdev = get_ichdev(substream);
978
979         if (ichdev->pcm_open_flag) {
980                 snd_ac97_pcm_close(ichdev->pcm);
981                 ichdev->pcm_open_flag = 0;
982         }
983         if (chip->fix_nocache && ichdev->page_attr_changed) {
984                 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
985                 ichdev->page_attr_changed = 0;
986         }
987         return snd_pcm_lib_free_pages(substream);
988 }
989
990 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
991                                        struct snd_pcm_runtime *runtime)
992 {
993         unsigned int cnt;
994         int dbl = runtime->rate > 48000;
995
996         spin_lock_irq(&chip->reg_lock);
997         switch (chip->device_type) {
998         case DEVICE_ALI:
999                 cnt = igetdword(chip, ICHREG(ALI_SCR));
1000                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1001                 if (runtime->channels == 4 || dbl)
1002                         cnt |= ICH_ALI_SC_PCM_4;
1003                 else if (runtime->channels == 6)
1004                         cnt |= ICH_ALI_SC_PCM_6;
1005                 iputdword(chip, ICHREG(ALI_SCR), cnt);
1006                 break;
1007         case DEVICE_SIS:
1008                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1009                 cnt &= ~ICH_SIS_PCM_246_MASK;
1010                 if (runtime->channels == 4 || dbl)
1011                         cnt |= ICH_SIS_PCM_4;
1012                 else if (runtime->channels == 6)
1013                         cnt |= ICH_SIS_PCM_6;
1014                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1015                 break;
1016         default:
1017                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1018                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1019                 if (runtime->channels == 4 || dbl)
1020                         cnt |= ICH_PCM_4;
1021                 else if (runtime->channels == 6)
1022                         cnt |= ICH_PCM_6;
1023                 if (chip->device_type == DEVICE_NFORCE) {
1024                         /* reset to 2ch once to keep the 6 channel data in alignment,
1025                          * to start from Front Left always
1026                          */
1027                         if (cnt & ICH_PCM_246_MASK) {
1028                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1029                                 spin_unlock_irq(&chip->reg_lock);
1030                                 msleep(50); /* grrr... */
1031                                 spin_lock_irq(&chip->reg_lock);
1032                         }
1033                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1034                         if (runtime->sample_bits > 16)
1035                                 cnt |= ICH_PCM_20BIT;
1036                 }
1037                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1038                 break;
1039         }
1040         spin_unlock_irq(&chip->reg_lock);
1041 }
1042
1043 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1044 {
1045         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1046         struct snd_pcm_runtime *runtime = substream->runtime;
1047         struct ichdev *ichdev = get_ichdev(substream);
1048
1049         ichdev->physbuf = runtime->dma_addr;
1050         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1051         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1052         if (ichdev->ichd == ICHD_PCMOUT) {
1053                 snd_intel8x0_setup_pcm_out(chip, runtime);
1054                 if (chip->device_type == DEVICE_INTEL_ICH4)
1055                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1056         }
1057         snd_intel8x0_setup_periods(chip, ichdev);
1058         return 0;
1059 }
1060
1061 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1062 {
1063         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1064         struct ichdev *ichdev = get_ichdev(substream);
1065         size_t ptr1, ptr;
1066         int civ, timeout = 100;
1067         unsigned int position;
1068
1069         spin_lock(&chip->reg_lock);
1070         do {
1071                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1072                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1073                 position = ichdev->position;
1074                 if (ptr1 == 0) {
1075                         udelay(10);
1076                         continue;
1077                 }
1078                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1079                     ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1080                         break;
1081         } while (timeout--);
1082         ptr1 <<= ichdev->pos_shift;
1083         ptr = ichdev->fragsize1 - ptr1;
1084         ptr += position;
1085         spin_unlock(&chip->reg_lock);
1086         if (ptr >= ichdev->size)
1087                 return 0;
1088         return bytes_to_frames(substream->runtime, ptr);
1089 }
1090
1091 static struct snd_pcm_hardware snd_intel8x0_stream =
1092 {
1093         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1094                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1095                                  SNDRV_PCM_INFO_MMAP_VALID |
1096                                  SNDRV_PCM_INFO_PAUSE |
1097                                  SNDRV_PCM_INFO_RESUME),
1098         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1099         .rates =                SNDRV_PCM_RATE_48000,
1100         .rate_min =             48000,
1101         .rate_max =             48000,
1102         .channels_min =         2,
1103         .channels_max =         2,
1104         .buffer_bytes_max =     128 * 1024,
1105         .period_bytes_min =     32,
1106         .period_bytes_max =     128 * 1024,
1107         .periods_min =          1,
1108         .periods_max =          1024,
1109         .fifo_size =            0,
1110 };
1111
1112 static unsigned int channels4[] = {
1113         2, 4,
1114 };
1115
1116 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1117         .count = ARRAY_SIZE(channels4),
1118         .list = channels4,
1119         .mask = 0,
1120 };
1121
1122 static unsigned int channels6[] = {
1123         2, 4, 6,
1124 };
1125
1126 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1127         .count = ARRAY_SIZE(channels6),
1128         .list = channels6,
1129         .mask = 0,
1130 };
1131
1132 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1133 {
1134         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1135         struct snd_pcm_runtime *runtime = substream->runtime;
1136         int err;
1137
1138         ichdev->substream = substream;
1139         runtime->hw = snd_intel8x0_stream;
1140         runtime->hw.rates = ichdev->pcm->rates;
1141         snd_pcm_limit_hw_rates(runtime);
1142         if (chip->device_type == DEVICE_SIS) {
1143                 runtime->hw.buffer_bytes_max = 64*1024;
1144                 runtime->hw.period_bytes_max = 64*1024;
1145         }
1146         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1147                 return err;
1148         runtime->private_data = ichdev;
1149         return 0;
1150 }
1151
1152 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1153 {
1154         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1155         struct snd_pcm_runtime *runtime = substream->runtime;
1156         int err;
1157
1158         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1159         if (err < 0)
1160                 return err;
1161
1162         if (chip->multi6) {
1163                 runtime->hw.channels_max = 6;
1164                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1165                                            &hw_constraints_channels6);
1166         } else if (chip->multi4) {
1167                 runtime->hw.channels_max = 4;
1168                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1169                                            &hw_constraints_channels4);
1170         }
1171         if (chip->dra) {
1172                 snd_ac97_pcm_double_rate_rules(runtime);
1173         }
1174         if (chip->smp20bit) {
1175                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1176                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1177         }
1178         return 0;
1179 }
1180
1181 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1182 {
1183         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1184
1185         chip->ichd[ICHD_PCMOUT].substream = NULL;
1186         return 0;
1187 }
1188
1189 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1190 {
1191         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1192
1193         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1194 }
1195
1196 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1197 {
1198         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1199
1200         chip->ichd[ICHD_PCMIN].substream = NULL;
1201         return 0;
1202 }
1203
1204 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1205 {
1206         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1207
1208         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1209 }
1210
1211 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1212 {
1213         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1214
1215         chip->ichd[ICHD_MIC].substream = NULL;
1216         return 0;
1217 }
1218
1219 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1220 {
1221         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1222
1223         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1224 }
1225
1226 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1227 {
1228         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1229
1230         chip->ichd[ICHD_MIC2].substream = NULL;
1231         return 0;
1232 }
1233
1234 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1235 {
1236         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1237
1238         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1239 }
1240
1241 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1242 {
1243         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1244
1245         chip->ichd[ICHD_PCM2IN].substream = NULL;
1246         return 0;
1247 }
1248
1249 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1250 {
1251         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1252         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1253
1254         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1255 }
1256
1257 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1258 {
1259         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1260         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1261
1262         chip->ichd[idx].substream = NULL;
1263         return 0;
1264 }
1265
1266 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1267 {
1268         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1269         unsigned int val;
1270
1271         spin_lock_irq(&chip->reg_lock);
1272         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1273         val |= ICH_ALI_IF_AC97SP;
1274         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1275         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1276         spin_unlock_irq(&chip->reg_lock);
1277
1278         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1279 }
1280
1281 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1282 {
1283         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1284         unsigned int val;
1285
1286         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1287         spin_lock_irq(&chip->reg_lock);
1288         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1289         val &= ~ICH_ALI_IF_AC97SP;
1290         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1291         spin_unlock_irq(&chip->reg_lock);
1292
1293         return 0;
1294 }
1295
1296 #if 0 // NYI
1297 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1298 {
1299         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1300
1301         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1302 }
1303
1304 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1305 {
1306         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1307
1308         chip->ichd[ALID_SPDIFIN].substream = NULL;
1309         return 0;
1310 }
1311
1312 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1313 {
1314         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1315
1316         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1317 }
1318
1319 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1320 {
1321         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1322
1323         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1324         return 0;
1325 }
1326 #endif
1327
1328 static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1329         .open =         snd_intel8x0_playback_open,
1330         .close =        snd_intel8x0_playback_close,
1331         .ioctl =        snd_pcm_lib_ioctl,
1332         .hw_params =    snd_intel8x0_hw_params,
1333         .hw_free =      snd_intel8x0_hw_free,
1334         .prepare =      snd_intel8x0_pcm_prepare,
1335         .trigger =      snd_intel8x0_pcm_trigger,
1336         .pointer =      snd_intel8x0_pcm_pointer,
1337 };
1338
1339 static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1340         .open =         snd_intel8x0_capture_open,
1341         .close =        snd_intel8x0_capture_close,
1342         .ioctl =        snd_pcm_lib_ioctl,
1343         .hw_params =    snd_intel8x0_hw_params,
1344         .hw_free =      snd_intel8x0_hw_free,
1345         .prepare =      snd_intel8x0_pcm_prepare,
1346         .trigger =      snd_intel8x0_pcm_trigger,
1347         .pointer =      snd_intel8x0_pcm_pointer,
1348 };
1349
1350 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1351         .open =         snd_intel8x0_mic_open,
1352         .close =        snd_intel8x0_mic_close,
1353         .ioctl =        snd_pcm_lib_ioctl,
1354         .hw_params =    snd_intel8x0_hw_params,
1355         .hw_free =      snd_intel8x0_hw_free,
1356         .prepare =      snd_intel8x0_pcm_prepare,
1357         .trigger =      snd_intel8x0_pcm_trigger,
1358         .pointer =      snd_intel8x0_pcm_pointer,
1359 };
1360
1361 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1362         .open =         snd_intel8x0_mic2_open,
1363         .close =        snd_intel8x0_mic2_close,
1364         .ioctl =        snd_pcm_lib_ioctl,
1365         .hw_params =    snd_intel8x0_hw_params,
1366         .hw_free =      snd_intel8x0_hw_free,
1367         .prepare =      snd_intel8x0_pcm_prepare,
1368         .trigger =      snd_intel8x0_pcm_trigger,
1369         .pointer =      snd_intel8x0_pcm_pointer,
1370 };
1371
1372 static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1373         .open =         snd_intel8x0_capture2_open,
1374         .close =        snd_intel8x0_capture2_close,
1375         .ioctl =        snd_pcm_lib_ioctl,
1376         .hw_params =    snd_intel8x0_hw_params,
1377         .hw_free =      snd_intel8x0_hw_free,
1378         .prepare =      snd_intel8x0_pcm_prepare,
1379         .trigger =      snd_intel8x0_pcm_trigger,
1380         .pointer =      snd_intel8x0_pcm_pointer,
1381 };
1382
1383 static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1384         .open =         snd_intel8x0_spdif_open,
1385         .close =        snd_intel8x0_spdif_close,
1386         .ioctl =        snd_pcm_lib_ioctl,
1387         .hw_params =    snd_intel8x0_hw_params,
1388         .hw_free =      snd_intel8x0_hw_free,
1389         .prepare =      snd_intel8x0_pcm_prepare,
1390         .trigger =      snd_intel8x0_pcm_trigger,
1391         .pointer =      snd_intel8x0_pcm_pointer,
1392 };
1393
1394 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1395         .open =         snd_intel8x0_playback_open,
1396         .close =        snd_intel8x0_playback_close,
1397         .ioctl =        snd_pcm_lib_ioctl,
1398         .hw_params =    snd_intel8x0_hw_params,
1399         .hw_free =      snd_intel8x0_hw_free,
1400         .prepare =      snd_intel8x0_pcm_prepare,
1401         .trigger =      snd_intel8x0_ali_trigger,
1402         .pointer =      snd_intel8x0_pcm_pointer,
1403 };
1404
1405 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1406         .open =         snd_intel8x0_capture_open,
1407         .close =        snd_intel8x0_capture_close,
1408         .ioctl =        snd_pcm_lib_ioctl,
1409         .hw_params =    snd_intel8x0_hw_params,
1410         .hw_free =      snd_intel8x0_hw_free,
1411         .prepare =      snd_intel8x0_pcm_prepare,
1412         .trigger =      snd_intel8x0_ali_trigger,
1413         .pointer =      snd_intel8x0_pcm_pointer,
1414 };
1415
1416 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1417         .open =         snd_intel8x0_mic_open,
1418         .close =        snd_intel8x0_mic_close,
1419         .ioctl =        snd_pcm_lib_ioctl,
1420         .hw_params =    snd_intel8x0_hw_params,
1421         .hw_free =      snd_intel8x0_hw_free,
1422         .prepare =      snd_intel8x0_pcm_prepare,
1423         .trigger =      snd_intel8x0_ali_trigger,
1424         .pointer =      snd_intel8x0_pcm_pointer,
1425 };
1426
1427 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1428         .open =         snd_intel8x0_ali_ac97spdifout_open,
1429         .close =        snd_intel8x0_ali_ac97spdifout_close,
1430         .ioctl =        snd_pcm_lib_ioctl,
1431         .hw_params =    snd_intel8x0_hw_params,
1432         .hw_free =      snd_intel8x0_hw_free,
1433         .prepare =      snd_intel8x0_pcm_prepare,
1434         .trigger =      snd_intel8x0_ali_trigger,
1435         .pointer =      snd_intel8x0_pcm_pointer,
1436 };
1437
1438 #if 0 // NYI
1439 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1440         .open =         snd_intel8x0_ali_spdifin_open,
1441         .close =        snd_intel8x0_ali_spdifin_close,
1442         .ioctl =        snd_pcm_lib_ioctl,
1443         .hw_params =    snd_intel8x0_hw_params,
1444         .hw_free =      snd_intel8x0_hw_free,
1445         .prepare =      snd_intel8x0_pcm_prepare,
1446         .trigger =      snd_intel8x0_pcm_trigger,
1447         .pointer =      snd_intel8x0_pcm_pointer,
1448 };
1449
1450 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1451         .open =         snd_intel8x0_ali_spdifout_open,
1452         .close =        snd_intel8x0_ali_spdifout_close,
1453         .ioctl =        snd_pcm_lib_ioctl,
1454         .hw_params =    snd_intel8x0_hw_params,
1455         .hw_free =      snd_intel8x0_hw_free,
1456         .prepare =      snd_intel8x0_pcm_prepare,
1457         .trigger =      snd_intel8x0_pcm_trigger,
1458         .pointer =      snd_intel8x0_pcm_pointer,
1459 };
1460 #endif // NYI
1461
1462 struct ich_pcm_table {
1463         char *suffix;
1464         struct snd_pcm_ops *playback_ops;
1465         struct snd_pcm_ops *capture_ops;
1466         size_t prealloc_size;
1467         size_t prealloc_max_size;
1468         int ac97_idx;
1469 };
1470
1471 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1472                                        struct ich_pcm_table *rec)
1473 {
1474         struct snd_pcm *pcm;
1475         int err;
1476         char name[32];
1477
1478         if (rec->suffix)
1479                 sprintf(name, "Intel ICH - %s", rec->suffix);
1480         else
1481                 strcpy(name, "Intel ICH");
1482         err = snd_pcm_new(chip->card, name, device,
1483                           rec->playback_ops ? 1 : 0,
1484                           rec->capture_ops ? 1 : 0, &pcm);
1485         if (err < 0)
1486                 return err;
1487
1488         if (rec->playback_ops)
1489                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1490         if (rec->capture_ops)
1491                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1492
1493         pcm->private_data = chip;
1494         pcm->info_flags = 0;
1495         if (rec->suffix)
1496                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1497         else
1498                 strcpy(pcm->name, chip->card->shortname);
1499         chip->pcm[device] = pcm;
1500
1501         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1502                                               snd_dma_pci_data(chip->pci),
1503                                               rec->prealloc_size, rec->prealloc_max_size);
1504
1505         return 0;
1506 }
1507
1508 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1509         {
1510                 .playback_ops = &snd_intel8x0_playback_ops,
1511                 .capture_ops = &snd_intel8x0_capture_ops,
1512                 .prealloc_size = 64 * 1024,
1513                 .prealloc_max_size = 128 * 1024,
1514         },
1515         {
1516                 .suffix = "MIC ADC",
1517                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1518                 .prealloc_size = 0,
1519                 .prealloc_max_size = 128 * 1024,
1520                 .ac97_idx = ICHD_MIC,
1521         },
1522         {
1523                 .suffix = "MIC2 ADC",
1524                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1525                 .prealloc_size = 0,
1526                 .prealloc_max_size = 128 * 1024,
1527                 .ac97_idx = ICHD_MIC2,
1528         },
1529         {
1530                 .suffix = "ADC2",
1531                 .capture_ops = &snd_intel8x0_capture2_ops,
1532                 .prealloc_size = 0,
1533                 .prealloc_max_size = 128 * 1024,
1534                 .ac97_idx = ICHD_PCM2IN,
1535         },
1536         {
1537                 .suffix = "IEC958",
1538                 .playback_ops = &snd_intel8x0_spdif_ops,
1539                 .prealloc_size = 64 * 1024,
1540                 .prealloc_max_size = 128 * 1024,
1541                 .ac97_idx = ICHD_SPBAR,
1542         },
1543 };
1544
1545 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1546         {
1547                 .playback_ops = &snd_intel8x0_playback_ops,
1548                 .capture_ops = &snd_intel8x0_capture_ops,
1549                 .prealloc_size = 64 * 1024,
1550                 .prealloc_max_size = 128 * 1024,
1551         },
1552         {
1553                 .suffix = "MIC ADC",
1554                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1555                 .prealloc_size = 0,
1556                 .prealloc_max_size = 128 * 1024,
1557                 .ac97_idx = NVD_MIC,
1558         },
1559         {
1560                 .suffix = "IEC958",
1561                 .playback_ops = &snd_intel8x0_spdif_ops,
1562                 .prealloc_size = 64 * 1024,
1563                 .prealloc_max_size = 128 * 1024,
1564                 .ac97_idx = NVD_SPBAR,
1565         },
1566 };
1567
1568 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1569         {
1570                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1571                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1572                 .prealloc_size = 64 * 1024,
1573                 .prealloc_max_size = 128 * 1024,
1574         },
1575         {
1576                 .suffix = "MIC ADC",
1577                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1578                 .prealloc_size = 0,
1579                 .prealloc_max_size = 128 * 1024,
1580                 .ac97_idx = ALID_MIC,
1581         },
1582         {
1583                 .suffix = "IEC958",
1584                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1585                 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1586                 .prealloc_size = 64 * 1024,
1587                 .prealloc_max_size = 128 * 1024,
1588                 .ac97_idx = ALID_AC97SPDIFOUT,
1589         },
1590 #if 0 // NYI
1591         {
1592                 .suffix = "HW IEC958",
1593                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1594                 .prealloc_size = 64 * 1024,
1595                 .prealloc_max_size = 128 * 1024,
1596         },
1597 #endif
1598 };
1599
1600 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1601 {
1602         int i, tblsize, device, err;
1603         struct ich_pcm_table *tbl, *rec;
1604
1605         switch (chip->device_type) {
1606         case DEVICE_INTEL_ICH4:
1607                 tbl = intel_pcms;
1608                 tblsize = ARRAY_SIZE(intel_pcms);
1609                 break;
1610         case DEVICE_NFORCE:
1611                 tbl = nforce_pcms;
1612                 tblsize = ARRAY_SIZE(nforce_pcms);
1613                 break;
1614         case DEVICE_ALI:
1615                 tbl = ali_pcms;
1616                 tblsize = ARRAY_SIZE(ali_pcms);
1617                 break;
1618         default:
1619                 tbl = intel_pcms;
1620                 tblsize = 2;
1621                 break;
1622         }
1623
1624         device = 0;
1625         for (i = 0; i < tblsize; i++) {
1626                 rec = tbl + i;
1627                 if (i > 0 && rec->ac97_idx) {
1628                         /* activate PCM only when associated AC'97 codec */
1629                         if (! chip->ichd[rec->ac97_idx].pcm)
1630                                 continue;
1631                 }
1632                 err = snd_intel8x0_pcm1(chip, device, rec);
1633                 if (err < 0)
1634                         return err;
1635                 device++;
1636         }
1637
1638         chip->pcm_devs = device;
1639         return 0;
1640 }
1641         
1642
1643 /*
1644  *  Mixer part
1645  */
1646
1647 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1648 {
1649         struct intel8x0 *chip = bus->private_data;
1650         chip->ac97_bus = NULL;
1651 }
1652
1653 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1654 {
1655         struct intel8x0 *chip = ac97->private_data;
1656         chip->ac97[ac97->num] = NULL;
1657 }
1658
1659 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1660         /* front PCM */
1661         {
1662                 .exclusive = 1,
1663                 .r = {  {
1664                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1665                                          (1 << AC97_SLOT_PCM_RIGHT) |
1666                                          (1 << AC97_SLOT_PCM_CENTER) |
1667                                          (1 << AC97_SLOT_PCM_SLEFT) |
1668                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1669                                          (1 << AC97_SLOT_LFE)
1670                         },
1671                         {
1672                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1673                                          (1 << AC97_SLOT_PCM_RIGHT) |
1674                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1675                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1676                         }
1677                 }
1678         },
1679         /* PCM IN #1 */
1680         {
1681                 .stream = 1,
1682                 .exclusive = 1,
1683                 .r = {  {
1684                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1685                                          (1 << AC97_SLOT_PCM_RIGHT)
1686                         }
1687                 }
1688         },
1689         /* MIC IN #1 */
1690         {
1691                 .stream = 1,
1692                 .exclusive = 1,
1693                 .r = {  {
1694                                 .slots = (1 << AC97_SLOT_MIC)
1695                         }
1696                 }
1697         },
1698         /* S/PDIF PCM */
1699         {
1700                 .exclusive = 1,
1701                 .spdif = 1,
1702                 .r = {  {
1703                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1704                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1705                         }
1706                 }
1707         },
1708         /* PCM IN #2 */
1709         {
1710                 .stream = 1,
1711                 .exclusive = 1,
1712                 .r = {  {
1713                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1714                                          (1 << AC97_SLOT_PCM_RIGHT)
1715                         }
1716                 }
1717         },
1718         /* MIC IN #2 */
1719         {
1720                 .stream = 1,
1721                 .exclusive = 1,
1722                 .r = {  {
1723                                 .slots = (1 << AC97_SLOT_MIC)
1724                         }
1725                 }
1726         },
1727 };
1728
1729 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1730         {
1731                 .subvendor = 0x0e11,
1732                 .subdevice = 0x008a,
1733                 .name = "Compaq Evo W4000",     /* AD1885 */
1734                 .type = AC97_TUNE_HP_ONLY
1735         },
1736         {
1737                 .subvendor = 0x0e11,
1738                 .subdevice = 0x00b8,
1739                 .name = "Compaq Evo D510C",
1740                 .type = AC97_TUNE_HP_ONLY
1741         },
1742         {
1743                 .subvendor = 0x0e11,
1744                 .subdevice = 0x0860,
1745                 .name = "HP/Compaq nx7010",
1746                 .type = AC97_TUNE_MUTE_LED
1747         },
1748         {
1749                 .subvendor = 0x1014,
1750                 .subdevice = 0x1f00,
1751                 .name = "MS-9128",
1752                 .type = AC97_TUNE_ALC_JACK
1753         },
1754         {
1755                 .subvendor = 0x1014,
1756                 .subdevice = 0x0267,
1757                 .name = "IBM NetVista A30p",    /* AD1981B */
1758                 .type = AC97_TUNE_HP_ONLY
1759         },
1760         {
1761                 .subvendor = 0x1025,
1762                 .subdevice = 0x0083,
1763                 .name = "Acer Aspire 3003LCi",
1764                 .type = AC97_TUNE_HP_ONLY
1765         },
1766         {
1767                 .subvendor = 0x1028,
1768                 .subdevice = 0x00d8,
1769                 .name = "Dell Precision 530",   /* AD1885 */
1770                 .type = AC97_TUNE_HP_ONLY
1771         },
1772         {
1773                 .subvendor = 0x1028,
1774                 .subdevice = 0x010d,
1775                 .name = "Dell", /* which model?  AD1885 */
1776                 .type = AC97_TUNE_HP_ONLY
1777         },
1778         {
1779                 .subvendor = 0x1028,
1780                 .subdevice = 0x0126,
1781                 .name = "Dell Optiplex GX260",  /* AD1981A */
1782                 .type = AC97_TUNE_HP_ONLY
1783         },
1784         {
1785                 .subvendor = 0x1028,
1786                 .subdevice = 0x012c,
1787                 .name = "Dell Precision 650",   /* AD1981A */
1788                 .type = AC97_TUNE_HP_ONLY
1789         },
1790         {
1791                 .subvendor = 0x1028,
1792                 .subdevice = 0x012d,
1793                 .name = "Dell Precision 450",   /* AD1981B*/
1794                 .type = AC97_TUNE_HP_ONLY
1795         },
1796         {
1797                 .subvendor = 0x1028,
1798                 .subdevice = 0x0147,
1799                 .name = "Dell", /* which model?  AD1981B*/
1800                 .type = AC97_TUNE_HP_ONLY
1801         },
1802         {
1803                 .subvendor = 0x1028,
1804                 .subdevice = 0x0151,
1805                 .name = "Dell Optiplex GX270",  /* AD1981B */
1806                 .type = AC97_TUNE_HP_ONLY
1807         },
1808         {
1809                 .subvendor = 0x1028,
1810                 .subdevice = 0x014e,
1811                 .name = "Dell D800", /* STAC9750/51 */
1812                 .type = AC97_TUNE_HP_ONLY
1813         },
1814         {
1815                 .subvendor = 0x1028,
1816                 .subdevice = 0x0163,
1817                 .name = "Dell Unknown", /* STAC9750/51 */
1818                 .type = AC97_TUNE_HP_ONLY
1819         },
1820         {
1821                 .subvendor = 0x1028,
1822                 .subdevice = 0x0191,
1823                 .name = "Dell Inspiron 8600",
1824                 .type = AC97_TUNE_HP_ONLY
1825         },
1826         {
1827                 .subvendor = 0x103c,
1828                 .subdevice = 0x006d,
1829                 .name = "HP zv5000",
1830                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1831         },
1832         {       /* FIXME: which codec? */
1833                 .subvendor = 0x103c,
1834                 .subdevice = 0x00c3,
1835                 .name = "HP xw6000",
1836                 .type = AC97_TUNE_HP_ONLY
1837         },
1838         {
1839                 .subvendor = 0x103c,
1840                 .subdevice = 0x088c,
1841                 .name = "HP nc8000",
1842                 .type = AC97_TUNE_MUTE_LED
1843         },
1844         {
1845                 .subvendor = 0x103c,
1846                 .subdevice = 0x0890,
1847                 .name = "HP nc6000",
1848                 .type = AC97_TUNE_MUTE_LED
1849         },
1850         {
1851                 .subvendor = 0x103c,
1852                 .subdevice = 0x0934,
1853                 .name = "HP nx8220",
1854                 .type = AC97_TUNE_MUTE_LED
1855         },
1856         {
1857                 .subvendor = 0x103c,
1858                 .subdevice = 0x129d,
1859                 .name = "HP xw8000",
1860                 .type = AC97_TUNE_HP_ONLY
1861         },
1862         {
1863                 .subvendor = 0x103c,
1864                 .subdevice = 0x0938,
1865                 .name = "HP nc4200",
1866                 .type = AC97_TUNE_HP_MUTE_LED
1867         },
1868         {
1869                 .subvendor = 0x103c,
1870                 .subdevice = 0x099c,
1871                 .name = "HP nx6110/nc6120",
1872                 .type = AC97_TUNE_HP_MUTE_LED
1873         },
1874         {
1875                 .subvendor = 0x103c,
1876                 .subdevice = 0x0944,
1877                 .name = "HP nc6220",
1878                 .type = AC97_TUNE_HP_MUTE_LED
1879         },
1880         {
1881                 .subvendor = 0x103c,
1882                 .subdevice = 0x0934,
1883                 .name = "HP nc8220",
1884                 .type = AC97_TUNE_HP_MUTE_LED
1885         },
1886         {
1887                 .subvendor = 0x103c,
1888                 .subdevice = 0x12f1,
1889                 .name = "HP xw8200",    /* AD1981B*/
1890                 .type = AC97_TUNE_HP_ONLY
1891         },
1892         {
1893                 .subvendor = 0x103c,
1894                 .subdevice = 0x12f2,
1895                 .name = "HP xw6200",
1896                 .type = AC97_TUNE_HP_ONLY
1897         },
1898         {
1899                 .subvendor = 0x103c,
1900                 .subdevice = 0x3008,
1901                 .name = "HP xw4200",    /* AD1981B*/
1902                 .type = AC97_TUNE_HP_ONLY
1903         },
1904         {
1905                 .subvendor = 0x104d,
1906                 .subdevice = 0x8197,
1907                 .name = "Sony S1XP",
1908                 .type = AC97_TUNE_INV_EAPD
1909         },
1910         {
1911                 .subvendor = 0x1043,
1912                 .subdevice = 0x80f3,
1913                 .name = "ASUS ICH5/AD1985",
1914                 .type = AC97_TUNE_AD_SHARING
1915         },
1916         {
1917                 .subvendor = 0x10cf,
1918                 .subdevice = 0x11c3,
1919                 .name = "Fujitsu-Siemens E4010",
1920                 .type = AC97_TUNE_HP_ONLY
1921         },
1922         {
1923                 .subvendor = 0x10cf,
1924                 .subdevice = 0x1225,
1925                 .name = "Fujitsu-Siemens T3010",
1926                 .type = AC97_TUNE_HP_ONLY
1927         },
1928         {
1929                 .subvendor = 0x10cf,
1930                 .subdevice = 0x1253,
1931                 .name = "Fujitsu S6210",        /* STAC9750/51 */
1932                 .type = AC97_TUNE_HP_ONLY
1933         },
1934         {
1935                 .subvendor = 0x10cf,
1936                 .subdevice = 0x12ec,
1937                 .name = "Fujitsu-Siemens 4010",
1938                 .type = AC97_TUNE_HP_ONLY
1939         },
1940         {
1941                 .subvendor = 0x10cf,
1942                 .subdevice = 0x12f2,
1943                 .name = "Fujitsu-Siemens Celsius H320",
1944                 .type = AC97_TUNE_SWAP_HP
1945         },
1946         {
1947                 .subvendor = 0x10f1,
1948                 .subdevice = 0x2665,
1949                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
1950                 .type = AC97_TUNE_HP_ONLY
1951         },
1952         {
1953                 .subvendor = 0x10f1,
1954                 .subdevice = 0x2885,
1955                 .name = "AMD64 Mobo",   /* ALC650 */
1956                 .type = AC97_TUNE_HP_ONLY
1957         },
1958         {
1959                 .subvendor = 0x10f1,
1960                 .subdevice = 0x2895,
1961                 .name = "Tyan Thunder K8WE",
1962                 .type = AC97_TUNE_HP_ONLY
1963         },
1964         {
1965                 .subvendor = 0x110a,
1966                 .subdevice = 0x0056,
1967                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
1968                 .type = AC97_TUNE_HP_ONLY
1969         },
1970         {
1971                 .subvendor = 0x11d4,
1972                 .subdevice = 0x5375,
1973                 .name = "ADI AD1985 (discrete)",
1974                 .type = AC97_TUNE_HP_ONLY
1975         },
1976         {
1977                 .subvendor = 0x1462,
1978                 .subdevice = 0x5470,
1979                 .name = "MSI P4 ATX 645 Ultra",
1980                 .type = AC97_TUNE_HP_ONLY
1981         },
1982         {
1983                 .subvendor = 0x1734,
1984                 .subdevice = 0x0088,
1985                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
1986                 .type = AC97_TUNE_HP_ONLY
1987         },
1988         {
1989                 .subvendor = 0x8086,
1990                 .subdevice = 0x2000,
1991                 .mask = 0xfff0,
1992                 .name = "Intel ICH5/AD1985",
1993                 .type = AC97_TUNE_AD_SHARING
1994         },
1995         {
1996                 .subvendor = 0x8086,
1997                 .subdevice = 0x4000,
1998                 .mask = 0xfff0,
1999                 .name = "Intel ICH5/AD1985",
2000                 .type = AC97_TUNE_AD_SHARING
2001         },
2002         {
2003                 .subvendor = 0x8086,
2004                 .subdevice = 0x4856,
2005                 .name = "Intel D845WN (82801BA)",
2006                 .type = AC97_TUNE_SWAP_HP
2007         },
2008         {
2009                 .subvendor = 0x8086,
2010                 .subdevice = 0x4d44,
2011                 .name = "Intel D850EMV2",       /* AD1885 */
2012                 .type = AC97_TUNE_HP_ONLY
2013         },
2014         {
2015                 .subvendor = 0x8086,
2016                 .subdevice = 0x4d56,
2017                 .name = "Intel ICH/AD1885",
2018                 .type = AC97_TUNE_HP_ONLY
2019         },
2020         {
2021                 .subvendor = 0x8086,
2022                 .subdevice = 0x6000,
2023                 .mask = 0xfff0,
2024                 .name = "Intel ICH5/AD1985",
2025                 .type = AC97_TUNE_AD_SHARING
2026         },
2027         {
2028                 .subvendor = 0x8086,
2029                 .subdevice = 0xe000,
2030                 .mask = 0xfff0,
2031                 .name = "Intel ICH5/AD1985",
2032                 .type = AC97_TUNE_AD_SHARING
2033         },
2034 #if 0 /* FIXME: this seems wrong on most boards */
2035         {
2036                 .subvendor = 0x8086,
2037                 .subdevice = 0xa000,
2038                 .mask = 0xfff0,
2039                 .name = "Intel ICH5/AD1985",
2040                 .type = AC97_TUNE_HP_ONLY
2041         },
2042 #endif
2043         { } /* terminator */
2044 };
2045
2046 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2047                                         const char *quirk_override)
2048 {
2049         struct snd_ac97_bus *pbus;
2050         struct snd_ac97_template ac97;
2051         int err;
2052         unsigned int i, codecs;
2053         unsigned int glob_sta = 0;
2054         struct snd_ac97_bus_ops *ops;
2055         static struct snd_ac97_bus_ops standard_bus_ops = {
2056                 .write = snd_intel8x0_codec_write,
2057                 .read = snd_intel8x0_codec_read,
2058         };
2059         static struct snd_ac97_bus_ops ali_bus_ops = {
2060                 .write = snd_intel8x0_ali_codec_write,
2061                 .read = snd_intel8x0_ali_codec_read,
2062         };
2063
2064         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2065         switch (chip->device_type) {
2066         case DEVICE_NFORCE:
2067                 chip->spdif_idx = NVD_SPBAR;
2068                 break;
2069         case DEVICE_ALI:
2070                 chip->spdif_idx = ALID_AC97SPDIFOUT;
2071                 break;
2072         case DEVICE_INTEL_ICH4:
2073                 chip->spdif_idx = ICHD_SPBAR;
2074                 break;
2075         };
2076
2077         chip->in_ac97_init = 1;
2078         
2079         memset(&ac97, 0, sizeof(ac97));
2080         ac97.private_data = chip;
2081         ac97.private_free = snd_intel8x0_mixer_free_ac97;
2082         ac97.scaps = AC97_SCAP_SKIP_MODEM;
2083         if (chip->xbox)
2084                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2085         if (chip->device_type != DEVICE_ALI) {
2086                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2087                 ops = &standard_bus_ops;
2088                 chip->in_sdin_init = 1;
2089                 codecs = 0;
2090                 for (i = 0; i < chip->max_codecs; i++) {
2091                         if (! (glob_sta & chip->codec_bit[i]))
2092                                 continue;
2093                         if (chip->device_type == DEVICE_INTEL_ICH4) {
2094                                 snd_intel8x0_codec_read_test(chip, codecs);
2095                                 chip->ac97_sdin[codecs] =
2096                                         igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2097                                 snd_assert(chip->ac97_sdin[codecs] < 3,
2098                                            chip->ac97_sdin[codecs] = 0);
2099                         } else
2100                                 chip->ac97_sdin[codecs] = i;
2101                         codecs++;
2102                 }
2103                 chip->in_sdin_init = 0;
2104                 if (! codecs)
2105                         codecs = 1;
2106         } else {
2107                 ops = &ali_bus_ops;
2108                 codecs = 1;
2109                 /* detect the secondary codec */
2110                 for (i = 0; i < 100; i++) {
2111                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2112                         if (reg & 0x40) {
2113                                 codecs = 2;
2114                                 break;
2115                         }
2116                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2117                         udelay(1);
2118                 }
2119         }
2120         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2121                 goto __err;
2122         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2123         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2124                 pbus->clock = ac97_clock;
2125         /* FIXME: my test board doesn't work well with VRA... */
2126         if (chip->device_type == DEVICE_ALI)
2127                 pbus->no_vra = 1;
2128         else
2129                 pbus->dra = 1;
2130         chip->ac97_bus = pbus;
2131         chip->ncodecs = codecs;
2132
2133         ac97.pci = chip->pci;
2134         for (i = 0; i < codecs; i++) {
2135                 ac97.num = i;
2136                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2137                         if (err != -EACCES)
2138                                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2139                         if (i == 0)
2140                                 goto __err;
2141                         continue;
2142                 }
2143         }
2144         /* tune up the primary codec */
2145         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2146         /* enable separate SDINs for ICH4 */
2147         if (chip->device_type == DEVICE_INTEL_ICH4)
2148                 pbus->isdin = 1;
2149         /* find the available PCM streams */
2150         i = ARRAY_SIZE(ac97_pcm_defs);
2151         if (chip->device_type != DEVICE_INTEL_ICH4)
2152                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2153         if (chip->spdif_idx < 0)
2154                 i--;            /* do not allocate S/PDIF */
2155         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2156         if (err < 0)
2157                 goto __err;
2158         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2159         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2160         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2161         if (chip->spdif_idx >= 0)
2162                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2163         if (chip->device_type == DEVICE_INTEL_ICH4) {
2164                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2165                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2166         }
2167         /* enable separate SDINs for ICH4 */
2168         if (chip->device_type == DEVICE_INTEL_ICH4) {
2169                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2170                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2171                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2172                 if (pcm) {
2173                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2174                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2175                         for (i = 1; i < 4; i++) {
2176                                 if (pcm->r[0].codec[i]) {
2177                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2178                                         break;
2179                                 }
2180                         }
2181                 } else {
2182                         tmp &= ~ICH_SE; /* steer disable */
2183                 }
2184                 iputbyte(chip, ICHREG(SDM), tmp);
2185         }
2186         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2187                 chip->multi4 = 1;
2188                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2189                         chip->multi6 = 1;
2190         }
2191         if (pbus->pcms[0].r[1].rslots[0]) {
2192                 chip->dra = 1;
2193         }
2194         if (chip->device_type == DEVICE_INTEL_ICH4) {
2195                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2196                         chip->smp20bit = 1;
2197         }
2198         if (chip->device_type == DEVICE_NFORCE) {
2199                 /* 48kHz only */
2200                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2201         }
2202         if (chip->device_type == DEVICE_INTEL_ICH4) {
2203                 /* use slot 10/11 for SPDIF */
2204                 u32 val;
2205                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2206                 val |= ICH_PCM_SPDIF_1011;
2207                 iputdword(chip, ICHREG(GLOB_CNT), val);
2208                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2209         }
2210         chip->in_ac97_init = 0;
2211         return 0;
2212
2213  __err:
2214         /* clear the cold-reset bit for the next chance */
2215         if (chip->device_type != DEVICE_ALI)
2216                 iputdword(chip, ICHREG(GLOB_CNT),
2217                           igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2218         return err;
2219 }
2220
2221
2222 /*
2223  *
2224  */
2225
2226 static void do_ali_reset(struct intel8x0 *chip)
2227 {
2228         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2229         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2230         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2231         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2232         iputdword(chip, ICHREG(ALI_INTERFACECR),
2233                   ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2234         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2235         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2236 }
2237
2238 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2239 {
2240         unsigned long end_time;
2241         unsigned int cnt, status, nstatus;
2242         
2243         /* put logic to right state */
2244         /* first clear status bits */
2245         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2246         if (chip->device_type == DEVICE_NFORCE)
2247                 status |= ICH_NVSPINT;
2248         cnt = igetdword(chip, ICHREG(GLOB_STA));
2249         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2250
2251         /* ACLink on, 2 channels */
2252         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2253         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2254 #ifdef CONFIG_SND_AC97_POWER_SAVE
2255         /* do cold reset - the full ac97 powerdown may leave the controller
2256          * in a warm state but actually it cannot communicate with the codec.
2257          */
2258         iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2259         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2260         udelay(10);
2261         iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2262         msleep(1);
2263 #else
2264         /* finish cold or do warm reset */
2265         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2266         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2267         end_time = (jiffies + (HZ / 4)) + 1;
2268         do {
2269                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2270                         goto __ok;
2271                 schedule_timeout_uninterruptible(1);
2272         } while (time_after_eq(end_time, jiffies));
2273         snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2274                    igetdword(chip, ICHREG(GLOB_CNT)));
2275         return -EIO;
2276
2277       __ok:
2278 #endif
2279         if (probing) {
2280                 /* wait for any codec ready status.
2281                  * Once it becomes ready it should remain ready
2282                  * as long as we do not disable the ac97 link.
2283                  */
2284                 end_time = jiffies + HZ;
2285                 do {
2286                         status = igetdword(chip, ICHREG(GLOB_STA)) &
2287                                 chip->codec_isr_bits;
2288                         if (status)
2289                                 break;
2290                         schedule_timeout_uninterruptible(1);
2291                 } while (time_after_eq(end_time, jiffies));
2292                 if (! status) {
2293                         /* no codec is found */
2294                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2295                                    igetdword(chip, ICHREG(GLOB_STA)));
2296                         return -EIO;
2297                 }
2298
2299                 /* wait for other codecs ready status. */
2300                 end_time = jiffies + HZ / 4;
2301                 while (status != chip->codec_isr_bits &&
2302                        time_after_eq(end_time, jiffies)) {
2303                         schedule_timeout_uninterruptible(1);
2304                         status |= igetdword(chip, ICHREG(GLOB_STA)) &
2305                                 chip->codec_isr_bits;
2306                 }
2307
2308         } else {
2309                 /* resume phase */
2310                 int i;
2311                 status = 0;
2312                 for (i = 0; i < chip->ncodecs; i++)
2313                         if (chip->ac97[i])
2314                                 status |= chip->codec_bit[chip->ac97_sdin[i]];
2315                 /* wait until all the probed codecs are ready */
2316                 end_time = jiffies + HZ;
2317                 do {
2318                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2319                                 chip->codec_isr_bits;
2320                         if (status == nstatus)
2321                                 break;
2322                         schedule_timeout_uninterruptible(1);
2323                 } while (time_after_eq(end_time, jiffies));
2324         }
2325
2326         if (chip->device_type == DEVICE_SIS) {
2327                 /* unmute the output on SIS7012 */
2328                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2329         }
2330         if (chip->device_type == DEVICE_NFORCE) {
2331                 /* enable SPDIF interrupt */
2332                 unsigned int val;
2333                 pci_read_config_dword(chip->pci, 0x4c, &val);
2334                 val |= 0x1000000;
2335                 pci_write_config_dword(chip->pci, 0x4c, val);
2336         }
2337         return 0;
2338 }
2339
2340 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2341 {
2342         u32 reg;
2343         int i = 0;
2344
2345         reg = igetdword(chip, ICHREG(ALI_SCR));
2346         if ((reg & 2) == 0)     /* Cold required */
2347                 reg |= 2;
2348         else
2349                 reg |= 1;       /* Warm */
2350         reg &= ~0x80000000;     /* ACLink on */
2351         iputdword(chip, ICHREG(ALI_SCR), reg);
2352
2353         for (i = 0; i < HZ / 2; i++) {
2354                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2355                         goto __ok;
2356                 schedule_timeout_uninterruptible(1);
2357         }
2358         snd_printk(KERN_ERR "AC'97 reset failed.\n");
2359         if (probing)
2360                 return -EIO;
2361
2362  __ok:
2363         for (i = 0; i < HZ / 2; i++) {
2364                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2365                 if (reg & 0x80) /* primary codec */
2366                         break;
2367                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2368                 schedule_timeout_uninterruptible(1);
2369         }
2370
2371         do_ali_reset(chip);
2372         return 0;
2373 }
2374
2375 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2376 {
2377         unsigned int i, timeout;
2378         int err;
2379         
2380         if (chip->device_type != DEVICE_ALI) {
2381                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2382                         return err;
2383                 iagetword(chip, 0);     /* clear semaphore flag */
2384         } else {
2385                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2386                         return err;
2387         }
2388
2389         /* disable interrupts */
2390         for (i = 0; i < chip->bdbars_count; i++)
2391                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2392         /* reset channels */
2393         for (i = 0; i < chip->bdbars_count; i++)
2394                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2395         for (i = 0; i < chip->bdbars_count; i++) {
2396                 timeout = 100000;
2397                 while (--timeout != 0) {
2398                         if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2399                                 break;
2400                 }
2401                 if (timeout == 0)
2402                         printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2403         }
2404         /* initialize Buffer Descriptor Lists */
2405         for (i = 0; i < chip->bdbars_count; i++)
2406                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2407                           chip->ichd[i].bdbar_addr);
2408         return 0;
2409 }
2410
2411 static int snd_intel8x0_free(struct intel8x0 *chip)
2412 {
2413         unsigned int i;
2414
2415         if (chip->irq < 0)
2416                 goto __hw_end;
2417         /* disable interrupts */
2418         for (i = 0; i < chip->bdbars_count; i++)
2419                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2420         /* reset channels */
2421         for (i = 0; i < chip->bdbars_count; i++)
2422                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2423         if (chip->device_type == DEVICE_NFORCE) {
2424                 /* stop the spdif interrupt */
2425                 unsigned int val;
2426                 pci_read_config_dword(chip->pci, 0x4c, &val);
2427                 val &= ~0x1000000;
2428                 pci_write_config_dword(chip->pci, 0x4c, val);
2429         }
2430         /* --- */
2431         synchronize_irq(chip->irq);
2432       __hw_end:
2433         if (chip->irq >= 0)
2434                 free_irq(chip->irq, chip);
2435         if (chip->bdbars.area) {
2436                 if (chip->fix_nocache)
2437                         fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2438                 snd_dma_free_pages(&chip->bdbars);
2439         }
2440         if (chip->remap_addr)
2441                 iounmap(chip->remap_addr);
2442         if (chip->remap_bmaddr)
2443                 iounmap(chip->remap_bmaddr);
2444         pci_release_regions(chip->pci);
2445         pci_disable_device(chip->pci);
2446         kfree(chip);
2447         return 0;
2448 }
2449
2450 #ifdef CONFIG_PM
2451 /*
2452  * power management
2453  */
2454 static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2455 {
2456         struct snd_card *card = pci_get_drvdata(pci);
2457         struct intel8x0 *chip = card->private_data;
2458         int i;
2459
2460         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2461         for (i = 0; i < chip->pcm_devs; i++)
2462                 snd_pcm_suspend_all(chip->pcm[i]);
2463         /* clear nocache */
2464         if (chip->fix_nocache) {
2465                 for (i = 0; i < chip->bdbars_count; i++) {
2466                         struct ichdev *ichdev = &chip->ichd[i];
2467                         if (ichdev->substream && ichdev->page_attr_changed) {
2468                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2469                                 if (runtime->dma_area)
2470                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2471                         }
2472                 }
2473         }
2474         for (i = 0; i < chip->ncodecs; i++)
2475                 snd_ac97_suspend(chip->ac97[i]);
2476         if (chip->device_type == DEVICE_INTEL_ICH4)
2477                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2478
2479         if (chip->irq >= 0) {
2480                 synchronize_irq(chip->irq);
2481                 free_irq(chip->irq, chip);
2482                 chip->irq = -1;
2483         }
2484         pci_disable_device(pci);
2485         pci_save_state(pci);
2486         pci_set_power_state(pci, pci_choose_state(pci, state));
2487         return 0;
2488 }
2489
2490 static int intel8x0_resume(struct pci_dev *pci)
2491 {
2492         struct snd_card *card = pci_get_drvdata(pci);
2493         struct intel8x0 *chip = card->private_data;
2494         int i;
2495
2496         pci_set_power_state(pci, PCI_D0);
2497         pci_restore_state(pci);
2498         if (pci_enable_device(pci) < 0) {
2499                 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2500                        "disabling device\n");
2501                 snd_card_disconnect(card);
2502                 return -EIO;
2503         }
2504         pci_set_master(pci);
2505         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2506                         IRQF_DISABLED|IRQF_SHARED, card->shortname, chip)) {
2507                 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2508                        "disabling device\n", pci->irq);
2509                 snd_card_disconnect(card);
2510                 return -EIO;
2511         }
2512         chip->irq = pci->irq;
2513         synchronize_irq(chip->irq);
2514         snd_intel8x0_chip_init(chip, 0);
2515
2516         /* re-initialize mixer stuff */
2517         if (chip->device_type == DEVICE_INTEL_ICH4) {
2518                 /* enable separate SDINs for ICH4 */
2519                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2520                 /* use slot 10/11 for SPDIF */
2521                 iputdword(chip, ICHREG(GLOB_CNT),
2522                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2523                           ICH_PCM_SPDIF_1011);
2524         }
2525
2526         /* refill nocache */
2527         if (chip->fix_nocache)
2528                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2529
2530         for (i = 0; i < chip->ncodecs; i++)
2531                 snd_ac97_resume(chip->ac97[i]);
2532
2533         /* refill nocache */
2534         if (chip->fix_nocache) {
2535                 for (i = 0; i < chip->bdbars_count; i++) {
2536                         struct ichdev *ichdev = &chip->ichd[i];
2537                         if (ichdev->substream && ichdev->page_attr_changed) {
2538                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2539                                 if (runtime->dma_area)
2540                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2541                         }
2542                 }
2543         }
2544
2545         /* resume status */
2546         for (i = 0; i < chip->bdbars_count; i++) {
2547                 struct ichdev *ichdev = &chip->ichd[i];
2548                 unsigned long port = ichdev->reg_offset;
2549                 if (! ichdev->substream || ! ichdev->suspended)
2550                         continue;
2551                 if (ichdev->ichd == ICHD_PCMOUT)
2552                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2553                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2554                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2555                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2556                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2557         }
2558
2559         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2560         return 0;
2561 }
2562 #endif /* CONFIG_PM */
2563
2564 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2565
2566 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2567 {
2568         struct snd_pcm_substream *subs;
2569         struct ichdev *ichdev;
2570         unsigned long port;
2571         unsigned long pos, t;
2572         struct timeval start_time, stop_time;
2573
2574         if (chip->ac97_bus->clock != 48000)
2575                 return; /* specified in module option */
2576
2577         subs = chip->pcm[0]->streams[0].substream;
2578         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2579                 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2580                 return;
2581         }
2582         ichdev = &chip->ichd[ICHD_PCMOUT];
2583         ichdev->physbuf = subs->dma_buffer.addr;
2584         ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2585         ichdev->substream = NULL; /* don't process interrupts */
2586
2587         /* set rate */
2588         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2589                 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2590                 return;
2591         }
2592         snd_intel8x0_setup_periods(chip, ichdev);
2593         port = ichdev->reg_offset;
2594         spin_lock_irq(&chip->reg_lock);
2595         chip->in_measurement = 1;
2596         /* trigger */
2597         if (chip->device_type != DEVICE_ALI)
2598                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2599         else {
2600                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2601                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2602         }
2603         do_gettimeofday(&start_time);
2604         spin_unlock_irq(&chip->reg_lock);
2605         msleep(50);
2606         spin_lock_irq(&chip->reg_lock);
2607         /* check the position */
2608         pos = ichdev->fragsize1;
2609         pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2610         pos += ichdev->position;
2611         chip->in_measurement = 0;
2612         do_gettimeofday(&stop_time);
2613         /* stop */
2614         if (chip->device_type == DEVICE_ALI) {
2615                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2616                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2617                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2618                         ;
2619         } else {
2620                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2621                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2622                         ;
2623         }
2624         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2625         spin_unlock_irq(&chip->reg_lock);
2626
2627         t = stop_time.tv_sec - start_time.tv_sec;
2628         t *= 1000000;
2629         t += stop_time.tv_usec - start_time.tv_usec;
2630         printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2631         if (t == 0) {
2632                 snd_printk(KERN_ERR "?? calculation error..\n");
2633                 return;
2634         }
2635         pos = (pos / 4) * 1000;
2636         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2637         if (pos < 40000 || pos >= 60000) 
2638                 /* abnormal value. hw problem? */
2639                 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2640         else if (pos < 47500 || pos > 48500)
2641                 /* not 48000Hz, tuning the clock.. */
2642                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2643         printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2644         snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2645 }
2646
2647 #ifdef CONFIG_PROC_FS
2648 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2649                                    struct snd_info_buffer *buffer)
2650 {
2651         struct intel8x0 *chip = entry->private_data;
2652         unsigned int tmp;
2653
2654         snd_iprintf(buffer, "Intel8x0\n\n");
2655         if (chip->device_type == DEVICE_ALI)
2656                 return;
2657         tmp = igetdword(chip, ICHREG(GLOB_STA));
2658         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2659         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2660         if (chip->device_type == DEVICE_INTEL_ICH4)
2661                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2662         snd_iprintf(buffer, "AC'97 codecs ready    :");
2663         if (tmp & chip->codec_isr_bits) {
2664                 int i;
2665                 static const char *codecs[3] = {
2666                         "primary", "secondary", "tertiary"
2667                 };
2668                 for (i = 0; i < chip->max_codecs; i++)
2669                         if (tmp & chip->codec_bit[i])
2670                                 snd_iprintf(buffer, " %s", codecs[i]);
2671         } else
2672                 snd_iprintf(buffer, " none");
2673         snd_iprintf(buffer, "\n");
2674         if (chip->device_type == DEVICE_INTEL_ICH4 ||
2675             chip->device_type == DEVICE_SIS)
2676                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2677                         chip->ac97_sdin[0],
2678                         chip->ac97_sdin[1],
2679                         chip->ac97_sdin[2]);
2680 }
2681
2682 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2683 {
2684         struct snd_info_entry *entry;
2685
2686         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2687                 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2688 }
2689 #else
2690 #define snd_intel8x0_proc_init(x)
2691 #endif
2692
2693 static int snd_intel8x0_dev_free(struct snd_device *device)
2694 {
2695         struct intel8x0 *chip = device->device_data;
2696         return snd_intel8x0_free(chip);
2697 }
2698
2699 struct ich_reg_info {
2700         unsigned int int_sta_mask;
2701         unsigned int offset;
2702 };
2703
2704 static unsigned int ich_codec_bits[3] = {
2705         ICH_PCR, ICH_SCR, ICH_TCR
2706 };
2707 static unsigned int sis_codec_bits[3] = {
2708         ICH_PCR, ICH_SCR, ICH_SIS_TCR
2709 };
2710
2711 static int __devinit snd_intel8x0_create(struct snd_card *card,
2712                                          struct pci_dev *pci,
2713                                          unsigned long device_type,
2714                                          struct intel8x0 ** r_intel8x0)
2715 {
2716         struct intel8x0 *chip;
2717         int err;
2718         unsigned int i;
2719         unsigned int int_sta_masks;
2720         struct ichdev *ichdev;
2721         static struct snd_device_ops ops = {
2722                 .dev_free =     snd_intel8x0_dev_free,
2723         };
2724
2725         static unsigned int bdbars[] = {
2726                 3, /* DEVICE_INTEL */
2727                 6, /* DEVICE_INTEL_ICH4 */
2728                 3, /* DEVICE_SIS */
2729                 6, /* DEVICE_ALI */
2730                 4, /* DEVICE_NFORCE */
2731         };
2732         static struct ich_reg_info intel_regs[6] = {
2733                 { ICH_PIINT, 0 },
2734                 { ICH_POINT, 0x10 },
2735                 { ICH_MCINT, 0x20 },
2736                 { ICH_M2INT, 0x40 },
2737                 { ICH_P2INT, 0x50 },
2738                 { ICH_SPINT, 0x60 },
2739         };
2740         static struct ich_reg_info nforce_regs[4] = {
2741                 { ICH_PIINT, 0 },
2742                 { ICH_POINT, 0x10 },
2743                 { ICH_MCINT, 0x20 },
2744                 { ICH_NVSPINT, 0x70 },
2745         };
2746         static struct ich_reg_info ali_regs[6] = {
2747                 { ALI_INT_PCMIN, 0x40 },
2748                 { ALI_INT_PCMOUT, 0x50 },
2749                 { ALI_INT_MICIN, 0x60 },
2750                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2751                 { ALI_INT_SPDIFIN, 0xa0 },
2752                 { ALI_INT_SPDIFOUT, 0xb0 },
2753         };
2754         struct ich_reg_info *tbl;
2755
2756         *r_intel8x0 = NULL;
2757
2758         if ((err = pci_enable_device(pci)) < 0)
2759                 return err;
2760
2761         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2762         if (chip == NULL) {
2763                 pci_disable_device(pci);
2764                 return -ENOMEM;
2765         }
2766         spin_lock_init(&chip->reg_lock);
2767         chip->device_type = device_type;
2768         chip->card = card;
2769         chip->pci = pci;
2770         chip->irq = -1;
2771
2772         /* module parameters */
2773         chip->buggy_irq = buggy_irq;
2774         chip->buggy_semaphore = buggy_semaphore;
2775         if (xbox)
2776                 chip->xbox = 1;
2777
2778         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2779             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2780                 chip->fix_nocache = 1; /* enable workaround */
2781
2782         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2783                 kfree(chip);
2784                 pci_disable_device(pci);
2785                 return err;
2786         }
2787
2788         if (device_type == DEVICE_ALI) {
2789                 /* ALI5455 has no ac97 region */
2790                 chip->bmaddr = pci_resource_start(pci, 0);
2791                 goto port_inited;
2792         }
2793
2794         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) {      /* ICH4 and Nforce */
2795                 chip->mmio = 1;
2796                 chip->addr = pci_resource_start(pci, 2);
2797                 chip->remap_addr = ioremap_nocache(chip->addr,
2798                                                    pci_resource_len(pci, 2));
2799                 if (chip->remap_addr == NULL) {
2800                         snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2801                         snd_intel8x0_free(chip);
2802                         return -EIO;
2803                 }
2804         } else {
2805                 chip->addr = pci_resource_start(pci, 0);
2806         }
2807         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) {      /* ICH4 */
2808                 chip->bm_mmio = 1;
2809                 chip->bmaddr = pci_resource_start(pci, 3);
2810                 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2811                                                      pci_resource_len(pci, 3));
2812                 if (chip->remap_bmaddr == NULL) {
2813                         snd_printk(KERN_ERR "Controller space ioremap problem\n");
2814                         snd_intel8x0_free(chip);
2815                         return -EIO;
2816                 }
2817         } else {
2818                 chip->bmaddr = pci_resource_start(pci, 1);
2819         }
2820
2821  port_inited:
2822         chip->bdbars_count = bdbars[device_type];
2823
2824         /* initialize offsets */
2825         switch (device_type) {
2826         case DEVICE_NFORCE:
2827                 tbl = nforce_regs;
2828                 break;
2829         case DEVICE_ALI:
2830                 tbl = ali_regs;
2831                 break;
2832         default:
2833                 tbl = intel_regs;
2834                 break;
2835         }
2836         for (i = 0; i < chip->bdbars_count; i++) {
2837                 ichdev = &chip->ichd[i];
2838                 ichdev->ichd = i;
2839                 ichdev->reg_offset = tbl[i].offset;
2840                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2841                 if (device_type == DEVICE_SIS) {
2842                         /* SiS 7012 swaps the registers */
2843                         ichdev->roff_sr = ICH_REG_OFF_PICB;
2844                         ichdev->roff_picb = ICH_REG_OFF_SR;
2845                 } else {
2846                         ichdev->roff_sr = ICH_REG_OFF_SR;
2847                         ichdev->roff_picb = ICH_REG_OFF_PICB;
2848                 }
2849                 if (device_type == DEVICE_ALI)
2850                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2851                 /* SIS7012 handles the pcm data in bytes, others are in samples */
2852                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2853         }
2854
2855         /* allocate buffer descriptor lists */
2856         /* the start of each lists must be aligned to 8 bytes */
2857         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2858                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2859                                 &chip->bdbars) < 0) {
2860                 snd_intel8x0_free(chip);
2861                 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2862                 return -ENOMEM;
2863         }
2864         /* tables must be aligned to 8 bytes here, but the kernel pages
2865            are much bigger, so we don't care (on i386) */
2866         /* workaround for 440MX */
2867         if (chip->fix_nocache)
2868                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2869         int_sta_masks = 0;
2870         for (i = 0; i < chip->bdbars_count; i++) {
2871                 ichdev = &chip->ichd[i];
2872                 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2873                         (i * ICH_MAX_FRAGS * 2);
2874                 ichdev->bdbar_addr = chip->bdbars.addr +
2875                         (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2876                 int_sta_masks |= ichdev->int_sta_mask;
2877         }
2878         chip->int_sta_reg = device_type == DEVICE_ALI ?
2879                 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2880         chip->int_sta_mask = int_sta_masks;
2881
2882         /* request irq after initializaing int_sta_mask, etc */
2883         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2884                         IRQF_DISABLED|IRQF_SHARED, card->shortname, chip)) {
2885                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2886                 snd_intel8x0_free(chip);
2887                 return -EBUSY;
2888         }
2889         chip->irq = pci->irq;
2890         pci_set_master(pci);
2891         synchronize_irq(chip->irq);
2892
2893         switch(chip->device_type) {
2894         case DEVICE_INTEL_ICH4:
2895                 /* ICH4 can have three codecs */
2896                 chip->max_codecs = 3;
2897                 chip->codec_bit = ich_codec_bits;
2898                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
2899                 break;
2900         case DEVICE_SIS:
2901                 /* recent SIS7012 can have three codecs */
2902                 chip->max_codecs = 3;
2903                 chip->codec_bit = sis_codec_bits;
2904                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
2905                 break;
2906         default:
2907                 /* others up to two codecs */
2908                 chip->max_codecs = 2;
2909                 chip->codec_bit = ich_codec_bits;
2910                 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
2911                 break;
2912         }
2913         for (i = 0; i < chip->max_codecs; i++)
2914                 chip->codec_isr_bits |= chip->codec_bit[i];
2915
2916         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2917                 snd_intel8x0_free(chip);
2918                 return err;
2919         }
2920
2921         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2922                 snd_intel8x0_free(chip);
2923                 return err;
2924         }
2925
2926         snd_card_set_dev(card, &pci->dev);
2927
2928         *r_intel8x0 = chip;
2929         return 0;
2930 }
2931
2932 static struct shortname_table {
2933         unsigned int id;
2934         const char *s;
2935 } shortnames[] __devinitdata = {
2936         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
2937         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
2938         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
2939         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2940         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
2941         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
2942         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
2943         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2944         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2945         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2946         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
2947         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2948         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
2949         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2950         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2951         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2952         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2953         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2954         { 0x003a, "NVidia MCP04" },
2955         { 0x746d, "AMD AMD8111" },
2956         { 0x7445, "AMD AMD768" },
2957         { 0x5455, "ALi M5455" },
2958         { 0, NULL },
2959 };
2960
2961 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2962                                         const struct pci_device_id *pci_id)
2963 {
2964         struct snd_card *card;
2965         struct intel8x0 *chip;
2966         int err;
2967         struct shortname_table *name;
2968
2969         card = snd_card_new(index, id, THIS_MODULE, 0);
2970         if (card == NULL)
2971                 return -ENOMEM;
2972
2973         switch (pci_id->driver_data) {
2974         case DEVICE_NFORCE:
2975                 strcpy(card->driver, "NFORCE");
2976                 break;
2977         case DEVICE_INTEL_ICH4:
2978                 strcpy(card->driver, "ICH4");
2979                 break;
2980         default:
2981                 strcpy(card->driver, "ICH");
2982                 break;
2983         }
2984
2985         strcpy(card->shortname, "Intel ICH");
2986         for (name = shortnames; name->id; name++) {
2987                 if (pci->device == name->id) {
2988                         strcpy(card->shortname, name->s);
2989                         break;
2990                 }
2991         }
2992
2993         if (buggy_irq < 0) {
2994                 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2995                  * Needs to return IRQ_HANDLED for unknown irqs.
2996                  */
2997                 if (pci_id->driver_data == DEVICE_NFORCE)
2998                         buggy_irq = 1;
2999                 else
3000                         buggy_irq = 0;
3001         }
3002
3003         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3004                                        &chip)) < 0) {
3005                 snd_card_free(card);
3006                 return err;
3007         }
3008         card->private_data = chip;
3009
3010         if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3011                 snd_card_free(card);
3012                 return err;
3013         }
3014         if ((err = snd_intel8x0_pcm(chip)) < 0) {
3015                 snd_card_free(card);
3016                 return err;
3017         }
3018         
3019         snd_intel8x0_proc_init(chip);
3020
3021         snprintf(card->longname, sizeof(card->longname),
3022                  "%s with %s at %#lx, irq %i", card->shortname,
3023                  snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
3024
3025         if (! ac97_clock)
3026                 intel8x0_measure_ac97_clock(chip);
3027
3028         if ((err = snd_card_register(card)) < 0) {
3029                 snd_card_free(card);
3030                 return err;
3031         }
3032         pci_set_drvdata(pci, card);
3033         return 0;
3034 }
3035
3036 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3037 {
3038         snd_card_free(pci_get_drvdata(pci));
3039         pci_set_drvdata(pci, NULL);
3040 }
3041
3042 static struct pci_driver driver = {
3043         .name = "Intel ICH",
3044         .id_table = snd_intel8x0_ids,
3045         .probe = snd_intel8x0_probe,
3046         .remove = __devexit_p(snd_intel8x0_remove),
3047 #ifdef CONFIG_PM
3048         .suspend = intel8x0_suspend,
3049         .resume = intel8x0_resume,
3050 #endif
3051 };
3052
3053
3054 static int __init alsa_card_intel8x0_init(void)
3055 {
3056         return pci_register_driver(&driver);
3057 }
3058
3059 static void __exit alsa_card_intel8x0_exit(void)
3060 {
3061         pci_unregister_driver(&driver);
3062 }
3063
3064 module_init(alsa_card_intel8x0_init)
3065 module_exit(alsa_card_intel8x0_exit)