4b570684a6aaeee45b75fd974d88f44a52e30bc4
[linux-2.6.git] / include / sound / ymfpci.h
1 #ifndef __SOUND_YMFPCI_H
2 #define __SOUND_YMFPCI_H
3
4 /*
5  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>
6  *  Definitions for Yahama YMF724/740/744/754 chips
7  *
8  *
9  *   This program is free software; you can redistribute it and/or modify
10  *   it under the terms of the GNU General Public License as published by
11  *   the Free Software Foundation; either version 2 of the License, or
12  *   (at your option) any later version.
13  *
14  *   This program is distributed in the hope that it will be useful,
15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *   GNU General Public License for more details.
18  *
19  *   You should have received a copy of the GNU General Public License
20  *   along with this program; if not, write to the Free Software
21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
22  *
23  */
24
25 #include "pcm.h"
26 #include "rawmidi.h"
27 #include "ac97_codec.h"
28 #include "timer.h"
29 #include <linux/gameport.h>
30
31 #ifndef PCI_VENDOR_ID_YAMAHA
32 #define PCI_VENDOR_ID_YAMAHA            0x1073
33 #endif
34 #ifndef PCI_DEVICE_ID_YAMAHA_724
35 #define PCI_DEVICE_ID_YAMAHA_724        0x0004
36 #endif
37 #ifndef PCI_DEVICE_ID_YAMAHA_724F
38 #define PCI_DEVICE_ID_YAMAHA_724F       0x000d
39 #endif
40 #ifndef PCI_DEVICE_ID_YAMAHA_740
41 #define PCI_DEVICE_ID_YAMAHA_740        0x000a
42 #endif
43 #ifndef PCI_DEVICE_ID_YAMAHA_740C
44 #define PCI_DEVICE_ID_YAMAHA_740C       0x000c
45 #endif
46 #ifndef PCI_DEVICE_ID_YAMAHA_744
47 #define PCI_DEVICE_ID_YAMAHA_744        0x0010
48 #endif
49 #ifndef PCI_DEVICE_ID_YAMAHA_754
50 #define PCI_DEVICE_ID_YAMAHA_754        0x0012
51 #endif
52
53 /*
54  *  Direct registers
55  */
56
57 #define YMFREG(chip, reg)               (chip->port + YDSXGR_##reg)
58
59 #define YDSXGR_INTFLAG                  0x0004
60 #define YDSXGR_ACTIVITY                 0x0006
61 #define YDSXGR_GLOBALCTRL               0x0008
62 #define YDSXGR_ZVCTRL                   0x000A
63 #define YDSXGR_TIMERCTRL                0x0010
64 #define YDSXGR_TIMERCOUNT               0x0012
65 #define YDSXGR_SPDIFOUTCTRL             0x0018
66 #define YDSXGR_SPDIFOUTSTATUS           0x001C
67 #define YDSXGR_EEPROMCTRL               0x0020
68 #define YDSXGR_SPDIFINCTRL              0x0034
69 #define YDSXGR_SPDIFINSTATUS            0x0038
70 #define YDSXGR_DSPPROGRAMDL             0x0048
71 #define YDSXGR_DLCNTRL                  0x004C
72 #define YDSXGR_GPIOININTFLAG            0x0050
73 #define YDSXGR_GPIOININTENABLE          0x0052
74 #define YDSXGR_GPIOINSTATUS             0x0054
75 #define YDSXGR_GPIOOUTCTRL              0x0056
76 #define YDSXGR_GPIOFUNCENABLE           0x0058
77 #define YDSXGR_GPIOTYPECONFIG           0x005A
78 #define YDSXGR_AC97CMDDATA              0x0060
79 #define YDSXGR_AC97CMDADR               0x0062
80 #define YDSXGR_PRISTATUSDATA            0x0064
81 #define YDSXGR_PRISTATUSADR             0x0066
82 #define YDSXGR_SECSTATUSDATA            0x0068
83 #define YDSXGR_SECSTATUSADR             0x006A
84 #define YDSXGR_SECCONFIG                0x0070
85 #define YDSXGR_LEGACYOUTVOL             0x0080
86 #define YDSXGR_LEGACYOUTVOLL            0x0080
87 #define YDSXGR_LEGACYOUTVOLR            0x0082
88 #define YDSXGR_NATIVEDACOUTVOL          0x0084
89 #define YDSXGR_NATIVEDACOUTVOLL         0x0084
90 #define YDSXGR_NATIVEDACOUTVOLR         0x0086
91 #define YDSXGR_ZVOUTVOL                 0x0088
92 #define YDSXGR_ZVOUTVOLL                0x0088
93 #define YDSXGR_ZVOUTVOLR                0x008A
94 #define YDSXGR_SECADCOUTVOL             0x008C
95 #define YDSXGR_SECADCOUTVOLL            0x008C
96 #define YDSXGR_SECADCOUTVOLR            0x008E
97 #define YDSXGR_PRIADCOUTVOL             0x0090
98 #define YDSXGR_PRIADCOUTVOLL            0x0090
99 #define YDSXGR_PRIADCOUTVOLR            0x0092
100 #define YDSXGR_LEGACYLOOPVOL            0x0094
101 #define YDSXGR_LEGACYLOOPVOLL           0x0094
102 #define YDSXGR_LEGACYLOOPVOLR           0x0096
103 #define YDSXGR_NATIVEDACLOOPVOL         0x0098
104 #define YDSXGR_NATIVEDACLOOPVOLL        0x0098
105 #define YDSXGR_NATIVEDACLOOPVOLR        0x009A
106 #define YDSXGR_ZVLOOPVOL                0x009C
107 #define YDSXGR_ZVLOOPVOLL               0x009E
108 #define YDSXGR_ZVLOOPVOLR               0x009E
109 #define YDSXGR_SECADCLOOPVOL            0x00A0
110 #define YDSXGR_SECADCLOOPVOLL           0x00A0
111 #define YDSXGR_SECADCLOOPVOLR           0x00A2
112 #define YDSXGR_PRIADCLOOPVOL            0x00A4
113 #define YDSXGR_PRIADCLOOPVOLL           0x00A4
114 #define YDSXGR_PRIADCLOOPVOLR           0x00A6
115 #define YDSXGR_NATIVEADCINVOL           0x00A8
116 #define YDSXGR_NATIVEADCINVOLL          0x00A8
117 #define YDSXGR_NATIVEADCINVOLR          0x00AA
118 #define YDSXGR_NATIVEDACINVOL           0x00AC
119 #define YDSXGR_NATIVEDACINVOLL          0x00AC
120 #define YDSXGR_NATIVEDACINVOLR          0x00AE
121 #define YDSXGR_BUF441OUTVOL             0x00B0
122 #define YDSXGR_BUF441OUTVOLL            0x00B0
123 #define YDSXGR_BUF441OUTVOLR            0x00B2
124 #define YDSXGR_BUF441LOOPVOL            0x00B4
125 #define YDSXGR_BUF441LOOPVOLL           0x00B4
126 #define YDSXGR_BUF441LOOPVOLR           0x00B6
127 #define YDSXGR_SPDIFOUTVOL              0x00B8
128 #define YDSXGR_SPDIFOUTVOLL             0x00B8
129 #define YDSXGR_SPDIFOUTVOLR             0x00BA
130 #define YDSXGR_SPDIFLOOPVOL             0x00BC
131 #define YDSXGR_SPDIFLOOPVOLL            0x00BC
132 #define YDSXGR_SPDIFLOOPVOLR            0x00BE
133 #define YDSXGR_ADCSLOTSR                0x00C0
134 #define YDSXGR_RECSLOTSR                0x00C4
135 #define YDSXGR_ADCFORMAT                0x00C8
136 #define YDSXGR_RECFORMAT                0x00CC
137 #define YDSXGR_P44SLOTSR                0x00D0
138 #define YDSXGR_STATUS                   0x0100
139 #define YDSXGR_CTRLSELECT               0x0104
140 #define YDSXGR_MODE                     0x0108
141 #define YDSXGR_SAMPLECOUNT              0x010C
142 #define YDSXGR_NUMOFSAMPLES             0x0110
143 #define YDSXGR_CONFIG                   0x0114
144 #define YDSXGR_PLAYCTRLSIZE             0x0140
145 #define YDSXGR_RECCTRLSIZE              0x0144
146 #define YDSXGR_EFFCTRLSIZE              0x0148
147 #define YDSXGR_WORKSIZE                 0x014C
148 #define YDSXGR_MAPOFREC                 0x0150
149 #define YDSXGR_MAPOFEFFECT              0x0154
150 #define YDSXGR_PLAYCTRLBASE             0x0158
151 #define YDSXGR_RECCTRLBASE              0x015C
152 #define YDSXGR_EFFCTRLBASE              0x0160
153 #define YDSXGR_WORKBASE                 0x0164
154 #define YDSXGR_DSPINSTRAM               0x1000
155 #define YDSXGR_CTRLINSTRAM              0x4000
156
157 #define YDSXG_AC97READCMD               0x8000
158 #define YDSXG_AC97WRITECMD              0x0000
159
160 #define PCIR_DSXG_LEGACY                0x40
161 #define PCIR_DSXG_ELEGACY               0x42
162 #define PCIR_DSXG_CTRL                  0x48
163 #define PCIR_DSXG_PWRCTRL1              0x4a
164 #define PCIR_DSXG_PWRCTRL2              0x4e
165 #define PCIR_DSXG_FMBASE                0x60
166 #define PCIR_DSXG_SBBASE                0x62
167 #define PCIR_DSXG_MPU401BASE            0x64
168 #define PCIR_DSXG_JOYBASE               0x66
169
170 #define YDSXG_DSPLENGTH                 0x0080
171 #define YDSXG_CTRLLENGTH                0x3000
172
173 #define YDSXG_DEFAULT_WORK_SIZE         0x0400
174
175 #define YDSXG_PLAYBACK_VOICES           64
176 #define YDSXG_CAPTURE_VOICES            2
177 #define YDSXG_EFFECT_VOICES             5
178
179 #define YMFPCI_LEGACY_SBEN      (1 << 0)        /* soundblaster enable */
180 #define YMFPCI_LEGACY_FMEN      (1 << 1)        /* OPL3 enable */
181 #define YMFPCI_LEGACY_JPEN      (1 << 2)        /* joystick enable */
182 #define YMFPCI_LEGACY_MEN       (1 << 3)        /* MPU401 enable */
183 #define YMFPCI_LEGACY_MIEN      (1 << 4)        /* MPU RX irq enable */
184 #define YMFPCI_LEGACY_IOBITS    (1 << 5)        /* i/o bits range, 0 = 16bit, 1 =10bit */
185 #define YMFPCI_LEGACY_SDMA      (3 << 6)        /* SB DMA select */
186 #define YMFPCI_LEGACY_SBIRQ     (7 << 8)        /* SB IRQ select */
187 #define YMFPCI_LEGACY_MPUIRQ    (7 << 11)       /* MPU IRQ select */
188 #define YMFPCI_LEGACY_SIEN      (1 << 14)       /* serialized IRQ */
189 #define YMFPCI_LEGACY_LAD       (1 << 15)       /* legacy audio disable */
190
191 #define YMFPCI_LEGACY2_FMIO     (3 << 0)        /* OPL3 i/o address (724/740) */
192 #define YMFPCI_LEGACY2_SBIO     (3 << 2)        /* SB i/o address (724/740) */
193 #define YMFPCI_LEGACY2_MPUIO    (3 << 4)        /* MPU401 i/o address (724/740) */
194 #define YMFPCI_LEGACY2_JSIO     (3 << 6)        /* joystick i/o address (724/740) */
195 #define YMFPCI_LEGACY2_MAIM     (1 << 8)        /* MPU401 ack intr mask */
196 #define YMFPCI_LEGACY2_SMOD     (3 << 11)       /* SB DMA mode */
197 #define YMFPCI_LEGACY2_SBVER    (3 << 13)       /* SB version select */
198 #define YMFPCI_LEGACY2_IMOD     (1 << 15)       /* legacy IRQ mode */
199 /* SIEN:IMOD 0:0 = legacy irq, 0:1 = INTA, 1:0 = serialized IRQ */
200
201 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
202 #define SUPPORT_JOYSTICK
203 #endif
204
205 /*
206  *
207  */
208
209 typedef struct _snd_ymfpci_playback_bank {
210         u32 format;
211         u32 loop_default;
212         u32 base;                       /* 32-bit address */
213         u32 loop_start;                 /* 32-bit offset */
214         u32 loop_end;                   /* 32-bit offset */
215         u32 loop_frac;                  /* 8-bit fraction - loop_start */
216         u32 delta_end;                  /* pitch delta end */
217         u32 lpfK_end;
218         u32 eg_gain_end;
219         u32 left_gain_end;
220         u32 right_gain_end;
221         u32 eff1_gain_end;
222         u32 eff2_gain_end;
223         u32 eff3_gain_end;
224         u32 lpfQ;
225         u32 status;
226         u32 num_of_frames;
227         u32 loop_count;
228         u32 start;
229         u32 start_frac;
230         u32 delta;
231         u32 lpfK;
232         u32 eg_gain;
233         u32 left_gain;
234         u32 right_gain;
235         u32 eff1_gain;
236         u32 eff2_gain;
237         u32 eff3_gain;
238         u32 lpfD1;
239         u32 lpfD2;
240 } snd_ymfpci_playback_bank_t;
241
242 typedef struct _snd_ymfpci_capture_bank {
243         u32 base;                       /* 32-bit address */
244         u32 loop_end;                   /* 32-bit offset */
245         u32 start;                      /* 32-bit offset */
246         u32 num_of_loops;               /* counter */
247 } snd_ymfpci_capture_bank_t;
248
249 typedef struct _snd_ymfpci_effect_bank {
250         u32 base;                       /* 32-bit address */
251         u32 loop_end;                   /* 32-bit offset */
252         u32 start;                      /* 32-bit offset */
253         u32 temp;
254 } snd_ymfpci_effect_bank_t;
255
256 typedef struct _snd_ymfpci_voice ymfpci_voice_t;
257 typedef struct _snd_ymfpci_pcm ymfpci_pcm_t;
258 typedef struct _snd_ymfpci ymfpci_t;
259
260 typedef enum {
261         YMFPCI_PCM,
262         YMFPCI_SYNTH,
263         YMFPCI_MIDI
264 } ymfpci_voice_type_t;
265
266 struct _snd_ymfpci_voice {
267         ymfpci_t *chip;
268         int number;
269         unsigned int use: 1,
270             pcm: 1,
271             synth: 1,
272             midi: 1;
273         snd_ymfpci_playback_bank_t *bank;
274         dma_addr_t bank_addr;
275         void (*interrupt)(ymfpci_t *chip, ymfpci_voice_t *voice);
276         ymfpci_pcm_t *ypcm;
277 };
278
279 typedef enum {
280         PLAYBACK_VOICE,
281         CAPTURE_REC,
282         CAPTURE_AC97,
283         EFFECT_DRY_LEFT,
284         EFFECT_DRY_RIGHT,
285         EFFECT_EFF1,
286         EFFECT_EFF2,
287         EFFECT_EFF3
288 } snd_ymfpci_pcm_type_t;
289
290 struct _snd_ymfpci_pcm {
291         ymfpci_t *chip;
292         snd_ymfpci_pcm_type_t type;
293         snd_pcm_substream_t *substream;
294         ymfpci_voice_t *voices[2];      /* playback only */
295         unsigned int running: 1;
296         unsigned int output_front: 1;
297         unsigned int output_rear: 1;
298         u32 period_size;                /* cached from runtime->period_size */
299         u32 buffer_size;                /* cached from runtime->buffer_size */
300         u32 period_pos;
301         u32 last_pos;
302         u32 capture_bank_number;
303         u32 shift;
304 };
305
306 struct _snd_ymfpci {
307         int irq;
308
309         unsigned int device_id; /* PCI device ID */
310         unsigned int rev;       /* PCI revision */
311         unsigned long reg_area_phys;
312         void __iomem *reg_area_virt;
313         struct resource *res_reg_area;
314         struct resource *fm_res;
315         struct resource *mpu_res;
316
317         unsigned short old_legacy_ctrl;
318 #ifdef SUPPORT_JOYSTICK
319         struct gameport *gameport;
320 #endif
321
322         struct snd_dma_buffer work_ptr;
323
324         unsigned int bank_size_playback;
325         unsigned int bank_size_capture;
326         unsigned int bank_size_effect;
327         unsigned int work_size;
328
329         void *bank_base_playback;
330         void *bank_base_capture;
331         void *bank_base_effect;
332         void *work_base;
333         dma_addr_t bank_base_playback_addr;
334         dma_addr_t bank_base_capture_addr;
335         dma_addr_t bank_base_effect_addr;
336         dma_addr_t work_base_addr;
337         struct snd_dma_buffer ac3_tmp_base;
338
339         u32 *ctrl_playback;
340         snd_ymfpci_playback_bank_t *bank_playback[YDSXG_PLAYBACK_VOICES][2];
341         snd_ymfpci_capture_bank_t *bank_capture[YDSXG_CAPTURE_VOICES][2];
342         snd_ymfpci_effect_bank_t *bank_effect[YDSXG_EFFECT_VOICES][2];
343
344         int start_count;
345
346         u32 active_bank;
347         ymfpci_voice_t voices[64];
348
349         ac97_bus_t *ac97_bus;
350         ac97_t *ac97;
351         snd_rawmidi_t *rawmidi;
352         snd_timer_t *timer;
353
354         struct pci_dev *pci;
355         snd_card_t *card;
356         snd_pcm_t *pcm;
357         snd_pcm_t *pcm2;
358         snd_pcm_t *pcm_spdif;
359         snd_pcm_t *pcm_4ch;
360         snd_pcm_substream_t *capture_substream[YDSXG_CAPTURE_VOICES];
361         snd_pcm_substream_t *effect_substream[YDSXG_EFFECT_VOICES];
362         snd_kcontrol_t *ctl_vol_recsrc;
363         snd_kcontrol_t *ctl_vol_adcrec;
364         snd_kcontrol_t *ctl_vol_spdifrec;
365         unsigned short spdif_bits, spdif_pcm_bits;
366         snd_kcontrol_t *spdif_pcm_ctl;
367         int mode_dup4ch;
368         int rear_opened;
369         int spdif_opened;
370
371         spinlock_t reg_lock;
372         spinlock_t voice_lock;
373         wait_queue_head_t interrupt_sleep;
374         atomic_t interrupt_sleep_count;
375         snd_info_entry_t *proc_entry;
376
377 #ifdef CONFIG_PM
378         u32 *saved_regs;
379         u32 saved_ydsxgr_mode;
380 #endif
381 };
382
383 int snd_ymfpci_create(snd_card_t * card,
384                       struct pci_dev *pci,
385                       unsigned short old_legacy_ctrl,
386                       ymfpci_t ** rcodec);
387 void snd_ymfpci_free_gameport(ymfpci_t *chip);
388
389 int snd_ymfpci_pcm(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
390 int snd_ymfpci_pcm2(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
391 int snd_ymfpci_pcm_spdif(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
392 int snd_ymfpci_pcm_4ch(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
393 int snd_ymfpci_mixer(ymfpci_t *chip, int rear_switch);
394 int snd_ymfpci_timer(ymfpci_t *chip, int device);
395
396 #endif /* __SOUND_YMFPCI_H */