mfd: Fix modular builds of rc5t583 regulator support
[linux-2.6.git] / include / linux / mfd / rc5t583.h
1 /*
2  * Core driver interface to access RICOH_RC5T583 power management chip.
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  * Author: Laxman dewangan <ldewangan@nvidia.com>
6  *
7  * Based on code
8  *      Copyright (C) 2011 RICOH COMPANY,LTD
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms and conditions of the GNU General Public License,
12  * version 2, as published by the Free Software Foundation.
13  *
14  * This program is distributed in the hope it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23
24 #ifndef __LINUX_MFD_RC5T583_H
25 #define __LINUX_MFD_RC5T583_H
26
27 #include <linux/mutex.h>
28 #include <linux/types.h>
29 #include <linux/regmap.h>
30
31 #define RC5T583_MAX_REGS                0xF8
32
33 /* Maximum number of main interrupts */
34 #define MAX_MAIN_INTERRUPT              5
35 #define RC5T583_MAX_GPEDGE_REG          2
36 #define RC5T583_MAX_INTERRUPT_MASK_REGS 9
37
38 /* Interrupt enable register */
39 #define RC5T583_INT_EN_SYS1     0x19
40 #define RC5T583_INT_EN_SYS2     0x1D
41 #define RC5T583_INT_EN_DCDC     0x41
42 #define RC5T583_INT_EN_RTC      0xED
43 #define RC5T583_INT_EN_ADC1     0x90
44 #define RC5T583_INT_EN_ADC2     0x91
45 #define RC5T583_INT_EN_ADC3     0x92
46
47 /* Interrupt status registers (monitor regs in Ricoh)*/
48 #define RC5T583_INTC_INTPOL     0xAD
49 #define RC5T583_INTC_INTEN      0xAE
50 #define RC5T583_INTC_INTMON     0xAF
51
52 #define RC5T583_INT_MON_GRP     0xAF
53 #define RC5T583_INT_MON_SYS1    0x1B
54 #define RC5T583_INT_MON_SYS2    0x1F
55 #define RC5T583_INT_MON_DCDC    0x43
56 #define RC5T583_INT_MON_RTC     0xEE
57
58 /* Interrupt clearing registers */
59 #define RC5T583_INT_IR_SYS1     0x1A
60 #define RC5T583_INT_IR_SYS2     0x1E
61 #define RC5T583_INT_IR_DCDC     0x42
62 #define RC5T583_INT_IR_RTC      0xEE
63 #define RC5T583_INT_IR_ADCL     0x94
64 #define RC5T583_INT_IR_ADCH     0x95
65 #define RC5T583_INT_IR_ADCEND   0x96
66 #define RC5T583_INT_IR_GPIOR    0xA9
67 #define RC5T583_INT_IR_GPIOF    0xAA
68
69 /* Sleep sequence registers */
70 #define RC5T583_SLPSEQ1         0x21
71 #define RC5T583_SLPSEQ2         0x22
72 #define RC5T583_SLPSEQ3         0x23
73 #define RC5T583_SLPSEQ4         0x24
74 #define RC5T583_SLPSEQ5         0x25
75 #define RC5T583_SLPSEQ6         0x26
76 #define RC5T583_SLPSEQ7         0x27
77 #define RC5T583_SLPSEQ8         0x28
78 #define RC5T583_SLPSEQ9         0x29
79 #define RC5T583_SLPSEQ10        0x2A
80 #define RC5T583_SLPSEQ11        0x2B
81
82 /* Regulator registers */
83 #define RC5T583_REG_DC0CTL      0x30
84 #define RC5T583_REG_DC0DAC      0x31
85 #define RC5T583_REG_DC0LATCTL   0x32
86 #define RC5T583_REG_SR0CTL      0x33
87
88 #define RC5T583_REG_DC1CTL      0x34
89 #define RC5T583_REG_DC1DAC      0x35
90 #define RC5T583_REG_DC1LATCTL   0x36
91 #define RC5T583_REG_SR1CTL      0x37
92
93 #define RC5T583_REG_DC2CTL      0x38
94 #define RC5T583_REG_DC2DAC      0x39
95 #define RC5T583_REG_DC2LATCTL   0x3A
96 #define RC5T583_REG_SR2CTL      0x3B
97
98 #define RC5T583_REG_DC3CTL      0x3C
99 #define RC5T583_REG_DC3DAC      0x3D
100 #define RC5T583_REG_DC3LATCTL   0x3E
101 #define RC5T583_REG_SR3CTL      0x3F
102
103
104 #define RC5T583_REG_LDOEN1      0x50
105 #define RC5T583_REG_LDOEN2      0x51
106 #define RC5T583_REG_LDODIS1     0x52
107 #define RC5T583_REG_LDODIS2     0x53
108
109 #define RC5T583_REG_LDO0DAC     0x54
110 #define RC5T583_REG_LDO1DAC     0x55
111 #define RC5T583_REG_LDO2DAC     0x56
112 #define RC5T583_REG_LDO3DAC     0x57
113 #define RC5T583_REG_LDO4DAC     0x58
114 #define RC5T583_REG_LDO5DAC     0x59
115 #define RC5T583_REG_LDO6DAC     0x5A
116 #define RC5T583_REG_LDO7DAC     0x5B
117 #define RC5T583_REG_LDO8DAC     0x5C
118 #define RC5T583_REG_LDO9DAC     0x5D
119
120 #define RC5T583_REG_DC0DAC_DS   0x60
121 #define RC5T583_REG_DC1DAC_DS   0x61
122 #define RC5T583_REG_DC2DAC_DS   0x62
123 #define RC5T583_REG_DC3DAC_DS   0x63
124
125 #define RC5T583_REG_LDO0DAC_DS  0x64
126 #define RC5T583_REG_LDO1DAC_DS  0x65
127 #define RC5T583_REG_LDO2DAC_DS  0x66
128 #define RC5T583_REG_LDO3DAC_DS  0x67
129 #define RC5T583_REG_LDO4DAC_DS  0x68
130 #define RC5T583_REG_LDO5DAC_DS  0x69
131 #define RC5T583_REG_LDO6DAC_DS  0x6A
132 #define RC5T583_REG_LDO7DAC_DS  0x6B
133 #define RC5T583_REG_LDO8DAC_DS  0x6C
134 #define RC5T583_REG_LDO9DAC_DS  0x6D
135
136 /* GPIO register base address */
137 #define RC5T583_GPIO_IOSEL      0xA0
138 #define RC5T583_GPIO_PDEN       0xA1
139 #define RC5T583_GPIO_IOOUT      0xA2
140 #define RC5T583_GPIO_PGSEL      0xA3
141 #define RC5T583_GPIO_GPINV      0xA4
142 #define RC5T583_GPIO_GPDEB      0xA5
143 #define RC5T583_GPIO_GPEDGE1    0xA6
144 #define RC5T583_GPIO_GPEDGE2    0xA7
145 #define RC5T583_GPIO_EN_INT     0xA8
146 #define RC5T583_GPIO_MON_IOIN   0xAB
147 #define RC5T583_GPIO_GPOFUNC    0xAC
148
149 /* RICOH_RC5T583 IRQ definitions */
150 enum {
151         RC5T583_IRQ_ONKEY,
152         RC5T583_IRQ_ACOK,
153         RC5T583_IRQ_LIDOPEN,
154         RC5T583_IRQ_PREOT,
155         RC5T583_IRQ_CLKSTP,
156         RC5T583_IRQ_ONKEY_OFF,
157         RC5T583_IRQ_WD,
158         RC5T583_IRQ_EN_PWRREQ1,
159         RC5T583_IRQ_EN_PWRREQ2,
160         RC5T583_IRQ_PRE_VINDET,
161
162         RC5T583_IRQ_DC0LIM,
163         RC5T583_IRQ_DC1LIM,
164         RC5T583_IRQ_DC2LIM,
165         RC5T583_IRQ_DC3LIM,
166
167         RC5T583_IRQ_CTC,
168         RC5T583_IRQ_YALE,
169         RC5T583_IRQ_DALE,
170         RC5T583_IRQ_WALE,
171
172         RC5T583_IRQ_AIN1L,
173         RC5T583_IRQ_AIN2L,
174         RC5T583_IRQ_AIN3L,
175         RC5T583_IRQ_VBATL,
176         RC5T583_IRQ_VIN3L,
177         RC5T583_IRQ_VIN8L,
178         RC5T583_IRQ_AIN1H,
179         RC5T583_IRQ_AIN2H,
180         RC5T583_IRQ_AIN3H,
181         RC5T583_IRQ_VBATH,
182         RC5T583_IRQ_VIN3H,
183         RC5T583_IRQ_VIN8H,
184         RC5T583_IRQ_ADCEND,
185
186         RC5T583_IRQ_GPIO0,
187         RC5T583_IRQ_GPIO1,
188         RC5T583_IRQ_GPIO2,
189         RC5T583_IRQ_GPIO3,
190         RC5T583_IRQ_GPIO4,
191         RC5T583_IRQ_GPIO5,
192         RC5T583_IRQ_GPIO6,
193         RC5T583_IRQ_GPIO7,
194
195         /* Should be last entry */
196         RC5T583_MAX_IRQS,
197 };
198
199 /* Ricoh583 gpio definitions */
200 enum {
201         RC5T583_GPIO0,
202         RC5T583_GPIO1,
203         RC5T583_GPIO2,
204         RC5T583_GPIO3,
205         RC5T583_GPIO4,
206         RC5T583_GPIO5,
207         RC5T583_GPIO6,
208         RC5T583_GPIO7,
209
210         /* Should be last entry */
211         RC5T583_MAX_GPIO,
212 };
213
214 enum {
215         RC5T583_DS_NONE,
216         RC5T583_DS_DC0,
217         RC5T583_DS_DC1,
218         RC5T583_DS_DC2,
219         RC5T583_DS_DC3,
220         RC5T583_DS_LDO0,
221         RC5T583_DS_LDO1,
222         RC5T583_DS_LDO2,
223         RC5T583_DS_LDO3,
224         RC5T583_DS_LDO4,
225         RC5T583_DS_LDO5,
226         RC5T583_DS_LDO6,
227         RC5T583_DS_LDO7,
228         RC5T583_DS_LDO8,
229         RC5T583_DS_LDO9,
230         RC5T583_DS_PSO0,
231         RC5T583_DS_PSO1,
232         RC5T583_DS_PSO2,
233         RC5T583_DS_PSO3,
234         RC5T583_DS_PSO4,
235         RC5T583_DS_PSO5,
236         RC5T583_DS_PSO6,
237         RC5T583_DS_PSO7,
238
239         /* Should be last entry */
240         RC5T583_DS_MAX,
241 };
242
243 /*
244  * Ricoh pmic RC5T583 supports sleep through two external controls.
245  * The output of gpios and regulator can be enable/disable through
246  * this external signals.
247  */
248 enum {
249         RC5T583_EXT_PWRREQ1_CONTROL = 0x1,
250         RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
251 };
252
253 struct rc5t583 {
254         struct device   *dev;
255         struct regmap   *regmap;
256         int             chip_irq;
257         int             irq_base;
258         struct mutex    irq_lock;
259         unsigned long   group_irq_en[MAX_MAIN_INTERRUPT];
260
261         /* For main interrupt bits in INTC */
262         uint8_t         intc_inten_reg;
263
264         /* For group interrupt bits and address */
265         uint8_t         irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS];
266
267         /* For gpio edge */
268         uint8_t         gpedge_reg[RC5T583_MAX_GPEDGE_REG];
269 };
270
271 /*
272  * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
273  * The board specific data is provided through this structure.
274  * @irq_base: Irq base number on which this device registers their interrupts.
275  * @enable_shutdown: Enable shutdown through the input pin "shutdown".
276  */
277
278 struct rc5t583_platform_data {
279         int             irq_base;
280         bool            enable_shutdown;
281 };
282
283 static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val)
284 {
285         struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
286         return regmap_write(rc5t583->regmap, reg, val);
287 }
288
289 static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val)
290 {
291         struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
292         unsigned int ival;
293         int ret;
294         ret = regmap_read(rc5t583->regmap, reg, &ival);
295         if (!ret)
296                 *val = (uint8_t)ival;
297         return ret;
298 }
299
300 static inline int rc5t583_set_bits(struct device *dev, unsigned int reg,
301                         unsigned int bit_mask)
302 {
303         struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
304         return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask);
305 }
306
307 static inline int rc5t583_clear_bits(struct device *dev, unsigned int reg,
308                         unsigned int bit_mask)
309 {
310         struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
311         return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0);
312 }
313
314 static inline int rc5t583_update(struct device *dev, unsigned int reg,
315                 unsigned int val, unsigned int mask)
316 {
317         struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
318         return regmap_update_bits(rc5t583->regmap, reg, mask, val);
319 }
320
321 int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id,
322         int ext_pwr_req, int deepsleep_slot_nr);
323 int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base);
324 int rc5t583_irq_exit(struct rc5t583 *rc5t583);
325
326 #endif