Remove tas()
[linux-2.6.git] / include / asm-x86_64 / system.h
1 #ifndef __ASM_SYSTEM_H
2 #define __ASM_SYSTEM_H
3
4 #include <linux/kernel.h>
5 #include <asm/segment.h>
6 #include <asm/alternative.h>
7
8 #ifdef __KERNEL__
9
10 #define __STR(x) #x
11 #define STR(x) __STR(x)
12
13 #define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
14 #define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
15
16 /* frame pointer must be last for get_wchan */
17 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
18 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
19
20 #define __EXTRA_CLOBBER  \
21         ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
22
23 /* Save restore flags to clear handle leaking NT */
24 #define switch_to(prev,next,last) \
25         asm volatile(SAVE_CONTEXT                                                   \
26                      "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
27                      "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
28                      "call __switch_to\n\t"                                       \
29                      ".globl thread_return\n"                                   \
30                      "thread_return:\n\t"                                           \
31                      "movq %%gs:%P[pda_pcurrent],%%rsi\n\t"                       \
32                      "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
33                      LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"        \
34                      "movq %%rax,%%rdi\n\t"                                       \
35                      "jc   ret_from_fork\n\t"                                     \
36                      RESTORE_CONTEXT                                                \
37                      : "=a" (last)                                                \
38                      : [next] "S" (next), [prev] "D" (prev),                      \
39                        [threadrsp] "i" (offsetof(struct task_struct, thread.rsp)), \
40                        [ti_flags] "i" (offsetof(struct thread_info, flags)),\
41                        [tif_fork] "i" (TIF_FORK),                         \
42                        [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
43                        [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent))   \
44                      : "memory", "cc" __EXTRA_CLOBBER)
45     
46 extern void load_gs_index(unsigned); 
47
48 /*
49  * Load a segment. Fall back on loading the zero
50  * segment if something goes wrong..
51  */
52 #define loadsegment(seg,value)  \
53         asm volatile("\n"                       \
54                 "1:\t"                          \
55                 "movl %k0,%%" #seg "\n"         \
56                 "2:\n"                          \
57                 ".section .fixup,\"ax\"\n"      \
58                 "3:\t"                          \
59                 "movl %1,%%" #seg "\n\t"        \
60                 "jmp 2b\n"                      \
61                 ".previous\n"                   \
62                 ".section __ex_table,\"a\"\n\t" \
63                 ".align 8\n\t"                  \
64                 ".quad 1b,3b\n"                 \
65                 ".previous"                     \
66                 : :"r" (value), "r" (0))
67
68 /*
69  * Clear and set 'TS' bit respectively
70  */
71 #define clts() __asm__ __volatile__ ("clts")
72
73 static inline unsigned long read_cr0(void)
74
75         unsigned long cr0;
76         asm volatile("movq %%cr0,%0" : "=r" (cr0));
77         return cr0;
78
79
80 static inline void write_cr0(unsigned long val) 
81
82         asm volatile("movq %0,%%cr0" :: "r" (val));
83
84
85 static inline unsigned long read_cr3(void)
86
87         unsigned long cr3;
88         asm("movq %%cr3,%0" : "=r" (cr3));
89         return cr3;
90
91
92 static inline void write_cr3(unsigned long val)
93 {
94         asm volatile("movq %0,%%cr3" :: "r" (val) : "memory");
95 }
96
97 static inline unsigned long read_cr4(void)
98
99         unsigned long cr4;
100         asm("movq %%cr4,%0" : "=r" (cr4));
101         return cr4;
102
103
104 static inline void write_cr4(unsigned long val)
105
106         asm volatile("movq %0,%%cr4" :: "r" (val) : "memory");
107
108
109 #define stts() write_cr0(8 | read_cr0())
110
111 #define wbinvd() \
112         __asm__ __volatile__ ("wbinvd": : :"memory");
113
114 /*
115  * On SMP systems, when the scheduler does migration-cost autodetection,
116  * it needs a way to flush as much of the CPU's caches as possible.
117  */
118 static inline void sched_cacheflush(void)
119 {
120         wbinvd();
121 }
122
123 #endif  /* __KERNEL__ */
124
125 #define nop() __asm__ __volatile__ ("nop")
126
127 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
128
129 #define __xg(x) ((volatile long *)(x))
130
131 static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
132 {
133         *ptr = val;
134 }
135
136 #define _set_64bit set_64bit
137
138 /*
139  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
140  * Note 2: xchg has side effect, so that attribute volatile is necessary,
141  *        but generally the primitive is invalid, *ptr is output argument. --ANK
142  */
143 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
144 {
145         switch (size) {
146                 case 1:
147                         __asm__ __volatile__("xchgb %b0,%1"
148                                 :"=q" (x)
149                                 :"m" (*__xg(ptr)), "0" (x)
150                                 :"memory");
151                         break;
152                 case 2:
153                         __asm__ __volatile__("xchgw %w0,%1"
154                                 :"=r" (x)
155                                 :"m" (*__xg(ptr)), "0" (x)
156                                 :"memory");
157                         break;
158                 case 4:
159                         __asm__ __volatile__("xchgl %k0,%1"
160                                 :"=r" (x)
161                                 :"m" (*__xg(ptr)), "0" (x)
162                                 :"memory");
163                         break;
164                 case 8:
165                         __asm__ __volatile__("xchgq %0,%1"
166                                 :"=r" (x)
167                                 :"m" (*__xg(ptr)), "0" (x)
168                                 :"memory");
169                         break;
170         }
171         return x;
172 }
173
174 /*
175  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
176  * store NEW in MEM.  Return the initial value in MEM.  Success is
177  * indicated by comparing RETURN with OLD.
178  */
179
180 #define __HAVE_ARCH_CMPXCHG 1
181
182 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
183                                       unsigned long new, int size)
184 {
185         unsigned long prev;
186         switch (size) {
187         case 1:
188                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
189                                      : "=a"(prev)
190                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
191                                      : "memory");
192                 return prev;
193         case 2:
194                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
195                                      : "=a"(prev)
196                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
197                                      : "memory");
198                 return prev;
199         case 4:
200                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %k1,%2"
201                                      : "=a"(prev)
202                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
203                                      : "memory");
204                 return prev;
205         case 8:
206                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgq %1,%2"
207                                      : "=a"(prev)
208                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
209                                      : "memory");
210                 return prev;
211         }
212         return old;
213 }
214
215 static inline unsigned long __cmpxchg_local(volatile void *ptr,
216                         unsigned long old, unsigned long new, int size)
217 {
218         unsigned long prev;
219         switch (size) {
220         case 1:
221                 __asm__ __volatile__("cmpxchgb %b1,%2"
222                                      : "=a"(prev)
223                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
224                                      : "memory");
225                 return prev;
226         case 2:
227                 __asm__ __volatile__("cmpxchgw %w1,%2"
228                                      : "=a"(prev)
229                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
230                                      : "memory");
231                 return prev;
232         case 4:
233                 __asm__ __volatile__("cmpxchgl %k1,%2"
234                                      : "=a"(prev)
235                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
236                                      : "memory");
237                 return prev;
238         case 8:
239                 __asm__ __volatile__("cmpxchgq %1,%2"
240                                      : "=a"(prev)
241                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
242                                      : "memory");
243                 return prev;
244         }
245         return old;
246 }
247
248 #define cmpxchg(ptr,o,n)\
249         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
250                                         (unsigned long)(n),sizeof(*(ptr))))
251 #define cmpxchg_local(ptr,o,n)\
252         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
253                                         (unsigned long)(n),sizeof(*(ptr))))
254
255 #ifdef CONFIG_SMP
256 #define smp_mb()        mb()
257 #define smp_rmb()       rmb()
258 #define smp_wmb()       wmb()
259 #define smp_read_barrier_depends()      do {} while(0)
260 #else
261 #define smp_mb()        barrier()
262 #define smp_rmb()       barrier()
263 #define smp_wmb()       barrier()
264 #define smp_read_barrier_depends()      do {} while(0)
265 #endif
266
267     
268 /*
269  * Force strict CPU ordering.
270  * And yes, this is required on UP too when we're talking
271  * to devices.
272  */
273 #define mb()    asm volatile("mfence":::"memory")
274 #define rmb()   asm volatile("lfence":::"memory")
275
276 #ifdef CONFIG_UNORDERED_IO
277 #define wmb()   asm volatile("sfence" ::: "memory")
278 #else
279 #define wmb()   asm volatile("" ::: "memory")
280 #endif
281 #define read_barrier_depends()  do {} while(0)
282 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
283
284 #define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
285
286 #include <linux/irqflags.h>
287
288 void cpu_idle_wait(void);
289
290 extern unsigned long arch_align_stack(unsigned long sp);
291 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
292
293 #endif