2 * Copyright (C) 1994 Linus Torvalds
5 #ifndef __ASM_I386_PROCESSOR_H
6 #define __ASM_I386_PROCESSOR_H
9 #include <asm/math_emu.h>
10 #include <asm/segment.h>
12 #include <asm/types.h>
13 #include <asm/sigcontext.h>
14 #include <asm/cpufeature.h>
16 #include <asm/system.h>
17 #include <linux/cache.h>
18 #include <linux/threads.h>
19 #include <asm/percpu.h>
20 #include <linux/cpumask.h>
21 #include <linux/init.h>
22 #include <asm/processor-flags.h>
24 /* flag for disabling the tsc */
25 extern int tsc_disable;
31 static inline int desc_empty(const void *ptr)
33 const u32 *desc = ptr;
34 return !(desc[0] | desc[1]);
38 * Default implementation of macro that returns current
39 * instruction pointer ("program counter").
41 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
44 * CPU type and hardware bug flags. Kept separately for each CPU.
45 * Members of this structure are referenced in head.S, so think twice
46 * before touching them. [mj]
50 __u8 x86; /* CPU family */
51 __u8 x86_vendor; /* CPU vendor */
54 char wp_works_ok; /* It doesn't on 386's */
55 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
58 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
59 unsigned long x86_capability[NCAPINTS];
60 char x86_vendor_id[16];
61 char x86_model_id[64];
62 int x86_cache_size; /* in KB - valid for CPUS which support this
64 int x86_cache_alignment; /* In bytes */
70 unsigned long loops_per_jiffy;
72 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
74 unsigned char x86_max_cores; /* cpuid returned max cores value */
76 unsigned short x86_clflush_size;
78 unsigned char booted_cores; /* number of cores as seen by OS */
79 __u8 phys_proc_id; /* Physical processor id. */
80 __u8 cpu_core_id; /* Core id */
81 __u8 cpu_index; /* index into per_cpu list */
83 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
85 #define X86_VENDOR_INTEL 0
86 #define X86_VENDOR_CYRIX 1
87 #define X86_VENDOR_AMD 2
88 #define X86_VENDOR_UMC 3
89 #define X86_VENDOR_NEXGEN 4
90 #define X86_VENDOR_CENTAUR 5
91 #define X86_VENDOR_TRANSMETA 7
92 #define X86_VENDOR_NSC 8
93 #define X86_VENDOR_NUM 9
94 #define X86_VENDOR_UNKNOWN 0xff
97 * capabilities of CPUs
100 extern struct cpuinfo_x86 boot_cpu_data;
101 extern struct cpuinfo_x86 new_cpu_data;
102 extern struct tss_struct doublefault_tss;
103 DECLARE_PER_CPU(struct tss_struct, init_tss);
106 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
107 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
108 #define current_cpu_data cpu_data(smp_processor_id())
110 #define cpu_data(cpu) boot_cpu_data
111 #define current_cpu_data boot_cpu_data
115 * the following now lives in the per cpu area:
116 * extern int cpu_llc_id[NR_CPUS];
118 DECLARE_PER_CPU(u8, cpu_llc_id);
119 extern char ignore_fpu_irq;
121 void __init cpu_detect(struct cpuinfo_x86 *c);
123 extern void identify_boot_cpu(void);
124 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
125 extern void print_cpu_info(struct cpuinfo_x86 *);
126 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
127 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
128 extern unsigned short num_cache_leaves;
131 extern void detect_ht(struct cpuinfo_x86 *c);
133 static inline void detect_ht(struct cpuinfo_x86 *c) {}
136 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
137 unsigned int *ecx, unsigned int *edx)
139 /* ecx is often an input as well as an output. */
145 : "0" (*eax), "2" (*ecx));
148 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
151 * Save the cr4 feature set we're using (ie
152 * Pentium 4MB enable and PPro Global page
153 * enable), so that any CPU's that boot up
154 * after us can get the correct flags.
156 extern unsigned long mmu_cr4_features;
158 static inline void set_in_cr4 (unsigned long mask)
161 mmu_cr4_features |= mask;
167 static inline void clear_in_cr4 (unsigned long mask)
170 mmu_cr4_features &= ~mask;
176 /* Stop speculative execution */
177 static inline void sync_core(void)
180 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
183 static inline void __monitor(const void *eax, unsigned long ecx,
186 /* "monitor %eax,%ecx,%edx;" */
188 ".byte 0x0f,0x01,0xc8;"
189 : :"a" (eax), "c" (ecx), "d"(edx));
192 static inline void __mwait(unsigned long eax, unsigned long ecx)
194 /* "mwait %eax,%ecx;" */
196 ".byte 0x0f,0x01,0xc9;"
197 : :"a" (eax), "c" (ecx));
200 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
202 /* from system description table in BIOS. Mostly for MCA use, but
203 others may find it useful. */
204 extern unsigned int machine_id;
205 extern unsigned int machine_submodel_id;
206 extern unsigned int BIOS_revision;
207 extern unsigned int mca_pentium_flag;
209 /* Boot loader type from the setup header */
210 extern int bootloader_type;
213 * User space process size: 3GB (default).
215 #define TASK_SIZE (PAGE_OFFSET)
217 /* This decides where the kernel will search for a free chunk of vm
218 * space during mmap's.
220 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
222 #define HAVE_ARCH_PICK_MMAP_LAYOUT
224 extern void hard_disable_TSC(void);
225 extern void disable_TSC(void);
226 extern void hard_enable_TSC(void);
231 #define IO_BITMAP_BITS 65536
232 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
233 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
234 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
235 #define INVALID_IO_BITMAP_OFFSET 0x8000
236 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
238 struct i387_fsave_struct {
246 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
247 long status; /* software status information */
250 struct i387_fxsave_struct {
261 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
262 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
264 } __attribute__ ((aligned (16)));
266 struct i387_soft_struct {
274 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
275 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
277 unsigned long entry_eip;
281 struct i387_fsave_struct fsave;
282 struct i387_fxsave_struct fxsave;
283 struct i387_soft_struct soft;
290 struct thread_struct;
292 /* This is the TSS defined by the hardware. */
294 unsigned short back_link,__blh;
296 unsigned short ss0,__ss0h;
298 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
300 unsigned short ss2,__ss2h;
303 unsigned long eflags;
304 unsigned long eax,ecx,edx,ebx;
309 unsigned short es, __esh;
310 unsigned short cs, __csh;
311 unsigned short ss, __ssh;
312 unsigned short ds, __dsh;
313 unsigned short fs, __fsh;
314 unsigned short gs, __gsh;
315 unsigned short ldt, __ldth;
316 unsigned short trace, io_bitmap_base;
317 } __attribute__((packed));
320 struct i386_hw_tss x86_tss;
323 * The extra 1 is there because the CPU will access an
324 * additional byte beyond the end of the IO permission
325 * bitmap. The extra byte must be all 1 bits, and must
326 * be within the limit.
328 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
330 * Cache the current maximum and the last task that used the bitmap:
332 unsigned long io_bitmap_max;
333 struct thread_struct *io_bitmap_owner;
335 * pads the TSS to be cacheline-aligned (size is 0x100)
337 unsigned long __cacheline_filler[35];
339 * .. and then another 0x100 bytes for emergency kernel stack
341 unsigned long stack[64];
342 } __attribute__((packed));
344 #define ARCH_MIN_TASKALIGN 16
346 struct thread_struct {
347 /* cached TLS descriptors. */
348 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
350 unsigned long sysenter_cs;
355 /* Hardware debugging registers */
356 unsigned long debugreg[8]; /* %%db0-7 debug registers */
358 unsigned long cr2, trap_no, error_code;
359 /* floating point info */
360 union i387_union i387;
361 /* virtual 86 mode info */
362 struct vm86_struct __user * vm86_info;
363 unsigned long screen_bitmap;
364 unsigned long v86flags, v86mask, saved_esp0;
365 unsigned int saved_fs, saved_gs;
367 unsigned long *io_bitmap_ptr;
369 /* max allowed port in the bitmap, in bytes: */
370 unsigned long io_bitmap_max;
373 #define INIT_THREAD { \
374 .esp0 = sizeof(init_stack) + (long)&init_stack, \
376 .sysenter_cs = __KERNEL_CS, \
377 .io_bitmap_ptr = NULL, \
378 .fs = __KERNEL_PERCPU, \
382 * Note that the .io_bitmap member must be extra-big. This is because
383 * the CPU will access an additional byte beyond the end of the IO
384 * permission bitmap. The extra byte must be all 1 bits, and must
385 * be within the limit.
389 .esp0 = sizeof(init_stack) + (long)&init_stack, \
390 .ss0 = __KERNEL_DS, \
391 .ss1 = __KERNEL_CS, \
392 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
394 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
397 #define start_thread(regs, new_eip, new_esp) do { \
398 __asm__("movl %0,%%gs": :"r" (0)); \
401 regs->xds = __USER_DS; \
402 regs->xes = __USER_DS; \
403 regs->xss = __USER_DS; \
404 regs->xcs = __USER_CS; \
405 regs->eip = new_eip; \
406 regs->esp = new_esp; \
409 /* Forward declaration, a strange C thing */
413 /* Free all resources held by a thread. */
414 extern void release_thread(struct task_struct *);
416 /* Prepare to copy thread state - unlazy all lazy status */
417 extern void prepare_to_copy(struct task_struct *tsk);
420 * create a kernel thread without removing it from tasklists
422 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
424 extern unsigned long thread_saved_pc(struct task_struct *tsk);
426 unsigned long get_wchan(struct task_struct *p);
428 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
429 #define KSTK_TOP(info) \
431 unsigned long *__ptr = (unsigned long *)(info); \
432 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
436 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
437 * This is necessary to guarantee that the entire "struct pt_regs"
438 * is accessable even if the CPU haven't stored the SS/ESP registers
439 * on the stack (interrupt gate does not save these registers
440 * when switching to the same priv ring).
441 * Therefore beware: accessing the xss/esp fields of the
442 * "struct pt_regs" is possible, but they may contain the
443 * completely wrong values.
445 #define task_pt_regs(task) \
447 struct pt_regs *__regs__; \
448 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
452 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
453 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
456 struct microcode_header {
464 unsigned int datasize;
465 unsigned int totalsize;
466 unsigned int reserved[3];
470 struct microcode_header hdr;
471 unsigned int bits[0];
474 typedef struct microcode microcode_t;
475 typedef struct microcode_header microcode_header_t;
477 /* microcode format is extended from prescott processors */
478 struct extended_signature {
484 struct extended_sigtable {
487 unsigned int reserved[3];
488 struct extended_signature sigs[0];
491 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
492 static inline void rep_nop(void)
494 __asm__ __volatile__("rep;nop": : :"memory");
497 #define cpu_relax() rep_nop()
499 static inline void native_load_esp0(struct tss_struct *tss, struct thread_struct *thread)
501 tss->x86_tss.esp0 = thread->esp0;
502 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
503 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
504 tss->x86_tss.ss1 = thread->sysenter_cs;
505 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
510 static inline unsigned long native_get_debugreg(int regno)
512 unsigned long val = 0; /* Damn you, gcc! */
516 asm("movl %%db0, %0" :"=r" (val)); break;
518 asm("movl %%db1, %0" :"=r" (val)); break;
520 asm("movl %%db2, %0" :"=r" (val)); break;
522 asm("movl %%db3, %0" :"=r" (val)); break;
524 asm("movl %%db6, %0" :"=r" (val)); break;
526 asm("movl %%db7, %0" :"=r" (val)); break;
533 static inline void native_set_debugreg(int regno, unsigned long value)
537 asm("movl %0,%%db0" : /* no output */ :"r" (value));
540 asm("movl %0,%%db1" : /* no output */ :"r" (value));
543 asm("movl %0,%%db2" : /* no output */ :"r" (value));
546 asm("movl %0,%%db3" : /* no output */ :"r" (value));
549 asm("movl %0,%%db6" : /* no output */ :"r" (value));
552 asm("movl %0,%%db7" : /* no output */ :"r" (value));
560 * Set IOPL bits in EFLAGS from given mask
562 static inline void native_set_iopl_mask(unsigned mask)
565 __asm__ __volatile__ ("pushfl;"
572 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
575 #ifdef CONFIG_PARAVIRT
576 #include <asm/paravirt.h>
578 #define paravirt_enabled() 0
579 #define __cpuid native_cpuid
581 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
583 native_load_esp0(tss, thread);
587 * These special macros can be used to get or set a debugging register
589 #define get_debugreg(var, register) \
590 (var) = native_get_debugreg(register)
591 #define set_debugreg(value, register) \
592 native_set_debugreg(register, value)
594 #define set_iopl_mask native_set_iopl_mask
595 #endif /* CONFIG_PARAVIRT */
598 * Generic CPUID function
599 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
600 * resulting in stale register contents being returned.
602 static inline void cpuid(unsigned int op,
603 unsigned int *eax, unsigned int *ebx,
604 unsigned int *ecx, unsigned int *edx)
608 __cpuid(eax, ebx, ecx, edx);
611 /* Some CPUID calls want 'count' to be placed in ecx */
612 static inline void cpuid_count(unsigned int op, int count,
613 unsigned int *eax, unsigned int *ebx,
614 unsigned int *ecx, unsigned int *edx)
618 __cpuid(eax, ebx, ecx, edx);
622 * CPUID functions returning a single datum
624 static inline unsigned int cpuid_eax(unsigned int op)
626 unsigned int eax, ebx, ecx, edx;
628 cpuid(op, &eax, &ebx, &ecx, &edx);
631 static inline unsigned int cpuid_ebx(unsigned int op)
633 unsigned int eax, ebx, ecx, edx;
635 cpuid(op, &eax, &ebx, &ecx, &edx);
638 static inline unsigned int cpuid_ecx(unsigned int op)
640 unsigned int eax, ebx, ecx, edx;
642 cpuid(op, &eax, &ebx, &ecx, &edx);
645 static inline unsigned int cpuid_edx(unsigned int op)
647 unsigned int eax, ebx, ecx, edx;
649 cpuid(op, &eax, &ebx, &ecx, &edx);
653 /* generic versions from gas */
654 #define GENERIC_NOP1 ".byte 0x90\n"
655 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
656 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
657 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
658 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
659 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
660 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
661 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
664 #define K8_NOP1 GENERIC_NOP1
665 #define K8_NOP2 ".byte 0x66,0x90\n"
666 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
667 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
668 #define K8_NOP5 K8_NOP3 K8_NOP2
669 #define K8_NOP6 K8_NOP3 K8_NOP3
670 #define K8_NOP7 K8_NOP4 K8_NOP3
671 #define K8_NOP8 K8_NOP4 K8_NOP4
674 /* uses eax dependencies (arbitary choice) */
675 #define K7_NOP1 GENERIC_NOP1
676 #define K7_NOP2 ".byte 0x8b,0xc0\n"
677 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
678 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
679 #define K7_NOP5 K7_NOP4 ASM_NOP1
680 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
681 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
682 #define K7_NOP8 K7_NOP7 ASM_NOP1
685 /* uses eax dependencies (Intel-recommended choice) */
686 #define P6_NOP1 GENERIC_NOP1
687 #define P6_NOP2 ".byte 0x66,0x90\n"
688 #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
689 #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
690 #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
691 #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
692 #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
693 #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
696 #define ASM_NOP1 K8_NOP1
697 #define ASM_NOP2 K8_NOP2
698 #define ASM_NOP3 K8_NOP3
699 #define ASM_NOP4 K8_NOP4
700 #define ASM_NOP5 K8_NOP5
701 #define ASM_NOP6 K8_NOP6
702 #define ASM_NOP7 K8_NOP7
703 #define ASM_NOP8 K8_NOP8
704 #elif defined(CONFIG_MK7)
705 #define ASM_NOP1 K7_NOP1
706 #define ASM_NOP2 K7_NOP2
707 #define ASM_NOP3 K7_NOP3
708 #define ASM_NOP4 K7_NOP4
709 #define ASM_NOP5 K7_NOP5
710 #define ASM_NOP6 K7_NOP6
711 #define ASM_NOP7 K7_NOP7
712 #define ASM_NOP8 K7_NOP8
713 #elif defined(CONFIG_M686) || defined(CONFIG_MPENTIUMII) || \
714 defined(CONFIG_MPENTIUMIII) || defined(CONFIG_MPENTIUMM) || \
715 defined(CONFIG_MCORE2) || defined(CONFIG_PENTIUM4)
716 #define ASM_NOP1 P6_NOP1
717 #define ASM_NOP2 P6_NOP2
718 #define ASM_NOP3 P6_NOP3
719 #define ASM_NOP4 P6_NOP4
720 #define ASM_NOP5 P6_NOP5
721 #define ASM_NOP6 P6_NOP6
722 #define ASM_NOP7 P6_NOP7
723 #define ASM_NOP8 P6_NOP8
725 #define ASM_NOP1 GENERIC_NOP1
726 #define ASM_NOP2 GENERIC_NOP2
727 #define ASM_NOP3 GENERIC_NOP3
728 #define ASM_NOP4 GENERIC_NOP4
729 #define ASM_NOP5 GENERIC_NOP5
730 #define ASM_NOP6 GENERIC_NOP6
731 #define ASM_NOP7 GENERIC_NOP7
732 #define ASM_NOP8 GENERIC_NOP8
735 #define ASM_NOP_MAX 8
737 /* Prefetch instructions for Pentium III and AMD Athlon */
738 /* It's not worth to care about 3dnow! prefetches for the K6
739 because they are microcoded there and very slow.
740 However we don't do prefetches for pre XP Athlons currently
741 That should be fixed. */
742 #define ARCH_HAS_PREFETCH
743 static inline void prefetch(const void *x)
745 alternative_input(ASM_NOP4,
751 #define ARCH_HAS_PREFETCH
752 #define ARCH_HAS_PREFETCHW
753 #define ARCH_HAS_SPINLOCK_PREFETCH
755 /* 3dnow! prefetch to get an exclusive cache line. Useful for
756 spinlocks to avoid one state transition in the cache coherency protocol. */
757 static inline void prefetchw(const void *x)
759 alternative_input(ASM_NOP4,
764 #define spin_lock_prefetch(x) prefetchw(x)
766 extern void select_idle_routine(const struct cpuinfo_x86 *c);
768 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
770 extern unsigned long boot_option_idle_override;
771 extern void enable_sep_cpu(void);
772 extern int sysenter_setup(void);
774 /* Defined in head.S */
775 extern struct Xgt_desc_struct early_gdt_descr;
777 extern void cpu_set_gdt(int);
778 extern void switch_to_new_gdt(void);
779 extern void cpu_init(void);
780 extern void init_gdt(int cpu);
782 extern int force_mwait;
784 #endif /* __ASM_I386_PROCESSOR_H */