Remove tas()
[linux-2.6.git] / include / asm-sparc64 / system.h
1 /* $Id: system.h,v 1.69 2002/02/09 19:49:31 davem Exp $ */
2 #ifndef __SPARC64_SYSTEM_H
3 #define __SPARC64_SYSTEM_H
4
5 #include <asm/ptrace.h>
6 #include <asm/processor.h>
7 #include <asm/visasm.h>
8
9 #ifndef __ASSEMBLY__
10
11 #include <linux/irqflags.h>
12
13 /*
14  * Sparc (general) CPU types
15  */
16 enum sparc_cpu {
17   sun4        = 0x00,
18   sun4c       = 0x01,
19   sun4m       = 0x02,
20   sun4d       = 0x03,
21   sun4e       = 0x04,
22   sun4u       = 0x05, /* V8 ploos ploos */
23   sun_unknown = 0x06,
24   ap1000      = 0x07, /* almost a sun4m */
25 };
26                   
27 #define sparc_cpu_model sun4u
28
29 /* This cannot ever be a sun4c nor sun4 :) That's just history. */
30 #define ARCH_SUN4C_SUN4 0
31 #define ARCH_SUN4 0
32
33 /* These are here in an effort to more fully work around Spitfire Errata
34  * #51.  Essentially, if a memory barrier occurs soon after a mispredicted
35  * branch, the chip can stop executing instructions until a trap occurs.
36  * Therefore, if interrupts are disabled, the chip can hang forever.
37  *
38  * It used to be believed that the memory barrier had to be right in the
39  * delay slot, but a case has been traced recently wherein the memory barrier
40  * was one instruction after the branch delay slot and the chip still hung.
41  * The offending sequence was the following in sym_wakeup_done() of the
42  * sym53c8xx_2 driver:
43  *
44  *      call    sym_ccb_from_dsa, 0
45  *       movge  %icc, 0, %l0
46  *      brz,pn  %o0, .LL1303
47  *       mov    %o0, %l2
48  *      membar  #LoadLoad
49  *
50  * The branch has to be mispredicted for the bug to occur.  Therefore, we put
51  * the memory barrier explicitly into a "branch always, predicted taken"
52  * delay slot to avoid the problem case.
53  */
54 #define membar_safe(type) \
55 do {    __asm__ __volatile__("ba,pt     %%xcc, 1f\n\t" \
56                              " membar   " type "\n" \
57                              "1:\n" \
58                              : : : "memory"); \
59 } while (0)
60
61 #define mb()    \
62         membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
63 #define rmb()   \
64         membar_safe("#LoadLoad")
65 #define wmb()   \
66         membar_safe("#StoreStore")
67 #define membar_storeload() \
68         membar_safe("#StoreLoad")
69 #define membar_storeload_storestore() \
70         membar_safe("#StoreLoad | #StoreStore")
71 #define membar_storeload_loadload() \
72         membar_safe("#StoreLoad | #LoadLoad")
73 #define membar_storestore_loadstore() \
74         membar_safe("#StoreStore | #LoadStore")
75
76 #endif
77
78 #define nop()           __asm__ __volatile__ ("nop")
79
80 #define read_barrier_depends()          do { } while(0)
81 #define set_mb(__var, __value) \
82         do { __var = __value; membar_storeload_storestore(); } while(0)
83
84 #ifdef CONFIG_SMP
85 #define smp_mb()        mb()
86 #define smp_rmb()       rmb()
87 #define smp_wmb()       wmb()
88 #define smp_read_barrier_depends()      read_barrier_depends()
89 #else
90 #define smp_mb()        __asm__ __volatile__("":::"memory")
91 #define smp_rmb()       __asm__ __volatile__("":::"memory")
92 #define smp_wmb()       __asm__ __volatile__("":::"memory")
93 #define smp_read_barrier_depends()      do { } while(0)
94 #endif
95
96 #define flushi(addr)    __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
97
98 #define flushw_all()    __asm__ __volatile__("flushw")
99
100 /* Performance counter register access. */
101 #define read_pcr(__p)  __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
102 #define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
103 #define read_pic(__p)  __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
104
105 /* Blackbird errata workaround.  See commentary in
106  * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
107  * for more information.
108  */
109 #define reset_pic()                                             \
110         __asm__ __volatile__("ba,pt     %xcc, 99f\n\t"          \
111                              ".align    64\n"                   \
112                           "99:wr        %g0, 0x0, %pic\n\t"     \
113                              "rd        %pic, %g0")
114
115 #ifndef __ASSEMBLY__
116
117 extern void sun_do_break(void);
118 extern int serial_console;
119 extern int stop_a_enabled;
120
121 static __inline__ int con_is_present(void)
122 {
123         return serial_console ? 0 : 1;
124 }
125
126 extern void synchronize_user_stack(void);
127
128 extern void __flushw_user(void);
129 #define flushw_user() __flushw_user()
130
131 #define flush_user_windows flushw_user
132 #define flush_register_windows flushw_all
133
134 /* Don't hold the runqueue lock over context switch */
135 #define __ARCH_WANT_UNLOCKED_CTXSW
136 #define prepare_arch_switch(next)               \
137 do {                                            \
138         flushw_all();                           \
139 } while (0)
140
141         /* See what happens when you design the chip correctly?
142          *
143          * We tell gcc we clobber all non-fixed-usage registers except
144          * for l0/l1.  It will use one for 'next' and the other to hold
145          * the output value of 'last'.  'next' is not referenced again
146          * past the invocation of switch_to in the scheduler, so we need
147          * not preserve it's value.  Hairy, but it lets us remove 2 loads
148          * and 2 stores in this critical code path.  -DaveM
149          */
150 #define EXTRA_CLOBBER ,"%l1"
151 #define switch_to(prev, next, last)                                     \
152 do {    if (test_thread_flag(TIF_PERFCTR)) {                            \
153                 unsigned long __tmp;                                    \
154                 read_pcr(__tmp);                                        \
155                 current_thread_info()->pcr_reg = __tmp;                 \
156                 read_pic(__tmp);                                        \
157                 current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
158                 current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
159         }                                                               \
160         flush_tlb_pending();                                            \
161         save_and_clear_fpu();                                           \
162         /* If you are tempted to conditionalize the following */        \
163         /* so that ASI is only written if it changes, think again. */   \
164         __asm__ __volatile__("wr %%g0, %0, %%asi"                       \
165         : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
166         trap_block[current_thread_info()->cpu].thread =                 \
167                 task_thread_info(next);                                 \
168         __asm__ __volatile__(                                           \
169         "mov    %%g4, %%g7\n\t"                                         \
170         "stx    %%i6, [%%sp + 2047 + 0x70]\n\t"                         \
171         "stx    %%i7, [%%sp + 2047 + 0x78]\n\t"                         \
172         "rdpr   %%wstate, %%o5\n\t"                                     \
173         "stx    %%o6, [%%g6 + %3]\n\t"                                  \
174         "stb    %%o5, [%%g6 + %2]\n\t"                                  \
175         "rdpr   %%cwp, %%o5\n\t"                                        \
176         "stb    %%o5, [%%g6 + %5]\n\t"                                  \
177         "mov    %1, %%g6\n\t"                                           \
178         "ldub   [%1 + %5], %%g1\n\t"                                    \
179         "wrpr   %%g1, %%cwp\n\t"                                        \
180         "ldx    [%%g6 + %3], %%o6\n\t"                                  \
181         "ldub   [%%g6 + %2], %%o5\n\t"                                  \
182         "ldub   [%%g6 + %4], %%o7\n\t"                                  \
183         "wrpr   %%o5, 0x0, %%wstate\n\t"                                \
184         "ldx    [%%sp + 2047 + 0x70], %%i6\n\t"                         \
185         "ldx    [%%sp + 2047 + 0x78], %%i7\n\t"                         \
186         "ldx    [%%g6 + %6], %%g4\n\t"                                  \
187         "brz,pt %%o7, 1f\n\t"                                           \
188         " mov   %%g7, %0\n\t"                                           \
189         "b,a ret_from_syscall\n\t"                                      \
190         "1:\n\t"                                                        \
191         : "=&r" (last)                                                  \
192         : "0" (task_thread_info(next)),                                 \
193           "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD),            \
194           "i" (TI_CWP), "i" (TI_TASK)                                   \
195         : "cc",                                                         \
196                 "g1", "g2", "g3",                   "g7",               \
197                       "l2", "l3", "l4", "l5", "l6", "l7",               \
198           "i0", "i1", "i2", "i3", "i4", "i5",                           \
199           "o0", "o1", "o2", "o3", "o4", "o5",       "o7" EXTRA_CLOBBER);\
200         /* If you fuck with this, update ret_from_syscall code too. */  \
201         if (test_thread_flag(TIF_PERFCTR)) {                            \
202                 write_pcr(current_thread_info()->pcr_reg);              \
203                 reset_pic();                                            \
204         }                                                               \
205 } while(0)
206
207 /*
208  * On SMP systems, when the scheduler does migration-cost autodetection,
209  * it needs a way to flush as much of the CPU's caches as possible.
210  *
211  * TODO: fill this in!
212  */
213 static inline void sched_cacheflush(void)
214 {
215 }
216
217 static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
218 {
219         unsigned long tmp1, tmp2;
220
221         __asm__ __volatile__(
222 "       membar          #StoreLoad | #LoadLoad\n"
223 "       mov             %0, %1\n"
224 "1:     lduw            [%4], %2\n"
225 "       cas             [%4], %2, %0\n"
226 "       cmp             %2, %0\n"
227 "       bne,a,pn        %%icc, 1b\n"
228 "        mov            %1, %0\n"
229 "       membar          #StoreLoad | #StoreStore\n"
230         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
231         : "0" (val), "r" (m)
232         : "cc", "memory");
233         return val;
234 }
235
236 static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
237 {
238         unsigned long tmp1, tmp2;
239
240         __asm__ __volatile__(
241 "       membar          #StoreLoad | #LoadLoad\n"
242 "       mov             %0, %1\n"
243 "1:     ldx             [%4], %2\n"
244 "       casx            [%4], %2, %0\n"
245 "       cmp             %2, %0\n"
246 "       bne,a,pn        %%xcc, 1b\n"
247 "        mov            %1, %0\n"
248 "       membar          #StoreLoad | #StoreStore\n"
249         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
250         : "0" (val), "r" (m)
251         : "cc", "memory");
252         return val;
253 }
254
255 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
256
257 extern void __xchg_called_with_bad_pointer(void);
258
259 static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
260                                        int size)
261 {
262         switch (size) {
263         case 4:
264                 return xchg32(ptr, x);
265         case 8:
266                 return xchg64(ptr, x);
267         };
268         __xchg_called_with_bad_pointer();
269         return x;
270 }
271
272 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
273
274 /* 
275  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
276  * store NEW in MEM.  Return the initial value in MEM.  Success is
277  * indicated by comparing RETURN with OLD.
278  */
279
280 #define __HAVE_ARCH_CMPXCHG 1
281
282 static __inline__ unsigned long
283 __cmpxchg_u32(volatile int *m, int old, int new)
284 {
285         __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
286                              "cas [%2], %3, %0\n\t"
287                              "membar #StoreLoad | #StoreStore"
288                              : "=&r" (new)
289                              : "0" (new), "r" (m), "r" (old)
290                              : "memory");
291
292         return new;
293 }
294
295 static __inline__ unsigned long
296 __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
297 {
298         __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
299                              "casx [%2], %3, %0\n\t"
300                              "membar #StoreLoad | #StoreStore"
301                              : "=&r" (new)
302                              : "0" (new), "r" (m), "r" (old)
303                              : "memory");
304
305         return new;
306 }
307
308 /* This function doesn't exist, so you'll get a linker error
309    if something tries to do an invalid cmpxchg().  */
310 extern void __cmpxchg_called_with_bad_pointer(void);
311
312 static __inline__ unsigned long
313 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
314 {
315         switch (size) {
316                 case 4:
317                         return __cmpxchg_u32(ptr, old, new);
318                 case 8:
319                         return __cmpxchg_u64(ptr, old, new);
320         }
321         __cmpxchg_called_with_bad_pointer();
322         return old;
323 }
324
325 #define cmpxchg(ptr,o,n)                                                 \
326   ({                                                                     \
327      __typeof__(*(ptr)) _o_ = (o);                                       \
328      __typeof__(*(ptr)) _n_ = (n);                                       \
329      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
330                                     (unsigned long)_n_, sizeof(*(ptr))); \
331   })
332
333 #endif /* !(__ASSEMBLY__) */
334
335 #define arch_align_stack(x) (x)
336
337 #endif /* !(__SPARC64_SYSTEM_H) */