[SPARC]: Fix serial console device detection.
[linux-2.6.git] / include / asm-sparc64 / system.h
1 /* $Id: system.h,v 1.69 2002/02/09 19:49:31 davem Exp $ */
2 #ifndef __SPARC64_SYSTEM_H
3 #define __SPARC64_SYSTEM_H
4
5 #include <asm/ptrace.h>
6 #include <asm/processor.h>
7 #include <asm/visasm.h>
8
9 #ifndef __ASSEMBLY__
10
11 #include <linux/irqflags.h>
12
13 /*
14  * Sparc (general) CPU types
15  */
16 enum sparc_cpu {
17   sun4        = 0x00,
18   sun4c       = 0x01,
19   sun4m       = 0x02,
20   sun4d       = 0x03,
21   sun4e       = 0x04,
22   sun4u       = 0x05, /* V8 ploos ploos */
23   sun_unknown = 0x06,
24   ap1000      = 0x07, /* almost a sun4m */
25 };
26                   
27 #define sparc_cpu_model sun4u
28
29 /* This cannot ever be a sun4c nor sun4 :) That's just history. */
30 #define ARCH_SUN4C_SUN4 0
31 #define ARCH_SUN4 0
32
33 /* These are here in an effort to more fully work around Spitfire Errata
34  * #51.  Essentially, if a memory barrier occurs soon after a mispredicted
35  * branch, the chip can stop executing instructions until a trap occurs.
36  * Therefore, if interrupts are disabled, the chip can hang forever.
37  *
38  * It used to be believed that the memory barrier had to be right in the
39  * delay slot, but a case has been traced recently wherein the memory barrier
40  * was one instruction after the branch delay slot and the chip still hung.
41  * The offending sequence was the following in sym_wakeup_done() of the
42  * sym53c8xx_2 driver:
43  *
44  *      call    sym_ccb_from_dsa, 0
45  *       movge  %icc, 0, %l0
46  *      brz,pn  %o0, .LL1303
47  *       mov    %o0, %l2
48  *      membar  #LoadLoad
49  *
50  * The branch has to be mispredicted for the bug to occur.  Therefore, we put
51  * the memory barrier explicitly into a "branch always, predicted taken"
52  * delay slot to avoid the problem case.
53  */
54 #define membar_safe(type) \
55 do {    __asm__ __volatile__("ba,pt     %%xcc, 1f\n\t" \
56                              " membar   " type "\n" \
57                              "1:\n" \
58                              : : : "memory"); \
59 } while (0)
60
61 #define mb()    \
62         membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
63 #define rmb()   \
64         membar_safe("#LoadLoad")
65 #define wmb()   \
66         membar_safe("#StoreStore")
67 #define membar_storeload() \
68         membar_safe("#StoreLoad")
69 #define membar_storeload_storestore() \
70         membar_safe("#StoreLoad | #StoreStore")
71 #define membar_storeload_loadload() \
72         membar_safe("#StoreLoad | #LoadLoad")
73 #define membar_storestore_loadstore() \
74         membar_safe("#StoreStore | #LoadStore")
75
76 #endif
77
78 #define nop()           __asm__ __volatile__ ("nop")
79
80 #define read_barrier_depends()          do { } while(0)
81 #define set_mb(__var, __value) \
82         do { __var = __value; membar_storeload_storestore(); } while(0)
83
84 #ifdef CONFIG_SMP
85 #define smp_mb()        mb()
86 #define smp_rmb()       rmb()
87 #define smp_wmb()       wmb()
88 #define smp_read_barrier_depends()      read_barrier_depends()
89 #else
90 #define smp_mb()        __asm__ __volatile__("":::"memory")
91 #define smp_rmb()       __asm__ __volatile__("":::"memory")
92 #define smp_wmb()       __asm__ __volatile__("":::"memory")
93 #define smp_read_barrier_depends()      do { } while(0)
94 #endif
95
96 #define flushi(addr)    __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
97
98 #define flushw_all()    __asm__ __volatile__("flushw")
99
100 /* Performance counter register access. */
101 #define read_pcr(__p)  __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
102 #define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
103 #define read_pic(__p)  __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
104
105 /* Blackbird errata workaround.  See commentary in
106  * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
107  * for more information.
108  */
109 #define reset_pic()                                             \
110         __asm__ __volatile__("ba,pt     %xcc, 99f\n\t"          \
111                              ".align    64\n"                   \
112                           "99:wr        %g0, 0x0, %pic\n\t"     \
113                              "rd        %pic, %g0")
114
115 #ifndef __ASSEMBLY__
116
117 extern void sun_do_break(void);
118 extern int stop_a_enabled;
119
120 extern void synchronize_user_stack(void);
121
122 extern void __flushw_user(void);
123 #define flushw_user() __flushw_user()
124
125 #define flush_user_windows flushw_user
126 #define flush_register_windows flushw_all
127
128 /* Don't hold the runqueue lock over context switch */
129 #define __ARCH_WANT_UNLOCKED_CTXSW
130 #define prepare_arch_switch(next)               \
131 do {                                            \
132         flushw_all();                           \
133 } while (0)
134
135         /* See what happens when you design the chip correctly?
136          *
137          * We tell gcc we clobber all non-fixed-usage registers except
138          * for l0/l1.  It will use one for 'next' and the other to hold
139          * the output value of 'last'.  'next' is not referenced again
140          * past the invocation of switch_to in the scheduler, so we need
141          * not preserve it's value.  Hairy, but it lets us remove 2 loads
142          * and 2 stores in this critical code path.  -DaveM
143          */
144 #define EXTRA_CLOBBER ,"%l1"
145 #define switch_to(prev, next, last)                                     \
146 do {    if (test_thread_flag(TIF_PERFCTR)) {                            \
147                 unsigned long __tmp;                                    \
148                 read_pcr(__tmp);                                        \
149                 current_thread_info()->pcr_reg = __tmp;                 \
150                 read_pic(__tmp);                                        \
151                 current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
152                 current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
153         }                                                               \
154         flush_tlb_pending();                                            \
155         save_and_clear_fpu();                                           \
156         /* If you are tempted to conditionalize the following */        \
157         /* so that ASI is only written if it changes, think again. */   \
158         __asm__ __volatile__("wr %%g0, %0, %%asi"                       \
159         : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
160         trap_block[current_thread_info()->cpu].thread =                 \
161                 task_thread_info(next);                                 \
162         __asm__ __volatile__(                                           \
163         "mov    %%g4, %%g7\n\t"                                         \
164         "stx    %%i6, [%%sp + 2047 + 0x70]\n\t"                         \
165         "stx    %%i7, [%%sp + 2047 + 0x78]\n\t"                         \
166         "rdpr   %%wstate, %%o5\n\t"                                     \
167         "stx    %%o6, [%%g6 + %3]\n\t"                                  \
168         "stb    %%o5, [%%g6 + %2]\n\t"                                  \
169         "rdpr   %%cwp, %%o5\n\t"                                        \
170         "stb    %%o5, [%%g6 + %5]\n\t"                                  \
171         "mov    %1, %%g6\n\t"                                           \
172         "ldub   [%1 + %5], %%g1\n\t"                                    \
173         "wrpr   %%g1, %%cwp\n\t"                                        \
174         "ldx    [%%g6 + %3], %%o6\n\t"                                  \
175         "ldub   [%%g6 + %2], %%o5\n\t"                                  \
176         "ldub   [%%g6 + %4], %%o7\n\t"                                  \
177         "wrpr   %%o5, 0x0, %%wstate\n\t"                                \
178         "ldx    [%%sp + 2047 + 0x70], %%i6\n\t"                         \
179         "ldx    [%%sp + 2047 + 0x78], %%i7\n\t"                         \
180         "ldx    [%%g6 + %6], %%g4\n\t"                                  \
181         "brz,pt %%o7, 1f\n\t"                                           \
182         " mov   %%g7, %0\n\t"                                           \
183         "b,a ret_from_syscall\n\t"                                      \
184         "1:\n\t"                                                        \
185         : "=&r" (last)                                                  \
186         : "0" (task_thread_info(next)),                                 \
187           "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD),            \
188           "i" (TI_CWP), "i" (TI_TASK)                                   \
189         : "cc",                                                         \
190                 "g1", "g2", "g3",                   "g7",               \
191                       "l2", "l3", "l4", "l5", "l6", "l7",               \
192           "i0", "i1", "i2", "i3", "i4", "i5",                           \
193           "o0", "o1", "o2", "o3", "o4", "o5",       "o7" EXTRA_CLOBBER);\
194         /* If you fuck with this, update ret_from_syscall code too. */  \
195         if (test_thread_flag(TIF_PERFCTR)) {                            \
196                 write_pcr(current_thread_info()->pcr_reg);              \
197                 reset_pic();                                            \
198         }                                                               \
199 } while(0)
200
201 static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
202 {
203         unsigned long tmp1, tmp2;
204
205         __asm__ __volatile__(
206 "       membar          #StoreLoad | #LoadLoad\n"
207 "       mov             %0, %1\n"
208 "1:     lduw            [%4], %2\n"
209 "       cas             [%4], %2, %0\n"
210 "       cmp             %2, %0\n"
211 "       bne,a,pn        %%icc, 1b\n"
212 "        mov            %1, %0\n"
213 "       membar          #StoreLoad | #StoreStore\n"
214         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
215         : "0" (val), "r" (m)
216         : "cc", "memory");
217         return val;
218 }
219
220 static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
221 {
222         unsigned long tmp1, tmp2;
223
224         __asm__ __volatile__(
225 "       membar          #StoreLoad | #LoadLoad\n"
226 "       mov             %0, %1\n"
227 "1:     ldx             [%4], %2\n"
228 "       casx            [%4], %2, %0\n"
229 "       cmp             %2, %0\n"
230 "       bne,a,pn        %%xcc, 1b\n"
231 "        mov            %1, %0\n"
232 "       membar          #StoreLoad | #StoreStore\n"
233         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
234         : "0" (val), "r" (m)
235         : "cc", "memory");
236         return val;
237 }
238
239 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
240
241 extern void __xchg_called_with_bad_pointer(void);
242
243 static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
244                                        int size)
245 {
246         switch (size) {
247         case 4:
248                 return xchg32(ptr, x);
249         case 8:
250                 return xchg64(ptr, x);
251         };
252         __xchg_called_with_bad_pointer();
253         return x;
254 }
255
256 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
257
258 /* 
259  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
260  * store NEW in MEM.  Return the initial value in MEM.  Success is
261  * indicated by comparing RETURN with OLD.
262  */
263
264 #define __HAVE_ARCH_CMPXCHG 1
265
266 static __inline__ unsigned long
267 __cmpxchg_u32(volatile int *m, int old, int new)
268 {
269         __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
270                              "cas [%2], %3, %0\n\t"
271                              "membar #StoreLoad | #StoreStore"
272                              : "=&r" (new)
273                              : "0" (new), "r" (m), "r" (old)
274                              : "memory");
275
276         return new;
277 }
278
279 static __inline__ unsigned long
280 __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
281 {
282         __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
283                              "casx [%2], %3, %0\n\t"
284                              "membar #StoreLoad | #StoreStore"
285                              : "=&r" (new)
286                              : "0" (new), "r" (m), "r" (old)
287                              : "memory");
288
289         return new;
290 }
291
292 /* This function doesn't exist, so you'll get a linker error
293    if something tries to do an invalid cmpxchg().  */
294 extern void __cmpxchg_called_with_bad_pointer(void);
295
296 static __inline__ unsigned long
297 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
298 {
299         switch (size) {
300                 case 4:
301                         return __cmpxchg_u32(ptr, old, new);
302                 case 8:
303                         return __cmpxchg_u64(ptr, old, new);
304         }
305         __cmpxchg_called_with_bad_pointer();
306         return old;
307 }
308
309 #define cmpxchg(ptr,o,n)                                                 \
310   ({                                                                     \
311      __typeof__(*(ptr)) _o_ = (o);                                       \
312      __typeof__(*(ptr)) _n_ = (n);                                       \
313      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
314                                     (unsigned long)_n_, sizeof(*(ptr))); \
315   })
316
317 #endif /* !(__ASSEMBLY__) */
318
319 #define arch_align_stack(x) (x)
320
321 #endif /* !(__SPARC64_SYSTEM_H) */