Remove tas()
[linux-2.6.git] / include / asm-i386 / system.h
1 #ifndef __ASM_SYSTEM_H
2 #define __ASM_SYSTEM_H
3
4 #include <linux/kernel.h>
5 #include <asm/segment.h>
6 #include <asm/cpufeature.h>
7 #include <linux/bitops.h> /* for LOCK_PREFIX */
8
9 #ifdef __KERNEL__
10
11 struct task_struct;     /* one of the stranger aspects of C forward declarations.. */
12 extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
13
14 /*
15  * Saving eflags is important. It switches not only IOPL between tasks,
16  * it also protects other tasks from NT leaking through sysenter etc.
17  */
18 #define switch_to(prev,next,last) do {                                  \
19         unsigned long esi,edi;                                          \
20         asm volatile("pushfl\n\t"               /* Save flags */        \
21                      "pushl %%ebp\n\t"                                  \
22                      "movl %%esp,%0\n\t"        /* save ESP */          \
23                      "movl %5,%%esp\n\t"        /* restore ESP */       \
24                      "movl $1f,%1\n\t"          /* save EIP */          \
25                      "pushl %6\n\t"             /* restore EIP */       \
26                      "jmp __switch_to\n"                                \
27                      "1:\t"                                             \
28                      "popl %%ebp\n\t"                                   \
29                      "popfl"                                            \
30                      :"=m" (prev->thread.esp),"=m" (prev->thread.eip),  \
31                       "=a" (last),"=S" (esi),"=D" (edi)                 \
32                      :"m" (next->thread.esp),"m" (next->thread.eip),    \
33                       "2" (prev), "d" (next));                          \
34 } while (0)
35
36 #define _set_base(addr,base) do { unsigned long __pr; \
37 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
38         "rorl $16,%%edx\n\t" \
39         "movb %%dl,%2\n\t" \
40         "movb %%dh,%3" \
41         :"=&d" (__pr) \
42         :"m" (*((addr)+2)), \
43          "m" (*((addr)+4)), \
44          "m" (*((addr)+7)), \
45          "0" (base) \
46         ); } while(0)
47
48 #define _set_limit(addr,limit) do { unsigned long __lr; \
49 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
50         "rorl $16,%%edx\n\t" \
51         "movb %2,%%dh\n\t" \
52         "andb $0xf0,%%dh\n\t" \
53         "orb %%dh,%%dl\n\t" \
54         "movb %%dl,%2" \
55         :"=&d" (__lr) \
56         :"m" (*(addr)), \
57          "m" (*((addr)+6)), \
58          "0" (limit) \
59         ); } while(0)
60
61 #define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
62 #define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1) )
63
64 /*
65  * Load a segment. Fall back on loading the zero
66  * segment if something goes wrong..
67  */
68 #define loadsegment(seg,value)                  \
69         asm volatile("\n"                       \
70                 "1:\t"                          \
71                 "mov %0,%%" #seg "\n"           \
72                 "2:\n"                          \
73                 ".section .fixup,\"ax\"\n"      \
74                 "3:\t"                          \
75                 "pushl $0\n\t"                  \
76                 "popl %%" #seg "\n\t"           \
77                 "jmp 2b\n"                      \
78                 ".previous\n"                   \
79                 ".section __ex_table,\"a\"\n\t" \
80                 ".align 4\n\t"                  \
81                 ".long 1b,3b\n"                 \
82                 ".previous"                     \
83                 : :"rm" (value))
84
85 /*
86  * Save a segment register away
87  */
88 #define savesegment(seg, value) \
89         asm volatile("mov %%" #seg ",%0":"=rm" (value))
90
91
92 static inline void native_clts(void)
93 {
94         asm volatile ("clts");
95 }
96
97 static inline unsigned long native_read_cr0(void)
98 {
99         unsigned long val;
100         asm volatile("movl %%cr0,%0\n\t" :"=r" (val));
101         return val;
102 }
103
104 static inline void native_write_cr0(unsigned long val)
105 {
106         asm volatile("movl %0,%%cr0": :"r" (val));
107 }
108
109 static inline unsigned long native_read_cr2(void)
110 {
111         unsigned long val;
112         asm volatile("movl %%cr2,%0\n\t" :"=r" (val));
113         return val;
114 }
115
116 static inline void native_write_cr2(unsigned long val)
117 {
118         asm volatile("movl %0,%%cr2": :"r" (val));
119 }
120
121 static inline unsigned long native_read_cr3(void)
122 {
123         unsigned long val;
124         asm volatile("movl %%cr3,%0\n\t" :"=r" (val));
125         return val;
126 }
127
128 static inline void native_write_cr3(unsigned long val)
129 {
130         asm volatile("movl %0,%%cr3": :"r" (val));
131 }
132
133 static inline unsigned long native_read_cr4(void)
134 {
135         unsigned long val;
136         asm volatile("movl %%cr4,%0\n\t" :"=r" (val));
137         return val;
138 }
139
140 static inline unsigned long native_read_cr4_safe(void)
141 {
142         unsigned long val;
143         /* This could fault if %cr4 does not exist */
144         asm("1: movl %%cr4, %0          \n"
145                 "2:                             \n"
146                 ".section __ex_table,\"a\"      \n"
147                 ".long 1b,2b                    \n"
148                 ".previous                      \n"
149                 : "=r" (val): "0" (0));
150         return val;
151 }
152
153 static inline void native_write_cr4(unsigned long val)
154 {
155         asm volatile("movl %0,%%cr4": :"r" (val));
156 }
157
158 static inline void native_wbinvd(void)
159 {
160         asm volatile("wbinvd": : :"memory");
161 }
162
163
164 #ifdef CONFIG_PARAVIRT
165 #include <asm/paravirt.h>
166 #else
167 #define read_cr0()      (native_read_cr0())
168 #define write_cr0(x)    (native_write_cr0(x))
169 #define read_cr2()      (native_read_cr2())
170 #define write_cr2(x)    (native_write_cr2(x))
171 #define read_cr3()      (native_read_cr3())
172 #define write_cr3(x)    (native_write_cr3(x))
173 #define read_cr4()      (native_read_cr4())
174 #define read_cr4_safe() (native_read_cr4_safe())
175 #define write_cr4(x)    (native_write_cr4(x))
176 #define wbinvd()        (native_wbinvd())
177
178 /* Clear the 'TS' bit */
179 #define clts()          (native_clts())
180
181 #endif/* CONFIG_PARAVIRT */
182
183 /* Set the 'TS' bit */
184 #define stts() write_cr0(8 | read_cr0())
185
186 #endif  /* __KERNEL__ */
187
188 static inline unsigned long get_limit(unsigned long segment)
189 {
190         unsigned long __limit;
191         __asm__("lsll %1,%0"
192                 :"=r" (__limit):"r" (segment));
193         return __limit+1;
194 }
195
196 #define nop() __asm__ __volatile__ ("nop")
197
198 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
199
200 struct __xchg_dummy { unsigned long a[100]; };
201 #define __xg(x) ((struct __xchg_dummy *)(x))
202
203
204 #ifdef CONFIG_X86_CMPXCHG64
205
206 /*
207  * The semantics of XCHGCMP8B are a bit strange, this is why
208  * there is a loop and the loading of %%eax and %%edx has to
209  * be inside. This inlines well in most cases, the cached
210  * cost is around ~38 cycles. (in the future we might want
211  * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
212  * might have an implicit FPU-save as a cost, so it's not
213  * clear which path to go.)
214  *
215  * cmpxchg8b must be used with the lock prefix here to allow
216  * the instruction to be executed atomically, see page 3-102
217  * of the instruction set reference 24319102.pdf. We need
218  * the reader side to see the coherent 64bit value.
219  */
220 static inline void __set_64bit (unsigned long long * ptr,
221                 unsigned int low, unsigned int high)
222 {
223         __asm__ __volatile__ (
224                 "\n1:\t"
225                 "movl (%0), %%eax\n\t"
226                 "movl 4(%0), %%edx\n\t"
227                 "lock cmpxchg8b (%0)\n\t"
228                 "jnz 1b"
229                 : /* no outputs */
230                 :       "D"(ptr),
231                         "b"(low),
232                         "c"(high)
233                 :       "ax","dx","memory");
234 }
235
236 static inline void __set_64bit_constant (unsigned long long *ptr,
237                                                  unsigned long long value)
238 {
239         __set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
240 }
241 #define ll_low(x)       *(((unsigned int*)&(x))+0)
242 #define ll_high(x)      *(((unsigned int*)&(x))+1)
243
244 static inline void __set_64bit_var (unsigned long long *ptr,
245                          unsigned long long value)
246 {
247         __set_64bit(ptr,ll_low(value), ll_high(value));
248 }
249
250 #define set_64bit(ptr,value) \
251 (__builtin_constant_p(value) ? \
252  __set_64bit_constant(ptr, value) : \
253  __set_64bit_var(ptr, value) )
254
255 #define _set_64bit(ptr,value) \
256 (__builtin_constant_p(value) ? \
257  __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
258  __set_64bit(ptr, ll_low(value), ll_high(value)) )
259
260 #endif
261
262 /*
263  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
264  * Note 2: xchg has side effect, so that attribute volatile is necessary,
265  *        but generally the primitive is invalid, *ptr is output argument. --ANK
266  */
267 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
268 {
269         switch (size) {
270                 case 1:
271                         __asm__ __volatile__("xchgb %b0,%1"
272                                 :"=q" (x)
273                                 :"m" (*__xg(ptr)), "0" (x)
274                                 :"memory");
275                         break;
276                 case 2:
277                         __asm__ __volatile__("xchgw %w0,%1"
278                                 :"=r" (x)
279                                 :"m" (*__xg(ptr)), "0" (x)
280                                 :"memory");
281                         break;
282                 case 4:
283                         __asm__ __volatile__("xchgl %0,%1"
284                                 :"=r" (x)
285                                 :"m" (*__xg(ptr)), "0" (x)
286                                 :"memory");
287                         break;
288         }
289         return x;
290 }
291
292 /*
293  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
294  * store NEW in MEM.  Return the initial value in MEM.  Success is
295  * indicated by comparing RETURN with OLD.
296  */
297
298 #ifdef CONFIG_X86_CMPXCHG
299 #define __HAVE_ARCH_CMPXCHG 1
300 #define cmpxchg(ptr,o,n)\
301         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
302                                         (unsigned long)(n),sizeof(*(ptr))))
303 #define sync_cmpxchg(ptr,o,n)\
304         ((__typeof__(*(ptr)))__sync_cmpxchg((ptr),(unsigned long)(o),\
305                                         (unsigned long)(n),sizeof(*(ptr))))
306 #define cmpxchg_local(ptr,o,n)\
307         ((__typeof__(*(ptr)))__cmpxchg_local((ptr),(unsigned long)(o),\
308                                         (unsigned long)(n),sizeof(*(ptr))))
309 #endif
310
311 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
312                                       unsigned long new, int size)
313 {
314         unsigned long prev;
315         switch (size) {
316         case 1:
317                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
318                                      : "=a"(prev)
319                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
320                                      : "memory");
321                 return prev;
322         case 2:
323                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
324                                      : "=a"(prev)
325                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
326                                      : "memory");
327                 return prev;
328         case 4:
329                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
330                                      : "=a"(prev)
331                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
332                                      : "memory");
333                 return prev;
334         }
335         return old;
336 }
337
338 /*
339  * Always use locked operations when touching memory shared with a
340  * hypervisor, since the system may be SMP even if the guest kernel
341  * isn't.
342  */
343 static inline unsigned long __sync_cmpxchg(volatile void *ptr,
344                                             unsigned long old,
345                                             unsigned long new, int size)
346 {
347         unsigned long prev;
348         switch (size) {
349         case 1:
350                 __asm__ __volatile__("lock; cmpxchgb %b1,%2"
351                                      : "=a"(prev)
352                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
353                                      : "memory");
354                 return prev;
355         case 2:
356                 __asm__ __volatile__("lock; cmpxchgw %w1,%2"
357                                      : "=a"(prev)
358                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
359                                      : "memory");
360                 return prev;
361         case 4:
362                 __asm__ __volatile__("lock; cmpxchgl %1,%2"
363                                      : "=a"(prev)
364                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
365                                      : "memory");
366                 return prev;
367         }
368         return old;
369 }
370
371 static inline unsigned long __cmpxchg_local(volatile void *ptr,
372                         unsigned long old, unsigned long new, int size)
373 {
374         unsigned long prev;
375         switch (size) {
376         case 1:
377                 __asm__ __volatile__("cmpxchgb %b1,%2"
378                                      : "=a"(prev)
379                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
380                                      : "memory");
381                 return prev;
382         case 2:
383                 __asm__ __volatile__("cmpxchgw %w1,%2"
384                                      : "=a"(prev)
385                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
386                                      : "memory");
387                 return prev;
388         case 4:
389                 __asm__ __volatile__("cmpxchgl %1,%2"
390                                      : "=a"(prev)
391                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
392                                      : "memory");
393                 return prev;
394         }
395         return old;
396 }
397
398 #ifndef CONFIG_X86_CMPXCHG
399 /*
400  * Building a kernel capable running on 80386. It may be necessary to
401  * simulate the cmpxchg on the 80386 CPU. For that purpose we define
402  * a function for each of the sizes we support.
403  */
404
405 extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
406 extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
407 extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
408
409 static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
410                                       unsigned long new, int size)
411 {
412         switch (size) {
413         case 1:
414                 return cmpxchg_386_u8(ptr, old, new);
415         case 2:
416                 return cmpxchg_386_u16(ptr, old, new);
417         case 4:
418                 return cmpxchg_386_u32(ptr, old, new);
419         }
420         return old;
421 }
422
423 #define cmpxchg(ptr,o,n)                                                \
424 ({                                                                      \
425         __typeof__(*(ptr)) __ret;                                       \
426         if (likely(boot_cpu_data.x86 > 3))                              \
427                 __ret = __cmpxchg((ptr), (unsigned long)(o),            \
428                                         (unsigned long)(n), sizeof(*(ptr))); \
429         else                                                            \
430                 __ret = cmpxchg_386((ptr), (unsigned long)(o),          \
431                                         (unsigned long)(n), sizeof(*(ptr))); \
432         __ret;                                                          \
433 })
434 #define cmpxchg_local(ptr,o,n)                                          \
435 ({                                                                      \
436         __typeof__(*(ptr)) __ret;                                       \
437         if (likely(boot_cpu_data.x86 > 3))                              \
438                 __ret = __cmpxchg_local((ptr), (unsigned long)(o),      \
439                                         (unsigned long)(n), sizeof(*(ptr))); \
440         else                                                            \
441                 __ret = cmpxchg_386((ptr), (unsigned long)(o),          \
442                                         (unsigned long)(n), sizeof(*(ptr))); \
443         __ret;                                                          \
444 })
445 #endif
446
447 #ifdef CONFIG_X86_CMPXCHG64
448
449 static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
450                                       unsigned long long new)
451 {
452         unsigned long long prev;
453         __asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
454                              : "=A"(prev)
455                              : "b"((unsigned long)new),
456                                "c"((unsigned long)(new >> 32)),
457                                "m"(*__xg(ptr)),
458                                "0"(old)
459                              : "memory");
460         return prev;
461 }
462
463 static inline unsigned long long __cmpxchg64_local(volatile void *ptr,
464                         unsigned long long old, unsigned long long new)
465 {
466         unsigned long long prev;
467         __asm__ __volatile__("cmpxchg8b %3"
468                              : "=A"(prev)
469                              : "b"((unsigned long)new),
470                                "c"((unsigned long)(new >> 32)),
471                                "m"(*__xg(ptr)),
472                                "0"(old)
473                              : "memory");
474         return prev;
475 }
476
477 #define cmpxchg64(ptr,o,n)\
478         ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
479                                         (unsigned long long)(n)))
480 #define cmpxchg64_local(ptr,o,n)\
481         ((__typeof__(*(ptr)))__cmpxchg64_local((ptr),(unsigned long long)(o),\
482                                         (unsigned long long)(n)))
483 #endif
484     
485 /*
486  * Force strict CPU ordering.
487  * And yes, this is required on UP too when we're talking
488  * to devices.
489  *
490  * For now, "wmb()" doesn't actually do anything, as all
491  * Intel CPU's follow what Intel calls a *Processor Order*,
492  * in which all writes are seen in the program order even
493  * outside the CPU.
494  *
495  * I expect future Intel CPU's to have a weaker ordering,
496  * but I'd also expect them to finally get their act together
497  * and add some real memory barriers if so.
498  *
499  * Some non intel clones support out of order store. wmb() ceases to be a
500  * nop for these.
501  */
502  
503
504 /* 
505  * Actually only lfence would be needed for mb() because all stores done 
506  * by the kernel should be already ordered. But keep a full barrier for now. 
507  */
508
509 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
510 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
511
512 /**
513  * read_barrier_depends - Flush all pending reads that subsequents reads
514  * depend on.
515  *
516  * No data-dependent reads from memory-like regions are ever reordered
517  * over this barrier.  All reads preceding this primitive are guaranteed
518  * to access memory (but not necessarily other CPUs' caches) before any
519  * reads following this primitive that depend on the data return by
520  * any of the preceding reads.  This primitive is much lighter weight than
521  * rmb() on most CPUs, and is never heavier weight than is
522  * rmb().
523  *
524  * These ordering constraints are respected by both the local CPU
525  * and the compiler.
526  *
527  * Ordering is not guaranteed by anything other than these primitives,
528  * not even by data dependencies.  See the documentation for
529  * memory_barrier() for examples and URLs to more information.
530  *
531  * For example, the following code would force ordering (the initial
532  * value of "a" is zero, "b" is one, and "p" is "&a"):
533  *
534  * <programlisting>
535  *      CPU 0                           CPU 1
536  *
537  *      b = 2;
538  *      memory_barrier();
539  *      p = &b;                         q = p;
540  *                                      read_barrier_depends();
541  *                                      d = *q;
542  * </programlisting>
543  *
544  * because the read of "*q" depends on the read of "p" and these
545  * two reads are separated by a read_barrier_depends().  However,
546  * the following code, with the same initial values for "a" and "b":
547  *
548  * <programlisting>
549  *      CPU 0                           CPU 1
550  *
551  *      a = 2;
552  *      memory_barrier();
553  *      b = 3;                          y = b;
554  *                                      read_barrier_depends();
555  *                                      x = a;
556  * </programlisting>
557  *
558  * does not enforce ordering, since there is no data dependency between
559  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
560  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
561  * in cases like this where there are no data dependencies.
562  **/
563
564 #define read_barrier_depends()  do { } while(0)
565
566 #ifdef CONFIG_X86_OOSTORE
567 /* Actually there are no OOO store capable CPUs for now that do SSE, 
568    but make it already an possibility. */
569 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
570 #else
571 #define wmb()   __asm__ __volatile__ ("": : :"memory")
572 #endif
573
574 #ifdef CONFIG_SMP
575 #define smp_mb()        mb()
576 #define smp_rmb()       rmb()
577 #define smp_wmb()       wmb()
578 #define smp_read_barrier_depends()      read_barrier_depends()
579 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
580 #else
581 #define smp_mb()        barrier()
582 #define smp_rmb()       barrier()
583 #define smp_wmb()       barrier()
584 #define smp_read_barrier_depends()      do { } while(0)
585 #define set_mb(var, value) do { var = value; barrier(); } while (0)
586 #endif
587
588 #include <linux/irqflags.h>
589
590 /*
591  * disable hlt during certain critical i/o operations
592  */
593 #define HAVE_DISABLE_HLT
594 void disable_hlt(void);
595 void enable_hlt(void);
596
597 extern int es7000_plat;
598 void cpu_idle_wait(void);
599
600 /*
601  * On SMP systems, when the scheduler does migration-cost autodetection,
602  * it needs a way to flush as much of the CPU's caches as possible:
603  */
604 static inline void sched_cacheflush(void)
605 {
606         wbinvd();
607 }
608
609 extern unsigned long arch_align_stack(unsigned long sp);
610 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
611
612 void default_idle(void);
613
614 #endif