[ARM] pxa: separate GPIOs and their mode definitions to pxa2xx-gpio.h
[linux-2.6.git] / drivers / video / pxafb.c
1 /*
2  *  linux/drivers/video/pxafb.c
3  *
4  *  Copyright (C) 1999 Eric A. Thomas.
5  *  Copyright (C) 2004 Jean-Frederic Clere.
6  *  Copyright (C) 2004 Ian Campbell.
7  *  Copyright (C) 2004 Jeff Lackey.
8  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9  *  which in turn is
10  *   Based on acornfb.c Copyright (C) Russell King.
11  *
12  * This file is subject to the terms and conditions of the GNU General Public
13  * License.  See the file COPYING in the main directory of this archive for
14  * more details.
15  *
16  *              Intel PXA250/210 LCD Controller Frame Buffer Driver
17  *
18  * Please direct your questions and comments on this driver to the following
19  * email address:
20  *
21  *      linux-arm-kernel@lists.arm.linux.org.uk
22  *
23  */
24
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
33 #include <linux/fb.h>
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/ioport.h>
37 #include <linux/cpufreq.h>
38 #include <linux/platform_device.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/clk.h>
41 #include <linux/err.h>
42
43 #include <asm/hardware.h>
44 #include <asm/io.h>
45 #include <asm/irq.h>
46 #include <asm/div64.h>
47 #include <asm/arch/pxa-regs.h>
48 #include <asm/arch/pxa2xx-gpio.h>
49 #include <asm/arch/bitfield.h>
50 #include <asm/arch/pxafb.h>
51
52 /*
53  * Complain if VAR is out of range.
54  */
55 #define DEBUG_VAR 1
56
57 #include "pxafb.h"
58
59 /* Bits which should not be set in machine configuration structures */
60 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
61 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
62
63 static void (*pxafb_backlight_power)(int);
64 static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
65
66 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
67 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
68
69 #ifdef CONFIG_FB_PXA_PARAMETERS
70 #define PXAFB_OPTIONS_SIZE 256
71 static char g_options[PXAFB_OPTIONS_SIZE] __devinitdata = "";
72 #endif
73
74 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
75 {
76         unsigned long flags;
77
78         local_irq_save(flags);
79         /*
80          * We need to handle two requests being made at the same time.
81          * There are two important cases:
82          *  1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
83          *     We must perform the unblanking, which will do our REENABLE for us.
84          *  2. When we are blanking, but immediately unblank before we have
85          *     blanked.  We do the "REENABLE" thing here as well, just to be sure.
86          */
87         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
88                 state = (u_int) -1;
89         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
90                 state = C_REENABLE;
91
92         if (state != (u_int)-1) {
93                 fbi->task_state = state;
94                 schedule_work(&fbi->task);
95         }
96         local_irq_restore(flags);
97 }
98
99 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
100 {
101         chan &= 0xffff;
102         chan >>= 16 - bf->length;
103         return chan << bf->offset;
104 }
105
106 static int
107 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
108                        u_int trans, struct fb_info *info)
109 {
110         struct pxafb_info *fbi = (struct pxafb_info *)info;
111         u_int val;
112
113         if (regno >= fbi->palette_size)
114                 return 1;
115
116         if (fbi->fb.var.grayscale) {
117                 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
118                 return 0;
119         }
120
121         switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
122         case LCCR4_PAL_FOR_0:
123                 val  = ((red   >>  0) & 0xf800);
124                 val |= ((green >>  5) & 0x07e0);
125                 val |= ((blue  >> 11) & 0x001f);
126                 fbi->palette_cpu[regno] = val;
127                 break;
128         case LCCR4_PAL_FOR_1:
129                 val  = ((red   << 8) & 0x00f80000);
130                 val |= ((green >> 0) & 0x0000fc00);
131                 val |= ((blue  >> 8) & 0x000000f8);
132                 ((u32*)(fbi->palette_cpu))[regno] = val;
133                 break;
134         case LCCR4_PAL_FOR_2:
135                 val  = ((red   << 8) & 0x00fc0000);
136                 val |= ((green >> 0) & 0x0000fc00);
137                 val |= ((blue  >> 8) & 0x000000fc);
138                 ((u32*)(fbi->palette_cpu))[regno] = val;
139                 break;
140         }
141
142         return 0;
143 }
144
145 static int
146 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
147                    u_int trans, struct fb_info *info)
148 {
149         struct pxafb_info *fbi = (struct pxafb_info *)info;
150         unsigned int val;
151         int ret = 1;
152
153         /*
154          * If inverse mode was selected, invert all the colours
155          * rather than the register number.  The register number
156          * is what you poke into the framebuffer to produce the
157          * colour you requested.
158          */
159         if (fbi->cmap_inverse) {
160                 red   = 0xffff - red;
161                 green = 0xffff - green;
162                 blue  = 0xffff - blue;
163         }
164
165         /*
166          * If greyscale is true, then we convert the RGB value
167          * to greyscale no matter what visual we are using.
168          */
169         if (fbi->fb.var.grayscale)
170                 red = green = blue = (19595 * red + 38470 * green +
171                                         7471 * blue) >> 16;
172
173         switch (fbi->fb.fix.visual) {
174         case FB_VISUAL_TRUECOLOR:
175                 /*
176                  * 16-bit True Colour.  We encode the RGB value
177                  * according to the RGB bitfield information.
178                  */
179                 if (regno < 16) {
180                         u32 *pal = fbi->fb.pseudo_palette;
181
182                         val  = chan_to_field(red, &fbi->fb.var.red);
183                         val |= chan_to_field(green, &fbi->fb.var.green);
184                         val |= chan_to_field(blue, &fbi->fb.var.blue);
185
186                         pal[regno] = val;
187                         ret = 0;
188                 }
189                 break;
190
191         case FB_VISUAL_STATIC_PSEUDOCOLOR:
192         case FB_VISUAL_PSEUDOCOLOR:
193                 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
194                 break;
195         }
196
197         return ret;
198 }
199
200 /*
201  *  pxafb_bpp_to_lccr3():
202  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
203  */
204 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
205 {
206         int ret = 0;
207         switch (var->bits_per_pixel) {
208         case 1:  ret = LCCR3_1BPP; break;
209         case 2:  ret = LCCR3_2BPP; break;
210         case 4:  ret = LCCR3_4BPP; break;
211         case 8:  ret = LCCR3_8BPP; break;
212         case 16: ret = LCCR3_16BPP; break;
213         }
214         return ret;
215 }
216
217 #ifdef CONFIG_CPU_FREQ
218 /*
219  *  pxafb_display_dma_period()
220  *    Calculate the minimum period (in picoseconds) between two DMA
221  *    requests for the LCD controller.  If we hit this, it means we're
222  *    doing nothing but LCD DMA.
223  */
224 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
225 {
226        /*
227         * Period = pixclock * bits_per_byte * bytes_per_transfer
228         *              / memory_bits_per_pixel;
229         */
230        return var->pixclock * 8 * 16 / var->bits_per_pixel;
231 }
232
233 extern unsigned int get_clk_frequency_khz(int info);
234 #endif
235
236 /*
237  * Select the smallest mode that allows the desired resolution to be
238  * displayed. If desired parameters can be rounded up.
239  */
240 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach, struct fb_var_screeninfo *var)
241 {
242         struct pxafb_mode_info *mode = NULL;
243         struct pxafb_mode_info *modelist = mach->modes;
244         unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
245         unsigned int i;
246
247         for (i = 0 ; i < mach->num_modes ; i++) {
248                 if (modelist[i].xres >= var->xres && modelist[i].yres >= var->yres &&
249                                 modelist[i].xres < best_x && modelist[i].yres < best_y &&
250                                 modelist[i].bpp >= var->bits_per_pixel ) {
251                         best_x = modelist[i].xres;
252                         best_y = modelist[i].yres;
253                         mode = &modelist[i];
254                 }
255         }
256
257         return mode;
258 }
259
260 static void pxafb_setmode(struct fb_var_screeninfo *var, struct pxafb_mode_info *mode)
261 {
262         var->xres               = mode->xres;
263         var->yres               = mode->yres;
264         var->bits_per_pixel     = mode->bpp;
265         var->pixclock           = mode->pixclock;
266         var->hsync_len          = mode->hsync_len;
267         var->left_margin        = mode->left_margin;
268         var->right_margin       = mode->right_margin;
269         var->vsync_len          = mode->vsync_len;
270         var->upper_margin       = mode->upper_margin;
271         var->lower_margin       = mode->lower_margin;
272         var->sync               = mode->sync;
273         var->grayscale          = mode->cmap_greyscale;
274         var->xres_virtual       = var->xres;
275         var->yres_virtual       = var->yres;
276 }
277
278 /*
279  *  pxafb_check_var():
280  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
281  *    if it's too big, return -EINVAL.
282  *
283  *    Round up in the following order: bits_per_pixel, xres,
284  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
285  *    bitfields, horizontal timing, vertical timing.
286  */
287 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
288 {
289         struct pxafb_info *fbi = (struct pxafb_info *)info;
290         struct pxafb_mach_info *inf = fbi->dev->platform_data;
291
292         if (var->xres < MIN_XRES)
293                 var->xres = MIN_XRES;
294         if (var->yres < MIN_YRES)
295                 var->yres = MIN_YRES;
296
297         if (inf->fixed_modes) {
298                 struct pxafb_mode_info *mode;
299
300                 mode = pxafb_getmode(inf, var);
301                 if (!mode)
302                         return -EINVAL;
303                 pxafb_setmode(var, mode);
304         } else {
305                 if (var->xres > inf->modes->xres)
306                         return -EINVAL;
307                 if (var->yres > inf->modes->yres)
308                         return -EINVAL;
309                 if (var->bits_per_pixel > inf->modes->bpp)
310                         return -EINVAL;
311         }
312
313         var->xres_virtual =
314                 max(var->xres_virtual, var->xres);
315         var->yres_virtual =
316                 max(var->yres_virtual, var->yres);
317
318         /*
319          * Setup the RGB parameters for this display.
320          *
321          * The pixel packing format is described on page 7-11 of the
322          * PXA2XX Developer's Manual.
323          */
324         if (var->bits_per_pixel == 16) {
325                 var->red.offset   = 11; var->red.length   = 5;
326                 var->green.offset = 5;  var->green.length = 6;
327                 var->blue.offset  = 0;  var->blue.length  = 5;
328                 var->transp.offset = var->transp.length = 0;
329         } else {
330                 var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
331                 var->red.length   = 8;
332                 var->green.length = 8;
333                 var->blue.length  = 8;
334                 var->transp.length = 0;
335         }
336
337 #ifdef CONFIG_CPU_FREQ
338         pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
339                  pxafb_display_dma_period(var),
340                  get_clk_frequency_khz(0));
341 #endif
342
343         return 0;
344 }
345
346 static inline void pxafb_set_truecolor(u_int is_true_color)
347 {
348         pr_debug("pxafb: true_color = %d\n", is_true_color);
349         // do your machine-specific setup if needed
350 }
351
352 /*
353  * pxafb_set_par():
354  *      Set the user defined part of the display for the specified console
355  */
356 static int pxafb_set_par(struct fb_info *info)
357 {
358         struct pxafb_info *fbi = (struct pxafb_info *)info;
359         struct fb_var_screeninfo *var = &info->var;
360         unsigned long palette_mem_size;
361
362         pr_debug("pxafb: set_par\n");
363
364         if (var->bits_per_pixel == 16)
365                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
366         else if (!fbi->cmap_static)
367                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
368         else {
369                 /*
370                  * Some people have weird ideas about wanting static
371                  * pseudocolor maps.  I suspect their user space
372                  * applications are broken.
373                  */
374                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
375         }
376
377         fbi->fb.fix.line_length = var->xres_virtual *
378                                   var->bits_per_pixel / 8;
379         if (var->bits_per_pixel == 16)
380                 fbi->palette_size = 0;
381         else
382                 fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel;
383
384         if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
385                 palette_mem_size = fbi->palette_size * sizeof(u16);
386         else
387                 palette_mem_size = fbi->palette_size * sizeof(u32);
388
389         pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
390
391         fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
392         fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
393
394         /*
395          * Set (any) board control register to handle new color depth
396          */
397         pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
398
399         if (fbi->fb.var.bits_per_pixel == 16)
400                 fb_dealloc_cmap(&fbi->fb.cmap);
401         else
402                 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
403
404         pxafb_activate_var(var, fbi);
405
406         return 0;
407 }
408
409 /*
410  * Formal definition of the VESA spec:
411  *  On
412  *      This refers to the state of the display when it is in full operation
413  *  Stand-By
414  *      This defines an optional operating state of minimal power reduction with
415  *      the shortest recovery time
416  *  Suspend
417  *      This refers to a level of power management in which substantial power
418  *      reduction is achieved by the display.  The display can have a longer
419  *      recovery time from this state than from the Stand-by state
420  *  Off
421  *      This indicates that the display is consuming the lowest level of power
422  *      and is non-operational. Recovery from this state may optionally require
423  *      the user to manually power on the monitor
424  *
425  *  Now, the fbdev driver adds an additional state, (blank), where they
426  *  turn off the video (maybe by colormap tricks), but don't mess with the
427  *  video itself: think of it semantically between on and Stand-By.
428  *
429  *  So here's what we should do in our fbdev blank routine:
430  *
431  *      VESA_NO_BLANKING (mode 0)       Video on,  front/back light on
432  *      VESA_VSYNC_SUSPEND (mode 1)     Video on,  front/back light off
433  *      VESA_HSYNC_SUSPEND (mode 2)     Video on,  front/back light off
434  *      VESA_POWERDOWN (mode 3)         Video off, front/back light off
435  *
436  *  This will match the matrox implementation.
437  */
438
439 /*
440  * pxafb_blank():
441  *      Blank the display by setting all palette values to zero.  Note, the
442  *      16 bpp mode does not really use the palette, so this will not
443  *      blank the display in all modes.
444  */
445 static int pxafb_blank(int blank, struct fb_info *info)
446 {
447         struct pxafb_info *fbi = (struct pxafb_info *)info;
448         int i;
449
450         pr_debug("pxafb: blank=%d\n", blank);
451
452         switch (blank) {
453         case FB_BLANK_POWERDOWN:
454         case FB_BLANK_VSYNC_SUSPEND:
455         case FB_BLANK_HSYNC_SUSPEND:
456         case FB_BLANK_NORMAL:
457                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
458                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
459                         for (i = 0; i < fbi->palette_size; i++)
460                                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
461
462                 pxafb_schedule_work(fbi, C_DISABLE);
463                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
464                 break;
465
466         case FB_BLANK_UNBLANK:
467                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
468                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
469                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
470                         fb_set_cmap(&fbi->fb.cmap, info);
471                 pxafb_schedule_work(fbi, C_ENABLE);
472         }
473         return 0;
474 }
475
476 static int pxafb_mmap(struct fb_info *info,
477                       struct vm_area_struct *vma)
478 {
479         struct pxafb_info *fbi = (struct pxafb_info *)info;
480         unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
481
482         if (off < info->fix.smem_len) {
483                 vma->vm_pgoff += 1;
484                 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
485                                              fbi->map_dma, fbi->map_size);
486         }
487         return -EINVAL;
488 }
489
490 static struct fb_ops pxafb_ops = {
491         .owner          = THIS_MODULE,
492         .fb_check_var   = pxafb_check_var,
493         .fb_set_par     = pxafb_set_par,
494         .fb_setcolreg   = pxafb_setcolreg,
495         .fb_fillrect    = cfb_fillrect,
496         .fb_copyarea    = cfb_copyarea,
497         .fb_imageblit   = cfb_imageblit,
498         .fb_blank       = pxafb_blank,
499         .fb_mmap        = pxafb_mmap,
500 };
501
502 /*
503  * Calculate the PCD value from the clock rate (in picoseconds).
504  * We take account of the PPCR clock setting.
505  * From PXA Developer's Manual:
506  *
507  *   PixelClock =      LCLK
508  *                -------------
509  *                2 ( PCD + 1 )
510  *
511  *   PCD =      LCLK
512  *         ------------- - 1
513  *         2(PixelClock)
514  *
515  * Where:
516  *   LCLK = LCD/Memory Clock
517  *   PCD = LCCR3[7:0]
518  *
519  * PixelClock here is in Hz while the pixclock argument given is the
520  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
521  *
522  * The function get_lclk_frequency_10khz returns LCLK in units of
523  * 10khz. Calling the result of this function lclk gives us the
524  * following
525  *
526  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
527  *          -------------------------------------- - 1
528  *                          2
529  *
530  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
531  */
532 static inline unsigned int get_pcd(struct pxafb_info *fbi, unsigned int pixclock)
533 {
534         unsigned long long pcd;
535
536         /* FIXME: Need to take into account Double Pixel Clock mode
537          * (DPC) bit? or perhaps set it based on the various clock
538          * speeds */
539         pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
540         pcd *= pixclock;
541         do_div(pcd, 100000000 * 2);
542         /* no need for this, since we should subtract 1 anyway. they cancel */
543         /* pcd += 1; */ /* make up for integer math truncations */
544         return (unsigned int)pcd;
545 }
546
547 /*
548  * Some touchscreens need hsync information from the video driver to
549  * function correctly. We export it here.  Note that 'hsync_time' and
550  * the value returned from pxafb_get_hsync_time() is the *reciprocal*
551  * of the hsync period in seconds.
552  */
553 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
554 {
555         unsigned long htime;
556
557         if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
558                 fbi->hsync_time=0;
559                 return;
560         }
561
562         htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
563
564         fbi->hsync_time = htime;
565 }
566
567 unsigned long pxafb_get_hsync_time(struct device *dev)
568 {
569         struct pxafb_info *fbi = dev_get_drvdata(dev);
570
571         /* If display is blanked/suspended, hsync isn't active */
572         if (!fbi || (fbi->state != C_ENABLE))
573                 return 0;
574
575         return fbi->hsync_time;
576 }
577 EXPORT_SYMBOL(pxafb_get_hsync_time);
578
579 /*
580  * pxafb_activate_var():
581  *      Configures LCD Controller based on entries in var parameter.  Settings are
582  *      only written to the controller if changes were made.
583  */
584 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
585 {
586         struct pxafb_lcd_reg new_regs;
587         u_long flags;
588         u_int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
589
590         pr_debug("pxafb: Configuring PXA LCD\n");
591
592         pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
593                  var->xres, var->hsync_len,
594                  var->left_margin, var->right_margin);
595         pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n",
596                  var->yres, var->vsync_len,
597                  var->upper_margin, var->lower_margin);
598         pr_debug("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
599
600 #if DEBUG_VAR
601         if (var->xres < 16        || var->xres > 1024)
602                 printk(KERN_ERR "%s: invalid xres %d\n",
603                         fbi->fb.fix.id, var->xres);
604         switch(var->bits_per_pixel) {
605         case 1:
606         case 2:
607         case 4:
608         case 8:
609         case 16:
610                 break;
611         default:
612                 printk(KERN_ERR "%s: invalid bit depth %d\n",
613                        fbi->fb.fix.id, var->bits_per_pixel);
614                 break;
615         }
616         if (var->hsync_len < 1    || var->hsync_len > 64)
617                 printk(KERN_ERR "%s: invalid hsync_len %d\n",
618                         fbi->fb.fix.id, var->hsync_len);
619         if (var->left_margin < 1  || var->left_margin > 255)
620                 printk(KERN_ERR "%s: invalid left_margin %d\n",
621                         fbi->fb.fix.id, var->left_margin);
622         if (var->right_margin < 1 || var->right_margin > 255)
623                 printk(KERN_ERR "%s: invalid right_margin %d\n",
624                         fbi->fb.fix.id, var->right_margin);
625         if (var->yres < 1         || var->yres > 1024)
626                 printk(KERN_ERR "%s: invalid yres %d\n",
627                         fbi->fb.fix.id, var->yres);
628         if (var->vsync_len < 1    || var->vsync_len > 64)
629                 printk(KERN_ERR "%s: invalid vsync_len %d\n",
630                         fbi->fb.fix.id, var->vsync_len);
631         if (var->upper_margin < 0 || var->upper_margin > 255)
632                 printk(KERN_ERR "%s: invalid upper_margin %d\n",
633                         fbi->fb.fix.id, var->upper_margin);
634         if (var->lower_margin < 0 || var->lower_margin > 255)
635                 printk(KERN_ERR "%s: invalid lower_margin %d\n",
636                         fbi->fb.fix.id, var->lower_margin);
637 #endif
638
639         new_regs.lccr0 = fbi->lccr0 |
640                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
641                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
642
643         new_regs.lccr1 =
644                 LCCR1_DisWdth(var->xres) +
645                 LCCR1_HorSnchWdth(var->hsync_len) +
646                 LCCR1_BegLnDel(var->left_margin) +
647                 LCCR1_EndLnDel(var->right_margin);
648
649         /*
650          * If we have a dual scan LCD, we need to halve
651          * the YRES parameter.
652          */
653         lines_per_panel = var->yres;
654         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
655                 lines_per_panel /= 2;
656
657         new_regs.lccr2 =
658                 LCCR2_DisHght(lines_per_panel) +
659                 LCCR2_VrtSnchWdth(var->vsync_len) +
660                 LCCR2_BegFrmDel(var->upper_margin) +
661                 LCCR2_EndFrmDel(var->lower_margin);
662
663         new_regs.lccr3 = fbi->lccr3 |
664                 pxafb_bpp_to_lccr3(var) |
665                 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
666                 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
667
668         if (pcd)
669                 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
670
671         pr_debug("nlccr0 = 0x%08x\n", new_regs.lccr0);
672         pr_debug("nlccr1 = 0x%08x\n", new_regs.lccr1);
673         pr_debug("nlccr2 = 0x%08x\n", new_regs.lccr2);
674         pr_debug("nlccr3 = 0x%08x\n", new_regs.lccr3);
675
676         /* Update shadow copy atomically */
677         local_irq_save(flags);
678
679         /* setup dma descriptors */
680         fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
681         fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
682         fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
683
684         fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
685         fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
686         fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
687
688 #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
689
690         /* populate descriptors */
691         fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
692         fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
693         fbi->dmadesc_fblow_cpu->fidr  = 0;
694         fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
695
696         fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
697
698         fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
699         fbi->dmadesc_fbhigh_cpu->fidr = 0;
700         fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
701
702         fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
703         fbi->dmadesc_palette_cpu->fidr  = 0;
704         if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
705                 fbi->dmadesc_palette_cpu->ldcmd = fbi->palette_size *
706                                                         sizeof(u16);
707         else
708                 fbi->dmadesc_palette_cpu->ldcmd = fbi->palette_size *
709                                                         sizeof(u32);
710         fbi->dmadesc_palette_cpu->ldcmd |= LDCMD_PAL;
711
712         if (var->bits_per_pixel == 16) {
713                 /* palette shouldn't be loaded in true-color mode */
714                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
715                 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
716                 /* init it to something, even though we won't be using it */
717                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
718         } else {
719                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
720                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
721                 fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
722         }
723
724 #if 0
725         pr_debug("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
726         pr_debug("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
727         pr_debug("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
728         pr_debug("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
729         pr_debug("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
730         pr_debug("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
731
732         pr_debug("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
733         pr_debug("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
734         pr_debug("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
735
736         pr_debug("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
737         pr_debug("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
738         pr_debug("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
739
740         pr_debug("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
741         pr_debug("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
742         pr_debug("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
743 #endif
744
745         fbi->reg_lccr0 = new_regs.lccr0;
746         fbi->reg_lccr1 = new_regs.lccr1;
747         fbi->reg_lccr2 = new_regs.lccr2;
748         fbi->reg_lccr3 = new_regs.lccr3;
749         fbi->reg_lccr4 = LCCR4 & (~LCCR4_PAL_FOR_MASK);
750         fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
751         set_hsync_time(fbi, pcd);
752         local_irq_restore(flags);
753
754         /*
755          * Only update the registers if the controller is enabled
756          * and something has changed.
757          */
758         if ((LCCR0  != fbi->reg_lccr0) || (LCCR1  != fbi->reg_lccr1) ||
759             (LCCR2  != fbi->reg_lccr2) || (LCCR3  != fbi->reg_lccr3) ||
760             (FDADR0 != fbi->fdadr0)    || (FDADR1 != fbi->fdadr1))
761                 pxafb_schedule_work(fbi, C_REENABLE);
762
763         return 0;
764 }
765
766 /*
767  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
768  * Do not call them directly; set_ctrlr_state does the correct serialisation
769  * to ensure that things happen in the right way 100% of time time.
770  *      -- rmk
771  */
772 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
773 {
774         pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
775
776         if (pxafb_backlight_power)
777                 pxafb_backlight_power(on);
778 }
779
780 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
781 {
782         pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
783
784         if (pxafb_lcd_power)
785                 pxafb_lcd_power(on, &fbi->fb.var);
786 }
787
788 static void pxafb_setup_gpio(struct pxafb_info *fbi)
789 {
790         int gpio, ldd_bits;
791         unsigned int lccr0 = fbi->lccr0;
792
793         /*
794          * setup is based on type of panel supported
795         */
796
797         /* 4 bit interface */
798         if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
799             (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
800             (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
801                 ldd_bits = 4;
802
803         /* 8 bit interface */
804         else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
805                   ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
806                  ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
807                   (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
808                 ldd_bits = 8;
809
810         /* 16 bit interface */
811         else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
812                  ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
813                 ldd_bits = 16;
814
815         else {
816                 printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
817                 return;
818         }
819
820         for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
821                 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
822         pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
823         pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
824         pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
825         pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
826 }
827
828 static void pxafb_enable_controller(struct pxafb_info *fbi)
829 {
830         pr_debug("pxafb: Enabling LCD controller\n");
831         pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
832         pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
833         pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
834         pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
835         pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
836         pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
837
838         /* enable LCD controller clock */
839         clk_enable(fbi->clk);
840
841         /* Sequence from 11.7.10 */
842         LCCR3 = fbi->reg_lccr3;
843         LCCR2 = fbi->reg_lccr2;
844         LCCR1 = fbi->reg_lccr1;
845         LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
846
847         FDADR0 = fbi->fdadr0;
848         FDADR1 = fbi->fdadr1;
849         LCCR0 |= LCCR0_ENB;
850
851         pr_debug("FDADR0 0x%08x\n", (unsigned int) FDADR0);
852         pr_debug("FDADR1 0x%08x\n", (unsigned int) FDADR1);
853         pr_debug("LCCR0 0x%08x\n", (unsigned int) LCCR0);
854         pr_debug("LCCR1 0x%08x\n", (unsigned int) LCCR1);
855         pr_debug("LCCR2 0x%08x\n", (unsigned int) LCCR2);
856         pr_debug("LCCR3 0x%08x\n", (unsigned int) LCCR3);
857         pr_debug("LCCR4 0x%08x\n", (unsigned int) LCCR4);
858 }
859
860 static void pxafb_disable_controller(struct pxafb_info *fbi)
861 {
862         DECLARE_WAITQUEUE(wait, current);
863
864         pr_debug("pxafb: disabling LCD controller\n");
865
866         set_current_state(TASK_UNINTERRUPTIBLE);
867         add_wait_queue(&fbi->ctrlr_wait, &wait);
868
869         LCSR = 0xffffffff;      /* Clear LCD Status Register */
870         LCCR0 &= ~LCCR0_LDM;    /* Enable LCD Disable Done Interrupt */
871         LCCR0 |= LCCR0_DIS;     /* Disable LCD Controller */
872
873         schedule_timeout(200 * HZ / 1000);
874         remove_wait_queue(&fbi->ctrlr_wait, &wait);
875
876         /* disable LCD controller clock */
877         clk_disable(fbi->clk);
878 }
879
880 /*
881  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
882  */
883 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
884 {
885         struct pxafb_info *fbi = dev_id;
886         unsigned int lcsr = LCSR;
887
888         if (lcsr & LCSR_LDD) {
889                 LCCR0 |= LCCR0_LDM;
890                 wake_up(&fbi->ctrlr_wait);
891         }
892
893         LCSR = lcsr;
894         return IRQ_HANDLED;
895 }
896
897 /*
898  * This function must be called from task context only, since it will
899  * sleep when disabling the LCD controller, or if we get two contending
900  * processes trying to alter state.
901  */
902 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
903 {
904         u_int old_state;
905
906         down(&fbi->ctrlr_sem);
907
908         old_state = fbi->state;
909
910         /*
911          * Hack around fbcon initialisation.
912          */
913         if (old_state == C_STARTUP && state == C_REENABLE)
914                 state = C_ENABLE;
915
916         switch (state) {
917         case C_DISABLE_CLKCHANGE:
918                 /*
919                  * Disable controller for clock change.  If the
920                  * controller is already disabled, then do nothing.
921                  */
922                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
923                         fbi->state = state;
924                         //TODO __pxafb_lcd_power(fbi, 0);
925                         pxafb_disable_controller(fbi);
926                 }
927                 break;
928
929         case C_DISABLE_PM:
930         case C_DISABLE:
931                 /*
932                  * Disable controller
933                  */
934                 if (old_state != C_DISABLE) {
935                         fbi->state = state;
936                         __pxafb_backlight_power(fbi, 0);
937                         __pxafb_lcd_power(fbi, 0);
938                         if (old_state != C_DISABLE_CLKCHANGE)
939                                 pxafb_disable_controller(fbi);
940                 }
941                 break;
942
943         case C_ENABLE_CLKCHANGE:
944                 /*
945                  * Enable the controller after clock change.  Only
946                  * do this if we were disabled for the clock change.
947                  */
948                 if (old_state == C_DISABLE_CLKCHANGE) {
949                         fbi->state = C_ENABLE;
950                         pxafb_enable_controller(fbi);
951                         //TODO __pxafb_lcd_power(fbi, 1);
952                 }
953                 break;
954
955         case C_REENABLE:
956                 /*
957                  * Re-enable the controller only if it was already
958                  * enabled.  This is so we reprogram the control
959                  * registers.
960                  */
961                 if (old_state == C_ENABLE) {
962                         __pxafb_lcd_power(fbi, 0);
963                         pxafb_disable_controller(fbi);
964                         pxafb_setup_gpio(fbi);
965                         pxafb_enable_controller(fbi);
966                         __pxafb_lcd_power(fbi, 1);
967                 }
968                 break;
969
970         case C_ENABLE_PM:
971                 /*
972                  * Re-enable the controller after PM.  This is not
973                  * perfect - think about the case where we were doing
974                  * a clock change, and we suspended half-way through.
975                  */
976                 if (old_state != C_DISABLE_PM)
977                         break;
978                 /* fall through */
979
980         case C_ENABLE:
981                 /*
982                  * Power up the LCD screen, enable controller, and
983                  * turn on the backlight.
984                  */
985                 if (old_state != C_ENABLE) {
986                         fbi->state = C_ENABLE;
987                         pxafb_setup_gpio(fbi);
988                         pxafb_enable_controller(fbi);
989                         __pxafb_lcd_power(fbi, 1);
990                         __pxafb_backlight_power(fbi, 1);
991                 }
992                 break;
993         }
994         up(&fbi->ctrlr_sem);
995 }
996
997 /*
998  * Our LCD controller task (which is called when we blank or unblank)
999  * via keventd.
1000  */
1001 static void pxafb_task(struct work_struct *work)
1002 {
1003         struct pxafb_info *fbi =
1004                 container_of(work, struct pxafb_info, task);
1005         u_int state = xchg(&fbi->task_state, -1);
1006
1007         set_ctrlr_state(fbi, state);
1008 }
1009
1010 #ifdef CONFIG_CPU_FREQ
1011 /*
1012  * CPU clock speed change handler.  We need to adjust the LCD timing
1013  * parameters when the CPU clock is adjusted by the power management
1014  * subsystem.
1015  *
1016  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1017  */
1018 static int
1019 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1020 {
1021         struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1022         //TODO struct cpufreq_freqs *f = data;
1023         u_int pcd;
1024
1025         switch (val) {
1026         case CPUFREQ_PRECHANGE:
1027                 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1028                 break;
1029
1030         case CPUFREQ_POSTCHANGE:
1031                 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1032                 set_hsync_time(fbi, pcd);
1033                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
1034                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1035                 break;
1036         }
1037         return 0;
1038 }
1039
1040 static int
1041 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1042 {
1043         struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1044         struct fb_var_screeninfo *var = &fbi->fb.var;
1045         struct cpufreq_policy *policy = data;
1046
1047         switch (val) {
1048         case CPUFREQ_ADJUST:
1049         case CPUFREQ_INCOMPATIBLE:
1050                 pr_debug("min dma period: %d ps, "
1051                         "new clock %d kHz\n", pxafb_display_dma_period(var),
1052                         policy->max);
1053                 // TODO: fill in min/max values
1054                 break;
1055 #if 0
1056         case CPUFREQ_NOTIFY:
1057                 printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
1058                 do {} while(0);
1059                 /* todo: panic if min/max values aren't fulfilled
1060                  * [can't really happen unless there's a bug in the
1061                  * CPU policy verification process *
1062                  */
1063                 break;
1064 #endif
1065         }
1066         return 0;
1067 }
1068 #endif
1069
1070 #ifdef CONFIG_PM
1071 /*
1072  * Power management hooks.  Note that we won't be called from IRQ context,
1073  * unlike the blank functions above, so we may sleep.
1074  */
1075 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1076 {
1077         struct pxafb_info *fbi = platform_get_drvdata(dev);
1078
1079         set_ctrlr_state(fbi, C_DISABLE_PM);
1080         return 0;
1081 }
1082
1083 static int pxafb_resume(struct platform_device *dev)
1084 {
1085         struct pxafb_info *fbi = platform_get_drvdata(dev);
1086
1087         set_ctrlr_state(fbi, C_ENABLE_PM);
1088         return 0;
1089 }
1090 #else
1091 #define pxafb_suspend   NULL
1092 #define pxafb_resume    NULL
1093 #endif
1094
1095 /*
1096  * pxafb_map_video_memory():
1097  *      Allocates the DRAM memory for the frame buffer.  This buffer is
1098  *      remapped into a non-cached, non-buffered, memory region to
1099  *      allow palette and pixel writes to occur without flushing the
1100  *      cache.  Once this area is remapped, all virtual memory
1101  *      access to the video memory should occur at the new region.
1102  */
1103 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
1104 {
1105         u_long palette_mem_size;
1106
1107         /*
1108          * We reserve one page for the palette, plus the size
1109          * of the framebuffer.
1110          */
1111         fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1112         fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1113                                               &fbi->map_dma, GFP_KERNEL);
1114
1115         if (fbi->map_cpu) {
1116                 /* prevent initial garbage on screen */
1117                 memset(fbi->map_cpu, 0, fbi->map_size);
1118                 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1119                 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1120                 /*
1121                  * FIXME: this is actually the wrong thing to place in
1122                  * smem_start.  But fbdev suffers from the problem that
1123                  * it needs an API which doesn't exist (in this case,
1124                  * dma_writecombine_mmap)
1125                  */
1126                 fbi->fb.fix.smem_start = fbi->screen_dma;
1127                 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1128
1129                 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1130                         palette_mem_size = fbi->palette_size * sizeof(u16);
1131                 else
1132                         palette_mem_size = fbi->palette_size * sizeof(u32);
1133
1134                 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
1135
1136                 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
1137                 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
1138         }
1139
1140         return fbi->map_cpu ? 0 : -ENOMEM;
1141 }
1142
1143 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1144 {
1145         struct pxafb_info *fbi;
1146         void *addr;
1147         struct pxafb_mach_info *inf = dev->platform_data;
1148         struct pxafb_mode_info *mode = inf->modes;
1149         int i, smemlen;
1150
1151         /* Alloc the pxafb_info and pseudo_palette in one step */
1152         fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1153         if (!fbi)
1154                 return NULL;
1155
1156         memset(fbi, 0, sizeof(struct pxafb_info));
1157         fbi->dev = dev;
1158
1159         fbi->clk = clk_get(dev, "LCDCLK");
1160         if (IS_ERR(fbi->clk)) {
1161                 kfree(fbi);
1162                 return NULL;
1163         }
1164
1165         strcpy(fbi->fb.fix.id, PXA_NAME);
1166
1167         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1168         fbi->fb.fix.type_aux    = 0;
1169         fbi->fb.fix.xpanstep    = 0;
1170         fbi->fb.fix.ypanstep    = 0;
1171         fbi->fb.fix.ywrapstep   = 0;
1172         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1173
1174         fbi->fb.var.nonstd      = 0;
1175         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1176         fbi->fb.var.height      = -1;
1177         fbi->fb.var.width       = -1;
1178         fbi->fb.var.accel_flags = 0;
1179         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1180
1181         fbi->fb.fbops           = &pxafb_ops;
1182         fbi->fb.flags           = FBINFO_DEFAULT;
1183         fbi->fb.node            = -1;
1184
1185         addr = fbi;
1186         addr = addr + sizeof(struct pxafb_info);
1187         fbi->fb.pseudo_palette  = addr;
1188
1189         pxafb_setmode(&fbi->fb.var, mode);
1190
1191         fbi->cmap_inverse               = inf->cmap_inverse;
1192         fbi->cmap_static                = inf->cmap_static;
1193
1194         fbi->lccr0                      = inf->lccr0;
1195         fbi->lccr3                      = inf->lccr3;
1196         fbi->lccr4                      = inf->lccr4;
1197         fbi->state                      = C_STARTUP;
1198         fbi->task_state                 = (u_char)-1;
1199
1200         for (i = 0; i < inf->num_modes; i++) {
1201                 smemlen = mode[i].xres * mode[i].yres * mode[i].bpp / 8;
1202                 if (smemlen > fbi->fb.fix.smem_len)
1203                         fbi->fb.fix.smem_len = smemlen;
1204         }
1205
1206         init_waitqueue_head(&fbi->ctrlr_wait);
1207         INIT_WORK(&fbi->task, pxafb_task);
1208         init_MUTEX(&fbi->ctrlr_sem);
1209
1210         return fbi;
1211 }
1212
1213 #ifdef CONFIG_FB_PXA_PARAMETERS
1214 static int __init pxafb_parse_options(struct device *dev, char *options)
1215 {
1216         struct pxafb_mach_info *inf = dev->platform_data;
1217         char *this_opt;
1218
1219         if (!options || !*options)
1220                 return 0;
1221
1222         dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1223
1224         /* could be made table driven or similar?... */
1225         while ((this_opt = strsep(&options, ",")) != NULL) {
1226                 if (!strncmp(this_opt, "mode:", 5)) {
1227                         const char *name = this_opt+5;
1228                         unsigned int namelen = strlen(name);
1229                         int res_specified = 0, bpp_specified = 0;
1230                         unsigned int xres = 0, yres = 0, bpp = 0;
1231                         int yres_specified = 0;
1232                         int i;
1233                         for (i = namelen-1; i >= 0; i--) {
1234                                 switch (name[i]) {
1235                                 case '-':
1236                                         namelen = i;
1237                                         if (!bpp_specified && !yres_specified) {
1238                                                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1239                                                 bpp_specified = 1;
1240                                         } else
1241                                                 goto done;
1242                                         break;
1243                                 case 'x':
1244                                         if (!yres_specified) {
1245                                                 yres = simple_strtoul(&name[i+1], NULL, 0);
1246                                                 yres_specified = 1;
1247                                         } else
1248                                                 goto done;
1249                                         break;
1250                                 case '0' ... '9':
1251                                         break;
1252                                 default:
1253                                         goto done;
1254                                 }
1255                         }
1256                         if (i < 0 && yres_specified) {
1257                                 xres = simple_strtoul(name, NULL, 0);
1258                                 res_specified = 1;
1259                         }
1260                 done:
1261                         if (res_specified) {
1262                                 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1263                                 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1264                         }
1265                         if (bpp_specified)
1266                                 switch (bpp) {
1267                                 case 1:
1268                                 case 2:
1269                                 case 4:
1270                                 case 8:
1271                                 case 16:
1272                                         inf->modes[0].bpp = bpp;
1273                                         dev_info(dev, "overriding bit depth: %d\n", bpp);
1274                                         break;
1275                                 default:
1276                                         dev_err(dev, "Depth %d is not valid\n", bpp);
1277                                 }
1278                 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1279                         inf->modes[0].pixclock = simple_strtoul(this_opt+9, NULL, 0);
1280                         dev_info(dev, "override pixclock: %ld\n", inf->modes[0].pixclock);
1281                 } else if (!strncmp(this_opt, "left:", 5)) {
1282                         inf->modes[0].left_margin = simple_strtoul(this_opt+5, NULL, 0);
1283                         dev_info(dev, "override left: %u\n", inf->modes[0].left_margin);
1284                 } else if (!strncmp(this_opt, "right:", 6)) {
1285                         inf->modes[0].right_margin = simple_strtoul(this_opt+6, NULL, 0);
1286                         dev_info(dev, "override right: %u\n", inf->modes[0].right_margin);
1287                 } else if (!strncmp(this_opt, "upper:", 6)) {
1288                         inf->modes[0].upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1289                         dev_info(dev, "override upper: %u\n", inf->modes[0].upper_margin);
1290                 } else if (!strncmp(this_opt, "lower:", 6)) {
1291                         inf->modes[0].lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1292                         dev_info(dev, "override lower: %u\n", inf->modes[0].lower_margin);
1293                 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1294                         inf->modes[0].hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1295                         dev_info(dev, "override hsynclen: %u\n", inf->modes[0].hsync_len);
1296                 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1297                         inf->modes[0].vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1298                         dev_info(dev, "override vsynclen: %u\n", inf->modes[0].vsync_len);
1299                 } else if (!strncmp(this_opt, "hsync:", 6)) {
1300                         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1301                                 dev_info(dev, "override hsync: Active Low\n");
1302                                 inf->modes[0].sync &= ~FB_SYNC_HOR_HIGH_ACT;
1303                         } else {
1304                                 dev_info(dev, "override hsync: Active High\n");
1305                                 inf->modes[0].sync |= FB_SYNC_HOR_HIGH_ACT;
1306                         }
1307                 } else if (!strncmp(this_opt, "vsync:", 6)) {
1308                         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1309                                 dev_info(dev, "override vsync: Active Low\n");
1310                                 inf->modes[0].sync &= ~FB_SYNC_VERT_HIGH_ACT;
1311                         } else {
1312                                 dev_info(dev, "override vsync: Active High\n");
1313                                 inf->modes[0].sync |= FB_SYNC_VERT_HIGH_ACT;
1314                         }
1315                 } else if (!strncmp(this_opt, "dpc:", 4)) {
1316                         if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1317                                 dev_info(dev, "override double pixel clock: false\n");
1318                                 inf->lccr3 &= ~LCCR3_DPC;
1319                         } else {
1320                                 dev_info(dev, "override double pixel clock: true\n");
1321                                 inf->lccr3 |= LCCR3_DPC;
1322                         }
1323                 } else if (!strncmp(this_opt, "outputen:", 9)) {
1324                         if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1325                                 dev_info(dev, "override output enable: active low\n");
1326                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1327                         } else {
1328                                 dev_info(dev, "override output enable: active high\n");
1329                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1330                         }
1331                 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1332                         if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1333                                 dev_info(dev, "override pixel clock polarity: falling edge\n");
1334                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1335                         } else {
1336                                 dev_info(dev, "override pixel clock polarity: rising edge\n");
1337                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1338                         }
1339                 } else if (!strncmp(this_opt, "color", 5)) {
1340                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1341                 } else if (!strncmp(this_opt, "mono", 4)) {
1342                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1343                 } else if (!strncmp(this_opt, "active", 6)) {
1344                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1345                 } else if (!strncmp(this_opt, "passive", 7)) {
1346                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1347                 } else if (!strncmp(this_opt, "single", 6)) {
1348                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1349                 } else if (!strncmp(this_opt, "dual", 4)) {
1350                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1351                 } else if (!strncmp(this_opt, "4pix", 4)) {
1352                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1353                 } else if (!strncmp(this_opt, "8pix", 4)) {
1354                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1355                 } else {
1356                         dev_err(dev, "unknown option: %s\n", this_opt);
1357                         return -EINVAL;
1358                 }
1359         }
1360         return 0;
1361
1362 }
1363 #endif
1364
1365 static int __init pxafb_probe(struct platform_device *dev)
1366 {
1367         struct pxafb_info *fbi;
1368         struct pxafb_mach_info *inf;
1369         int ret;
1370
1371         dev_dbg(&dev->dev, "pxafb_probe\n");
1372
1373         inf = dev->dev.platform_data;
1374         ret = -ENOMEM;
1375         fbi = NULL;
1376         if (!inf)
1377                 goto failed;
1378
1379 #ifdef CONFIG_FB_PXA_PARAMETERS
1380         ret = pxafb_parse_options(&dev->dev, g_options);
1381         if (ret < 0)
1382                 goto failed;
1383 #endif
1384
1385 #ifdef DEBUG_VAR
1386         /* Check for various illegal bit-combinations. Currently only
1387          * a warning is given. */
1388
1389         if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1390                 dev_warn(&dev->dev, "machine LCCR0 setting contains illegal bits: %08x\n",
1391                         inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1392         if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1393                 dev_warn(&dev->dev, "machine LCCR3 setting contains illegal bits: %08x\n",
1394                         inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1395         if (inf->lccr0 & LCCR0_DPD &&
1396             ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1397              (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1398              (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1399                 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
1400                          " single panel mode\n");
1401         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1402             (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1403                 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
1404         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1405              (inf->modes->upper_margin || inf->modes->lower_margin))
1406                 dev_warn(&dev->dev, "Upper and lower margins must be 0 in passive mode\n");
1407 #endif
1408
1409         dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",inf->modes->xres, inf->modes->yres, inf->modes->bpp);
1410         if (inf->modes->xres == 0 || inf->modes->yres == 0 || inf->modes->bpp == 0) {
1411                 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1412                 ret = -EINVAL;
1413                 goto failed;
1414         }
1415         pxafb_backlight_power = inf->pxafb_backlight_power;
1416         pxafb_lcd_power = inf->pxafb_lcd_power;
1417         fbi = pxafb_init_fbinfo(&dev->dev);
1418         if (!fbi) {
1419                 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1420                 ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
1421                 goto failed;
1422         }
1423
1424         /* Initialize video memory */
1425         ret = pxafb_map_video_memory(fbi);
1426         if (ret) {
1427                 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1428                 ret = -ENOMEM;
1429                 goto failed;
1430         }
1431
1432         ret = request_irq(IRQ_LCD, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1433         if (ret) {
1434                 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1435                 ret = -EBUSY;
1436                 goto failed;
1437         }
1438
1439         /*
1440          * This makes sure that our colour bitfield
1441          * descriptors are correctly initialised.
1442          */
1443         pxafb_check_var(&fbi->fb.var, &fbi->fb);
1444         pxafb_set_par(&fbi->fb);
1445
1446         platform_set_drvdata(dev, fbi);
1447
1448         ret = register_framebuffer(&fbi->fb);
1449         if (ret < 0) {
1450                 dev_err(&dev->dev, "Failed to register framebuffer device: %d\n", ret);
1451                 goto failed;
1452         }
1453
1454 #ifdef CONFIG_PM
1455         // TODO
1456 #endif
1457
1458 #ifdef CONFIG_CPU_FREQ
1459         fbi->freq_transition.notifier_call = pxafb_freq_transition;
1460         fbi->freq_policy.notifier_call = pxafb_freq_policy;
1461         cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1462         cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1463 #endif
1464
1465         /*
1466          * Ok, now enable the LCD controller
1467          */
1468         set_ctrlr_state(fbi, C_ENABLE);
1469
1470         return 0;
1471
1472 failed:
1473         platform_set_drvdata(dev, NULL);
1474         kfree(fbi);
1475         return ret;
1476 }
1477
1478 static struct platform_driver pxafb_driver = {
1479         .probe          = pxafb_probe,
1480 #ifdef CONFIG_PM
1481         .suspend        = pxafb_suspend,
1482         .resume         = pxafb_resume,
1483 #endif
1484         .driver         = {
1485                 .name   = "pxa2xx-fb",
1486         },
1487 };
1488
1489 #ifndef MODULE
1490 static int __devinit pxafb_setup(char *options)
1491 {
1492 # ifdef CONFIG_FB_PXA_PARAMETERS
1493         if (options)
1494                 strlcpy(g_options, options, sizeof(g_options));
1495 # endif
1496         return 0;
1497 }
1498 #else
1499 # ifdef CONFIG_FB_PXA_PARAMETERS
1500 module_param_string(options, g_options, sizeof(g_options), 0);
1501 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1502 # endif
1503 #endif
1504
1505 static int __devinit pxafb_init(void)
1506 {
1507 #ifndef MODULE
1508         char *option = NULL;
1509
1510         if (fb_get_options("pxafb", &option))
1511                 return -ENODEV;
1512         pxafb_setup(option);
1513 #endif
1514         return platform_driver_register(&pxafb_driver);
1515 }
1516
1517 module_init(pxafb_init);
1518
1519 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1520 MODULE_LICENSE("GPL");