[SPARC]: Fix serial console device detection.
[linux-2.6.git] / drivers / video / aty / atyfb_base.c
1 /*
2  *  ATI Frame Buffer Device Driver Core
3  *
4  *      Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
5  *      Copyright (C) 1997-2001  Geert Uytterhoeven
6  *      Copyright (C) 1998  Bernd Harries
7  *      Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
8  *
9  *  This driver supports the following ATI graphics chips:
10  *    - ATI Mach64
11  *
12  *  To do: add support for
13  *    - ATI Rage128 (from aty128fb.c)
14  *    - ATI Radeon (from radeonfb.c)
15  *
16  *  This driver is partly based on the PowerMac console driver:
17  *
18  *      Copyright (C) 1996 Paul Mackerras
19  *
20  *  and on the PowerMac ATI/mach64 display driver:
21  *
22  *      Copyright (C) 1997 Michael AK Tesch
23  *
24  *            with work by Jon Howell
25  *                         Harry AC Eaton
26  *                         Anthony Tong <atong@uiuc.edu>
27  *
28  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
30  *
31  *  This file is subject to the terms and conditions of the GNU General Public
32  *  License. See the file COPYING in the main directory of this archive for
33  *  more details.
34  *
35  *  Many thanks to Nitya from ATI devrel for support and patience !
36  */
37
38 /******************************************************************************
39
40   TODO:
41
42     - cursor support on all cards and all ramdacs.
43     - cursor parameters controlable via ioctl()s.
44     - guess PLL and MCLK based on the original PLL register values initialized
45       by Open Firmware (if they are initialized). BIOS is done
46
47     (Anyone with Mac to help with this?)
48
49 ******************************************************************************/
50
51
52 #include <linux/module.h>
53 #include <linux/moduleparam.h>
54 #include <linux/kernel.h>
55 #include <linux/errno.h>
56 #include <linux/string.h>
57 #include <linux/mm.h>
58 #include <linux/slab.h>
59 #include <linux/vmalloc.h>
60 #include <linux/delay.h>
61 #include <linux/console.h>
62 #include <linux/fb.h>
63 #include <linux/init.h>
64 #include <linux/pci.h>
65 #include <linux/interrupt.h>
66 #include <linux/spinlock.h>
67 #include <linux/wait.h>
68 #include <linux/backlight.h>
69
70 #include <asm/io.h>
71 #include <asm/uaccess.h>
72
73 #include <video/mach64.h>
74 #include "atyfb.h"
75 #include "ati_ids.h"
76
77 #ifdef __powerpc__
78 #include <asm/machdep.h>
79 #include <asm/prom.h>
80 #include "../macmodes.h"
81 #endif
82 #ifdef __sparc__
83 #include <asm/fbio.h>
84 #include <asm/oplib.h>
85 #include <asm/prom.h>
86 #endif
87
88 #ifdef CONFIG_ADB_PMU
89 #include <linux/adb.h>
90 #include <linux/pmu.h>
91 #endif
92 #ifdef CONFIG_BOOTX_TEXT
93 #include <asm/btext.h>
94 #endif
95 #ifdef CONFIG_PMAC_BACKLIGHT
96 #include <asm/backlight.h>
97 #endif
98 #ifdef CONFIG_MTRR
99 #include <asm/mtrr.h>
100 #endif
101
102 /*
103  * Debug flags.
104  */
105 #undef DEBUG
106 /*#define DEBUG*/
107
108 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
109 /*  - must be large enough to catch all GUI-Regs   */
110 /*  - must be aligned to a PAGE boundary           */
111 #define GUI_RESERVE     (1 * PAGE_SIZE)
112
113 /* FIXME: remove the FAIL definition */
114 #define FAIL(msg) do { \
115         if (!(var->activate & FB_ACTIVATE_TEST)) \
116                 printk(KERN_CRIT "atyfb: " msg "\n"); \
117         return -EINVAL; \
118 } while (0)
119 #define FAIL_MAX(msg, x, _max_) do { \
120         if (x > _max_) { \
121                 if (!(var->activate & FB_ACTIVATE_TEST)) \
122                         printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
123                 return -EINVAL; \
124         } \
125 } while (0)
126 #ifdef DEBUG
127 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "atyfb: " fmt, ## args)
128 #else
129 #define DPRINTK(fmt, args...)
130 #endif
131
132 #define PRINTKI(fmt, args...)   printk(KERN_INFO "atyfb: " fmt, ## args)
133 #define PRINTKE(fmt, args...)    printk(KERN_ERR "atyfb: " fmt, ## args)
134
135 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
136 defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
137 static const u32 lt_lcd_regs[] = {
138         CONFIG_PANEL_LG,
139         LCD_GEN_CNTL_LG,
140         DSTN_CONTROL_LG,
141         HFB_PITCH_ADDR_LG,
142         HORZ_STRETCHING_LG,
143         VERT_STRETCHING_LG,
144         0, /* EXT_VERT_STRETCH */
145         LT_GIO_LG,
146         POWER_MANAGEMENT_LG
147 };
148
149 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
150 {
151         if (M64_HAS(LT_LCD_REGS)) {
152                 aty_st_le32(lt_lcd_regs[index], val, par);
153         } else {
154                 unsigned long temp;
155
156                 /* write addr byte */
157                 temp = aty_ld_le32(LCD_INDEX, par);
158                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
159                 /* write the register value */
160                 aty_st_le32(LCD_DATA, val, par);
161         }
162 }
163
164 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
165 {
166         if (M64_HAS(LT_LCD_REGS)) {
167                 return aty_ld_le32(lt_lcd_regs[index], par);
168         } else {
169                 unsigned long temp;
170
171                 /* write addr byte */
172                 temp = aty_ld_le32(LCD_INDEX, par);
173                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
174                 /* read the register value */
175                 return aty_ld_le32(LCD_DATA, par);
176         }
177 }
178 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
179
180 #ifdef CONFIG_FB_ATY_GENERIC_LCD
181 /*
182  * ATIReduceRatio --
183  *
184  * Reduce a fraction by factoring out the largest common divider of the
185  * fraction's numerator and denominator.
186  */
187 static void ATIReduceRatio(int *Numerator, int *Denominator)
188 {
189     int Multiplier, Divider, Remainder;
190
191     Multiplier = *Numerator;
192     Divider = *Denominator;
193
194     while ((Remainder = Multiplier % Divider))
195     {
196         Multiplier = Divider;
197         Divider = Remainder;
198     }
199
200     *Numerator /= Divider;
201     *Denominator /= Divider;
202 }
203 #endif
204     /*
205      *  The Hardware parameters for each card
206      */
207
208 struct pci_mmap_map {
209         unsigned long voff;
210         unsigned long poff;
211         unsigned long size;
212         unsigned long prot_flag;
213         unsigned long prot_mask;
214 };
215
216 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
217         .id             = "ATY Mach64",
218         .type           = FB_TYPE_PACKED_PIXELS,
219         .visual         = FB_VISUAL_PSEUDOCOLOR,
220         .xpanstep       = 8,
221         .ypanstep       = 1,
222 };
223
224     /*
225      *  Frame buffer device API
226      */
227
228 static int atyfb_open(struct fb_info *info, int user);
229 static int atyfb_release(struct fb_info *info, int user);
230 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
231 static int atyfb_set_par(struct fb_info *info);
232 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
233         u_int transp, struct fb_info *info);
234 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
235 static int atyfb_blank(int blank, struct fb_info *info);
236 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
237 #ifdef __sparc__
238 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
239 #endif
240 static int atyfb_sync(struct fb_info *info);
241
242     /*
243      *  Internal routines
244      */
245
246 static int aty_init(struct fb_info *info);
247 static void aty_resume_chip(struct fb_info *info);
248 #ifdef CONFIG_ATARI
249 static int store_video_par(char *videopar, unsigned char m64_num);
250 #endif
251
252 static struct crtc saved_crtc;
253 static union aty_pll saved_pll;
254 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
255
256 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
257 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
258 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
259 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
260 #ifdef CONFIG_PPC
261 static int read_aty_sense(const struct atyfb_par *par);
262 #endif
263
264
265     /*
266      *  Interface used by the world
267      */
268
269 static struct fb_var_screeninfo default_var = {
270         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
271         640, 480, 640, 480, 0, 0, 8, 0,
272         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
273         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
274         0, FB_VMODE_NONINTERLACED
275 };
276
277 static struct fb_videomode defmode = {
278         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
279         NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
280         0, FB_VMODE_NONINTERLACED
281 };
282
283 static struct fb_ops atyfb_ops = {
284         .owner          = THIS_MODULE,
285         .fb_open        = atyfb_open,
286         .fb_release     = atyfb_release,
287         .fb_check_var   = atyfb_check_var,
288         .fb_set_par     = atyfb_set_par,
289         .fb_setcolreg   = atyfb_setcolreg,
290         .fb_pan_display = atyfb_pan_display,
291         .fb_blank       = atyfb_blank,
292         .fb_ioctl       = atyfb_ioctl,
293         .fb_fillrect    = atyfb_fillrect,
294         .fb_copyarea    = atyfb_copyarea,
295         .fb_imageblit   = atyfb_imageblit,
296 #ifdef __sparc__
297         .fb_mmap        = atyfb_mmap,
298 #endif
299         .fb_sync        = atyfb_sync,
300 };
301
302 static int noaccel;
303 #ifdef CONFIG_MTRR
304 static int nomtrr;
305 #endif
306 static int vram;
307 static int pll;
308 static int mclk;
309 static int xclk;
310 static int comp_sync __devinitdata = -1;
311 static char *mode;
312
313 #ifdef CONFIG_PMAC_BACKLIGHT
314 static int backlight __devinitdata = 1;
315 #else
316 static int backlight __devinitdata = 0;
317 #endif
318
319 #ifdef CONFIG_PPC
320 static int default_vmode __devinitdata = VMODE_CHOOSE;
321 static int default_cmode __devinitdata = CMODE_CHOOSE;
322
323 module_param_named(vmode, default_vmode, int, 0);
324 MODULE_PARM_DESC(vmode, "int: video mode for mac");
325 module_param_named(cmode, default_cmode, int, 0);
326 MODULE_PARM_DESC(cmode, "int: color mode for mac");
327 #endif
328
329 #ifdef CONFIG_ATARI
330 static unsigned int mach64_count __devinitdata = 0;
331 static unsigned long phys_vmembase[FB_MAX] __devinitdata = { 0, };
332 static unsigned long phys_size[FB_MAX] __devinitdata = { 0, };
333 static unsigned long phys_guiregbase[FB_MAX] __devinitdata = { 0, };
334 #endif
335
336 /* top -> down is an evolution of mach64 chipset, any corrections? */
337 #define ATI_CHIP_88800GX   (M64F_GX)
338 #define ATI_CHIP_88800CX   (M64F_GX)
339
340 #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
341 #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
342
343 #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
344 #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
345
346 #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
347 #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
348 #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
349
350 /* FIXME what is this chip? */
351 #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
352
353 /* make sets shorter */
354 #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
355
356 #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
357 /*#define ATI_CHIP_264GTDVD  ?*/
358 #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
359
360 #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
361 #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
362 #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
363
364 #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
365 #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
366
367 static struct {
368         u16 pci_id;
369         const char *name;
370         int pll, mclk, xclk, ecp_max;
371         u32 features;
372 } aty_chips[] __devinitdata = {
373 #ifdef CONFIG_FB_ATY_GX
374         /* Mach64 GX */
375         { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
376         { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
377 #endif /* CONFIG_FB_ATY_GX */
378
379 #ifdef CONFIG_FB_ATY_CT
380         { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
381         { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
382
383         /* FIXME what is this chip? */
384         { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
385
386         { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
387         { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
388
389         { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
390         { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
391
392         { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
393
394         { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
395
396         { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
397         { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
398         { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
399         { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
400
401         { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
402         { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
403         { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
404         { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
405         { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
406
407         { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
408         { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
409         { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
410         { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1024x768 },
411         { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
412
413         { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
414         { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
415         { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
416         { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
417         { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
418         { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
419
420         { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
421         { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
422         { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
423         { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
424 #endif /* CONFIG_FB_ATY_CT */
425 };
426
427 /* can not fail */
428 static int __devinit correct_chipset(struct atyfb_par *par)
429 {
430         u8 rev;
431         u16 type;
432         u32 chip_id;
433         const char *name;
434         int i;
435
436         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
437                 if (par->pci_id == aty_chips[i].pci_id)
438                         break;
439
440         name = aty_chips[i].name;
441         par->pll_limits.pll_max = aty_chips[i].pll;
442         par->pll_limits.mclk = aty_chips[i].mclk;
443         par->pll_limits.xclk = aty_chips[i].xclk;
444         par->pll_limits.ecp_max = aty_chips[i].ecp_max;
445         par->features = aty_chips[i].features;
446
447         chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
448         type = chip_id & CFG_CHIP_TYPE;
449         rev = (chip_id & CFG_CHIP_REV) >> 24;
450
451         switch(par->pci_id) {
452 #ifdef CONFIG_FB_ATY_GX
453         case PCI_CHIP_MACH64GX:
454                 if(type != 0x00d7)
455                         return -ENODEV;
456                 break;
457         case PCI_CHIP_MACH64CX:
458                 if(type != 0x0057)
459                         return -ENODEV;
460                 break;
461 #endif
462 #ifdef CONFIG_FB_ATY_CT
463         case PCI_CHIP_MACH64VT:
464                 switch (rev & 0x07) {
465                 case 0x00:
466                         switch (rev & 0xc0) {
467                         case 0x00:
468                                 name = "ATI264VT (A3) (Mach64 VT)";
469                                 par->pll_limits.pll_max = 170;
470                                 par->pll_limits.mclk = 67;
471                                 par->pll_limits.xclk = 67;
472                                 par->pll_limits.ecp_max = 80;
473                                 par->features = ATI_CHIP_264VT;
474                                 break;
475                         case 0x40:
476                                 name = "ATI264VT2 (A4) (Mach64 VT)";
477                                 par->pll_limits.pll_max = 200;
478                                 par->pll_limits.mclk = 67;
479                                 par->pll_limits.xclk = 67;
480                                 par->pll_limits.ecp_max = 80;
481                                 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
482                                 break;
483                         }
484                         break;
485                 case 0x01:
486                         name = "ATI264VT3 (B1) (Mach64 VT)";
487                         par->pll_limits.pll_max = 200;
488                         par->pll_limits.mclk = 67;
489                         par->pll_limits.xclk = 67;
490                         par->pll_limits.ecp_max = 80;
491                         par->features = ATI_CHIP_264VTB;
492                         break;
493                 case 0x02:
494                         name = "ATI264VT3 (B2) (Mach64 VT)";
495                         par->pll_limits.pll_max = 200;
496                         par->pll_limits.mclk = 67;
497                         par->pll_limits.xclk = 67;
498                         par->pll_limits.ecp_max = 80;
499                         par->features = ATI_CHIP_264VT3;
500                         break;
501                 }
502                 break;
503         case PCI_CHIP_MACH64GT:
504                 switch (rev & 0x07) {
505                 case 0x01:
506                         name = "3D RAGE II (Mach64 GT)";
507                         par->pll_limits.pll_max = 170;
508                         par->pll_limits.mclk = 67;
509                         par->pll_limits.xclk = 67;
510                         par->pll_limits.ecp_max = 80;
511                         par->features = ATI_CHIP_264GTB;
512                         break;
513                 case 0x02:
514                         name = "3D RAGE II+ (Mach64 GT)";
515                         par->pll_limits.pll_max = 200;
516                         par->pll_limits.mclk = 67;
517                         par->pll_limits.xclk = 67;
518                         par->pll_limits.ecp_max = 100;
519                         par->features = ATI_CHIP_264GTB;
520                         break;
521                 }
522                 break;
523 #endif
524         }
525
526         PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
527         return 0;
528 }
529
530 static char ram_dram[] __devinitdata = "DRAM";
531 static char ram_resv[] __devinitdata = "RESV";
532 #ifdef CONFIG_FB_ATY_GX
533 static char ram_vram[] __devinitdata = "VRAM";
534 #endif /* CONFIG_FB_ATY_GX */
535 #ifdef CONFIG_FB_ATY_CT
536 static char ram_edo[] __devinitdata = "EDO";
537 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
538 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
539 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
540 static char ram_off[] __devinitdata = "OFF";
541 #endif /* CONFIG_FB_ATY_CT */
542
543
544 static u32 pseudo_palette[16];
545
546 #ifdef CONFIG_FB_ATY_GX
547 static char *aty_gx_ram[8] __devinitdata = {
548         ram_dram, ram_vram, ram_vram, ram_dram,
549         ram_dram, ram_vram, ram_vram, ram_resv
550 };
551 #endif /* CONFIG_FB_ATY_GX */
552
553 #ifdef CONFIG_FB_ATY_CT
554 static char *aty_ct_ram[8] __devinitdata = {
555         ram_off, ram_dram, ram_edo, ram_edo,
556         ram_sdram, ram_sgram, ram_sdram32, ram_resv
557 };
558 #endif /* CONFIG_FB_ATY_CT */
559
560 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
561 {
562         u32 pixclock = var->pixclock;
563 #ifdef CONFIG_FB_ATY_GENERIC_LCD
564         u32 lcd_on_off;
565         par->pll.ct.xres = 0;
566         if (par->lcd_table != 0) {
567                 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
568                 if(lcd_on_off & LCD_ON) {
569                         par->pll.ct.xres = var->xres;
570                         pixclock = par->lcd_pixclock;
571                 }
572         }
573 #endif
574         return pixclock;
575 }
576
577 #if defined(CONFIG_PPC)
578
579 /*
580  *  Apple monitor sense
581  */
582
583 static int __devinit read_aty_sense(const struct atyfb_par *par)
584 {
585         int sense, i;
586
587         aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
588         __delay(200);
589         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
590         __delay(2000);
591         i = aty_ld_le32(GP_IO, par); /* get primary sense value */
592         sense = ((i & 0x3000) >> 3) | (i & 0x100);
593
594         /* drive each sense line low in turn and collect the other 2 */
595         aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
596         __delay(2000);
597         i = aty_ld_le32(GP_IO, par);
598         sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
599         aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
600         __delay(200);
601
602         aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
603         __delay(2000);
604         i = aty_ld_le32(GP_IO, par);
605         sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
606         aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
607         __delay(200);
608
609         aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
610         __delay(2000);
611         sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
612         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
613         return sense;
614 }
615
616 #endif /* defined(CONFIG_PPC) */
617
618 /* ------------------------------------------------------------------------- */
619
620 /*
621  *  CRTC programming
622  */
623
624 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
625 {
626 #ifdef CONFIG_FB_ATY_GENERIC_LCD
627         if (par->lcd_table != 0) {
628                 if(!M64_HAS(LT_LCD_REGS)) {
629                     crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
630                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
631                 }
632                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
633                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
634
635
636                 /* switch to non shadow registers */
637                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
638                     ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
639
640                 /* save stretching */
641                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
642                 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
643                 if (!M64_HAS(LT_LCD_REGS))
644                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
645         }
646 #endif
647         crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
648         crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
649         crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
650         crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
651         crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
652         crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
653         crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
654
655 #ifdef CONFIG_FB_ATY_GENERIC_LCD
656         if (par->lcd_table != 0) {
657                 /* switch to shadow registers */
658                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
659                         SHADOW_EN | SHADOW_RW_EN, par);
660
661                 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
662                 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
663                 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
664                 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
665
666                 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
667         }
668 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
669 }
670
671 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
672 {
673 #ifdef CONFIG_FB_ATY_GENERIC_LCD
674         if (par->lcd_table != 0) {
675                 /* stop CRTC */
676                 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
677
678                 /* update non-shadow registers first */
679                 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
680                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
681                         ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
682
683                 /* temporarily disable stretching */
684                 aty_st_lcd(HORZ_STRETCHING,
685                         crtc->horz_stretching &
686                         ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
687                 aty_st_lcd(VERT_STRETCHING,
688                         crtc->vert_stretching &
689                         ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
690                         VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
691         }
692 #endif
693         /* turn off CRT */
694         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
695
696         DPRINTK("setting up CRTC\n");
697         DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
698             ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
699             (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
700             (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
701
702         DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
703         DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
704         DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
705         DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
706         DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
707         DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
708         DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
709
710         aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
711         aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
712         aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
713         aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
714         aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
715         aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
716
717         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
718 #if 0
719         FIXME
720         if (par->accel_flags & FB_ACCELF_TEXT)
721                 aty_init_engine(par, info);
722 #endif
723 #ifdef CONFIG_FB_ATY_GENERIC_LCD
724         /* after setting the CRTC registers we should set the LCD registers. */
725         if (par->lcd_table != 0) {
726                 /* switch to shadow registers */
727                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
728                         (SHADOW_EN | SHADOW_RW_EN), par);
729
730                 DPRINTK("set shadow CRT to %ix%i %c%c\n",
731                     ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
732                     (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
733
734                 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
735                 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
736                 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
737                 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
738
739                 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
740                 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
741                 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
742                 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
743
744                 /* restore CRTC selection & shadow state and enable stretching */
745                 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
746                 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
747                 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
748                 if(!M64_HAS(LT_LCD_REGS))
749                     DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
750
751                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
752                 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
753                 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
754                 if(!M64_HAS(LT_LCD_REGS)) {
755                     aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
756                     aty_ld_le32(LCD_INDEX, par);
757                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
758                 }
759         }
760 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
761 }
762
763 static int aty_var_to_crtc(const struct fb_info *info,
764         const struct fb_var_screeninfo *var, struct crtc *crtc)
765 {
766         struct atyfb_par *par = (struct atyfb_par *) info->par;
767         u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
768         u32 sync, vmode, vdisplay;
769         u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
770         u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
771         u32 pix_width, dp_pix_width, dp_chain_mask;
772
773         /* input */
774         xres = var->xres;
775         yres = var->yres;
776         vxres = var->xres_virtual;
777         vyres = var->yres_virtual;
778         xoffset = var->xoffset;
779         yoffset = var->yoffset;
780         bpp = var->bits_per_pixel;
781         if (bpp == 16)
782                 bpp = (var->green.length == 5) ? 15 : 16;
783         sync = var->sync;
784         vmode = var->vmode;
785
786         /* convert (and round up) and validate */
787         if (vxres < xres + xoffset)
788                 vxres = xres + xoffset;
789         h_disp = xres;
790
791         if (vyres < yres + yoffset)
792                 vyres = yres + yoffset;
793         v_disp = yres;
794
795         if (bpp <= 8) {
796                 bpp = 8;
797                 pix_width = CRTC_PIX_WIDTH_8BPP;
798                 dp_pix_width =
799                     HOST_8BPP | SRC_8BPP | DST_8BPP |
800                     BYTE_ORDER_LSB_TO_MSB;
801                 dp_chain_mask = DP_CHAIN_8BPP;
802         } else if (bpp <= 15) {
803                 bpp = 16;
804                 pix_width = CRTC_PIX_WIDTH_15BPP;
805                 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
806                     BYTE_ORDER_LSB_TO_MSB;
807                 dp_chain_mask = DP_CHAIN_15BPP;
808         } else if (bpp <= 16) {
809                 bpp = 16;
810                 pix_width = CRTC_PIX_WIDTH_16BPP;
811                 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
812                     BYTE_ORDER_LSB_TO_MSB;
813                 dp_chain_mask = DP_CHAIN_16BPP;
814         } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
815                 bpp = 24;
816                 pix_width = CRTC_PIX_WIDTH_24BPP;
817                 dp_pix_width =
818                     HOST_8BPP | SRC_8BPP | DST_8BPP |
819                     BYTE_ORDER_LSB_TO_MSB;
820                 dp_chain_mask = DP_CHAIN_24BPP;
821         } else if (bpp <= 32) {
822                 bpp = 32;
823                 pix_width = CRTC_PIX_WIDTH_32BPP;
824                 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
825                     BYTE_ORDER_LSB_TO_MSB;
826                 dp_chain_mask = DP_CHAIN_32BPP;
827         } else
828                 FAIL("invalid bpp");
829
830         if (vxres * vyres * bpp / 8 > info->fix.smem_len)
831                 FAIL("not enough video RAM");
832
833         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
834         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
835
836         if((xres > 1600) || (yres > 1200)) {
837                 FAIL("MACH64 chips are designed for max 1600x1200\n"
838                 "select anoter resolution.");
839         }
840         h_sync_strt = h_disp + var->right_margin;
841         h_sync_end = h_sync_strt + var->hsync_len;
842         h_sync_dly  = var->right_margin & 7;
843         h_total = h_sync_end + h_sync_dly + var->left_margin;
844
845         v_sync_strt = v_disp + var->lower_margin;
846         v_sync_end = v_sync_strt + var->vsync_len;
847         v_total = v_sync_end + var->upper_margin;
848
849 #ifdef CONFIG_FB_ATY_GENERIC_LCD
850         if (par->lcd_table != 0) {
851                 if(!M64_HAS(LT_LCD_REGS)) {
852                     u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
853                     crtc->lcd_index = lcd_index &
854                         ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
855                     aty_st_le32(LCD_INDEX, lcd_index, par);
856                 }
857
858                 if (!M64_HAS(MOBIL_BUS))
859                         crtc->lcd_index |= CRTC2_DISPLAY_DIS;
860
861                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
862                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
863
864                 crtc->lcd_gen_cntl &=
865                         ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
866                         /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
867                         USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
868                 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
869
870                 if((crtc->lcd_gen_cntl & LCD_ON) &&
871                         ((xres > par->lcd_width) || (yres > par->lcd_height))) {
872                         /* We cannot display the mode on the LCD. If the CRT is enabled
873                            we can turn off the LCD.
874                            If the CRT is off, it isn't a good idea to switch it on; we don't
875                            know if one is connected. So it's better to fail then.
876                          */
877                         if (crtc->lcd_gen_cntl & CRT_ON) {
878                                 if (!(var->activate & FB_ACTIVATE_TEST))
879                                         PRINTKI("Disable LCD panel, because video mode does not fit.\n");
880                                 crtc->lcd_gen_cntl &= ~LCD_ON;
881                                 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
882                         } else {
883                                 if (!(var->activate & FB_ACTIVATE_TEST))
884                                         PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
885                                 return -EINVAL;
886                         }
887                 }
888         }
889
890         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
891                 int VScan = 1;
892                 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
893                 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
894                 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
895
896                 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
897
898                 /* This is horror! When we simulate, say 640x480 on an 800x600
899                    LCD monitor, the CRTC should be programmed 800x600 values for
900                    the non visible part, but 640x480 for the visible part.
901                    This code has been tested on a laptop with it's 1400x1050 LCD
902                    monitor and a conventional monitor both switched on.
903                    Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
904                     works with little glitches also with DOUBLESCAN modes
905                  */
906                 if (yres < par->lcd_height) {
907                         VScan = par->lcd_height / yres;
908                         if(VScan > 1) {
909                                 VScan = 2;
910                                 vmode |= FB_VMODE_DOUBLE;
911                         }
912                 }
913
914                 h_sync_strt = h_disp + par->lcd_right_margin;
915                 h_sync_end = h_sync_strt + par->lcd_hsync_len;
916                 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
917                 h_total = h_disp + par->lcd_hblank_len;
918
919                 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
920                 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
921                 v_total = v_disp + par->lcd_vblank_len / VScan;
922         }
923 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
924
925         h_disp = (h_disp >> 3) - 1;
926         h_sync_strt = (h_sync_strt >> 3) - 1;
927         h_sync_end = (h_sync_end >> 3) - 1;
928         h_total = (h_total >> 3) - 1;
929         h_sync_wid = h_sync_end - h_sync_strt;
930
931         FAIL_MAX("h_disp too large", h_disp, 0xff);
932         FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
933         /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
934         if(h_sync_wid > 0x1f)
935                 h_sync_wid = 0x1f;
936         FAIL_MAX("h_total too large", h_total, 0x1ff);
937
938         if (vmode & FB_VMODE_DOUBLE) {
939                 v_disp <<= 1;
940                 v_sync_strt <<= 1;
941                 v_sync_end <<= 1;
942                 v_total <<= 1;
943         }
944
945         vdisplay = yres;
946 #ifdef CONFIG_FB_ATY_GENERIC_LCD
947         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
948                 vdisplay  = par->lcd_height;
949 #endif
950
951         v_disp--;
952         v_sync_strt--;
953         v_sync_end--;
954         v_total--;
955         v_sync_wid = v_sync_end - v_sync_strt;
956
957         FAIL_MAX("v_disp too large", v_disp, 0x7ff);
958         FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
959         /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
960         if(v_sync_wid > 0x1f)
961                 v_sync_wid = 0x1f;
962         FAIL_MAX("v_total too large", v_total, 0x7ff);
963
964         c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
965
966         /* output */
967         crtc->vxres = vxres;
968         crtc->vyres = vyres;
969         crtc->xoffset = xoffset;
970         crtc->yoffset = yoffset;
971         crtc->bpp = bpp;
972         crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
973         crtc->vline_crnt_vline = 0;
974
975         crtc->h_tot_disp = h_total | (h_disp<<16);
976         crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
977                 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
978         crtc->v_tot_disp = v_total | (v_disp<<16);
979         crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
980
981         /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
982         crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
983         crtc->gen_cntl |= CRTC_VGA_LINEAR;
984
985         /* Enable doublescan mode if requested */
986         if (vmode & FB_VMODE_DOUBLE)
987                 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
988         /* Enable interlaced mode if requested */
989         if (vmode & FB_VMODE_INTERLACED)
990                 crtc->gen_cntl |= CRTC_INTERLACE_EN;
991 #ifdef CONFIG_FB_ATY_GENERIC_LCD
992         if (par->lcd_table != 0) {
993                 vdisplay = yres;
994                 if(vmode & FB_VMODE_DOUBLE)
995                         vdisplay <<= 1;
996                 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
997                 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
998                         /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
999                         USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
1000                 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
1001
1002                 /* MOBILITY M1 tested, FIXME: LT */
1003                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1004                 if (!M64_HAS(LT_LCD_REGS))
1005                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1006                                 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1007
1008                 crtc->horz_stretching &=
1009                         ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1010                         HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1011                 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1012                         do {
1013                                 /*
1014                                 * The horizontal blender misbehaves when HDisplay is less than a
1015                                 * a certain threshold (440 for a 1024-wide panel).  It doesn't
1016                                 * stretch such modes enough.  Use pixel replication instead of
1017                                 * blending to stretch modes that can be made to exactly fit the
1018                                 * panel width.  The undocumented "NoLCDBlend" option allows the
1019                                 * pixel-replicated mode to be slightly wider or narrower than the
1020                                 * panel width.  It also causes a mode that is exactly half as wide
1021                                 * as the panel to be pixel-replicated, rather than blended.
1022                                 */
1023                                 int HDisplay  = xres & ~7;
1024                                 int nStretch  = par->lcd_width / HDisplay;
1025                                 int Remainder = par->lcd_width % HDisplay;
1026
1027                                 if ((!Remainder && ((nStretch > 2))) ||
1028                                         (((HDisplay * 16) / par->lcd_width) < 7)) {
1029                                         static const char StretchLoops[] = {10, 12, 13, 15, 16};
1030                                         int horz_stretch_loop = -1, BestRemainder;
1031                                         int Numerator = HDisplay, Denominator = par->lcd_width;
1032                                         int Index = 5;
1033                                         ATIReduceRatio(&Numerator, &Denominator);
1034
1035                                         BestRemainder = (Numerator * 16) / Denominator;
1036                                         while (--Index >= 0) {
1037                                                 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1038                                                         Denominator;
1039                                                 if (Remainder < BestRemainder) {
1040                                                         horz_stretch_loop = Index;
1041                                                         if (!(BestRemainder = Remainder))
1042                                                                 break;
1043                                                 }
1044                                         }
1045
1046                                         if ((horz_stretch_loop >= 0) && !BestRemainder) {
1047                                                 int horz_stretch_ratio = 0, Accumulator = 0;
1048                                                 int reuse_previous = 1;
1049
1050                                                 Index = StretchLoops[horz_stretch_loop];
1051
1052                                                 while (--Index >= 0) {
1053                                                         if (Accumulator > 0)
1054                                                                 horz_stretch_ratio |= reuse_previous;
1055                                                         else
1056                                                                 Accumulator += Denominator;
1057                                                         Accumulator -= Numerator;
1058                                                         reuse_previous <<= 1;
1059                                                 }
1060
1061                                                 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1062                                                         ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1063                                                         (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1064                                                 break;      /* Out of the do { ... } while (0) */
1065                                         }
1066                                 }
1067
1068                                 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1069                                         (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1070                         } while (0);
1071                 }
1072
1073                 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1074                         crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1075                                 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1076
1077                         if (!M64_HAS(LT_LCD_REGS) &&
1078                             xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1079                                 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1080                 } else {
1081                         /*
1082                          * Don't use vertical blending if the mode is too wide or not
1083                          * vertically stretched.
1084                          */
1085                         crtc->vert_stretching = 0;
1086                 }
1087                 /* copy to shadow crtc */
1088                 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1089                 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1090                 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1091                 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1092         }
1093 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1094
1095         if (M64_HAS(MAGIC_FIFO)) {
1096                 /* FIXME: display FIFO low watermark values */
1097                 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1098         }
1099         crtc->dp_pix_width = dp_pix_width;
1100         crtc->dp_chain_mask = dp_chain_mask;
1101
1102         return 0;
1103 }
1104
1105 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1106 {
1107         u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1108         u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1109             h_sync_pol;
1110         u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1111         u32 pix_width;
1112         u32 double_scan, interlace;
1113
1114         /* input */
1115         h_total = crtc->h_tot_disp & 0x1ff;
1116         h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1117         h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1118         h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1119         h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1120         h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1121         v_total = crtc->v_tot_disp & 0x7ff;
1122         v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1123         v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1124         v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1125         v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1126         c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1127         pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1128         double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1129         interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1130
1131         /* convert */
1132         xres = (h_disp + 1) * 8;
1133         yres = v_disp + 1;
1134         left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1135         right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1136         hslen = h_sync_wid * 8;
1137         upper = v_total - v_sync_strt - v_sync_wid;
1138         lower = v_sync_strt - v_disp;
1139         vslen = v_sync_wid;
1140         sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1141             (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1142             (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1143
1144         switch (pix_width) {
1145 #if 0
1146         case CRTC_PIX_WIDTH_4BPP:
1147                 bpp = 4;
1148                 var->red.offset = 0;
1149                 var->red.length = 8;
1150                 var->green.offset = 0;
1151                 var->green.length = 8;
1152                 var->blue.offset = 0;
1153                 var->blue.length = 8;
1154                 var->transp.offset = 0;
1155                 var->transp.length = 0;
1156                 break;
1157 #endif
1158         case CRTC_PIX_WIDTH_8BPP:
1159                 bpp = 8;
1160                 var->red.offset = 0;
1161                 var->red.length = 8;
1162                 var->green.offset = 0;
1163                 var->green.length = 8;
1164                 var->blue.offset = 0;
1165                 var->blue.length = 8;
1166                 var->transp.offset = 0;
1167                 var->transp.length = 0;
1168                 break;
1169         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1170                 bpp = 16;
1171                 var->red.offset = 10;
1172                 var->red.length = 5;
1173                 var->green.offset = 5;
1174                 var->green.length = 5;
1175                 var->blue.offset = 0;
1176                 var->blue.length = 5;
1177                 var->transp.offset = 0;
1178                 var->transp.length = 0;
1179                 break;
1180         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1181                 bpp = 16;
1182                 var->red.offset = 11;
1183                 var->red.length = 5;
1184                 var->green.offset = 5;
1185                 var->green.length = 6;
1186                 var->blue.offset = 0;
1187                 var->blue.length = 5;
1188                 var->transp.offset = 0;
1189                 var->transp.length = 0;
1190                 break;
1191         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1192                 bpp = 24;
1193                 var->red.offset = 16;
1194                 var->red.length = 8;
1195                 var->green.offset = 8;
1196                 var->green.length = 8;
1197                 var->blue.offset = 0;
1198                 var->blue.length = 8;
1199                 var->transp.offset = 0;
1200                 var->transp.length = 0;
1201                 break;
1202         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1203                 bpp = 32;
1204                 var->red.offset = 16;
1205                 var->red.length = 8;
1206                 var->green.offset = 8;
1207                 var->green.length = 8;
1208                 var->blue.offset = 0;
1209                 var->blue.length = 8;
1210                 var->transp.offset = 24;
1211                 var->transp.length = 8;
1212                 break;
1213         default:
1214                 PRINTKE("Invalid pixel width\n");
1215                 return -EINVAL;
1216         }
1217
1218         /* output */
1219         var->xres = xres;
1220         var->yres = yres;
1221         var->xres_virtual = crtc->vxres;
1222         var->yres_virtual = crtc->vyres;
1223         var->bits_per_pixel = bpp;
1224         var->left_margin = left;
1225         var->right_margin = right;
1226         var->upper_margin = upper;
1227         var->lower_margin = lower;
1228         var->hsync_len = hslen;
1229         var->vsync_len = vslen;
1230         var->sync = sync;
1231         var->vmode = FB_VMODE_NONINTERLACED;
1232         /* In double scan mode, the vertical parameters are doubled, so we need to
1233            half them to get the right values.
1234            In interlaced mode the values are already correct, so no correction is
1235            necessary.
1236          */
1237         if (interlace)
1238                 var->vmode = FB_VMODE_INTERLACED;
1239
1240         if (double_scan) {
1241                 var->vmode = FB_VMODE_DOUBLE;
1242                 var->yres>>=1;
1243                 var->upper_margin>>=1;
1244                 var->lower_margin>>=1;
1245                 var->vsync_len>>=1;
1246         }
1247
1248         return 0;
1249 }
1250
1251 /* ------------------------------------------------------------------------- */
1252
1253 static int atyfb_set_par(struct fb_info *info)
1254 {
1255         struct atyfb_par *par = (struct atyfb_par *) info->par;
1256         struct fb_var_screeninfo *var = &info->var;
1257         u32 tmp, pixclock;
1258         int err;
1259 #ifdef DEBUG
1260         struct fb_var_screeninfo debug;
1261         u32 pixclock_in_ps;
1262 #endif
1263         if (par->asleep)
1264                 return 0;
1265
1266         if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1267                 return err;
1268
1269         pixclock = atyfb_get_pixclock(var, par);
1270
1271         if (pixclock == 0) {
1272                 PRINTKE("Invalid pixclock\n");
1273                 return -EINVAL;
1274         } else {
1275                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1276                         return err;
1277         }
1278
1279         par->accel_flags = var->accel_flags; /* hack */
1280
1281         if (var->accel_flags) {
1282                 info->fbops->fb_sync = atyfb_sync;
1283                 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1284         } else {
1285                 info->fbops->fb_sync = NULL;
1286                 info->flags |= FBINFO_HWACCEL_DISABLED;
1287         }
1288
1289         if (par->blitter_may_be_busy)
1290                 wait_for_idle(par);
1291
1292         aty_set_crtc(par, &par->crtc);
1293         par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1294         par->pll_ops->set_pll(info, &par->pll);
1295
1296 #ifdef DEBUG
1297         if(par->pll_ops && par->pll_ops->pll_to_var)
1298                 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1299         else
1300                 pixclock_in_ps = 0;
1301
1302         if(0 == pixclock_in_ps) {
1303                 PRINTKE("ALERT ops->pll_to_var get 0\n");
1304                 pixclock_in_ps = pixclock;
1305         }
1306
1307         memset(&debug, 0, sizeof(debug));
1308         if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1309                 u32 hSync, vRefresh;
1310                 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1311                 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1312
1313                 h_disp = debug.xres;
1314                 h_sync_strt = h_disp + debug.right_margin;
1315                 h_sync_end = h_sync_strt + debug.hsync_len;
1316                 h_total = h_sync_end + debug.left_margin;
1317                 v_disp = debug.yres;
1318                 v_sync_strt = v_disp + debug.lower_margin;
1319                 v_sync_end = v_sync_strt + debug.vsync_len;
1320                 v_total = v_sync_end + debug.upper_margin;
1321
1322                 hSync = 1000000000 / (pixclock_in_ps * h_total);
1323                 vRefresh = (hSync * 1000) / v_total;
1324                 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1325                 vRefresh *= 2;
1326                 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1327                 vRefresh /= 2;
1328
1329                 DPRINTK("atyfb_set_par\n");
1330                 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1331                 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1332                         var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1333                 DPRINTK(" Dot clock:           %i MHz\n", 1000000 / pixclock_in_ps);
1334                 DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
1335                 DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
1336                 DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
1337                         1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1338                         h_disp, h_sync_strt, h_sync_end, h_total,
1339                         v_disp, v_sync_strt, v_sync_end, v_total);
1340                 DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
1341                         pixclock_in_ps,
1342                         debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1343                         debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1344         }
1345 #endif /* DEBUG */
1346
1347         if (!M64_HAS(INTEGRATED)) {
1348                 /* Don't forget MEM_CNTL */
1349                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1350                 switch (var->bits_per_pixel) {
1351                 case 8:
1352                         tmp |= 0x02000000;
1353                         break;
1354                 case 16:
1355                         tmp |= 0x03000000;
1356                         break;
1357                 case 32:
1358                         tmp |= 0x06000000;
1359                         break;
1360                 }
1361                 aty_st_le32(MEM_CNTL, tmp, par);
1362         } else {
1363                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1364                 if (!M64_HAS(MAGIC_POSTDIV))
1365                         tmp |= par->mem_refresh_rate << 20;
1366                 switch (var->bits_per_pixel) {
1367                 case 8:
1368                 case 24:
1369                         tmp |= 0x00000000;
1370                         break;
1371                 case 16:
1372                         tmp |= 0x04000000;
1373                         break;
1374                 case 32:
1375                         tmp |= 0x08000000;
1376                         break;
1377                 }
1378                 if (M64_HAS(CT_BUS)) {
1379                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1380                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1381                 } else if (M64_HAS(VT_BUS)) {
1382                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1383                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1384                 } else if (M64_HAS(MOBIL_BUS)) {
1385                         aty_st_le32(DAC_CNTL, 0x80010102, par);
1386                         aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1387                 } else {
1388                         /* GT */
1389                         aty_st_le32(DAC_CNTL, 0x86010102, par);
1390                         aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1391                         aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1392                 }
1393                 aty_st_le32(MEM_CNTL, tmp, par);
1394         }
1395         aty_st_8(DAC_MASK, 0xff, par);
1396
1397         info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1398         info->fix.visual = var->bits_per_pixel <= 8 ?
1399                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1400
1401         /* Initialize the graphics engine */
1402         if (par->accel_flags & FB_ACCELF_TEXT)
1403                 aty_init_engine(par, info);
1404
1405 #ifdef CONFIG_BOOTX_TEXT
1406         btext_update_display(info->fix.smem_start,
1407                 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1408                 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1409                 var->bits_per_pixel,
1410                 par->crtc.vxres * var->bits_per_pixel / 8);
1411 #endif /* CONFIG_BOOTX_TEXT */
1412 #if 0
1413         /* switch to accelerator mode */
1414         if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1415                 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1416 #endif
1417 #ifdef DEBUG
1418 {
1419         /* dump non shadow CRTC, pll, LCD registers */
1420         int i; u32 base;
1421
1422         /* CRTC registers */
1423         base = 0x2000;
1424         printk("debug atyfb: Mach64 non-shadow register values:");
1425         for (i = 0; i < 256; i = i+4) {
1426                 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1427                 printk(" %08X", aty_ld_le32(i, par));
1428         }
1429         printk("\n\n");
1430
1431 #ifdef CONFIG_FB_ATY_CT
1432         /* PLL registers */
1433         base = 0x00;
1434         printk("debug atyfb: Mach64 PLL register values:");
1435         for (i = 0; i < 64; i++) {
1436                 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1437                 if(i%4 == 0)  printk(" ");
1438                 printk("%02X", aty_ld_pll_ct(i, par));
1439         }
1440         printk("\n\n");
1441 #endif  /* CONFIG_FB_ATY_CT */
1442
1443 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1444         if (par->lcd_table != 0) {
1445                 /* LCD registers */
1446                 base = 0x00;
1447                 printk("debug atyfb: LCD register values:");
1448                 if(M64_HAS(LT_LCD_REGS)) {
1449                     for(i = 0; i <= POWER_MANAGEMENT; i++) {
1450                         if(i == EXT_VERT_STRETCH)
1451                             continue;
1452                         printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1453                         printk(" %08X", aty_ld_lcd(i, par));
1454                     }
1455
1456                 } else {
1457                     for (i = 0; i < 64; i++) {
1458                         if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1459                         printk(" %08X", aty_ld_lcd(i, par));
1460                     }
1461                 }
1462                 printk("\n\n");
1463         }
1464 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1465 }
1466 #endif /* DEBUG */
1467         return 0;
1468 }
1469
1470 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1471 {
1472         struct atyfb_par *par = (struct atyfb_par *) info->par;
1473         int err;
1474         struct crtc crtc;
1475         union aty_pll pll;
1476         u32 pixclock;
1477
1478         memcpy(&pll, &(par->pll), sizeof(pll));
1479
1480         if((err = aty_var_to_crtc(info, var, &crtc)))
1481                 return err;
1482
1483         pixclock = atyfb_get_pixclock(var, par);
1484
1485         if (pixclock == 0) {
1486                 if (!(var->activate & FB_ACTIVATE_TEST))
1487                         PRINTKE("Invalid pixclock\n");
1488                 return -EINVAL;
1489         } else {
1490                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1491                         return err;
1492         }
1493
1494         if (var->accel_flags & FB_ACCELF_TEXT)
1495                 info->var.accel_flags = FB_ACCELF_TEXT;
1496         else
1497                 info->var.accel_flags = 0;
1498
1499         aty_crtc_to_var(&crtc, var);
1500         var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1501         return 0;
1502 }
1503
1504 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1505 {
1506         u32 xoffset = info->var.xoffset;
1507         u32 yoffset = info->var.yoffset;
1508         u32 vxres = par->crtc.vxres;
1509         u32 bpp = info->var.bits_per_pixel;
1510
1511         par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1512 }
1513
1514
1515     /*
1516      *  Open/Release the frame buffer device
1517      */
1518
1519 static int atyfb_open(struct fb_info *info, int user)
1520 {
1521         struct atyfb_par *par = (struct atyfb_par *) info->par;
1522
1523         if (user) {
1524                 par->open++;
1525 #ifdef __sparc__
1526                 par->mmaped = 0;
1527 #endif
1528         }
1529         return (0);
1530 }
1531
1532 static irqreturn_t aty_irq(int irq, void *dev_id)
1533 {
1534         struct atyfb_par *par = dev_id;
1535         int handled = 0;
1536         u32 int_cntl;
1537
1538         spin_lock(&par->int_lock);
1539
1540         int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1541
1542         if (int_cntl & CRTC_VBLANK_INT) {
1543                 /* clear interrupt */
1544                 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1545                 par->vblank.count++;
1546                 if (par->vblank.pan_display) {
1547                         par->vblank.pan_display = 0;
1548                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1549                 }
1550                 wake_up_interruptible(&par->vblank.wait);
1551                 handled = 1;
1552         }
1553
1554         spin_unlock(&par->int_lock);
1555
1556         return IRQ_RETVAL(handled);
1557 }
1558
1559 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1560 {
1561         u32 int_cntl;
1562
1563         if (!test_and_set_bit(0, &par->irq_flags)) {
1564                 if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
1565                         clear_bit(0, &par->irq_flags);
1566                         return -EINVAL;
1567                 }
1568                 spin_lock_irq(&par->int_lock);
1569                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1570                 /* clear interrupt */
1571                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1572                 /* enable interrupt */
1573                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1574                 spin_unlock_irq(&par->int_lock);
1575         } else if (reenable) {
1576                 spin_lock_irq(&par->int_lock);
1577                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1578                 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1579                         printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1580                         /* re-enable interrupt */
1581                         aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1582                 }
1583                 spin_unlock_irq(&par->int_lock);
1584         }
1585
1586         return 0;
1587 }
1588
1589 static int aty_disable_irq(struct atyfb_par *par)
1590 {
1591         u32 int_cntl;
1592
1593         if (test_and_clear_bit(0, &par->irq_flags)) {
1594                 if (par->vblank.pan_display) {
1595                         par->vblank.pan_display = 0;
1596                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1597                 }
1598                 spin_lock_irq(&par->int_lock);
1599                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1600                 /* disable interrupt */
1601                 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1602                 spin_unlock_irq(&par->int_lock);
1603                 free_irq(par->irq, par);
1604         }
1605
1606         return 0;
1607 }
1608
1609 static int atyfb_release(struct fb_info *info, int user)
1610 {
1611         struct atyfb_par *par = (struct atyfb_par *) info->par;
1612         if (user) {
1613                 par->open--;
1614                 mdelay(1);
1615                 wait_for_idle(par);
1616                 if (!par->open) {
1617 #ifdef __sparc__
1618                         int was_mmaped = par->mmaped;
1619
1620                         par->mmaped = 0;
1621
1622                         if (was_mmaped) {
1623                                 struct fb_var_screeninfo var;
1624
1625                                 /* Now reset the default display config, we have no
1626                                  * idea what the program(s) which mmap'd the chip did
1627                                  * to the configuration, nor whether it restored it
1628                                  * correctly.
1629                                  */
1630                                 var = default_var;
1631                                 if (noaccel)
1632                                         var.accel_flags &= ~FB_ACCELF_TEXT;
1633                                 else
1634                                         var.accel_flags |= FB_ACCELF_TEXT;
1635                                 if (var.yres == var.yres_virtual) {
1636                                         u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1637                                         var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1638                                         if (var.yres_virtual < var.yres)
1639                                                 var.yres_virtual = var.yres;
1640                                 }
1641                         }
1642 #endif
1643                         aty_disable_irq(par);
1644                 }
1645         }
1646         return (0);
1647 }
1648
1649     /*
1650      *  Pan or Wrap the Display
1651      *
1652      *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1653      */
1654
1655 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1656 {
1657         struct atyfb_par *par = (struct atyfb_par *) info->par;
1658         u32 xres, yres, xoffset, yoffset;
1659
1660         xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1661         yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1662         if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1663                 yres >>= 1;
1664         xoffset = (var->xoffset + 7) & ~7;
1665         yoffset = var->yoffset;
1666         if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1667                 return -EINVAL;
1668         info->var.xoffset = xoffset;
1669         info->var.yoffset = yoffset;
1670         if (par->asleep)
1671                 return 0;
1672
1673         set_off_pitch(par, info);
1674         if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1675                 par->vblank.pan_display = 1;
1676         } else {
1677                 par->vblank.pan_display = 0;
1678                 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1679         }
1680
1681         return 0;
1682 }
1683
1684 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1685 {
1686         struct aty_interrupt *vbl;
1687         unsigned int count;
1688         int ret;
1689
1690         switch (crtc) {
1691         case 0:
1692                 vbl = &par->vblank;
1693                 break;
1694         default:
1695                 return -ENODEV;
1696         }
1697
1698         ret = aty_enable_irq(par, 0);
1699         if (ret)
1700                 return ret;
1701
1702         count = vbl->count;
1703         ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1704         if (ret < 0) {
1705                 return ret;
1706         }
1707         if (ret == 0) {
1708                 aty_enable_irq(par, 1);
1709                 return -ETIMEDOUT;
1710         }
1711
1712         return 0;
1713 }
1714
1715
1716 #ifdef DEBUG
1717 #define ATYIO_CLKR              0x41545900      /* ATY\00 */
1718 #define ATYIO_CLKW              0x41545901      /* ATY\01 */
1719
1720 struct atyclk {
1721         u32 ref_clk_per;
1722         u8 pll_ref_div;
1723         u8 mclk_fb_div;
1724         u8 mclk_post_div;       /* 1,2,3,4,8 */
1725         u8 mclk_fb_mult;        /* 2 or 4 */
1726         u8 xclk_post_div;       /* 1,2,3,4,8 */
1727         u8 vclk_fb_div;
1728         u8 vclk_post_div;       /* 1,2,3,4,6,8,12 */
1729         u32 dsp_xclks_per_row;  /* 0-16383 */
1730         u32 dsp_loop_latency;   /* 0-15 */
1731         u32 dsp_precision;      /* 0-7 */
1732         u32 dsp_on;             /* 0-2047 */
1733         u32 dsp_off;            /* 0-2047 */
1734 };
1735
1736 #define ATYIO_FEATR             0x41545902      /* ATY\02 */
1737 #define ATYIO_FEATW             0x41545903      /* ATY\03 */
1738 #endif
1739
1740 #ifndef FBIO_WAITFORVSYNC
1741 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1742 #endif
1743
1744 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1745 {
1746         struct atyfb_par *par = (struct atyfb_par *) info->par;
1747 #ifdef __sparc__
1748         struct fbtype fbtyp;
1749 #endif
1750
1751         switch (cmd) {
1752 #ifdef __sparc__
1753         case FBIOGTYPE:
1754                 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1755                 fbtyp.fb_width = par->crtc.vxres;
1756                 fbtyp.fb_height = par->crtc.vyres;
1757                 fbtyp.fb_depth = info->var.bits_per_pixel;
1758                 fbtyp.fb_cmsize = info->cmap.len;
1759                 fbtyp.fb_size = info->fix.smem_len;
1760                 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1761                         return -EFAULT;
1762                 break;
1763 #endif /* __sparc__ */
1764
1765         case FBIO_WAITFORVSYNC:
1766                 {
1767                         u32 crtc;
1768
1769                         if (get_user(crtc, (__u32 __user *) arg))
1770                                 return -EFAULT;
1771
1772                         return aty_waitforvblank(par, crtc);
1773                 }
1774                 break;
1775
1776 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1777         case ATYIO_CLKR:
1778                 if (M64_HAS(INTEGRATED)) {
1779                         struct atyclk clk;
1780                         union aty_pll *pll = &(par->pll);
1781                         u32 dsp_config = pll->ct.dsp_config;
1782                         u32 dsp_on_off = pll->ct.dsp_on_off;
1783                         clk.ref_clk_per = par->ref_clk_per;
1784                         clk.pll_ref_div = pll->ct.pll_ref_div;
1785                         clk.mclk_fb_div = pll->ct.mclk_fb_div;
1786                         clk.mclk_post_div = pll->ct.mclk_post_div_real;
1787                         clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1788                         clk.xclk_post_div = pll->ct.xclk_post_div_real;
1789                         clk.vclk_fb_div = pll->ct.vclk_fb_div;
1790                         clk.vclk_post_div = pll->ct.vclk_post_div_real;
1791                         clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1792                         clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1793                         clk.dsp_precision = (dsp_config >> 20) & 7;
1794                         clk.dsp_off = dsp_on_off & 0x7ff;
1795                         clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1796                         if (copy_to_user((struct atyclk __user *) arg, &clk,
1797                                          sizeof(clk)))
1798                                 return -EFAULT;
1799                 } else
1800                         return -EINVAL;
1801                 break;
1802         case ATYIO_CLKW:
1803                 if (M64_HAS(INTEGRATED)) {
1804                         struct atyclk clk;
1805                         union aty_pll *pll = &(par->pll);
1806                         if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1807                                 return -EFAULT;
1808                         par->ref_clk_per = clk.ref_clk_per;
1809                         pll->ct.pll_ref_div = clk.pll_ref_div;
1810                         pll->ct.mclk_fb_div = clk.mclk_fb_div;
1811                         pll->ct.mclk_post_div_real = clk.mclk_post_div;
1812                         pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1813                         pll->ct.xclk_post_div_real = clk.xclk_post_div;
1814                         pll->ct.vclk_fb_div = clk.vclk_fb_div;
1815                         pll->ct.vclk_post_div_real = clk.vclk_post_div;
1816                         pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1817                                 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1818                         pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1819                         /*aty_calc_pll_ct(info, &pll->ct);*/
1820                         aty_set_pll_ct(info, pll);
1821                 } else
1822                         return -EINVAL;
1823                 break;
1824         case ATYIO_FEATR:
1825                 if (get_user(par->features, (u32 __user *) arg))
1826                         return -EFAULT;
1827                 break;
1828         case ATYIO_FEATW:
1829                 if (put_user(par->features, (u32 __user *) arg))
1830                         return -EFAULT;
1831                 break;
1832 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1833         default:
1834                 return -EINVAL;
1835         }
1836         return 0;
1837 }
1838
1839 static int atyfb_sync(struct fb_info *info)
1840 {
1841         struct atyfb_par *par = (struct atyfb_par *) info->par;
1842
1843         if (par->blitter_may_be_busy)
1844                 wait_for_idle(par);
1845         return 0;
1846 }
1847
1848 #ifdef __sparc__
1849 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1850 {
1851         struct atyfb_par *par = (struct atyfb_par *) info->par;
1852         unsigned int size, page, map_size = 0;
1853         unsigned long map_offset = 0;
1854         unsigned long off;
1855         int i;
1856
1857         if (!par->mmap_map)
1858                 return -ENXIO;
1859
1860         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1861                 return -EINVAL;
1862
1863         off = vma->vm_pgoff << PAGE_SHIFT;
1864         size = vma->vm_end - vma->vm_start;
1865
1866         /* To stop the swapper from even considering these pages. */
1867         vma->vm_flags |= (VM_IO | VM_RESERVED);
1868
1869         if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1870             ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1871                 off += 0x8000000000000000UL;
1872
1873         vma->vm_pgoff = off >> PAGE_SHIFT;      /* propagate off changes */
1874
1875         /* Each page, see which map applies */
1876         for (page = 0; page < size;) {
1877                 map_size = 0;
1878                 for (i = 0; par->mmap_map[i].size; i++) {
1879                         unsigned long start = par->mmap_map[i].voff;
1880                         unsigned long end = start + par->mmap_map[i].size;
1881                         unsigned long offset = off + page;
1882
1883                         if (start > offset)
1884                                 continue;
1885                         if (offset >= end)
1886                                 continue;
1887
1888                         map_size = par->mmap_map[i].size - (offset - start);
1889                         map_offset =
1890                             par->mmap_map[i].poff + (offset - start);
1891                         break;
1892                 }
1893                 if (!map_size) {
1894                         page += PAGE_SIZE;
1895                         continue;
1896                 }
1897                 if (page + map_size > size)
1898                         map_size = size - page;
1899
1900                 pgprot_val(vma->vm_page_prot) &=
1901                     ~(par->mmap_map[i].prot_mask);
1902                 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1903
1904                 if (remap_pfn_range(vma, vma->vm_start + page,
1905                         map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1906                         return -EAGAIN;
1907
1908                 page += map_size;
1909         }
1910
1911         if (!map_size)
1912                 return -EINVAL;
1913
1914         if (!par->mmaped)
1915                 par->mmaped = 1;
1916         return 0;
1917 }
1918
1919 static struct {
1920         u32 yoffset;
1921         u8 r[2][256];
1922         u8 g[2][256];
1923         u8 b[2][256];
1924 } atyfb_save;
1925
1926 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1927 {
1928         int i, tmp;
1929
1930         for (i = 0; i < 256; i++) {
1931                 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1932                 if (M64_HAS(EXTRA_BRIGHT))
1933                         tmp |= 0x2;
1934                 aty_st_8(DAC_CNTL, tmp, par);
1935                 aty_st_8(DAC_MASK, 0xff, par);
1936
1937                 aty_st_8(DAC_R_INDEX, i, par);
1938                 atyfb_save.r[enter][i] = aty_ld_8(DAC_DATA, par);
1939                 atyfb_save.g[enter][i] = aty_ld_8(DAC_DATA, par);
1940                 atyfb_save.b[enter][i] = aty_ld_8(DAC_DATA, par);
1941                 aty_st_8(DAC_W_INDEX, i, par);
1942                 aty_st_8(DAC_DATA, atyfb_save.r[1 - enter][i], par);
1943                 aty_st_8(DAC_DATA, atyfb_save.g[1 - enter][i], par);
1944                 aty_st_8(DAC_DATA, atyfb_save.b[1 - enter][i], par);
1945         }
1946 }
1947
1948 static void atyfb_palette(int enter)
1949 {
1950         struct atyfb_par *par;
1951         struct fb_info *info;
1952         int i;
1953
1954         for (i = 0; i < FB_MAX; i++) {
1955                 info = registered_fb[i];
1956                 if (info && info->fbops == &atyfb_ops) {
1957                         par = (struct atyfb_par *) info->par;
1958                         
1959                         atyfb_save_palette(par, enter);
1960                         if (enter) {
1961                                 atyfb_save.yoffset = info->var.yoffset;
1962                                 info->var.yoffset = 0;
1963                                 set_off_pitch(par, info);
1964                         } else {
1965                                 info->var.yoffset = atyfb_save.yoffset;
1966                                 set_off_pitch(par, info);
1967                         }
1968                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1969                         break;
1970                 }
1971         }
1972 }
1973 #endif /* __sparc__ */
1974
1975
1976
1977 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1978
1979 #ifdef CONFIG_PPC_PMAC
1980 /* Power management routines. Those are used for PowerBook sleep.
1981  */
1982 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1983 {
1984         u32 pm;
1985         int timeout;
1986
1987         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1988         pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1989         aty_st_lcd(POWER_MANAGEMENT, pm, par);
1990         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1991
1992         timeout = 2000;
1993         if (sleep) {
1994                 /* Sleep */
1995                 pm &= ~PWR_MGT_ON;
1996                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1997                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1998                 udelay(10);
1999                 pm &= ~(PWR_BLON | AUTO_PWR_UP);
2000                 pm |= SUSPEND_NOW;
2001                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2002                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2003                 udelay(10);
2004                 pm |= PWR_MGT_ON;
2005                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2006                 do {
2007                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2008                         mdelay(1);
2009                         if ((--timeout) == 0)
2010                                 break;
2011                 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2012         } else {
2013                 /* Wakeup */
2014                 pm &= ~PWR_MGT_ON;
2015                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2016                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2017                 udelay(10);
2018                 pm &= ~SUSPEND_NOW;
2019                 pm |= (PWR_BLON | AUTO_PWR_UP);
2020                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2021                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2022                 udelay(10);
2023                 pm |= PWR_MGT_ON;
2024                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2025                 do {
2026                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2027                         mdelay(1);
2028                         if ((--timeout) == 0)
2029                                 break;
2030                 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2031         }
2032         mdelay(500);
2033
2034         return timeout ? 0 : -EIO;
2035 }
2036 #endif
2037
2038 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2039 {
2040         struct fb_info *info = pci_get_drvdata(pdev);
2041         struct atyfb_par *par = (struct atyfb_par *) info->par;
2042
2043         if (state.event == pdev->dev.power.power_state.event)
2044                 return 0;
2045
2046         acquire_console_sem();
2047
2048         fb_set_suspend(info, 1);
2049
2050         /* Idle & reset engine */
2051         wait_for_idle(par);
2052         aty_reset_engine(par);
2053
2054         /* Blank display and LCD */
2055         atyfb_blank(FB_BLANK_POWERDOWN, info);
2056
2057         par->asleep = 1;
2058         par->lock_blank = 1;
2059
2060 #ifdef CONFIG_PPC_PMAC
2061         /* Set chip to "suspend" mode */
2062         if (aty_power_mgmt(1, par)) {
2063                 par->asleep = 0;
2064                 par->lock_blank = 0;
2065                 atyfb_blank(FB_BLANK_UNBLANK, info);
2066                 fb_set_suspend(info, 0);
2067                 release_console_sem();
2068                 return -EIO;
2069         }
2070 #else
2071         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2072 #endif
2073
2074         release_console_sem();
2075
2076         pdev->dev.power.power_state = state;
2077
2078         return 0;
2079 }
2080
2081 static int atyfb_pci_resume(struct pci_dev *pdev)
2082 {
2083         struct fb_info *info = pci_get_drvdata(pdev);
2084         struct atyfb_par *par = (struct atyfb_par *) info->par;
2085
2086         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2087                 return 0;
2088
2089         acquire_console_sem();
2090
2091 #ifdef CONFIG_PPC_PMAC
2092         if (pdev->dev.power.power_state.event == 2)
2093                 aty_power_mgmt(0, par);
2094 #else
2095         pci_set_power_state(pdev, PCI_D0);
2096 #endif
2097
2098         aty_resume_chip(info);
2099
2100         par->asleep = 0;
2101
2102         /* Restore display */
2103         atyfb_set_par(info);
2104
2105         /* Refresh */
2106         fb_set_suspend(info, 0);
2107
2108         /* Unblank */
2109         par->lock_blank = 0;
2110         atyfb_blank(FB_BLANK_UNBLANK, info);
2111
2112         release_console_sem();
2113
2114         pdev->dev.power.power_state = PMSG_ON;
2115
2116         return 0;
2117 }
2118
2119 #endif /*  defined(CONFIG_PM) && defined(CONFIG_PCI) */
2120
2121 /* Backlight */
2122 #ifdef CONFIG_FB_ATY_BACKLIGHT
2123 #define MAX_LEVEL 0xFF
2124
2125 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2126 {
2127         struct fb_info *info = pci_get_drvdata(par->pdev);
2128         int atylevel;
2129
2130         /* Get and convert the value */
2131         /* No locking of bl_curve since we read a single value */
2132         atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2133
2134         if (atylevel < 0)
2135                 atylevel = 0;
2136         else if (atylevel > MAX_LEVEL)
2137                 atylevel = MAX_LEVEL;
2138
2139         return atylevel;
2140 }
2141
2142 static int aty_bl_update_status(struct backlight_device *bd)
2143 {
2144         struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2145         unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2146         int level;
2147
2148         if (bd->props.power != FB_BLANK_UNBLANK ||
2149             bd->props.fb_blank != FB_BLANK_UNBLANK)
2150                 level = 0;
2151         else
2152                 level = bd->props.brightness;
2153
2154         reg |= (BLMOD_EN | BIASMOD_EN);
2155         if (level > 0) {
2156                 reg &= ~BIAS_MOD_LEVEL_MASK;
2157                 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2158         } else {
2159                 reg &= ~BIAS_MOD_LEVEL_MASK;
2160                 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2161         }
2162         aty_st_lcd(LCD_MISC_CNTL, reg, par);
2163
2164         return 0;
2165 }
2166
2167 static int aty_bl_get_brightness(struct backlight_device *bd)
2168 {
2169         return bd->props.brightness;
2170 }
2171
2172 static struct backlight_ops aty_bl_data = {
2173         .get_brightness = aty_bl_get_brightness,
2174         .update_status  = aty_bl_update_status,
2175 };
2176
2177 static void aty_bl_init(struct atyfb_par *par)
2178 {
2179         struct fb_info *info = pci_get_drvdata(par->pdev);
2180         struct backlight_device *bd;
2181         char name[12];
2182
2183 #ifdef CONFIG_PMAC_BACKLIGHT
2184         if (!pmac_has_backlight_type("ati"))
2185                 return;
2186 #endif
2187
2188         snprintf(name, sizeof(name), "atybl%d", info->node);
2189
2190         bd = backlight_device_register(name, info->dev, par, &aty_bl_data);
2191         if (IS_ERR(bd)) {
2192                 info->bl_dev = NULL;
2193                 printk(KERN_WARNING "aty: Backlight registration failed\n");
2194                 goto error;
2195         }
2196
2197         info->bl_dev = bd;
2198         fb_bl_default_curve(info, 0,
2199                 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2200                 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2201
2202         bd->props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
2203         bd->props.brightness = bd->props.max_brightness;
2204         bd->props.power = FB_BLANK_UNBLANK;
2205         backlight_update_status(bd);
2206
2207         printk("aty: Backlight initialized (%s)\n", name);
2208
2209         return;
2210
2211 error:
2212         return;
2213 }
2214
2215 static void aty_bl_exit(struct backlight_device *bd)
2216 {
2217         backlight_device_unregister(bd);
2218         printk("aty: Backlight unloaded\n");
2219 }
2220
2221 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2222
2223 static void __devinit aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2224 {
2225         const int ragepro_tbl[] = {
2226                 44, 50, 55, 66, 75, 80, 100
2227         };
2228         const int ragexl_tbl[] = {
2229                 50, 66, 75, 83, 90, 95, 100, 105,
2230                 110, 115, 120, 125, 133, 143, 166
2231         };
2232         const int *refresh_tbl;
2233         int i, size;
2234
2235         if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2236                 refresh_tbl = ragexl_tbl;
2237                 size = ARRAY_SIZE(ragexl_tbl);
2238         } else {
2239                 refresh_tbl = ragepro_tbl;
2240                 size = ARRAY_SIZE(ragepro_tbl);
2241         }
2242
2243         for (i=0; i < size; i++) {
2244                 if (xclk < refresh_tbl[i])
2245                 break;
2246         }
2247         par->mem_refresh_rate = i;
2248 }
2249
2250     /*
2251      *  Initialisation
2252      */
2253
2254 static struct fb_info *fb_list = NULL;
2255
2256 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2257 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2258                                                 struct fb_var_screeninfo *var)
2259 {
2260         int ret = -EINVAL;
2261
2262         if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2263                 *var = default_var;
2264                 var->xres = var->xres_virtual = par->lcd_hdisp;
2265                 var->right_margin = par->lcd_right_margin;
2266                 var->left_margin = par->lcd_hblank_len -
2267                         (par->lcd_right_margin + par->lcd_hsync_dly +
2268                          par->lcd_hsync_len);
2269                 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2270                 var->yres = var->yres_virtual = par->lcd_vdisp;
2271                 var->lower_margin = par->lcd_lower_margin;
2272                 var->upper_margin = par->lcd_vblank_len -
2273                         (par->lcd_lower_margin + par->lcd_vsync_len);
2274                 var->vsync_len = par->lcd_vsync_len;
2275                 var->pixclock = par->lcd_pixclock;
2276                 ret = 0;
2277         }
2278
2279         return ret;
2280 }
2281 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2282
2283 static int __devinit aty_init(struct fb_info *info)
2284 {
2285         struct atyfb_par *par = (struct atyfb_par *) info->par;
2286         const char *ramname = NULL, *xtal;
2287         int gtb_memsize, has_var = 0;
2288         struct fb_var_screeninfo var;
2289
2290         init_waitqueue_head(&par->vblank.wait);
2291         spin_lock_init(&par->int_lock);
2292
2293 #ifdef CONFIG_FB_ATY_GX
2294         if (!M64_HAS(INTEGRATED)) {
2295                 u32 stat0;
2296                 u8 dac_type, dac_subtype, clk_type;
2297                 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2298                 par->bus_type = (stat0 >> 0) & 0x07;
2299                 par->ram_type = (stat0 >> 3) & 0x07;
2300                 ramname = aty_gx_ram[par->ram_type];
2301                 /* FIXME: clockchip/RAMDAC probing? */
2302                 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2303 #ifdef CONFIG_ATARI
2304                 clk_type = CLK_ATI18818_1;
2305                 dac_type = (stat0 >> 9) & 0x07;
2306                 if (dac_type == 0x07)
2307                         dac_subtype = DAC_ATT20C408;
2308                 else
2309                         dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2310 #else
2311                 dac_type = DAC_IBMRGB514;
2312                 dac_subtype = DAC_IBMRGB514;
2313                 clk_type = CLK_IBMRGB514;
2314 #endif
2315                 switch (dac_subtype) {
2316                 case DAC_IBMRGB514:
2317                         par->dac_ops = &aty_dac_ibm514;
2318                         break;
2319 #ifdef CONFIG_ATARI
2320                 case DAC_ATI68860_B:
2321                 case DAC_ATI68860_C:
2322                         par->dac_ops = &aty_dac_ati68860b;
2323                         break;
2324                 case DAC_ATT20C408:
2325                 case DAC_ATT21C498:
2326                         par->dac_ops = &aty_dac_att21c498;
2327                         break;
2328 #endif
2329                 default:
2330                         PRINTKI("aty_init: DAC type not implemented yet!\n");
2331                         par->dac_ops = &aty_dac_unsupported;
2332                         break;
2333                 }
2334                 switch (clk_type) {
2335 #ifdef CONFIG_ATARI
2336                 case CLK_ATI18818_1:
2337                         par->pll_ops = &aty_pll_ati18818_1;
2338                         break;
2339 #else
2340                 case CLK_IBMRGB514:
2341                         par->pll_ops = &aty_pll_ibm514;
2342                         break;
2343 #endif
2344 #if 0 /* dead code */
2345                 case CLK_STG1703:
2346                         par->pll_ops = &aty_pll_stg1703;
2347                         break;
2348                 case CLK_CH8398:
2349                         par->pll_ops = &aty_pll_ch8398;
2350                         break;
2351                 case CLK_ATT20C408:
2352                         par->pll_ops = &aty_pll_att20c408;
2353                         break;
2354 #endif
2355                 default:
2356                         PRINTKI("aty_init: CLK type not implemented yet!");
2357                         par->pll_ops = &aty_pll_unsupported;
2358                         break;
2359                 }
2360         }
2361 #endif /* CONFIG_FB_ATY_GX */
2362 #ifdef CONFIG_FB_ATY_CT
2363         if (M64_HAS(INTEGRATED)) {
2364                 par->dac_ops = &aty_dac_ct;
2365                 par->pll_ops = &aty_pll_ct;
2366                 par->bus_type = PCI;
2367                 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2368                 ramname = aty_ct_ram[par->ram_type];
2369                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2370                 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2371                         par->pll_limits.mclk = 63;
2372                 /* Mobility + 32bit memory interface need halved XCLK. */
2373                 if (M64_HAS(MOBIL_BUS) && par->ram_type == SDRAM32)
2374                         par->pll_limits.xclk = (par->pll_limits.xclk + 1) >> 1;
2375         }
2376 #endif
2377 #ifdef CONFIG_PPC_PMAC
2378         /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2379          * and set the frequency manually. */
2380         if (machine_is_compatible("PowerBook2,1")) {
2381                 par->pll_limits.mclk = 70;
2382                 par->pll_limits.xclk = 53;
2383         }
2384 #endif
2385
2386         /* Allow command line to override clocks. */
2387         if (pll)
2388                 par->pll_limits.pll_max = pll;
2389         if (mclk)
2390                 par->pll_limits.mclk = mclk;
2391         if (xclk)
2392                 par->pll_limits.xclk = xclk;
2393
2394         aty_calc_mem_refresh(par, par->pll_limits.xclk);
2395         par->pll_per = 1000000/par->pll_limits.pll_max;
2396         par->mclk_per = 1000000/par->pll_limits.mclk;
2397         par->xclk_per = 1000000/par->pll_limits.xclk;
2398
2399         par->ref_clk_per = 1000000000000ULL / 14318180;
2400         xtal = "14.31818";
2401
2402 #ifdef CONFIG_FB_ATY_CT
2403         if (M64_HAS(GTB_DSP)) {
2404                 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
2405
2406                 if (pll_ref_div) {
2407                         int diff1, diff2;
2408                         diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2409                         diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2410                         if (diff1 < 0)
2411                                 diff1 = -diff1;
2412                         if (diff2 < 0)
2413                                 diff2 = -diff2;
2414                         if (diff2 < diff1) {
2415                                 par->ref_clk_per = 1000000000000ULL / 29498928;
2416                                 xtal = "29.498928";
2417                         }
2418                 }
2419         }
2420 #endif /* CONFIG_FB_ATY_CT */
2421
2422         /* save previous video mode */
2423         aty_get_crtc(par, &saved_crtc);
2424         if(par->pll_ops->get_pll)
2425                 par->pll_ops->get_pll(info, &saved_pll);
2426
2427         par->mem_cntl = aty_ld_le32(MEM_CNTL, par);
2428         gtb_memsize = M64_HAS(GTB_DSP);
2429         if (gtb_memsize)
2430                 switch (par->mem_cntl & 0xF) {  /* 0xF used instead of MEM_SIZE_ALIAS */
2431                 case MEM_SIZE_512K:
2432                         info->fix.smem_len = 0x80000;
2433                         break;
2434                 case MEM_SIZE_1M:
2435                         info->fix.smem_len = 0x100000;
2436                         break;
2437                 case MEM_SIZE_2M_GTB:
2438                         info->fix.smem_len = 0x200000;
2439                         break;
2440                 case MEM_SIZE_4M_GTB:
2441                         info->fix.smem_len = 0x400000;
2442                         break;
2443                 case MEM_SIZE_6M_GTB:
2444                         info->fix.smem_len = 0x600000;
2445                         break;
2446                 case MEM_SIZE_8M_GTB:
2447                         info->fix.smem_len = 0x800000;
2448                         break;
2449                 default:
2450                         info->fix.smem_len = 0x80000;
2451         } else
2452                 switch (par->mem_cntl & MEM_SIZE_ALIAS) {
2453                 case MEM_SIZE_512K:
2454                         info->fix.smem_len = 0x80000;
2455                         break;
2456                 case MEM_SIZE_1M:
2457                         info->fix.smem_len = 0x100000;
2458                         break;
2459                 case MEM_SIZE_2M:
2460                         info->fix.smem_len = 0x200000;
2461                         break;
2462                 case MEM_SIZE_4M:
2463                         info->fix.smem_len = 0x400000;
2464                         break;
2465                 case MEM_SIZE_6M:
2466                         info->fix.smem_len = 0x600000;
2467                         break;
2468                 case MEM_SIZE_8M:
2469                         info->fix.smem_len = 0x800000;
2470                         break;
2471                 default:
2472                         info->fix.smem_len = 0x80000;
2473                 }
2474
2475         if (M64_HAS(MAGIC_VRAM_SIZE)) {
2476                 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2477                         info->fix.smem_len += 0x400000;
2478         }
2479
2480         if (vram) {
2481                 info->fix.smem_len = vram * 1024;
2482                 par->mem_cntl &= ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2483                 if (info->fix.smem_len <= 0x80000)
2484                         par->mem_cntl |= MEM_SIZE_512K;
2485                 else if (info->fix.smem_len <= 0x100000)
2486                         par->mem_cntl |= MEM_SIZE_1M;
2487                 else if (info->fix.smem_len <= 0x200000)
2488                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2489                 else if (info->fix.smem_len <= 0x400000)
2490                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2491                 else if (info->fix.smem_len <= 0x600000)
2492                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2493                 else
2494                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2495                 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2496         }
2497
2498         /*
2499          *  Reg Block 0 (CT-compatible block) is at mmio_start
2500          *  Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2501          */
2502         if (M64_HAS(GX)) {
2503                 info->fix.mmio_len = 0x400;
2504                 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2505         } else if (M64_HAS(CT)) {
2506                 info->fix.mmio_len = 0x400;
2507                 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2508         } else if (M64_HAS(VT)) {
2509                 info->fix.mmio_start -= 0x400;
2510                 info->fix.mmio_len = 0x800;
2511                 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2512         } else {/* GT */
2513                 info->fix.mmio_start -= 0x400;
2514                 info->fix.mmio_len = 0x800;
2515                 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2516         }
2517
2518         PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2519                info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2520                info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2521                par->pll_limits.mclk, par->pll_limits.xclk);
2522
2523 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
2524         if (M64_HAS(INTEGRATED)) {
2525                 int i;
2526                 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2527                        "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2528                        "debug atyfb: %08x %08x %08x %08x     %08x      %08x   %08x   %08x\n"
2529                        "debug atyfb: PLL",
2530                         aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2531                         aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2532                         aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2533                         aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2534                 for (i = 0; i < 40; i++)
2535                         printk(" %02x", aty_ld_pll_ct(i, par));
2536                 printk("\n");
2537         }
2538 #endif
2539         if(par->pll_ops->init_pll)
2540                 par->pll_ops->init_pll(info, &par->pll);
2541         if (par->pll_ops->resume_pll)
2542                 par->pll_ops->resume_pll(info, &par->pll);
2543
2544         /*
2545          *  Last page of 8 MB (4 MB on ISA) aperture is MMIO,
2546          *  unless the auxiliary register aperture is used.
2547          */
2548
2549         if (!par->aux_start &&
2550                 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2551                 info->fix.smem_len -= GUI_RESERVE;
2552
2553         /*
2554          *  Disable register access through the linear aperture
2555          *  if the auxiliary aperture is used so we can access
2556          *  the full 8 MB of video RAM on 8 MB boards.
2557          */
2558         if (par->aux_start)
2559                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2560
2561 #ifdef CONFIG_MTRR
2562         par->mtrr_aper = -1;
2563         par->mtrr_reg = -1;
2564         if (!nomtrr) {
2565                 /* Cover the whole resource. */
2566                  par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2567                  if (par->mtrr_aper >= 0 && !par->aux_start) {
2568                         /* Make a hole for mmio. */
2569                         par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2570                                 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2571                         if (par->mtrr_reg < 0) {
2572                                 mtrr_del(par->mtrr_aper, 0, 0);
2573                                 par->mtrr_aper = -1;
2574                         }
2575                  }
2576         }
2577 #endif
2578
2579         info->fbops = &atyfb_ops;
2580         info->pseudo_palette = pseudo_palette;
2581         info->flags = FBINFO_DEFAULT           |
2582                       FBINFO_HWACCEL_IMAGEBLIT |
2583                       FBINFO_HWACCEL_FILLRECT  |
2584                       FBINFO_HWACCEL_COPYAREA  |
2585                       FBINFO_HWACCEL_YPAN;
2586
2587 #ifdef CONFIG_PMAC_BACKLIGHT
2588         if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2589                 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2590                 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2591                            | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2592         } else
2593 #endif
2594         if (M64_HAS(MOBIL_BUS) && backlight) {
2595 #ifdef CONFIG_FB_ATY_BACKLIGHT
2596                 aty_bl_init (par);
2597 #endif
2598         }
2599
2600         memset(&var, 0, sizeof(var));
2601 #ifdef CONFIG_PPC
2602         if (machine_is(powermac)) {
2603                 /*
2604                  *  FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2605                  *         applies to all Mac video cards
2606                  */
2607                 if (mode) {
2608                         if (mac_find_mode(&var, info, mode, 8))
2609                                 has_var = 1;
2610                 } else {
2611                         if (default_vmode == VMODE_CHOOSE) {
2612                                 int sense;
2613                                 if (M64_HAS(G3_PB_1024x768))
2614                                         /* G3 PowerBook with 1024x768 LCD */
2615                                         default_vmode = VMODE_1024_768_60;
2616                                 else if (machine_is_compatible("iMac"))
2617                                         default_vmode = VMODE_1024_768_75;
2618                                 else if (machine_is_compatible
2619                                          ("PowerBook2,1"))
2620                                         /* iBook with 800x600 LCD */
2621                                         default_vmode = VMODE_800_600_60;
2622                                 else
2623                                         default_vmode = VMODE_640_480_67;
2624                                 sense = read_aty_sense(par);
2625                                 PRINTKI("monitor sense=%x, mode %d\n",
2626                                         sense,  mac_map_monitor_sense(sense));
2627                         }
2628                         if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2629                                 default_vmode = VMODE_640_480_60;
2630                         if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2631                                 default_cmode = CMODE_8;
2632                         if (!mac_vmode_to_var(default_vmode, default_cmode,
2633                                                &var))
2634                                 has_var = 1;
2635                 }
2636         }
2637
2638 #endif /* !CONFIG_PPC */
2639
2640 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2641         if (!atyfb_get_timings_from_lcd(par, &var))
2642                 has_var = 1;
2643 #endif
2644
2645         if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2646                 has_var = 1;
2647
2648         if (!has_var)
2649                 var = default_var;
2650
2651         if (noaccel)
2652                 var.accel_flags &= ~FB_ACCELF_TEXT;
2653         else
2654                 var.accel_flags |= FB_ACCELF_TEXT;
2655
2656         if (comp_sync != -1) {
2657                 if (!comp_sync)
2658                         var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2659                 else
2660                         var.sync |= FB_SYNC_COMP_HIGH_ACT;
2661         }
2662
2663         if (var.yres == var.yres_virtual) {
2664                 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2665                 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2666                 if (var.yres_virtual < var.yres)
2667                         var.yres_virtual = var.yres;
2668         }
2669
2670         if (atyfb_check_var(&var, info)) {
2671                 PRINTKE("can't set default video mode\n");
2672                 goto aty_init_exit;
2673         }
2674
2675 #ifdef __sparc__
2676         atyfb_save_palette(par, 0);
2677 #endif
2678
2679 #ifdef CONFIG_FB_ATY_CT
2680         if (!noaccel && M64_HAS(INTEGRATED))
2681                 aty_init_cursor(info);
2682 #endif /* CONFIG_FB_ATY_CT */
2683         info->var = var;
2684
2685         fb_alloc_cmap(&info->cmap, 256, 0);
2686
2687         if (register_framebuffer(info) < 0)
2688                 goto aty_init_exit;
2689
2690         fb_list = info;
2691
2692         PRINTKI("fb%d: %s frame buffer device on %s\n",
2693                 info->node, info->fix.id, par->bus_type == ISA ? "ISA" : "PCI");
2694         return 0;
2695
2696 aty_init_exit:
2697         /* restore video mode */
2698         aty_set_crtc(par, &saved_crtc);
2699         par->pll_ops->set_pll(info, &saved_pll);
2700
2701 #ifdef CONFIG_MTRR
2702         if (par->mtrr_reg >= 0) {
2703             mtrr_del(par->mtrr_reg, 0, 0);
2704             par->mtrr_reg = -1;
2705         }
2706         if (par->mtrr_aper >= 0) {
2707             mtrr_del(par->mtrr_aper, 0, 0);
2708             par->mtrr_aper = -1;
2709         }
2710 #endif
2711         return -1;
2712 }
2713
2714 static void aty_resume_chip(struct fb_info *info)
2715 {
2716         struct atyfb_par *par = info->par;
2717
2718         aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2719
2720         if (par->pll_ops->resume_pll)
2721                 par->pll_ops->resume_pll(info, &par->pll);
2722
2723         if (par->aux_start)
2724                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2725 }
2726
2727 #ifdef CONFIG_ATARI
2728 static int __devinit store_video_par(char *video_str, unsigned char m64_num)
2729 {
2730         char *p;
2731         unsigned long vmembase, size, guiregbase;
2732
2733         PRINTKI("store_video_par() '%s' \n", video_str);
2734
2735         if (!(p = strsep(&video_str, ";")) || !*p)
2736                 goto mach64_invalid;
2737         vmembase = simple_strtoul(p, NULL, 0);
2738         if (!(p = strsep(&video_str, ";")) || !*p)
2739                 goto mach64_invalid;
2740         size = simple_strtoul(p, NULL, 0);
2741         if (!(p = strsep(&video_str, ";")) || !*p)
2742                 goto mach64_invalid;
2743         guiregbase = simple_strtoul(p, NULL, 0);
2744
2745         phys_vmembase[m64_num] = vmembase;
2746         phys_size[m64_num] = size;
2747         phys_guiregbase[m64_num] = guiregbase;
2748         PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2749                guiregbase);
2750         return 0;
2751
2752       mach64_invalid:
2753         phys_vmembase[m64_num] = 0;
2754         return -1;
2755 }
2756 #endif /* CONFIG_ATARI */
2757
2758     /*
2759      *  Blank the display.
2760      */
2761
2762 static int atyfb_blank(int blank, struct fb_info *info)
2763 {
2764         struct atyfb_par *par = (struct atyfb_par *) info->par;
2765         u32 gen_cntl;
2766
2767         if (par->lock_blank || par->asleep)
2768                 return 0;
2769
2770 #ifdef CONFIG_FB_ATY_BACKLIGHT
2771 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2772         if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2773             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2774                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2775                 pm &= ~PWR_BLON;
2776                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2777         }
2778 #endif
2779
2780         gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2781         gen_cntl &= ~0x400004c;
2782         switch (blank) {
2783                 case FB_BLANK_UNBLANK:
2784                         break;
2785                 case FB_BLANK_NORMAL:
2786                         gen_cntl |= 0x4000040;
2787                         break;
2788                 case FB_BLANK_VSYNC_SUSPEND:
2789                         gen_cntl |= 0x4000048;
2790                         break;
2791                 case FB_BLANK_HSYNC_SUSPEND:
2792                         gen_cntl |= 0x4000044;
2793                         break;
2794                 case FB_BLANK_POWERDOWN:
2795                         gen_cntl |= 0x400004c;
2796                         break;
2797         }
2798         aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2799
2800 #ifdef CONFIG_FB_ATY_BACKLIGHT
2801 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2802         if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2803             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2804                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2805                 pm |= PWR_BLON;
2806                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2807         }
2808 #endif
2809
2810         return 0;
2811 }
2812
2813 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2814                        const struct atyfb_par *par)
2815 {
2816         aty_st_8(DAC_W_INDEX, regno, par);
2817         aty_st_8(DAC_DATA, red, par);
2818         aty_st_8(DAC_DATA, green, par);
2819         aty_st_8(DAC_DATA, blue, par);
2820 }
2821
2822     /*
2823      *  Set a single color register. The values supplied are already
2824      *  rounded down to the hardware's capabilities (according to the
2825      *  entries in the var structure). Return != 0 for invalid regno.
2826      *  !! 4 & 8 =  PSEUDO, > 8 = DIRECTCOLOR
2827      */
2828
2829 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2830         u_int transp, struct fb_info *info)
2831 {
2832         struct atyfb_par *par = (struct atyfb_par *) info->par;
2833         int i, depth;
2834         u32 *pal = info->pseudo_palette;
2835
2836         depth = info->var.bits_per_pixel;
2837         if (depth == 16)
2838                 depth = (info->var.green.length == 5) ? 15 : 16;
2839
2840         if (par->asleep)
2841                 return 0;
2842
2843         if (regno > 255 ||
2844             (depth == 16 && regno > 63) ||
2845             (depth == 15 && regno > 31))
2846                 return 1;
2847
2848         red >>= 8;
2849         green >>= 8;
2850         blue >>= 8;
2851
2852         par->palette[regno].red = red;
2853         par->palette[regno].green = green;
2854         par->palette[regno].blue = blue;
2855
2856         if (regno < 16) {
2857                 switch (depth) {
2858                 case 15:
2859                         pal[regno] = (regno << 10) | (regno << 5) | regno;
2860                         break;
2861                 case 16:
2862                         pal[regno] = (regno << 11) | (regno << 5) | regno;
2863                         break;
2864                 case 24:
2865                         pal[regno] = (regno << 16) | (regno << 8) | regno;
2866                         break;
2867                 case 32:
2868                         i = (regno << 8) | regno;
2869                         pal[regno] = (i << 16) | i;
2870                         break;
2871                 }
2872         }
2873
2874         i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2875         if (M64_HAS(EXTRA_BRIGHT))
2876                 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2877         aty_st_8(DAC_CNTL, i, par);
2878         aty_st_8(DAC_MASK, 0xff, par);
2879
2880         if (M64_HAS(INTEGRATED)) {
2881                 if (depth == 16) {
2882                         if (regno < 32)
2883                                 aty_st_pal(regno << 3, red,
2884                                            par->palette[regno<<1].green,
2885                                            blue, par);
2886                         red = par->palette[regno>>1].red;
2887                         blue = par->palette[regno>>1].blue;
2888                         regno <<= 2;
2889                 } else if (depth == 15) {
2890                         regno <<= 3;
2891                         for(i = 0; i < 8; i++) {
2892                             aty_st_pal(regno + i, red, green, blue, par);
2893                         }
2894                 }
2895         }
2896         aty_st_pal(regno, red, green, blue, par);
2897
2898         return 0;
2899 }
2900
2901 #ifdef CONFIG_PCI
2902
2903 #ifdef __sparc__
2904
2905 extern void (*prom_palette) (int);
2906
2907 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2908                         struct fb_info *info, unsigned long addr)
2909 {
2910         struct atyfb_par *par = info->par;
2911         struct device_node *dp;
2912         char prop[128];
2913         int node, len, i, j, ret;
2914         u32 mem, chip_id;
2915
2916         /*
2917          * Map memory-mapped registers.
2918          */
2919         par->ati_regbase = (void *)addr + 0x7ffc00UL;
2920         info->fix.mmio_start = addr + 0x7ffc00UL;
2921
2922         /*
2923          * Map in big-endian aperture.
2924          */
2925         info->screen_base = (char *) (addr + 0x800000UL);
2926         info->fix.smem_start = addr + 0x800000UL;
2927
2928         /*
2929          * Figure mmap addresses from PCI config space.
2930          * Split Framebuffer in big- and little-endian halfs.
2931          */
2932         for (i = 0; i < 6 && pdev->resource[i].start; i++)
2933                 /* nothing */ ;
2934         j = i + 4;
2935
2936         par->mmap_map = kcalloc(j, sizeof(*par->mmap_map), GFP_ATOMIC);
2937         if (!par->mmap_map) {
2938                 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2939                 return -ENOMEM;
2940         }
2941
2942         for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2943                 struct resource *rp = &pdev->resource[i];
2944                 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2945                 unsigned long base;
2946                 u32 size, pbase;
2947
2948                 base = rp->start;
2949
2950                 io = (rp->flags & IORESOURCE_IO);
2951
2952                 size = rp->end - base + 1;
2953
2954                 pci_read_config_dword(pdev, breg, &pbase);
2955
2956                 if (io)
2957                         size &= ~1;
2958
2959                 /*
2960                  * Map the framebuffer a second time, this time without
2961                  * the braindead _PAGE_IE setting. This is used by the
2962                  * fixed Xserver, but we need to maintain the old mapping
2963                  * to stay compatible with older ones...
2964                  */
2965                 if (base == addr) {
2966                         par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2967                         par->mmap_map[j].poff = base & PAGE_MASK;
2968                         par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2969                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2970                         par->mmap_map[j].prot_flag = _PAGE_E;
2971                         j++;
2972                 }
2973
2974                 /*
2975                  * Here comes the old framebuffer mapping with _PAGE_IE
2976                  * set for the big endian half of the framebuffer...
2977                  */
2978                 if (base == addr) {
2979                         par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2980                         par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2981                         par->mmap_map[j].size = 0x800000;
2982                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2983                         par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2984                         size -= 0x800000;
2985                         j++;
2986                 }
2987
2988                 par->mmap_map[j].voff = pbase & PAGE_MASK;
2989                 par->mmap_map[j].poff = base & PAGE_MASK;
2990                 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2991                 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2992                 par->mmap_map[j].prot_flag = _PAGE_E;
2993                 j++;
2994         }
2995
2996         if((ret = correct_chipset(par)))
2997                 return ret;
2998
2999         if (IS_XL(pdev->device)) {
3000                 /*
3001                  * Fix PROMs idea of MEM_CNTL settings...
3002                  */
3003                 mem = aty_ld_le32(MEM_CNTL, par);
3004                 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
3005                 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
3006                         switch (mem & 0x0f) {
3007                         case 3:
3008                                 mem = (mem & ~(0x0f)) | 2;
3009                                 break;
3010                         case 7:
3011                                 mem = (mem & ~(0x0f)) | 3;
3012                                 break;
3013                         case 9:
3014                                 mem = (mem & ~(0x0f)) | 4;
3015                                 break;
3016                         case 11:
3017                                 mem = (mem & ~(0x0f)) | 5;
3018                                 break;
3019                         default:
3020                                 break;
3021                         }
3022                         if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
3023                                 mem &= ~(0x00700000);
3024                 }
3025                 mem &= ~(0xcf80e000);   /* Turn off all undocumented bits. */
3026                 aty_st_le32(MEM_CNTL, mem, par);
3027         }
3028
3029         /*
3030          * If this is the console device, we will set default video
3031          * settings to what the PROM left us with.
3032          */
3033         node = prom_getchild(prom_root_node);
3034         node = prom_searchsiblings(node, "aliases");
3035         if (node) {
3036                 len = prom_getproperty(node, "screen", prop, sizeof(prop));
3037                 if (len > 0) {
3038                         prop[len] = '\0';
3039                         node = prom_finddevice(prop);
3040                 } else
3041                         node = 0;
3042         }
3043
3044         dp = pci_device_to_OF_node(pdev);
3045         if (node == dp->node) {
3046                 struct fb_var_screeninfo *var = &default_var;
3047                 unsigned int N, P, Q, M, T, R;
3048                 u32 v_total, h_total;
3049                 struct crtc crtc;
3050                 u8 pll_regs[16];
3051                 u8 clock_cntl;
3052
3053                 crtc.vxres = prom_getintdefault(node, "width", 1024);
3054                 crtc.vyres = prom_getintdefault(node, "height", 768);
3055                 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
3056                 var->xoffset = var->yoffset = 0;
3057                 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3058                 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3059                 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3060                 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3061                 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3062                 aty_crtc_to_var(&crtc, var);
3063
3064                 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3065                 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3066
3067                 /*
3068                  * Read the PLL to figure actual Refresh Rate.
3069                  */
3070                 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3071                 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3072                 for (i = 0; i < 16; i++)
3073                         pll_regs[i] = aty_ld_pll_ct(i, par);
3074
3075                 /*
3076                  * PLL Reference Divider M:
3077                  */
3078                 M = pll_regs[2];
3079
3080                 /*
3081                  * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3082                  */
3083                 N = pll_regs[7 + (clock_cntl & 3)];
3084
3085                 /*
3086                  * PLL Post Divider P (Dependant on CLOCK_CNTL):
3087                  */
3088                 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3089
3090                 /*
3091                  * PLL Divider Q:
3092                  */
3093                 Q = N / P;
3094
3095                 /*
3096                  * Target Frequency:
3097                  *
3098                  *      T * M
3099                  * Q = -------
3100                  *      2 * R
3101                  *
3102                  * where R is XTALIN (= 14318 or 29498 kHz).
3103                  */
3104                 if (IS_XL(pdev->device))
3105                         R = 29498;
3106                 else
3107                         R = 14318;
3108
3109                 T = 2 * Q * R / M;
3110
3111                 default_var.pixclock = 1000000000 / T;
3112         }
3113
3114         return 0;
3115 }
3116
3117 #else /* __sparc__ */
3118
3119 #ifdef __i386__
3120 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3121 static void __devinit aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3122 {
3123         u32 driv_inf_tab, sig;
3124         u16 lcd_ofs;
3125
3126         /* To support an LCD panel, we should know it's dimensions and
3127          *  it's desired pixel clock.
3128          * There are two ways to do it:
3129          *  - Check the startup video mode and calculate the panel
3130          *    size from it. This is unreliable.
3131          *  - Read it from the driver information table in the video BIOS.
3132         */
3133         /* Address of driver information table is at offset 0x78. */
3134         driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3135
3136         /* Check for the driver information table signature. */
3137         sig = (*(u32 *)driv_inf_tab);
3138         if ((sig == 0x54504c24) || /* Rage LT pro */
3139                 (sig == 0x544d5224) || /* Rage mobility */
3140                 (sig == 0x54435824) || /* Rage XC */
3141                 (sig == 0x544c5824)) { /* Rage XL */
3142                 PRINTKI("BIOS contains driver information table.\n");
3143                 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3144                 par->lcd_table = 0;
3145                 if (lcd_ofs != 0) {
3146                         par->lcd_table = bios_base + lcd_ofs;
3147                 }
3148         }
3149
3150         if (par->lcd_table != 0) {
3151                 char model[24];
3152                 char strbuf[16];
3153                 char refresh_rates_buf[100];
3154                 int id, tech, f, i, m, default_refresh_rate;
3155                 char *txtcolour;
3156                 char *txtmonitor;
3157                 char *txtdual;
3158                 char *txtformat;
3159                 u16 width, height, panel_type, refresh_rates;
3160                 u16 *lcdmodeptr;
3161                 u32 format;
3162                 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3163                 /* The most important information is the panel size at
3164                  * offset 25 and 27, but there's some other nice information
3165                  * which we print to the screen.
3166                  */
3167                 id = *(u8 *)par->lcd_table;
3168                 strncpy(model,(char *)par->lcd_table+1,24);
3169                 model[23]=0;
3170
3171                 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3172                 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3173                 panel_type = *(u16 *)(par->lcd_table+29);
3174                 if (panel_type & 1)
3175                         txtcolour = "colour";
3176                 else
3177                         txtcolour = "monochrome";
3178                 if (panel_type & 2)
3179                         txtdual = "dual (split) ";
3180                 else
3181                         txtdual = "";
3182                 tech = (panel_type>>2) & 63;
3183                 switch (tech) {
3184                 case 0:
3185                         txtmonitor = "passive matrix";
3186                         break;
3187                 case 1:
3188                         txtmonitor = "active matrix";
3189                         break;
3190                 case 2:
3191                         txtmonitor = "active addressed STN";
3192                         break;
3193                 case 3:
3194                         txtmonitor = "EL";
3195                         break;
3196                 case 4:
3197                         txtmonitor = "plasma";
3198                         break;
3199                 default:
3200                         txtmonitor = "unknown";
3201                 }
3202                 format = *(u32 *)(par->lcd_table+57);
3203                 if (tech == 0 || tech == 2) {
3204                         switch (format & 7) {
3205                         case 0:
3206                                 txtformat = "12 bit interface";
3207                                 break;
3208                         case 1:
3209                                 txtformat = "16 bit interface";
3210                                 break;
3211                         case 2:
3212                                 txtformat = "24 bit interface";
3213                                 break;
3214                         default:
3215                                 txtformat = "unkown format";
3216                         }
3217                 } else {
3218                         switch (format & 7) {
3219                         case 0:
3220                                 txtformat = "8 colours";
3221                                 break;
3222                         case 1:
3223                                 txtformat = "512 colours";
3224                                 break;
3225                         case 2:
3226                                 txtformat = "4096 colours";
3227                                 break;
3228                         case 4:
3229                                 txtformat = "262144 colours (LT mode)";
3230                                 break;
3231                         case 5:
3232                                 txtformat = "16777216 colours";
3233                                 break;
3234                         case 6:
3235                                 txtformat = "262144 colours (FDPI-2 mode)";
3236                                 break;
3237                         default:
3238                                 txtformat = "unkown format";
3239                         }
3240                 }
3241                 PRINTKI("%s%s %s monitor detected: %s\n",
3242                         txtdual ,txtcolour, txtmonitor, model);
3243                 PRINTKI("       id=%d, %dx%d pixels, %s\n",
3244                         id, width, height, txtformat);
3245                 refresh_rates_buf[0] = 0;
3246                 refresh_rates = *(u16 *)(par->lcd_table+62);
3247                 m = 1;
3248                 f = 0;
3249                 for (i=0;i<16;i++) {
3250                         if (refresh_rates & m) {
3251                                 if (f == 0) {
3252                                         sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3253                                         f++;
3254                                 } else {
3255                                         sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3256                                 }
3257                                 strcat(refresh_rates_buf,strbuf);
3258                         }
3259                         m = m << 1;
3260                 }
3261                 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3262                 PRINTKI("       supports refresh rates [%s], default %d Hz\n",
3263                         refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3264                 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3265                 /* We now need to determine the crtc parameters for the
3266                  * LCD monitor. This is tricky, because they are not stored
3267                  * individually in the BIOS. Instead, the BIOS contains a
3268                  * table of display modes that work for this monitor.
3269                  *
3270                  * The idea is that we search for a mode of the same dimensions
3271                  * as the dimensions of the LCD monitor. Say our LCD monitor
3272                  * is 800x600 pixels, we search for a 800x600 monitor.
3273                  * The CRTC parameters we find here are the ones that we need
3274                  * to use to simulate other resolutions on the LCD screen.
3275                  */
3276                 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3277                 while (*lcdmodeptr != 0) {
3278                         u32 modeptr;
3279                         u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3280                         modeptr = bios_base + *lcdmodeptr;
3281
3282                         mwidth = *((u16 *)(modeptr+0));
3283                         mheight = *((u16 *)(modeptr+2));
3284
3285                         if (mwidth == width && mheight == height) {
3286                                 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3287                                 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3288                                 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3289                                 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3290                                 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3291                                 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3292
3293                                 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3294                                 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3295                                 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3296                                 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3297
3298                                 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3299                                 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3300                                 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3301                                 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3302
3303                                 par->lcd_vtotal++;
3304                                 par->lcd_vdisp++;
3305                                 lcd_vsync_start++;
3306
3307                                 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3308                                 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3309                                 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3310                                 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3311                                 break;
3312                         }
3313
3314                         lcdmodeptr++;
3315                 }
3316                 if (*lcdmodeptr == 0) {
3317                         PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3318                         /* To do: Switch to CRT if possible. */
3319                 } else {
3320                         PRINTKI("       LCD CRTC parameters: %d.%d  %d %d %d %d  %d %d %d %d\n",
3321                                 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3322                                 par->lcd_hdisp,
3323                                 par->lcd_hdisp + par->lcd_right_margin,
3324                                 par->lcd_hdisp + par->lcd_right_margin
3325                                         + par->lcd_hsync_dly + par->lcd_hsync_len,
3326                                 par->lcd_htotal,
3327                                 par->lcd_vdisp,
3328                                 par->lcd_vdisp + par->lcd_lower_margin,
3329                                 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3330                                 par->lcd_vtotal);
3331                         PRINTKI("                          : %d %d %d %d %d %d %d %d %d\n",
3332                                 par->lcd_pixclock,
3333                                 par->lcd_hblank_len - (par->lcd_right_margin +
3334                                         par->lcd_hsync_dly + par->lcd_hsync_len),
3335                                 par->lcd_hdisp,
3336                                 par->lcd_right_margin,
3337                                 par->lcd_hsync_len,
3338                                 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3339                                 par->lcd_vdisp,
3340                                 par->lcd_lower_margin,
3341                                 par->lcd_vsync_len);
3342                 }
3343         }
3344 }
3345 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3346
3347 static int __devinit init_from_bios(struct atyfb_par *par)
3348 {
3349         u32 bios_base, rom_addr;
3350         int ret;
3351
3352         rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3353         bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3354
3355         /* The BIOS starts with 0xaa55. */
3356         if (*((u16 *)bios_base) == 0xaa55) {
3357
3358                 u8 *bios_ptr;
3359                 u16 rom_table_offset, freq_table_offset;
3360                 PLL_BLOCK_MACH64 pll_block;
3361
3362                 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3363
3364                 /* check for frequncy table */
3365                 bios_ptr = (u8*)bios_base;
3366                 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3367                 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3368                 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3369
3370                 PRINTKI("BIOS frequency table:\n");
3371                 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3372                         pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3373                         pll_block.ref_freq, pll_block.ref_divider);
3374                 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3375                         pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3376                         pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3377
3378                 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3379                 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3380                 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3381                 par->pll_limits.ref_div = pll_block.ref_divider;
3382                 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3383                 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3384                 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3385                 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3386 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3387                 aty_init_lcd(par, bios_base);
3388 #endif
3389                 ret = 0;
3390         } else {
3391                 PRINTKE("no BIOS frequency table found, use parameters\n");
3392                 ret = -ENXIO;
3393         }
3394         iounmap((void* __iomem )bios_base);
3395
3396         return ret;
3397 }
3398 #endif /* __i386__ */
3399
3400 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3401 {
3402         struct atyfb_par *par = info->par;
3403         u16 tmp;
3404         unsigned long raddr;
3405         struct resource *rrp;
3406         int ret = 0;
3407
3408         raddr = addr + 0x7ff000UL;
3409         rrp = &pdev->resource[2];
3410         if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3411                 par->aux_start = rrp->start;
3412                 par->aux_size = rrp->end - rrp->start + 1;
3413                 raddr = rrp->start;
3414                 PRINTKI("using auxiliary register aperture\n");
3415         }
3416
3417         info->fix.mmio_start = raddr;
3418         par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3419         if (par->ati_regbase == 0)
3420                 return -ENOMEM;
3421
3422         info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3423         par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3424
3425         /*
3426          * Enable memory-space accesses using config-space
3427          * command register.
3428          */
3429         pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3430         if (!(tmp & PCI_COMMAND_MEMORY)) {
3431                 tmp |= PCI_COMMAND_MEMORY;
3432                 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3433         }
3434 #ifdef __BIG_ENDIAN
3435         /* Use the big-endian aperture */
3436         addr += 0x800000;
3437 #endif
3438
3439         /* Map in frame buffer */
3440         info->fix.smem_start = addr;
3441         info->screen_base = ioremap(addr, 0x800000);
3442         if (info->screen_base == NULL) {
3443                 ret = -ENOMEM;
3444                 goto atyfb_setup_generic_fail;
3445         }
3446
3447         if((ret = correct_chipset(par)))
3448                 goto atyfb_setup_generic_fail;
3449 #ifdef __i386__
3450         if((ret = init_from_bios(par)))
3451                 goto atyfb_setup_generic_fail;
3452 #endif
3453         if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3454                 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3455         else
3456                 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3457
3458         /* according to ATI, we should use clock 3 for acelerated mode */
3459         par->clk_wr_offset = 3;
3460
3461         return 0;
3462
3463 atyfb_setup_generic_fail:
3464         iounmap(par->ati_regbase);
3465         par->ati_regbase = NULL;
3466         if (info->screen_base) {
3467                 iounmap(info->screen_base);
3468                 info->screen_base = NULL;
3469         }
3470         return ret;
3471 }
3472
3473 #endif /* !__sparc__ */
3474
3475 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3476 {
3477         unsigned long addr, res_start, res_size;
3478         struct fb_info *info;
3479         struct resource *rp;
3480         struct atyfb_par *par;
3481         int i, rc = -ENOMEM;
3482
3483         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
3484                 if (pdev->device == aty_chips[i].pci_id)
3485                         break;
3486
3487         if (i < 0)
3488                 return -ENODEV;
3489
3490         /* Enable device in PCI config */
3491         if (pci_enable_device(pdev)) {
3492                 PRINTKE("Cannot enable PCI device\n");
3493                 return -ENXIO;
3494         }
3495
3496         /* Find which resource to use */
3497         rp = &pdev->resource[0];
3498         if (rp->flags & IORESOURCE_IO)
3499                 rp = &pdev->resource[1];
3500         addr = rp->start;
3501         if (!addr)
3502                 return -ENXIO;
3503
3504         /* Reserve space */
3505         res_start = rp->start;
3506         res_size = rp->end - rp->start + 1;
3507         if (!request_mem_region (res_start, res_size, "atyfb"))
3508                 return -EBUSY;
3509
3510         /* Allocate framebuffer */
3511         info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3512         if (!info) {
3513                 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3514                 return -ENOMEM;
3515         }
3516         par = info->par;
3517         info->fix = atyfb_fix;
3518         info->device = &pdev->dev;
3519         par->pci_id = aty_chips[i].pci_id;
3520         par->res_start = res_start;
3521         par->res_size = res_size;
3522         par->irq = pdev->irq;
3523         par->pdev = pdev;
3524
3525         /* Setup "info" structure */
3526 #ifdef __sparc__
3527         rc = atyfb_setup_sparc(pdev, info, addr);
3528 #else
3529         rc = atyfb_setup_generic(pdev, info, addr);
3530 #endif
3531         if (rc)
3532                 goto err_release_mem;
3533
3534         pci_set_drvdata(pdev, info);
3535
3536         /* Init chip & register framebuffer */
3537         if (aty_init(info))
3538                 goto err_release_io;
3539
3540 #ifdef __sparc__
3541         if (!prom_palette)
3542                 prom_palette = atyfb_palette;
3543
3544         /*
3545          * Add /dev/fb mmap values.
3546          */
3547         par->mmap_map[0].voff = 0x8000000000000000UL;
3548         par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3549         par->mmap_map[0].size = info->fix.smem_len;
3550         par->mmap_map[0].prot_mask = _PAGE_CACHE;
3551         par->mmap_map[0].prot_flag = _PAGE_E;
3552         par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3553         par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3554         par->mmap_map[1].size = PAGE_SIZE;
3555         par->mmap_map[1].prot_mask = _PAGE_CACHE;
3556         par->mmap_map[1].prot_flag = _PAGE_E;
3557 #endif /* __sparc__ */
3558
3559         return 0;
3560
3561 err_release_io:
3562 #ifdef __sparc__
3563         kfree(par->mmap_map);
3564 #else
3565         if (par->ati_regbase)
3566                 iounmap(par->ati_regbase);
3567         if (info->screen_base)
3568                 iounmap(info->screen_base);
3569 #endif
3570 err_release_mem:
3571         if (par->aux_start)
3572                 release_mem_region(par->aux_start, par->aux_size);
3573
3574         release_mem_region(par->res_start, par->res_size);
3575         framebuffer_release(info);
3576
3577         return rc;
3578 }
3579
3580 #endif /* CONFIG_PCI */
3581
3582 #ifdef CONFIG_ATARI
3583
3584 static int __init atyfb_atari_probe(void)
3585 {
3586         struct atyfb_par *par;
3587         struct fb_info *info;
3588         int m64_num;
3589         u32 clock_r;
3590         int num_found = 0;
3591
3592         for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3593                 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3594                     !phys_guiregbase[m64_num]) {
3595                     PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3596                         continue;
3597                 }
3598
3599                 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3600                 if (!info) {
3601                         PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3602                         return -ENOMEM;
3603                 }
3604                 par = info->par;
3605
3606                 info->fix = atyfb_fix;
3607
3608                 par->irq = (unsigned int) -1; /* something invalid */
3609
3610                 /*
3611                  *  Map the video memory (physical address given) to somewhere in the
3612                  *  kernel address space.
3613                  */
3614                 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3615                 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3616                 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3617                                                 0xFC00ul;
3618                 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3619
3620                 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3621                 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3622
3623                 switch (clock_r & 0x003F) {
3624                 case 0x12:
3625                         par->clk_wr_offset = 3; /*  */
3626                         break;
3627                 case 0x34:
3628                         par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3629                         break;
3630                 case 0x16:
3631                         par->clk_wr_offset = 1; /*  */
3632                         break;
3633                 case 0x38:
3634                         par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3635                         break;
3636                 }
3637
3638                 /* Fake pci_id for correct_chipset() */
3639                 switch (aty_ld_le32(CONFIG_CHIP_ID, par) & CFG_CHIP_TYPE) {
3640                 case 0x00d7:
3641                         par->pci_id = PCI_CHIP_MACH64GX;
3642                         break;
3643                 case 0x0057:
3644                         par->pci_id = PCI_CHIP_MACH64CX;
3645                         break;
3646                 default:
3647                         break;
3648                 }
3649
3650                 if (correct_chipset(par) || aty_init(info)) {
3651                         iounmap(info->screen_base);
3652                         iounmap(par->ati_regbase);
3653                         framebuffer_release(info);
3654                 } else {
3655                         num_found++;
3656                 }
3657         }
3658
3659         return num_found ? 0 : -ENXIO;
3660 }
3661
3662 #endif /* CONFIG_ATARI */
3663
3664 #ifdef CONFIG_PCI
3665
3666 static void __devexit atyfb_remove(struct fb_info *info)
3667 {
3668         struct atyfb_par *par = (struct atyfb_par *) info->par;
3669
3670         /* restore video mode */
3671         aty_set_crtc(par, &saved_crtc);
3672         par->pll_ops->set_pll(info, &saved_pll);
3673
3674         unregister_framebuffer(info);
3675
3676 #ifdef CONFIG_FB_ATY_BACKLIGHT
3677         if (M64_HAS(MOBIL_BUS))
3678                 aty_bl_exit(info->bl_dev);
3679 #endif
3680
3681 #ifdef CONFIG_MTRR
3682         if (par->mtrr_reg >= 0) {
3683             mtrr_del(par->mtrr_reg, 0, 0);
3684             par->mtrr_reg = -1;
3685         }
3686         if (par->mtrr_aper >= 0) {
3687             mtrr_del(par->mtrr_aper, 0, 0);
3688             par->mtrr_aper = -1;
3689         }
3690 #endif
3691 #ifndef __sparc__
3692         if (par->ati_regbase)
3693                 iounmap(par->ati_regbase);
3694         if (info->screen_base)
3695                 iounmap(info->screen_base);
3696 #ifdef __BIG_ENDIAN
3697         if (info->sprite.addr)
3698                 iounmap(info->sprite.addr);
3699 #endif
3700 #endif
3701 #ifdef __sparc__
3702         kfree(par->mmap_map);
3703 #endif
3704         if (par->aux_start)
3705                 release_mem_region(par->aux_start, par->aux_size);
3706
3707         if (par->res_start)
3708                 release_mem_region(par->res_start, par->res_size);
3709
3710         framebuffer_release(info);
3711 }
3712
3713
3714 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3715 {
3716         struct fb_info *info = pci_get_drvdata(pdev);
3717
3718         atyfb_remove(info);
3719 }
3720
3721 /*
3722  * This driver uses its own matching table. That will be more difficult
3723  * to fix, so for now, we just match against any ATI ID and let the
3724  * probe() function find out what's up. That also mean we don't have
3725  * a module ID table though.
3726  */
3727 static struct pci_device_id atyfb_pci_tbl[] = {
3728         { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3729           PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3730         { 0, }
3731 };
3732
3733 static struct pci_driver atyfb_driver = {
3734         .name           = "atyfb",
3735         .id_table       = atyfb_pci_tbl,
3736         .probe          = atyfb_pci_probe,
3737         .remove         = __devexit_p(atyfb_pci_remove),
3738 #ifdef CONFIG_PM
3739         .suspend        = atyfb_pci_suspend,
3740         .resume         = atyfb_pci_resume,
3741 #endif /* CONFIG_PM */
3742 };
3743
3744 #endif /* CONFIG_PCI */
3745
3746 #ifndef MODULE
3747 static int __init atyfb_setup(char *options)
3748 {
3749         char *this_opt;
3750
3751         if (!options || !*options)
3752                 return 0;
3753
3754         while ((this_opt = strsep(&options, ",")) != NULL) {
3755                 if (!strncmp(this_opt, "noaccel", 7)) {
3756                         noaccel = 1;
3757 #ifdef CONFIG_MTRR
3758                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3759                         nomtrr = 1;
3760 #endif
3761                 } else if (!strncmp(this_opt, "vram:", 5))
3762                         vram = simple_strtoul(this_opt + 5, NULL, 0);
3763                 else if (!strncmp(this_opt, "pll:", 4))
3764                         pll = simple_strtoul(this_opt + 4, NULL, 0);
3765                 else if (!strncmp(this_opt, "mclk:", 5))
3766                         mclk = simple_strtoul(this_opt + 5, NULL, 0);
3767                 else if (!strncmp(this_opt, "xclk:", 5))
3768                         xclk = simple_strtoul(this_opt+5, NULL, 0);
3769                 else if (!strncmp(this_opt, "comp_sync:", 10))
3770                         comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3771                 else if (!strncmp(this_opt, "backlight:", 10))
3772                         backlight = simple_strtoul(this_opt+10, NULL, 0);
3773 #ifdef CONFIG_PPC
3774                 else if (!strncmp(this_opt, "vmode:", 6)) {
3775                         unsigned int vmode =
3776                             simple_strtoul(this_opt + 6, NULL, 0);
3777                         if (vmode > 0 && vmode <= VMODE_MAX)
3778                                 default_vmode = vmode;
3779                 } else if (!strncmp(this_opt, "cmode:", 6)) {
3780                         unsigned int cmode =
3781                             simple_strtoul(this_opt + 6, NULL, 0);
3782                         switch (cmode) {
3783                         case 0:
3784                         case 8:
3785                                 default_cmode = CMODE_8;
3786                                 break;
3787                         case 15:
3788                         case 16:
3789                                 default_cmode = CMODE_16;
3790                                 break;
3791                         case 24:
3792                         case 32:
3793                                 default_cmode = CMODE_32;
3794                                 break;
3795                         }
3796                 }
3797 #endif
3798 #ifdef CONFIG_ATARI
3799                 /*
3800                  * Why do we need this silly Mach64 argument?
3801                  * We are already here because of mach64= so its redundant.
3802                  */
3803                 else if (MACH_IS_ATARI
3804                          && (!strncmp(this_opt, "Mach64:", 7))) {
3805                         static unsigned char m64_num;
3806                         static char mach64_str[80];
3807                         strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3808                         if (!store_video_par(mach64_str, m64_num)) {
3809                                 m64_num++;
3810                                 mach64_count = m64_num;
3811                         }
3812                 }
3813 #endif
3814                 else
3815                         mode = this_opt;
3816         }
3817         return 0;
3818 }
3819 #endif  /*  MODULE  */
3820
3821 static int __init atyfb_init(void)
3822 {
3823     int err1 = 1, err2 = 1;
3824 #ifndef MODULE
3825     char *option = NULL;
3826
3827     if (fb_get_options("atyfb", &option))
3828         return -ENODEV;
3829     atyfb_setup(option);
3830 #endif
3831
3832 #ifdef CONFIG_PCI
3833     err1 = pci_register_driver(&atyfb_driver);
3834 #endif
3835 #ifdef CONFIG_ATARI
3836     err2 = atyfb_atari_probe();
3837 #endif
3838
3839     return (err1 && err2) ? -ENODEV : 0;
3840 }
3841
3842 static void __exit atyfb_exit(void)
3843 {
3844 #ifdef CONFIG_PCI
3845         pci_unregister_driver(&atyfb_driver);
3846 #endif
3847 }
3848
3849 module_init(atyfb_init);
3850 module_exit(atyfb_exit);
3851
3852 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3853 MODULE_LICENSE("GPL");
3854 module_param(noaccel, bool, 0);
3855 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3856 module_param(vram, int, 0);
3857 MODULE_PARM_DESC(vram, "int: override size of video ram");
3858 module_param(pll, int, 0);
3859 MODULE_PARM_DESC(pll, "int: override video clock");
3860 module_param(mclk, int, 0);
3861 MODULE_PARM_DESC(mclk, "int: override memory clock");
3862 module_param(xclk, int, 0);
3863 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3864 module_param(comp_sync, int, 0);
3865 MODULE_PARM_DESC(comp_sync,
3866                  "Set composite sync signal to low (0) or high (1)");
3867 module_param(mode, charp, 0);
3868 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3869 #ifdef CONFIG_MTRR
3870 module_param(nomtrr, bool, 0);
3871 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3872 #endif