drivers/staging/tidspbridge/core/tiomap3430.c

   1 /*
   2  * tiomap.c
   3  *
   4  * DSP-BIOS Bridge driver support functions for TI OMAP processors.
   5  *
   6  * Processor Manager Driver for TI OMAP3430 EVM.
   7  *
   8  * Copyright (C) 2005-2006 Texas Instruments, Inc.
   9  *
  10  * This package is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  16  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  17  */
  18
  19 #include <plat/dsp.h>
  20
  21 #include <linux/types.h>
  22 /*  ----------------------------------- Host OS */
  23 #include <dspbridge/host_os.h>
  24 #include <linux/mm.h>
  25 #include <linux/mmzone.h>
  26
  27 /*  ----------------------------------- DSP/BIOS Bridge */
  28 #include <dspbridge/dbdefs.h>
  29
  30 /*  ----------------------------------- Trace & Debug */
  31 #include <dspbridge/dbc.h>
  32
  33 /*  ----------------------------------- OS Adaptation Layer */
  34 #include <dspbridge/drv.h>
  35 #include <dspbridge/sync.h>
  36
  37 /* ------------------------------------ Hardware Abstraction Layer */
  38 #include <hw_defs.h>
  39 #include <hw_mmu.h>
  40
  41 /*  ----------------------------------- Link Driver */
  42 #include <dspbridge/dspdefs.h>
  43 #include <dspbridge/dspchnl.h>
  44 #include <dspbridge/dspdeh.h>
  45 #include <dspbridge/dspio.h>
  46 #include <dspbridge/dspmsg.h>
  47 #include <dspbridge/pwr.h>
  48 #include <dspbridge/io_sm.h>
  49
  50 /*  ----------------------------------- Platform Manager */
  51 #include <dspbridge/dev.h>
  52 #include <dspbridge/dspapi.h>
  53 #include <dspbridge/dmm.h>
  54 #include <dspbridge/wdt.h>
  55
  56 /*  ----------------------------------- Local */
  57 #include "_tiomap.h"
  58 #include "_tiomap_pwr.h"
  59 #include "tiomap_io.h"
  60
  61 /* Offset in shared mem to write to in order to synchronize start with DSP */
  62 #define SHMSYNCOFFSET 4         /* GPP byte offset */
  63
  64 #define BUFFERSIZE 1024
  65
  66 #define TIHELEN_ACKTIMEOUT  10000
  67
  68 #define MMU_SECTION_ADDR_MASK    0xFFF00000
  69 #define MMU_SSECTION_ADDR_MASK   0xFF000000
  70 #define MMU_LARGE_PAGE_MASK      0xFFFF0000
  71 #define MMU_SMALL_PAGE_MASK      0xFFFFF000
  72 #define OMAP3_IVA2_BOOTADDR_MASK 0xFFFFFC00
  73 #define PAGES_II_LVL_TABLE   512
  74 #define PHYS_TO_PAGE(phys)      pfn_to_page((phys) >> PAGE_SHIFT)
  75
  76 /*
  77  * This is a totally ugly layer violation, but needed until
  78  * omap_ctrl_set_dsp_boot*() are provided.
  79  */
  80 #define OMAP3_IVA2_BOOTMOD_IDLE 1
  81 #define OMAP2_CONTROL_GENERAL 0x270
  82 #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
  83 #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
  84
  85 #define OMAP343X_CTRL_REGADDR(reg) \
  86         OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
  87
  88
  89 /* Forward Declarations: */
  90 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt);
  91 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
  92                                   u8 *host_buff,
  93                                   u32 dsp_addr, u32 ul_num_bytes,
  94                                   u32 mem_type);
  95 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
  96                                    u32 dsp_addr);
  97 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
  98                                     int *board_state);
  99 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt);
 100 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
 101                                    u8 *host_buff,
 102                                    u32 dsp_addr, u32 ul_num_bytes,
 103                                    u32 mem_type);
 104 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
 105                                     u32 brd_state);
 106 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
 107                                    u32 dsp_dest_addr, u32 dsp_src_addr,
 108                                    u32 ul_num_bytes, u32 mem_type);
 109 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
 110                                     u8 *host_buff, u32 dsp_addr,
 111                                     u32 ul_num_bytes, u32 mem_type);
 112 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
 113                                   u32 ul_mpu_addr, u32 virt_addr,
 114                                   u32 ul_num_bytes, u32 ul_map_attr,
 115                                   struct page **mapped_pages);
 116 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
 117                                      u32 virt_addr, u32 ul_num_bytes);
 118 static int bridge_dev_create(struct bridge_dev_context
 119                                         **dev_cntxt,
 120                                         struct dev_object *hdev_obj,
 121                                         struct cfg_hostres *config_param);
 122 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
 123                                   u32 dw_cmd, void *pargs);
 124 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt);
 125 static u32 user_va2_pa(struct mm_struct *mm, u32 address);
 126 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
 127                              u32 va, u32 size,
 128                              struct hw_mmu_map_attrs_t *map_attrs);
 129 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
 130                           u32 size, struct hw_mmu_map_attrs_t *attrs);
 131 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
 132                                   u32 ul_mpu_addr, u32 virt_addr,
 133                                   u32 ul_num_bytes,
 134                                   struct hw_mmu_map_attrs_t *hw_attrs);
 135
 136 bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr);
 137
 138 /*  ----------------------------------- Globals */
 139
 140 /* Attributes of L2 page tables for DSP MMU */
 141 struct page_info {
 142         u32 num_entries;        /* Number of valid PTEs in the L2 PT */
 143 };
 144
 145 /* Attributes used to manage the DSP MMU page tables */
 146 struct pg_table_attrs {
 147         spinlock_t pg_lock;     /* Critical section object handle */
 148
 149         u32 l1_base_pa;         /* Physical address of the L1 PT */
 150         u32 l1_base_va;         /* Virtual  address of the L1 PT */
 151         u32 l1_size;            /* Size of the L1 PT */
 152         u32 l1_tbl_alloc_pa;
 153         /* Physical address of Allocated mem for L1 table. May not be aligned */
 154         u32 l1_tbl_alloc_va;
 155         /* Virtual address of Allocated mem for L1 table. May not be aligned */
 156         u32 l1_tbl_alloc_sz;
 157         /* Size of consistent memory allocated for L1 table.
 158          * May not be aligned */
 159
 160         u32 l2_base_pa;         /* Physical address of the L2 PT */
 161         u32 l2_base_va;         /* Virtual  address of the L2 PT */
 162         u32 l2_size;            /* Size of the L2 PT */
 163         u32 l2_tbl_alloc_pa;
 164         /* Physical address of Allocated mem for L2 table. May not be aligned */
 165         u32 l2_tbl_alloc_va;
 166         /* Virtual address of Allocated mem for L2 table. May not be aligned */
 167         u32 l2_tbl_alloc_sz;
 168         /* Size of consistent memory allocated for L2 table.
 169          * May not be aligned */
 170
 171         u32 l2_num_pages;       /* Number of allocated L2 PT */
 172         /* Array [l2_num_pages] of L2 PT info structs */
 173         struct page_info *pg_info;
 174 };
 175
 176 /*
 177  *  This Bridge driver's function interface table.
 178  */
 179 static struct bridge_drv_interface drv_interface_fxns = {
 180         /* Bridge API ver. for which this bridge driver is built. */
 181         BRD_API_MAJOR_VERSION,
 182         BRD_API_MINOR_VERSION,
 183         bridge_dev_create,
 184         bridge_dev_destroy,
 185         bridge_dev_ctrl,
 186         bridge_brd_monitor,
 187         bridge_brd_start,
 188         bridge_brd_stop,
 189         bridge_brd_status,
 190         bridge_brd_read,
 191         bridge_brd_write,
 192         bridge_brd_set_state,
 193         bridge_brd_mem_copy,
 194         bridge_brd_mem_write,
 195         bridge_brd_mem_map,
 196         bridge_brd_mem_un_map,
 197         /* The following CHNL functions are provided by chnl_io.lib: */
 198         bridge_chnl_create,
 199         bridge_chnl_destroy,
 200         bridge_chnl_open,
 201         bridge_chnl_close,
 202         bridge_chnl_add_io_req,
 203         bridge_chnl_get_ioc,
 204         bridge_chnl_cancel_io,
 205         bridge_chnl_flush_io,
 206         bridge_chnl_get_info,
 207         bridge_chnl_get_mgr_info,
 208         bridge_chnl_idle,
 209         bridge_chnl_register_notify,
 210         /* The following IO functions are provided by chnl_io.lib: */
 211         bridge_io_create,
 212         bridge_io_destroy,
 213         bridge_io_on_loaded,
 214         bridge_io_get_proc_load,
 215         /* The following msg_ctrl functions are provided by chnl_io.lib: */
 216         bridge_msg_create,
 217         bridge_msg_create_queue,
 218         bridge_msg_delete,
 219         bridge_msg_delete_queue,
 220         bridge_msg_get,
 221         bridge_msg_put,
 222         bridge_msg_register_notify,
 223         bridge_msg_set_queue_id,
 224 };
 225
 226 static inline void flush_all(struct bridge_dev_context *dev_context)
 227 {
 228         if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION ||
 229             dev_context->dw_brd_state == BRD_HIBERNATION)
 230                 wake_dsp(dev_context, NULL);
 231
 232         hw_mmu_tlb_flush_all(dev_context->dw_dsp_mmu_base);
 233 }
 234
 235 static void bad_page_dump(u32 pa, struct page *pg)
 236 {
 237         pr_emerg("DSPBRIDGE: MAP function: COUNT 0 FOR PA 0x%x\n", pa);
 238         pr_emerg("Bad page state in process '%s'\n"
 239                  "page:%p flags:0x%0*lx mapping:%p mapcount:%d count:%d\n"
 240                  "Backtrace:\n",
 241                  current->comm, pg, (int)(2 * sizeof(unsigned long)),
 242                  (unsigned long)pg->flags, pg->mapping,
 243                  page_mapcount(pg), page_count(pg));
 244         dump_stack();
 245 }
 246
 247 /*
 248  *  ======== bridge_drv_entry ========
 249  *  purpose:
 250  *      Bridge Driver entry point.
 251  */
 252 void bridge_drv_entry(struct bridge_drv_interface **drv_intf,
 253                    const char *driver_file_name)
 254 {
 255
 256         DBC_REQUIRE(driver_file_name != NULL);
 257
 258         io_sm_init();           /* Initialization of io_sm module */
 259
 260         if (strcmp(driver_file_name, "UMA") == 0)
 261                 *drv_intf = &drv_interface_fxns;
 262         else
 263                 dev_dbg(bridge, "%s Unknown Bridge file name", __func__);
 264
 265 }
 266
 267 /*
 268  *  ======== bridge_brd_monitor ========
 269  *  purpose:
 270  *      This bridge_brd_monitor puts DSP into a Loadable state.
 271  *      i.e Application can load and start the device.
 272  *
 273  *  Preconditions:
 274  *      Device in 'OFF' state.
 275  */
 276 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt)
 277 {
 278         struct bridge_dev_context *dev_context = dev_ctxt;
 279         u32 temp;
 280         struct omap_dsp_platform_data *pdata =
 281                 omap_dspbridge_dev->dev.platform_data;
 282
 283         temp = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
 284                                         OMAP_POWERSTATEST_MASK;
 285         if (!(temp & 0x02)) {
 286                 /* IVA2 is not in ON state */
 287                 /* Read and set PM_PWSTCTRL_IVA2  to ON */
 288                 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
 289                         PWRDM_POWER_ON, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
 290                 /* Set the SW supervised state transition */
 291                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP,
 292                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 293
 294                 /* Wait until the state has moved to ON */
 295                 while ((*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
 296                                                 OMAP_INTRANSITION_MASK)
 297                         ;
 298                 /* Disable Automatic transition */
 299                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_DISABLE_AUTO,
 300                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 301         }
 302         (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
 303                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 304         dsp_clk_enable(DSP_CLK_IVA2);
 305
 306         /* set the device state to IDLE */
 307         dev_context->dw_brd_state = BRD_IDLE;
 308
 309         return 0;
 310 }
 311
 312 /*
 313  *  ======== bridge_brd_read ========
 314  *  purpose:
 315  *      Reads buffers for DSP memory.
 316  */
 317 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
 318                                   u8 *host_buff, u32 dsp_addr,
 319                                   u32 ul_num_bytes, u32 mem_type)
 320 {
 321         int status = 0;
 322         struct bridge_dev_context *dev_context = dev_ctxt;
 323         u32 offset;
 324         u32 dsp_base_addr = dev_ctxt->dw_dsp_base_addr;
 325
 326         if (dsp_addr < dev_context->dw_dsp_start_add) {
 327                 status = -EPERM;
 328                 return status;
 329         }
 330         /* change here to account for the 3 bands of the DSP internal memory */
 331         if ((dsp_addr - dev_context->dw_dsp_start_add) <
 332             dev_context->dw_internal_size) {
 333                 offset = dsp_addr - dev_context->dw_dsp_start_add;
 334         } else {
 335                 status = read_ext_dsp_data(dev_context, host_buff, dsp_addr,
 336                                            ul_num_bytes, mem_type);
 337                 return status;
 338         }
 339         /* copy the data from  DSP memory, */
 340         memcpy(host_buff, (void *)(dsp_base_addr + offset), ul_num_bytes);
 341         return status;
 342 }
 343
 344 /*
 345  *  ======== bridge_brd_set_state ========
 346  *  purpose:
 347  *      This routine updates the Board status.
 348  */
 349 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
 350                                     u32 brd_state)
 351 {
 352         int status = 0;
 353         struct bridge_dev_context *dev_context = dev_ctxt;
 354
 355         dev_context->dw_brd_state = brd_state;
 356         return status;
 357 }
 358
 359 /*
 360  *  ======== bridge_brd_start ========
 361  *  purpose:
 362  *      Initializes DSP MMU and Starts DSP.
 363  *
 364  *  Preconditions:
 365  *  a) DSP domain is 'ACTIVE'.
 366  *  b) DSP_RST1 is asserted.
 367  *  b) DSP_RST2 is released.
 368  */
 369 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
 370                                    u32 dsp_addr)
 371 {
 372         int status = 0;
 373         struct bridge_dev_context *dev_context = dev_ctxt;
 374         u32 dw_sync_addr = 0;
 375         u32 ul_shm_base;        /* Gpp Phys SM base addr(byte) */
 376         u32 ul_shm_base_virt;   /* Dsp Virt SM base addr */
 377         u32 ul_tlb_base_virt;   /* Base of MMU TLB entry */
 378         /* Offset of shm_base_virt from tlb_base_virt */
 379         u32 ul_shm_offset_virt;
 380         s32 entry_ndx;
 381         s32 itmp_entry_ndx = 0; /* DSP-MMU TLB entry base address */
 382         struct cfg_hostres *resources = NULL;
 383         u32 temp;
 384         u32 ul_dsp_clk_rate;
 385         u32 ul_dsp_clk_addr;
 386         u32 ul_bios_gp_timer;
 387         u32 clk_cmd;
 388         struct io_mgr *hio_mgr;
 389         u32 ul_load_monitor_timer;
 390         struct omap_dsp_platform_data *pdata =
 391                 omap_dspbridge_dev->dev.platform_data;
 392
 393         /* The device context contains all the mmu setup info from when the
 394          * last dsp base image was loaded. The first entry is always
 395          * SHMMEM base. */
 396         /* Get SHM_BEG - convert to byte address */
 397         (void)dev_get_symbol(dev_context->hdev_obj, SHMBASENAME,
 398                              &ul_shm_base_virt);
 399         ul_shm_base_virt *= DSPWORDSIZE;
 400         DBC_ASSERT(ul_shm_base_virt != 0);
 401         /* DSP Virtual address */
 402         ul_tlb_base_virt = dev_context->atlb_entry[0].ul_dsp_va;
 403         DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt);
 404         ul_shm_offset_virt =
 405             ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE);
 406         /* Kernel logical address */
 407         ul_shm_base = dev_context->atlb_entry[0].ul_gpp_va + ul_shm_offset_virt;
 408
 409         DBC_ASSERT(ul_shm_base != 0);
 410         /* 2nd wd is used as sync field */
 411         dw_sync_addr = ul_shm_base + SHMSYNCOFFSET;
 412         /* Write a signature into the shm base + offset; this will
 413          * get cleared when the DSP program starts. */
 414         if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
 415                 pr_err("%s: Illegal SM base\n", __func__);
 416                 status = -EPERM;
 417         } else
 418                 __raw_writel(0xffffffff, dw_sync_addr);
 419
 420         if (!status) {
 421                 resources = dev_context->resources;
 422                 if (!resources)
 423                         status = -EPERM;
 424
 425                 /* Assert RST1 i.e only the RST only for DSP megacell */
 426                 if (!status) {
 427                         (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
 428                                         OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
 429                                         OMAP2_RM_RSTCTRL);
 430                         /* Mask address with 1K for compatibility */
 431                         __raw_writel(dsp_addr & OMAP3_IVA2_BOOTADDR_MASK,
 432                                         OMAP343X_CTRL_REGADDR(
 433                                         OMAP343X_CONTROL_IVA2_BOOTADDR));
 434                         /*
 435                          * Set bootmode to self loop if dsp_debug flag is true
 436                          */
 437                         __raw_writel((dsp_debug) ? OMAP3_IVA2_BOOTMOD_IDLE : 0,
 438                                         OMAP343X_CTRL_REGADDR(
 439                                         OMAP343X_CONTROL_IVA2_BOOTMOD));
 440                 }
 441         }
 442         if (!status) {
 443                 /* Reset and Unreset the RST2, so that BOOTADDR is copied to
 444                  * IVA2 SYSC register */
 445                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK,
 446                         OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 447                 udelay(100);
 448                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
 449                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 450                 udelay(100);
 451
 452                 /* Disbale the DSP MMU */
 453                 hw_mmu_disable(resources->dw_dmmu_base);
 454                 /* Disable TWL */
 455                 hw_mmu_twl_disable(resources->dw_dmmu_base);
 456
 457                 /* Only make TLB entry if both addresses are non-zero */
 458                 for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB;
 459                      entry_ndx++) {
 460                         struct bridge_ioctl_extproc *e = &dev_context->atlb_entry[entry_ndx];
 461                         struct hw_mmu_map_attrs_t map_attrs = {
 462                                 .endianism = e->endianism,
 463                                 .element_size = e->elem_size,
 464                                 .mixed_size = e->mixed_mode,
 465                         };
 466
 467                         if (!e->ul_gpp_pa || !e->ul_dsp_va)
 468                                 continue;
 469
 470                         dev_dbg(bridge,
 471                                         "MMU %d, pa: 0x%x, va: 0x%x, size: 0x%x",
 472                                         itmp_entry_ndx,
 473                                         e->ul_gpp_pa,
 474                                         e->ul_dsp_va,
 475                                         e->ul_size);
 476
 477                         hw_mmu_tlb_add(dev_context->dw_dsp_mmu_base,
 478                                         e->ul_gpp_pa,
 479                                         e->ul_dsp_va,
 480                                         e->ul_size,
 481                                         itmp_entry_ndx,
 482                                         &map_attrs, 1, 1);
 483
 484                         itmp_entry_ndx++;
 485                 }
 486         }
 487
 488         /* Lock the above TLB entries and get the BIOS and load monitor timer
 489          * information */
 490         if (!status) {
 491                 hw_mmu_num_locked_set(resources->dw_dmmu_base, itmp_entry_ndx);
 492                 hw_mmu_victim_num_set(resources->dw_dmmu_base, itmp_entry_ndx);
 493                 hw_mmu_ttb_set(resources->dw_dmmu_base,
 494                                dev_context->pt_attrs->l1_base_pa);
 495                 hw_mmu_twl_enable(resources->dw_dmmu_base);
 496                 /* Enable the SmartIdle and AutoIdle bit for MMU_SYSCONFIG */
 497
 498                 temp = __raw_readl((resources->dw_dmmu_base) + 0x10);
 499                 temp = (temp & 0xFFFFFFEF) | 0x11;
 500                 __raw_writel(temp, (resources->dw_dmmu_base) + 0x10);
 501
 502                 /* Let the DSP MMU run */
 503                 hw_mmu_enable(resources->dw_dmmu_base);
 504
 505                 /* Enable the BIOS clock */
 506                 (void)dev_get_symbol(dev_context->hdev_obj,
 507                                      BRIDGEINIT_BIOSGPTIMER, &ul_bios_gp_timer);
 508                 (void)dev_get_symbol(dev_context->hdev_obj,
 509                                      BRIDGEINIT_LOADMON_GPTIMER,
 510                                      &ul_load_monitor_timer);
 511         }
 512
 513         if (!status) {
 514                 if (ul_load_monitor_timer != 0xFFFF) {
 515                         clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
 516                             ul_load_monitor_timer;
 517                         dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
 518                 } else {
 519                         dev_dbg(bridge, "Not able to get the symbol for Load "
 520                                 "Monitor Timer\n");
 521                 }
 522         }
 523
 524         if (!status) {
 525                 if (ul_bios_gp_timer != 0xFFFF) {
 526                         clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
 527                             ul_bios_gp_timer;
 528                         dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
 529                 } else {
 530                         dev_dbg(bridge,
 531                                 "Not able to get the symbol for BIOS Timer\n");
 532                 }
 533         }
 534
 535         if (!status) {
 536                 /* Set the DSP clock rate */
 537                 (void)dev_get_symbol(dev_context->hdev_obj,
 538                                      "_BRIDGEINIT_DSP_FREQ", &ul_dsp_clk_addr);
 539                 /*Set Autoidle Mode for IVA2 PLL */
 540                 (*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 541                                 OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
 542
 543                 if ((unsigned int *)ul_dsp_clk_addr != NULL) {
 544                         /* Get the clock rate */
 545                         ul_dsp_clk_rate = dsp_clk_get_iva2_rate();
 546                         dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n",
 547                                 __func__, ul_dsp_clk_rate);
 548                         (void)bridge_brd_write(dev_context,
 549                                                (u8 *) &ul_dsp_clk_rate,
 550                                                ul_dsp_clk_addr, sizeof(u32), 0);
 551                 }
 552                 /*
 553                  * Enable Mailbox events and also drain any pending
 554                  * stale messages.
 555                  */
 556                 dev_context->mbox = omap_mbox_get("dsp");
 557                 if (IS_ERR(dev_context->mbox)) {
 558                         dev_context->mbox = NULL;
 559                         pr_err("%s: Failed to get dsp mailbox handle\n",
 560                                                                 __func__);
 561                         status = -EPERM;
 562                 }
 563
 564         }
 565         if (!status) {
 566                 dev_context->mbox->rxq->callback = (int (*)(void *))io_mbox_msg;
 567
 568 /*PM_IVA2GRPSEL_PER = 0xC0;*/
 569                 temp = readl(resources->dw_per_pm_base + 0xA8);
 570                 temp = (temp & 0xFFFFFF30) | 0xC0;
 571                 writel(temp, resources->dw_per_pm_base + 0xA8);
 572
 573 /*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */
 574                 temp = readl(resources->dw_per_pm_base + 0xA4);
 575                 temp = (temp & 0xFFFFFF3F);
 576                 writel(temp, resources->dw_per_pm_base + 0xA4);
 577 /*CM_SLEEPDEP_PER |= 0x04; */
 578                 temp = readl(resources->dw_per_base + 0x44);
 579                 temp = (temp & 0xFFFFFFFB) | 0x04;
 580                 writel(temp, resources->dw_per_base + 0x44);
 581
 582 /*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */
 583                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO,
 584                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 585
 586                 /* Let DSP go */
 587                 dev_dbg(bridge, "%s Unreset\n", __func__);
 588                 /* Enable DSP MMU Interrupts */
 589                 hw_mmu_event_enable(resources->dw_dmmu_base,
 590                                     HW_MMU_ALL_INTERRUPTS);
 591                 /* release the RST1, DSP starts executing now .. */
 592                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
 593                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 594
 595                 dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", dw_sync_addr);
 596                 dev_dbg(bridge, "DSP c_int00 Address =  0x%x\n", dsp_addr);
 597                 if (dsp_debug)
 598                         while (__raw_readw(dw_sync_addr))
 599                                 ;
 600
 601                 /* Wait for DSP to clear word in shared memory */
 602                 /* Read the Location */
 603                 if (!wait_for_start(dev_context, dw_sync_addr))
 604                         status = -ETIMEDOUT;
 605
 606                 /* Start wdt */
 607                 dsp_wdt_sm_set((void *)ul_shm_base);
 608                 dsp_wdt_enable(true);
 609
 610                 status = dev_get_io_mgr(dev_context->hdev_obj, &hio_mgr);
 611                 if (hio_mgr) {
 612                         io_sh_msetting(hio_mgr, SHM_OPPINFO, NULL);
 613                         /* Write the synchronization bit to indicate the
 614                          * completion of OPP table update to DSP
 615                          */
 616                         __raw_writel(0XCAFECAFE, dw_sync_addr);
 617
 618                         /* update board state */
 619                         dev_context->dw_brd_state = BRD_RUNNING;
 620                         /* (void)chnlsm_enable_interrupt(dev_context); */
 621                 } else {
 622                         dev_context->dw_brd_state = BRD_UNKNOWN;
 623                 }
 624         }
 625         return status;
 626 }
 627
 628 /*
 629  *  ======== bridge_brd_stop ========
 630  *  purpose:
 631  *      Puts DSP in self loop.
 632  *
 633  *  Preconditions :
 634  *  a) None
 635  */
 636 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
 637 {
 638         int status = 0;
 639         struct bridge_dev_context *dev_context = dev_ctxt;
 640         struct pg_table_attrs *pt_attrs;
 641         u32 dsp_pwr_state;
 642         struct omap_dsp_platform_data *pdata =
 643                 omap_dspbridge_dev->dev.platform_data;
 644
 645         if (dev_context->dw_brd_state == BRD_STOPPED)
 646                 return status;
 647
 648         /* as per TRM, it is advised to first drive the IVA2 to 'Standby' mode,
 649          * before turning off the clocks.. This is to ensure that there are no
 650          * pending L3 or other transactons from IVA2 */
 651         dsp_pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
 652                                         OMAP_POWERSTATEST_MASK;
 653         if (dsp_pwr_state != PWRDM_POWER_OFF) {
 654                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
 655                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 656                 sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE);
 657                 mdelay(10);
 658
 659                 /* IVA2 is not in OFF state */
 660                 /* Set PM_PWSTCTRL_IVA2  to OFF */
 661                 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
 662                         PWRDM_POWER_OFF, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
 663                 /* Set the SW supervised state transition for Sleep */
 664                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP,
 665                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 666         }
 667         udelay(10);
 668         /* Release the Ext Base virtual Address as the next DSP Program
 669          * may have a different load address */
 670         if (dev_context->dw_dsp_ext_base_addr)
 671                 dev_context->dw_dsp_ext_base_addr = 0;
 672
 673         dev_context->dw_brd_state = BRD_STOPPED;        /* update board state */
 674
 675         dsp_wdt_enable(false);
 676
 677         /* This is a good place to clear the MMU page tables as well */
 678         if (dev_context->pt_attrs) {
 679                 pt_attrs = dev_context->pt_attrs;
 680                 memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size);
 681                 memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size);
 682                 memset((u8 *) pt_attrs->pg_info, 0x00,
 683                        (pt_attrs->l2_num_pages * sizeof(struct page_info)));
 684         }
 685         /* Disable the mailbox interrupts */
 686         if (dev_context->mbox) {
 687                 omap_mbox_disable_irq(dev_context->mbox, IRQ_RX);
 688                 omap_mbox_put(dev_context->mbox);
 689                 dev_context->mbox = NULL;
 690         }
 691         /* Reset IVA2 clocks*/
 692         (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK |
 693                         OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 694
 695         dsp_clock_disable_all(dev_context->dsp_per_clks);
 696         dsp_clk_disable(DSP_CLK_IVA2);
 697
 698         return status;
 699 }
 700
 701 /*
 702  *  ======== bridge_brd_status ========
 703  *      Returns the board status.
 704  */
 705 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
 706                                     int *board_state)
 707 {
 708         struct bridge_dev_context *dev_context = dev_ctxt;
 709         *board_state = dev_context->dw_brd_state;
 710         return 0;
 711 }
 712
 713 /*
 714  *  ======== bridge_brd_write ========
 715  *      Copies the buffers to DSP internal or external memory.
 716  */
 717 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
 718                                    u8 *host_buff, u32 dsp_addr,
 719                                    u32 ul_num_bytes, u32 mem_type)
 720 {
 721         int status = 0;
 722         struct bridge_dev_context *dev_context = dev_ctxt;
 723
 724         if (dsp_addr < dev_context->dw_dsp_start_add) {
 725                 status = -EPERM;
 726                 return status;
 727         }
 728         if ((dsp_addr - dev_context->dw_dsp_start_add) <
 729             dev_context->dw_internal_size) {
 730                 status = write_dsp_data(dev_ctxt, host_buff, dsp_addr,
 731                                         ul_num_bytes, mem_type);
 732         } else {
 733                 status = write_ext_dsp_data(dev_context, host_buff, dsp_addr,
 734                                             ul_num_bytes, mem_type, false);
 735         }
 736
 737         return status;
 738 }
 739
 740 /*
 741  *  ======== bridge_dev_create ========
 742  *      Creates a driver object. Puts DSP in self loop.
 743  */
 744 static int bridge_dev_create(struct bridge_dev_context
 745                                         **dev_cntxt,
 746                                         struct dev_object *hdev_obj,
 747                                         struct cfg_hostres *config_param)
 748 {
 749         int status = 0;
 750         struct bridge_dev_context *dev_context = NULL;
 751         s32 entry_ndx;
 752         struct cfg_hostres *resources = config_param;
 753         struct pg_table_attrs *pt_attrs;
 754         u32 pg_tbl_pa;
 755         u32 pg_tbl_va;
 756         u32 align_size;
 757         struct drv_data *drv_datap = dev_get_drvdata(bridge);
 758
 759         /* Allocate and initialize a data structure to contain the bridge driver
 760          *  state, which becomes the context for later calls into this driver */
 761         dev_context = kzalloc(sizeof(struct bridge_dev_context), GFP_KERNEL);
 762         if (!dev_context) {
 763                 status = -ENOMEM;
 764                 goto func_end;
 765         }
 766
 767         dev_context->dw_dsp_start_add = (u32) OMAP_GEM_BASE;
 768         dev_context->dw_self_loop = (u32) NULL;
 769         dev_context->dsp_per_clks = 0;
 770         dev_context->dw_internal_size = OMAP_DSP_SIZE;
 771         /*  Clear dev context MMU table entries.
 772          *  These get set on bridge_io_on_loaded() call after program loaded. */
 773         for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; entry_ndx++) {
 774                 dev_context->atlb_entry[entry_ndx].ul_gpp_pa =
 775                     dev_context->atlb_entry[entry_ndx].ul_dsp_va = 0;
 776         }
 777         dev_context->dw_dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)
 778                                                                  (config_param->
 779                                                                   dw_mem_base
 780                                                                   [3]),
 781                                                                  config_param->
 782                                                                  dw_mem_length
 783                                                                  [3]);
 784         if (!dev_context->dw_dsp_base_addr)
 785                 status = -EPERM;
 786
 787         pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
 788         if (pt_attrs != NULL) {
 789                 /* Assuming that we use only DSP's memory map
 790                  * until 0x4000:0000 , we would need only 1024
 791                  * L1 enties i.e L1 size = 4K */
 792                 pt_attrs->l1_size = 0x1000;
 793                 align_size = pt_attrs->l1_size;
 794                 /* Align sizes are expected to be power of 2 */
 795                 /* we like to get aligned on L1 table size */
 796                 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l1_size,
 797                                                      align_size, &pg_tbl_pa);
 798
 799                 /* Check if the PA is aligned for us */
 800                 if ((pg_tbl_pa) & (align_size - 1)) {
 801                         /* PA not aligned to page table size ,
 802                          * try with more allocation and align */
 803                         mem_free_phys_mem((void *)pg_tbl_va, pg_tbl_pa,
 804                                           pt_attrs->l1_size);
 805                         /* we like to get aligned on L1 table size */
 806                         pg_tbl_va =
 807                             (u32) mem_alloc_phys_mem((pt_attrs->l1_size) * 2,
 808                                                      align_size, &pg_tbl_pa);
 809                         /* We should be able to get aligned table now */
 810                         pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
 811                         pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
 812                         pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size * 2;
 813                         /* Align the PA to the next 'align'  boundary */
 814                         pt_attrs->l1_base_pa =
 815                             ((pg_tbl_pa) +
 816                              (align_size - 1)) & (~(align_size - 1));
 817                         pt_attrs->l1_base_va =
 818                             pg_tbl_va + (pt_attrs->l1_base_pa - pg_tbl_pa);
 819                 } else {
 820                         /* We got aligned PA, cool */
 821                         pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
 822                         pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
 823                         pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size;
 824                         pt_attrs->l1_base_pa = pg_tbl_pa;
 825                         pt_attrs->l1_base_va = pg_tbl_va;
 826                 }
 827                 if (pt_attrs->l1_base_va)
 828                         memset((u8 *) pt_attrs->l1_base_va, 0x00,
 829                                pt_attrs->l1_size);
 830
 831                 /* number of L2 page tables = DMM pool used + SHMMEM +EXTMEM +
 832                  * L4 pages */
 833                 pt_attrs->l2_num_pages = ((DMMPOOLSIZE >> 20) + 6);
 834                 pt_attrs->l2_size = HW_MMU_COARSE_PAGE_SIZE *
 835                     pt_attrs->l2_num_pages;
 836                 align_size = 4; /* Make it u32 aligned */
 837                 /* we like to get aligned on L1 table size */
 838                 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l2_size,
 839                                                      align_size, &pg_tbl_pa);
 840                 pt_attrs->l2_tbl_alloc_pa = pg_tbl_pa;
 841                 pt_attrs->l2_tbl_alloc_va = pg_tbl_va;
 842                 pt_attrs->l2_tbl_alloc_sz = pt_attrs->l2_size;
 843                 pt_attrs->l2_base_pa = pg_tbl_pa;
 844                 pt_attrs->l2_base_va = pg_tbl_va;
 845
 846                 if (pt_attrs->l2_base_va)
 847                         memset((u8 *) pt_attrs->l2_base_va, 0x00,
 848                                pt_attrs->l2_size);
 849
 850                 pt_attrs->pg_info = kzalloc(pt_attrs->l2_num_pages *
 851                                         sizeof(struct page_info), GFP_KERNEL);
 852                 dev_dbg(bridge,
 853                         "L1 pa %x, va %x, size %x\n L2 pa %x, va "
 854                         "%x, size %x\n", pt_attrs->l1_base_pa,
 855                         pt_attrs->l1_base_va, pt_attrs->l1_size,
 856                         pt_attrs->l2_base_pa, pt_attrs->l2_base_va,
 857                         pt_attrs->l2_size);
 858                 dev_dbg(bridge, "pt_attrs %p L2 NumPages %x pg_info %p\n",
 859                         pt_attrs, pt_attrs->l2_num_pages, pt_attrs->pg_info);
 860         }
 861         if ((pt_attrs != NULL) && (pt_attrs->l1_base_va != 0) &&
 862             (pt_attrs->l2_base_va != 0) && (pt_attrs->pg_info != NULL))
 863                 dev_context->pt_attrs = pt_attrs;
 864         else
 865                 status = -ENOMEM;
 866
 867         if (!status) {
 868                 spin_lock_init(&pt_attrs->pg_lock);
 869                 dev_context->tc_word_swap_on = drv_datap->tc_wordswapon;
 870
 871                 /* Set the Clock Divisor for the DSP module */
 872                 udelay(5);
 873                 /* MMU address is obtained from the host
 874                  * resources struct */
 875                 dev_context->dw_dsp_mmu_base = resources->dw_dmmu_base;
 876         }
 877         if (!status) {
 878                 dev_context->hdev_obj = hdev_obj;
 879                 /* Store current board state. */
 880                 dev_context->dw_brd_state = BRD_UNKNOWN;
 881                 dev_context->resources = resources;
 882                 dsp_clk_enable(DSP_CLK_IVA2);
 883                 bridge_brd_stop(dev_context);
 884                 /* Return ptr to our device state to the DSP API for storage */
 885                 *dev_cntxt = dev_context;
 886         } else {
 887                 if (pt_attrs != NULL) {
 888                         kfree(pt_attrs->pg_info);
 889
 890                         if (pt_attrs->l2_tbl_alloc_va) {
 891                                 mem_free_phys_mem((void *)
 892                                                   pt_attrs->l2_tbl_alloc_va,
 893                                                   pt_attrs->l2_tbl_alloc_pa,
 894                                                   pt_attrs->l2_tbl_alloc_sz);
 895                         }
 896                         if (pt_attrs->l1_tbl_alloc_va) {
 897                                 mem_free_phys_mem((void *)
 898                                                   pt_attrs->l1_tbl_alloc_va,
 899                                                   pt_attrs->l1_tbl_alloc_pa,
 900                                                   pt_attrs->l1_tbl_alloc_sz);
 901                         }
 902                 }
 903                 kfree(pt_attrs);
 904                 kfree(dev_context);
 905         }
 906 func_end:
 907         return status;
 908 }
 909
 910 /*
 911  *  ======== bridge_dev_ctrl ========
 912  *      Receives device specific commands.
 913  */
 914 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
 915                                   u32 dw_cmd, void *pargs)
 916 {
 917         int status = 0;
 918         struct bridge_ioctl_extproc *pa_ext_proc =
 919                                         (struct bridge_ioctl_extproc *)pargs;
 920         s32 ndx;
 921
 922         switch (dw_cmd) {
 923         case BRDIOCTL_CHNLREAD:
 924                 break;
 925         case BRDIOCTL_CHNLWRITE:
 926                 break;
 927         case BRDIOCTL_SETMMUCONFIG:
 928                 /* store away dsp-mmu setup values for later use */
 929                 for (ndx = 0; ndx < BRDIOCTL_NUMOFMMUTLB; ndx++, pa_ext_proc++)
 930                         dev_context->atlb_entry[ndx] = *pa_ext_proc;
 931                 break;
 932         case BRDIOCTL_DEEPSLEEP:
 933         case BRDIOCTL_EMERGENCYSLEEP:
 934                 /* Currently only DSP Idle is supported Need to update for
 935                  * later releases */
 936                 status = sleep_dsp(dev_context, PWR_DEEPSLEEP, pargs);
 937                 break;
 938         case BRDIOCTL_WAKEUP:
 939                 status = wake_dsp(dev_context, pargs);
 940                 break;
 941         case BRDIOCTL_CLK_CTRL:
 942                 status = 0;
 943                 /* Looking For Baseport Fix for Clocks */
 944                 status = dsp_peripheral_clk_ctrl(dev_context, pargs);
 945                 break;
 946         case BRDIOCTL_PWR_HIBERNATE:
 947                 status = handle_hibernation_from_dsp(dev_context);
 948                 break;
 949         case BRDIOCTL_PRESCALE_NOTIFY:
 950                 status = pre_scale_dsp(dev_context, pargs);
 951                 break;
 952         case BRDIOCTL_POSTSCALE_NOTIFY:
 953                 status = post_scale_dsp(dev_context, pargs);
 954                 break;
 955         case BRDIOCTL_CONSTRAINT_REQUEST:
 956                 status = handle_constraints_set(dev_context, pargs);
 957                 break;
 958         default:
 959                 status = -EPERM;
 960                 break;
 961         }
 962         return status;
 963 }
 964
 965 /*
 966  *  ======== bridge_dev_destroy ========
 967  *      Destroys the driver object.
 968  */
 969 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
 970 {
 971         struct pg_table_attrs *pt_attrs;
 972         int status = 0;
 973         struct bridge_dev_context *dev_context = (struct bridge_dev_context *)
 974             dev_ctxt;
 975         struct cfg_hostres *host_res;
 976         u32 shm_size;
 977         struct drv_data *drv_datap = dev_get_drvdata(bridge);
 978
 979         /* It should never happen */
 980         if (!dev_ctxt)
 981                 return -EFAULT;
 982
 983         /* first put the device to stop state */
 984         bridge_brd_stop(dev_context);
 985         if (dev_context->pt_attrs) {
 986                 pt_attrs = dev_context->pt_attrs;
 987                 kfree(pt_attrs->pg_info);
 988
 989                 if (pt_attrs->l2_tbl_alloc_va) {
 990                         mem_free_phys_mem((void *)pt_attrs->l2_tbl_alloc_va,
 991                                           pt_attrs->l2_tbl_alloc_pa,
 992                                           pt_attrs->l2_tbl_alloc_sz);
 993                 }
 994                 if (pt_attrs->l1_tbl_alloc_va) {
 995                         mem_free_phys_mem((void *)pt_attrs->l1_tbl_alloc_va,
 996                                           pt_attrs->l1_tbl_alloc_pa,
 997                                           pt_attrs->l1_tbl_alloc_sz);
 998                 }
 999                 kfree(pt_attrs);
1000
1001         }
1002
1003         if (dev_context->resources) {
1004                 host_res = dev_context->resources;
1005                 shm_size = drv_datap->shm_size;
1006                 if (shm_size >= 0x10000) {
1007                         if ((host_res->dw_mem_base[1]) &&
1008                             (host_res->dw_mem_phys[1])) {
1009                                 mem_free_phys_mem((void *)
1010                                                   host_res->dw_mem_base
1011                                                   [1],
1012                                                   host_res->dw_mem_phys
1013                                                   [1], shm_size);
1014                         }
1015                 } else {
1016                         dev_dbg(bridge, "%s: Error getting shm size "
1017                                 "from registry: %x. Not calling "
1018                                 "mem_free_phys_mem\n", __func__,
1019                                 status);
1020                 }
1021                 host_res->dw_mem_base[1] = 0;
1022                 host_res->dw_mem_phys[1] = 0;
1023
1024                 if (host_res->dw_mem_base[0])
1025                         iounmap((void *)host_res->dw_mem_base[0]);
1026                 if (host_res->dw_mem_base[2])
1027                         iounmap((void *)host_res->dw_mem_base[2]);
1028                 if (host_res->dw_mem_base[3])
1029                         iounmap((void *)host_res->dw_mem_base[3]);
1030                 if (host_res->dw_mem_base[4])
1031                         iounmap((void *)host_res->dw_mem_base[4]);
1032                 if (host_res->dw_dmmu_base)
1033                         iounmap(host_res->dw_dmmu_base);
1034                 if (host_res->dw_per_base)
1035                         iounmap(host_res->dw_per_base);
1036                 if (host_res->dw_per_pm_base)
1037                         iounmap((void *)host_res->dw_per_pm_base);
1038                 if (host_res->dw_core_pm_base)
1039                         iounmap((void *)host_res->dw_core_pm_base);
1040                 if (host_res->dw_sys_ctrl_base)
1041                         iounmap(host_res->dw_sys_ctrl_base);
1042
1043                 host_res->dw_mem_base[0] = (u32) NULL;
1044                 host_res->dw_mem_base[2] = (u32) NULL;
1045                 host_res->dw_mem_base[3] = (u32) NULL;
1046                 host_res->dw_mem_base[4] = (u32) NULL;
1047                 host_res->dw_dmmu_base = NULL;
1048                 host_res->dw_sys_ctrl_base = NULL;
1049
1050                 kfree(host_res);
1051         }
1052
1053         /* Free the driver's device context: */
1054         kfree(drv_datap->base_img);
1055         kfree(drv_datap);
1056         dev_set_drvdata(bridge, NULL);
1057         kfree((void *)dev_ctxt);
1058         return status;
1059 }
1060
1061 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
1062                                    u32 dsp_dest_addr, u32 dsp_src_addr,
1063                                    u32 ul_num_bytes, u32 mem_type)
1064 {
1065         int status = 0;
1066         u32 src_addr = dsp_src_addr;
1067         u32 dest_addr = dsp_dest_addr;
1068         u32 copy_bytes = 0;
1069         u32 total_bytes = ul_num_bytes;
1070         u8 host_buf[BUFFERSIZE];
1071         struct bridge_dev_context *dev_context = dev_ctxt;
1072         while (total_bytes > 0 && !status) {
1073                 copy_bytes =
1074                     total_bytes > BUFFERSIZE ? BUFFERSIZE : total_bytes;
1075                 /* Read from External memory */
1076                 status = read_ext_dsp_data(dev_ctxt, host_buf, src_addr,
1077                                            copy_bytes, mem_type);
1078                 if (!status) {
1079                         if (dest_addr < (dev_context->dw_dsp_start_add +
1080                                          dev_context->dw_internal_size)) {
1081                                 /* Write to Internal memory */
1082                                 status = write_dsp_data(dev_ctxt, host_buf,
1083                                                         dest_addr, copy_bytes,
1084                                                         mem_type);
1085                         } else {
1086                                 /* Write to External memory */
1087                                 status =
1088                                     write_ext_dsp_data(dev_ctxt, host_buf,
1089                                                        dest_addr, copy_bytes,
1090                                                        mem_type, false);
1091                         }
1092                 }
1093                 total_bytes -= copy_bytes;
1094                 src_addr += copy_bytes;
1095                 dest_addr += copy_bytes;
1096         }
1097         return status;
1098 }
1099
1100 /* Mem Write does not halt the DSP to write unlike bridge_brd_write */
1101 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
1102                                     u8 *host_buff, u32 dsp_addr,
1103                                     u32 ul_num_bytes, u32 mem_type)
1104 {
1105         int status = 0;
1106         struct bridge_dev_context *dev_context = dev_ctxt;
1107         u32 ul_remain_bytes = 0;
1108         u32 ul_bytes = 0;
1109         ul_remain_bytes = ul_num_bytes;
1110         while (ul_remain_bytes > 0 && !status) {
1111                 ul_bytes =
1112                     ul_remain_bytes > BUFFERSIZE ? BUFFERSIZE : ul_remain_bytes;
1113                 if (dsp_addr < (dev_context->dw_dsp_start_add +
1114                                  dev_context->dw_internal_size)) {
1115                         status =
1116                             write_dsp_data(dev_ctxt, host_buff, dsp_addr,
1117                                            ul_bytes, mem_type);
1118                 } else {
1119                         status = write_ext_dsp_data(dev_ctxt, host_buff,
1120                                                     dsp_addr, ul_bytes,
1121                                                     mem_type, true);
1122                 }
1123                 ul_remain_bytes -= ul_bytes;
1124                 dsp_addr += ul_bytes;
1125                 host_buff = host_buff + ul_bytes;
1126         }
1127         return status;
1128 }
1129
1130 /*
1131  *  ======== bridge_brd_mem_map ========
1132  *      This function maps MPU buffer to the DSP address space. It performs
1133  *  linear to physical address translation if required. It translates each
1134  *  page since linear addresses can be physically non-contiguous
1135  *  All address & size arguments are assumed to be page aligned (in proc.c)
1136  *
1137  *  TODO: Disable MMU while updating the page tables (but that'll stall DSP)
1138  */
1139 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
1140                                   u32 ul_mpu_addr, u32 virt_addr,
1141                                   u32 ul_num_bytes, u32 ul_map_attr,
1142                                   struct page **mapped_pages)
1143 {
1144         u32 attrs;
1145         int status = 0;
1146         struct bridge_dev_context *dev_context = dev_ctxt;
1147         struct hw_mmu_map_attrs_t hw_attrs;
1148         struct vm_area_struct *vma;
1149         struct mm_struct *mm = current->mm;
1150         u32 write = 0;
1151         u32 num_usr_pgs = 0;
1152         struct page *mapped_page, *pg;
1153         s32 pg_num;
1154         u32 va = virt_addr;
1155         struct task_struct *curr_task = current;
1156         u32 pg_i = 0;
1157         u32 mpu_addr, pa;
1158
1159         dev_dbg(bridge,
1160                 "%s hDevCtxt %p, pa %x, va %x, size %x, ul_map_attr %x\n",
1161                 __func__, dev_ctxt, ul_mpu_addr, virt_addr, ul_num_bytes,
1162                 ul_map_attr);
1163         if (ul_num_bytes == 0)
1164                 return -EINVAL;
1165
1166         if (ul_map_attr & DSP_MAP_DIR_MASK) {
1167                 attrs = ul_map_attr;
1168         } else {
1169                 /* Assign default attributes */
1170                 attrs = ul_map_attr | (DSP_MAPVIRTUALADDR | DSP_MAPELEMSIZE16);
1171         }
1172         /* Take mapping properties */
1173         if (attrs & DSP_MAPBIGENDIAN)
1174                 hw_attrs.endianism = HW_BIG_ENDIAN;
1175         else
1176                 hw_attrs.endianism = HW_LITTLE_ENDIAN;
1177
1178         hw_attrs.mixed_size = (enum hw_mmu_mixed_size_t)
1179             ((attrs & DSP_MAPMIXEDELEMSIZE) >> 2);
1180         /* Ignore element_size if mixed_size is enabled */
1181         if (hw_attrs.mixed_size == 0) {
1182                 if (attrs & DSP_MAPELEMSIZE8) {
1183                         /* Size is 8 bit */
1184                         hw_attrs.element_size = HW_ELEM_SIZE8BIT;
1185                 } else if (attrs & DSP_MAPELEMSIZE16) {
1186                         /* Size is 16 bit */
1187                         hw_attrs.element_size = HW_ELEM_SIZE16BIT;
1188                 } else if (attrs & DSP_MAPELEMSIZE32) {
1189                         /* Size is 32 bit */
1190                         hw_attrs.element_size = HW_ELEM_SIZE32BIT;
1191                 } else if (attrs & DSP_MAPELEMSIZE64) {
1192                         /* Size is 64 bit */
1193                         hw_attrs.element_size = HW_ELEM_SIZE64BIT;
1194                 } else {
1195                         /*
1196                          * Mixedsize isn't enabled, so size can't be
1197                          * zero here
1198                          */
1199                         return -EINVAL;
1200                 }
1201         }
1202         if (attrs & DSP_MAPDONOTLOCK)
1203                 hw_attrs.donotlockmpupage = 1;
1204         else
1205                 hw_attrs.donotlockmpupage = 0;
1206
1207         if (attrs & DSP_MAPVMALLOCADDR) {
1208                 return mem_map_vmalloc(dev_ctxt, ul_mpu_addr, virt_addr,
1209                                        ul_num_bytes, &hw_attrs);
1210         }
1211         /*
1212          * Do OS-specific user-va to pa translation.
1213          * Combine physically contiguous regions to reduce TLBs.
1214          * Pass the translated pa to pte_update.
1215          */
1216         if ((attrs & DSP_MAPPHYSICALADDR)) {
1217                 status = pte_update(dev_context, ul_mpu_addr, virt_addr,
1218                                     ul_num_bytes, &hw_attrs);
1219                 goto func_cont;
1220         }
1221
1222         /*
1223          * Important Note: ul_mpu_addr is mapped from user application process
1224          * to current process - it must lie completely within the current
1225          * virtual memory address space in order to be of use to us here!
1226          */
1227         down_read(&mm->mmap_sem);
1228         vma = find_vma(mm, ul_mpu_addr);
1229         if (vma)
1230                 dev_dbg(bridge,
1231                         "VMAfor UserBuf: ul_mpu_addr=%x, ul_num_bytes=%x, "
1232                         "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1233                         ul_num_bytes, vma->vm_start, vma->vm_end,
1234                         vma->vm_flags);
1235
1236         /*
1237          * It is observed that under some circumstances, the user buffer is
1238          * spread across several VMAs. So loop through and check if the entire
1239          * user buffer is covered
1240          */
1241         while ((vma) && (ul_mpu_addr + ul_num_bytes > vma->vm_end)) {
1242                 /* jump to the next VMA region */
1243                 vma = find_vma(mm, vma->vm_end + 1);
1244                 dev_dbg(bridge,
1245                         "VMA for UserBuf ul_mpu_addr=%x ul_num_bytes=%x, "
1246                         "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1247                         ul_num_bytes, vma->vm_start, vma->vm_end,
1248                         vma->vm_flags);
1249         }
1250         if (!vma) {
1251                 pr_err("%s: Failed to get VMA region for 0x%x (%d)\n",
1252                        __func__, ul_mpu_addr, ul_num_bytes);
1253                 status = -EINVAL;
1254                 up_read(&mm->mmap_sem);
1255                 goto func_cont;
1256         }
1257
1258         if (vma->vm_flags & VM_IO) {
1259                 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1260                 mpu_addr = ul_mpu_addr;
1261
1262                 /* Get the physical addresses for user buffer */
1263                 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1264                         pa = user_va2_pa(mm, mpu_addr);
1265                         if (!pa) {
1266                                 status = -EPERM;
1267                                 pr_err("DSPBRIDGE: VM_IO mapping physical"
1268                                        "address is invalid\n");
1269                                 break;
1270                         }
1271                         if (pfn_valid(__phys_to_pfn(pa))) {
1272                                 pg = PHYS_TO_PAGE(pa);
1273                                 get_page(pg);
1274                                 if (page_count(pg) < 1) {
1275                                         pr_err("Bad page in VM_IO buffer\n");
1276                                         bad_page_dump(pa, pg);
1277                                 }
1278                         }
1279                         status = pte_set(dev_context->pt_attrs, pa,
1280                                          va, HW_PAGE_SIZE4KB, &hw_attrs);
1281                         if (status)
1282                                 break;
1283
1284                         va += HW_PAGE_SIZE4KB;
1285                         mpu_addr += HW_PAGE_SIZE4KB;
1286                         pa += HW_PAGE_SIZE4KB;
1287                 }
1288         } else {
1289                 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1290                 if (vma->vm_flags & (VM_WRITE | VM_MAYWRITE))
1291                         write = 1;
1292
1293                 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1294                         pg_num = get_user_pages(curr_task, mm, ul_mpu_addr, 1,
1295                                                 write, 1, &mapped_page, NULL);
1296                         if (pg_num > 0) {
1297                                 if (page_count(mapped_page) < 1) {
1298                                         pr_err("Bad page count after doing"
1299                                                "get_user_pages on"
1300                                                "user buffer\n");
1301                                         bad_page_dump(page_to_phys(mapped_page),
1302                                                       mapped_page);
1303                                 }
1304                                 status = pte_set(dev_context->pt_attrs,
1305                                                  page_to_phys(mapped_page), va,
1306                                                  HW_PAGE_SIZE4KB, &hw_attrs);
1307                                 if (status)
1308                                         break;
1309
1310                                 if (mapped_pages)
1311                                         mapped_pages[pg_i] = mapped_page;
1312
1313                                 va += HW_PAGE_SIZE4KB;
1314                                 ul_mpu_addr += HW_PAGE_SIZE4KB;
1315                         } else {
1316                                 pr_err("DSPBRIDGE: get_user_pages FAILED,"
1317                                        "MPU addr = 0x%x,"
1318                                        "vma->vm_flags = 0x%lx,"
1319                                        "get_user_pages Err"
1320                                        "Value = %d, Buffer"
1321                                        "size=0x%x\n", ul_mpu_addr,
1322                                        vma->vm_flags, pg_num, ul_num_bytes);
1323                                 status = -EPERM;
1324                                 break;
1325                         }
1326                 }
1327         }
1328         up_read(&mm->mmap_sem);
1329 func_cont:
1330         if (status) {
1331                 /*
1332                  * Roll out the mapped pages incase it failed in middle of
1333                  * mapping
1334                  */
1335                 if (pg_i) {
1336                         bridge_brd_mem_un_map(dev_context, virt_addr,
1337                                            (pg_i * PG_SIZE4K));
1338                 }
1339                 status = -EPERM;
1340         }
1341         /*
1342          * In any case, flush the TLB
1343          * This is called from here instead from pte_update to avoid unnecessary
1344          * repetition while mapping non-contiguous physical regions of a virtual
1345          * region
1346          */
1347         flush_all(dev_context);
1348         dev_dbg(bridge, "%s status %x\n", __func__, status);
1349         return status;
1350 }
1351
1352 /*
1353  *  ======== bridge_brd_mem_un_map ========
1354  *      Invalidate the PTEs for the DSP VA block to be unmapped.
1355  *
1356  *      PTEs of a mapped memory block are contiguous in any page table
1357  *      So, instead of looking up the PTE address for every 4K block,
1358  *      we clear consecutive PTEs until we unmap all the bytes
1359  */
1360 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
1361                                      u32 virt_addr, u32 ul_num_bytes)
1362 {
1363         u32 l1_base_va;
1364         u32 l2_base_va;
1365         u32 l2_base_pa;
1366         u32 l2_page_num;
1367         u32 pte_val;
1368         u32 pte_size;
1369         u32 pte_count;
1370         u32 pte_addr_l1;
1371         u32 pte_addr_l2 = 0;
1372         u32 rem_bytes;
1373         u32 rem_bytes_l2;
1374         u32 va_curr;
1375         struct page *pg = NULL;
1376         int status = 0;
1377         struct bridge_dev_context *dev_context = dev_ctxt;
1378         struct pg_table_attrs *pt = dev_context->pt_attrs;
1379         u32 temp;
1380         u32 paddr;
1381         u32 numof4k_pages = 0;
1382
1383         va_curr = virt_addr;
1384         rem_bytes = ul_num_bytes;
1385         rem_bytes_l2 = 0;
1386         l1_base_va = pt->l1_base_va;
1387         pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1388         dev_dbg(bridge, "%s dev_ctxt %p, va %x, NumBytes %x l1_base_va %x, "
1389                 "pte_addr_l1 %x\n", __func__, dev_ctxt, virt_addr,
1390                 ul_num_bytes, l1_base_va, pte_addr_l1);
1391
1392         while (rem_bytes && !status) {
1393                 u32 va_curr_orig = va_curr;
1394                 /* Find whether the L1 PTE points to a valid L2 PT */
1395                 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1396                 pte_val = *(u32 *) pte_addr_l1;
1397                 pte_size = hw_mmu_pte_size_l1(pte_val);
1398
1399                 if (pte_size != HW_MMU_COARSE_PAGE_SIZE)
1400                         goto skip_coarse_page;
1401
1402                 /*
1403                  * Get the L2 PA from the L1 PTE, and find
1404                  * corresponding L2 VA
1405                  */
1406                 l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1407                 l2_base_va = l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1408                 l2_page_num =
1409                     (l2_base_pa - pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1410                 /*
1411                  * Find the L2 PTE address from which we will start
1412                  * clearing, the number of PTEs to be cleared on this
1413                  * page, and the size of VA space that needs to be
1414                  * cleared on this L2 page
1415                  */
1416                 pte_addr_l2 = hw_mmu_pte_addr_l2(l2_base_va, va_curr);
1417                 pte_count = pte_addr_l2 & (HW_MMU_COARSE_PAGE_SIZE - 1);
1418                 pte_count = (HW_MMU_COARSE_PAGE_SIZE - pte_count) / sizeof(u32);
1419                 if (rem_bytes < (pte_count * PG_SIZE4K))
1420                         pte_count = rem_bytes / PG_SIZE4K;
1421                 rem_bytes_l2 = pte_count * PG_SIZE4K;
1422
1423                 /*
1424                  * Unmap the VA space on this L2 PT. A quicker way
1425                  * would be to clear pte_count entries starting from
1426                  * pte_addr_l2. However, below code checks that we don't
1427                  * clear invalid entries or less than 64KB for a 64KB
1428                  * entry. Similar checking is done for L1 PTEs too
1429                  * below
1430                  */
1431                 while (rem_bytes_l2 && !status) {
1432                         pte_val = *(u32 *) pte_addr_l2;
1433                         pte_size = hw_mmu_pte_size_l2(pte_val);
1434                         /* va_curr aligned to pte_size? */
1435                         if (pte_size == 0 || rem_bytes_l2 < pte_size ||
1436                             va_curr & (pte_size - 1)) {
1437                                 status = -EPERM;
1438                                 break;
1439                         }
1440
1441                         /* Collect Physical addresses from VA */
1442                         paddr = (pte_val & ~(pte_size - 1));
1443                         if (pte_size == HW_PAGE_SIZE64KB)
1444                                 numof4k_pages = 16;
1445                         else
1446                                 numof4k_pages = 1;
1447                         temp = 0;
1448                         while (temp++ < numof4k_pages) {
1449                                 if (!pfn_valid(__phys_to_pfn(paddr))) {
1450                                         paddr += HW_PAGE_SIZE4KB;
1451                                         continue;
1452                                 }
1453                                 pg = PHYS_TO_PAGE(paddr);
1454                                 if (page_count(pg) < 1) {
1455                                         pr_info("DSPBRIDGE: UNMAP function: "
1456                                                 "COUNT 0 FOR PA 0x%x, size = "
1457                                                 "0x%x\n", paddr, ul_num_bytes);
1458                                         bad_page_dump(paddr, pg);
1459                                 } else {
1460                                         set_page_dirty(pg);
1461                                         page_cache_release(pg);
1462                                 }
1463                                 paddr += HW_PAGE_SIZE4KB;
1464                         }
1465                         if (hw_mmu_pte_clear(pte_addr_l2, va_curr, pte_size)) {
1466                                 status = -EPERM;
1467                                 goto EXIT_LOOP;
1468                         }
1469
1470                         status = 0;
1471                         rem_bytes_l2 -= pte_size;
1472                         va_curr += pte_size;
1473                         pte_addr_l2 += (pte_size >> 12) * sizeof(u32);
1474                 }
1475                 spin_lock(&pt->pg_lock);
1476                 if (rem_bytes_l2 == 0) {
1477                         pt->pg_info[l2_page_num].num_entries -= pte_count;
1478                         if (pt->pg_info[l2_page_num].num_entries == 0) {
1479                                 /*
1480                                  * Clear the L1 PTE pointing to the L2 PT
1481                                  */
1482                                 if (!hw_mmu_pte_clear(l1_base_va, va_curr_orig,
1483                                                      HW_MMU_COARSE_PAGE_SIZE))
1484                                         status = 0;
1485                                 else {
1486                                         status = -EPERM;
1487                                         spin_unlock(&pt->pg_lock);
1488                                         goto EXIT_LOOP;
1489                                 }
1490                         }
1491                         rem_bytes -= pte_count * PG_SIZE4K;
1492                 } else
1493                         status = -EPERM;
1494
1495                 spin_unlock(&pt->pg_lock);
1496                 continue;
1497 skip_coarse_page:
1498                 /* va_curr aligned to pte_size? */
1499                 /* pte_size = 1 MB or 16 MB */
1500                 if (pte_size == 0 || rem_bytes < pte_size ||
1501                     va_curr & (pte_size - 1)) {
1502                         status = -EPERM;
1503                         break;
1504                 }
1505
1506                 if (pte_size == HW_PAGE_SIZE1MB)
1507                         numof4k_pages = 256;
1508                 else
1509                         numof4k_pages = 4096;
1510                 temp = 0;
1511                 /* Collect Physical addresses from VA */
1512                 paddr = (pte_val & ~(pte_size - 1));
1513                 while (temp++ < numof4k_pages) {
1514                         if (pfn_valid(__phys_to_pfn(paddr))) {
1515                                 pg = PHYS_TO_PAGE(paddr);
1516                                 if (page_count(pg) < 1) {
1517                                         pr_info("DSPBRIDGE: UNMAP function: "
1518                                                 "COUNT 0 FOR PA 0x%x, size = "
1519                                                 "0x%x\n", paddr, ul_num_bytes);
1520                                         bad_page_dump(paddr, pg);
1521                                 } else {
1522                                         set_page_dirty(pg);
1523                                         page_cache_release(pg);
1524                                 }
1525                         }
1526                         paddr += HW_PAGE_SIZE4KB;
1527                 }
1528                 if (!hw_mmu_pte_clear(l1_base_va, va_curr, pte_size)) {
1529                         status = 0;
1530                         rem_bytes -= pte_size;
1531                         va_curr += pte_size;
1532                 } else {
1533                         status = -EPERM;
1534                         goto EXIT_LOOP;
1535                 }
1536         }
1537         /*
1538          * It is better to flush the TLB here, so that any stale old entries
1539          * get flushed
1540          */
1541 EXIT_LOOP:
1542         flush_all(dev_context);
1543         dev_dbg(bridge,
1544                 "%s: va_curr %x, pte_addr_l1 %x pte_addr_l2 %x rem_bytes %x,"
1545                 " rem_bytes_l2 %x status %x\n", __func__, va_curr, pte_addr_l1,
1546                 pte_addr_l2, rem_bytes, rem_bytes_l2, status);
1547         return status;
1548 }
1549
1550 /*
1551  *  ======== user_va2_pa ========
1552  *  Purpose:
1553  *      This function walks through the page tables to convert a userland
1554  *      virtual address to physical address
1555  */
1556 static u32 user_va2_pa(struct mm_struct *mm, u32 address)
1557 {
1558         pgd_t *pgd;
1559         pmd_t *pmd;
1560         pte_t *ptep, pte;
1561
1562         pgd = pgd_offset(mm, address);
1563         if (!(pgd_none(*pgd) || pgd_bad(*pgd))) {
1564                 pmd = pmd_offset(pgd, address);
1565                 if (!(pmd_none(*pmd) || pmd_bad(*pmd))) {
1566                         ptep = pte_offset_map(pmd, address);
1567                         if (ptep) {
1568                                 pte = *ptep;
1569                                 if (pte_present(pte))
1570                                         return pte & PAGE_MASK;
1571                         }
1572                 }
1573         }
1574
1575         return 0;
1576 }
1577
1578 /*
1579  *  ======== pte_update ========
1580  *      This function calculates the optimum page-aligned addresses and sizes
1581  *      Caller must pass page-aligned values
1582  */
1583 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
1584                              u32 va, u32 size,
1585                              struct hw_mmu_map_attrs_t *map_attrs)
1586 {
1587         u32 i;
1588         u32 all_bits;
1589         u32 pa_curr = pa;
1590         u32 va_curr = va;
1591         u32 num_bytes = size;
1592         struct bridge_dev_context *dev_context = dev_ctxt;
1593         int status = 0;
1594         u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB,
1595                 HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB
1596         };
1597
1598         while (num_bytes && !status) {
1599                 /* To find the max. page size with which both PA & VA are
1600                  * aligned */
1601                 all_bits = pa_curr | va_curr;
1602
1603                 for (i = 0; i < 4; i++) {
1604                         if ((num_bytes >= page_size[i]) && ((all_bits &
1605                                                              (page_size[i] -
1606                                                               1)) == 0)) {
1607                                 status =
1608                                     pte_set(dev_context->pt_attrs, pa_curr,
1609                                             va_curr, page_size[i], map_attrs);
1610                                 pa_curr += page_size[i];
1611                                 va_curr += page_size[i];
1612                                 num_bytes -= page_size[i];
1613                                 /* Don't try smaller sizes. Hopefully we have
1614                                  * reached an address aligned to a bigger page
1615                                  * size */
1616                                 break;
1617                         }
1618                 }
1619         }
1620
1621         return status;
1622 }
1623
1624 /*
1625  *  ======== pte_set ========
1626  *      This function calculates PTE address (MPU virtual) to be updated
1627  *      It also manages the L2 page tables
1628  */
1629 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
1630                           u32 size, struct hw_mmu_map_attrs_t *attrs)
1631 {
1632         u32 i;
1633         u32 pte_val;
1634         u32 pte_addr_l1;
1635         u32 pte_size;
1636         /* Base address of the PT that will be updated */
1637         u32 pg_tbl_va;
1638         u32 l1_base_va;
1639         /* Compiler warns that the next three variables might be used
1640          * uninitialized in this function. Doesn't seem so. Working around,
1641          * anyways. */
1642         u32 l2_base_va = 0;
1643         u32 l2_base_pa = 0;
1644         u32 l2_page_num = 0;
1645         int status = 0;
1646
1647         l1_base_va = pt->l1_base_va;
1648         pg_tbl_va = l1_base_va;
1649         if ((size == HW_PAGE_SIZE64KB) || (size == HW_PAGE_SIZE4KB)) {
1650                 /* Find whether the L1 PTE points to a valid L2 PT */
1651                 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va);
1652                 if (pte_addr_l1 <= (pt->l1_base_va + pt->l1_size)) {
1653                         pte_val = *(u32 *) pte_addr_l1;
1654                         pte_size = hw_mmu_pte_size_l1(pte_val);
1655                 } else {
1656                         return -EPERM;
1657                 }
1658                 spin_lock(&pt->pg_lock);
1659                 if (pte_size == HW_MMU_COARSE_PAGE_SIZE) {
1660                         /* Get the L2 PA from the L1 PTE, and find
1661                          * corresponding L2 VA */
1662                         l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1663                         l2_base_va =
1664                             l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1665                         l2_page_num =
1666                             (l2_base_pa -
1667                              pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1668                 } else if (pte_size == 0) {
1669                         /* L1 PTE is invalid. Allocate a L2 PT and
1670                          * point the L1 PTE to it */
1671                         /* Find a free L2 PT. */
1672                         for (i = 0; (i < pt->l2_num_pages) &&
1673                              (pt->pg_info[i].num_entries != 0); i++)
1674                                 ;
1675                         if (i < pt->l2_num_pages) {
1676                                 l2_page_num = i;
1677                                 l2_base_pa = pt->l2_base_pa + (l2_page_num *
1678                                                 HW_MMU_COARSE_PAGE_SIZE);
1679                                 l2_base_va = pt->l2_base_va + (l2_page_num *
1680                                                 HW_MMU_COARSE_PAGE_SIZE);
1681                                 /* Endianness attributes are ignored for
1682                                  * HW_MMU_COARSE_PAGE_SIZE */
1683                                 status =
1684                                     hw_mmu_pte_set(l1_base_va, l2_base_pa, va,
1685                                                    HW_MMU_COARSE_PAGE_SIZE,
1686                                                    attrs);
1687                         } else {
1688                                 status = -ENOMEM;
1689                         }
1690                 } else {
1691                         /* Found valid L1 PTE of another size.
1692                          * Should not overwrite it. */
1693                         status = -EPERM;
1694                 }
1695                 if (!status) {
1696                         pg_tbl_va = l2_base_va;
1697                         if (size == HW_PAGE_SIZE64KB)
1698                                 pt->pg_info[l2_page_num].num_entries += 16;
1699                         else
1700                                 pt->pg_info[l2_page_num].num_entries++;
1701                         dev_dbg(bridge, "PTE: L2 BaseVa %x, BasePa %x, PageNum "
1702                                 "%x, num_entries %x\n", l2_base_va,
1703                                 l2_base_pa, l2_page_num,
1704                                 pt->pg_info[l2_page_num].num_entries);
1705                 }
1706                 spin_unlock(&pt->pg_lock);
1707         }
1708         if (!status) {
1709                 dev_dbg(bridge, "PTE: pg_tbl_va %x, pa %x, va %x, size %x\n",
1710                         pg_tbl_va, pa, va, size);
1711                 dev_dbg(bridge, "PTE: endianism %x, element_size %x, "
1712                         "mixed_size %x\n", attrs->endianism,
1713                         attrs->element_size, attrs->mixed_size);
1714                 status = hw_mmu_pte_set(pg_tbl_va, pa, va, size, attrs);
1715         }
1716
1717         return status;
1718 }
1719
1720 /* Memory map kernel VA -- memory allocated with vmalloc */
1721 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
1722                                   u32 ul_mpu_addr, u32 virt_addr,
1723                                   u32 ul_num_bytes,
1724                                   struct hw_mmu_map_attrs_t *hw_attrs)
1725 {
1726         int status = 0;
1727         struct page *page[1];
1728         u32 i;
1729         u32 pa_curr;
1730         u32 pa_next;
1731         u32 va_curr;
1732         u32 size_curr;
1733         u32 num_pages;
1734         u32 pa;
1735         u32 num_of4k_pages;
1736         u32 temp = 0;
1737
1738         /*
1739          * Do Kernel va to pa translation.
1740          * Combine physically contiguous regions to reduce TLBs.
1741          * Pass the translated pa to pte_update.
1742          */
1743         num_pages = ul_num_bytes / PAGE_SIZE;   /* PAGE_SIZE = OS page size */
1744         i = 0;
1745         va_curr = ul_mpu_addr;
1746         page[0] = vmalloc_to_page((void *)va_curr);
1747         pa_next = page_to_phys(page[0]);
1748         while (!status && (i < num_pages)) {
1749                 /*
1750                  * Reuse pa_next from the previous iteraion to avoid
1751                  * an extra va2pa call
1752                  */
1753                 pa_curr = pa_next;
1754                 size_curr = PAGE_SIZE;
1755                 /*
1756                  * If the next page is physically contiguous,
1757                  * map it with the current one by increasing
1758                  * the size of the region to be mapped
1759                  */
1760                 while (++i < num_pages) {
1761                         page[0] =
1762                             vmalloc_to_page((void *)(va_curr + size_curr));
1763                         pa_next = page_to_phys(page[0]);
1764
1765                         if (pa_next == (pa_curr + size_curr))
1766                                 size_curr += PAGE_SIZE;
1767                         else
1768                                 break;
1769
1770                 }
1771                 if (pa_next == 0) {
1772                         status = -ENOMEM;
1773                         break;
1774                 }
1775                 pa = pa_curr;
1776                 num_of4k_pages = size_curr / HW_PAGE_SIZE4KB;
1777                 while (temp++ < num_of4k_pages) {
1778                         get_page(PHYS_TO_PAGE(pa));
1779                         pa += HW_PAGE_SIZE4KB;
1780                 }
1781                 status = pte_update(dev_context, pa_curr, virt_addr +
1782                                     (va_curr - ul_mpu_addr), size_curr,
1783                                     hw_attrs);
1784                 va_curr += size_curr;
1785         }
1786         /*
1787          * In any case, flush the TLB
1788          * This is called from here instead from pte_update to avoid unnecessary
1789          * repetition while mapping non-contiguous physical regions of a virtual
1790          * region
1791          */
1792         flush_all(dev_context);
1793         dev_dbg(bridge, "%s status %x\n", __func__, status);
1794         return status;
1795 }
1796
1797 /*
1798  *  ======== wait_for_start ========
1799  *      Wait for the singal from DSP that it has started, or time out.
1800  */
1801 bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr)
1802 {
1803         u16 timeout = TIHELEN_ACKTIMEOUT;
1804
1805         /*  Wait for response from board */
1806         while (__raw_readw(dw_sync_addr) && --timeout)
1807                 udelay(10);
1808
1809         /*  If timed out: return false */
1810         if (!timeout) {
1811                 pr_err("%s: Timed out waiting DSP to Start\n", __func__);
1812                 return false;
1813         }
1814         return true;
1815 }