dw_spi: Fix missing final read in some polling situations
[linux-2.6.git] / drivers / spi / dw_spi.c
1 /*
2  * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
3  *
4  * Copyright (c) 2009, Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18  */
19
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/highmem.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25
26 #include <linux/spi/dw_spi.h>
27 #include <linux/spi/spi.h>
28
29 #ifdef CONFIG_DEBUG_FS
30 #include <linux/debugfs.h>
31 #endif
32
33 #define START_STATE     ((void *)0)
34 #define RUNNING_STATE   ((void *)1)
35 #define DONE_STATE      ((void *)2)
36 #define ERROR_STATE     ((void *)-1)
37
38 #define QUEUE_RUNNING   0
39 #define QUEUE_STOPPED   1
40
41 #define MRST_SPI_DEASSERT       0
42 #define MRST_SPI_ASSERT         1
43
44 /* Slave spi_dev related */
45 struct chip_data {
46         u16 cr0;
47         u8 cs;                  /* chip select pin */
48         u8 n_bytes;             /* current is a 1/2/4 byte op */
49         u8 tmode;               /* TR/TO/RO/EEPROM */
50         u8 type;                /* SPI/SSP/MicroWire */
51
52         u8 poll_mode;           /* 1 means use poll mode */
53
54         u32 dma_width;
55         u32 rx_threshold;
56         u32 tx_threshold;
57         u8 enable_dma;
58         u8 bits_per_word;
59         u16 clk_div;            /* baud rate divider */
60         u32 speed_hz;           /* baud rate */
61         int (*write)(struct dw_spi *dws);
62         int (*read)(struct dw_spi *dws);
63         void (*cs_control)(u32 command);
64 };
65
66 #ifdef CONFIG_DEBUG_FS
67 static int spi_show_regs_open(struct inode *inode, struct file *file)
68 {
69         file->private_data = inode->i_private;
70         return 0;
71 }
72
73 #define SPI_REGS_BUFSIZE        1024
74 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
75                                 size_t count, loff_t *ppos)
76 {
77         struct dw_spi *dws;
78         char *buf;
79         u32 len = 0;
80         ssize_t ret;
81
82         dws = file->private_data;
83
84         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
85         if (!buf)
86                 return 0;
87
88         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
89                         "MRST SPI0 registers:\n");
90         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
91                         "=================================\n");
92         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
93                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
94         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
95                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
96         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
97                         "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
98         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
99                         "SER: \t\t0x%08x\n", dw_readl(dws, ser));
100         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
101                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
102         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
103                         "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
104         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
105                         "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
106         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
107                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
108         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
109                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
110         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
111                         "SR: \t\t0x%08x\n", dw_readl(dws, sr));
112         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
113                         "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
114         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
115                         "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
116         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
117                         "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
118         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
119                         "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
120         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
121                         "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
122         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
123                         "=================================\n");
124
125         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
126         kfree(buf);
127         return ret;
128 }
129
130 static const struct file_operations mrst_spi_regs_ops = {
131         .owner          = THIS_MODULE,
132         .open           = spi_show_regs_open,
133         .read           = spi_show_regs,
134         .llseek         = default_llseek,
135 };
136
137 static int mrst_spi_debugfs_init(struct dw_spi *dws)
138 {
139         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
140         if (!dws->debugfs)
141                 return -ENOMEM;
142
143         debugfs_create_file("registers", S_IFREG | S_IRUGO,
144                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
145         return 0;
146 }
147
148 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
149 {
150         if (dws->debugfs)
151                 debugfs_remove_recursive(dws->debugfs);
152 }
153
154 #else
155 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
156 {
157         return 0;
158 }
159
160 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
161 {
162 }
163 #endif /* CONFIG_DEBUG_FS */
164
165 static void wait_till_not_busy(struct dw_spi *dws)
166 {
167         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
168
169         while (time_before(jiffies, end)) {
170                 if (!(dw_readw(dws, sr) & SR_BUSY))
171                         return;
172         }
173         dev_err(&dws->master->dev,
174                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
175 }
176
177 static void flush(struct dw_spi *dws)
178 {
179         while (dw_readw(dws, sr) & SR_RF_NOT_EMPT)
180                 dw_readw(dws, dr);
181
182         wait_till_not_busy(dws);
183 }
184
185 static int null_writer(struct dw_spi *dws)
186 {
187         u8 n_bytes = dws->n_bytes;
188
189         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
190                 || (dws->tx == dws->tx_end))
191                 return 0;
192         dw_writew(dws, dr, 0);
193         dws->tx += n_bytes;
194
195         wait_till_not_busy(dws);
196         return 1;
197 }
198
199 static int null_reader(struct dw_spi *dws)
200 {
201         u8 n_bytes = dws->n_bytes;
202
203         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
204                 && (dws->rx < dws->rx_end)) {
205                 dw_readw(dws, dr);
206                 dws->rx += n_bytes;
207         }
208         wait_till_not_busy(dws);
209         return dws->rx == dws->rx_end;
210 }
211
212 static int u8_writer(struct dw_spi *dws)
213 {
214         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
215                 || (dws->tx == dws->tx_end))
216                 return 0;
217
218         dw_writew(dws, dr, *(u8 *)(dws->tx));
219         ++dws->tx;
220
221         wait_till_not_busy(dws);
222         return 1;
223 }
224
225 static int u8_reader(struct dw_spi *dws)
226 {
227         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
228                 && (dws->rx < dws->rx_end)) {
229                 *(u8 *)(dws->rx) = dw_readw(dws, dr);
230                 ++dws->rx;
231         }
232
233         wait_till_not_busy(dws);
234         return dws->rx == dws->rx_end;
235 }
236
237 static int u16_writer(struct dw_spi *dws)
238 {
239         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
240                 || (dws->tx == dws->tx_end))
241                 return 0;
242
243         dw_writew(dws, dr, *(u16 *)(dws->tx));
244         dws->tx += 2;
245
246         wait_till_not_busy(dws);
247         return 1;
248 }
249
250 static int u16_reader(struct dw_spi *dws)
251 {
252         u16 temp;
253
254         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
255                 && (dws->rx < dws->rx_end)) {
256                 temp = dw_readw(dws, dr);
257                 *(u16 *)(dws->rx) = temp;
258                 dws->rx += 2;
259         }
260
261         wait_till_not_busy(dws);
262         return dws->rx == dws->rx_end;
263 }
264
265 static void *next_transfer(struct dw_spi *dws)
266 {
267         struct spi_message *msg = dws->cur_msg;
268         struct spi_transfer *trans = dws->cur_transfer;
269
270         /* Move to next transfer */
271         if (trans->transfer_list.next != &msg->transfers) {
272                 dws->cur_transfer =
273                         list_entry(trans->transfer_list.next,
274                                         struct spi_transfer,
275                                         transfer_list);
276                 return RUNNING_STATE;
277         } else
278                 return DONE_STATE;
279 }
280
281 /*
282  * Note: first step is the protocol driver prepares
283  * a dma-capable memory, and this func just need translate
284  * the virt addr to physical
285  */
286 static int map_dma_buffers(struct dw_spi *dws)
287 {
288         if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
289                 || !dws->cur_chip->enable_dma)
290                 return 0;
291
292         if (dws->cur_transfer->tx_dma)
293                 dws->tx_dma = dws->cur_transfer->tx_dma;
294
295         if (dws->cur_transfer->rx_dma)
296                 dws->rx_dma = dws->cur_transfer->rx_dma;
297
298         return 1;
299 }
300
301 /* Caller already set message->status; dma and pio irqs are blocked */
302 static void giveback(struct dw_spi *dws)
303 {
304         struct spi_transfer *last_transfer;
305         unsigned long flags;
306         struct spi_message *msg;
307
308         spin_lock_irqsave(&dws->lock, flags);
309         msg = dws->cur_msg;
310         dws->cur_msg = NULL;
311         dws->cur_transfer = NULL;
312         dws->prev_chip = dws->cur_chip;
313         dws->cur_chip = NULL;
314         dws->dma_mapped = 0;
315         queue_work(dws->workqueue, &dws->pump_messages);
316         spin_unlock_irqrestore(&dws->lock, flags);
317
318         last_transfer = list_entry(msg->transfers.prev,
319                                         struct spi_transfer,
320                                         transfer_list);
321
322         if (!last_transfer->cs_change && dws->cs_control)
323                 dws->cs_control(MRST_SPI_DEASSERT);
324
325         msg->state = NULL;
326         if (msg->complete)
327                 msg->complete(msg->context);
328 }
329
330 static void int_error_stop(struct dw_spi *dws, const char *msg)
331 {
332         /* Stop and reset hw */
333         flush(dws);
334         spi_enable_chip(dws, 0);
335
336         dev_err(&dws->master->dev, "%s\n", msg);
337         dws->cur_msg->state = ERROR_STATE;
338         tasklet_schedule(&dws->pump_transfers);
339 }
340
341 static void transfer_complete(struct dw_spi *dws)
342 {
343         /* Update total byte transfered return count actual bytes read */
344         dws->cur_msg->actual_length += dws->len;
345
346         /* Move to next transfer */
347         dws->cur_msg->state = next_transfer(dws);
348
349         /* Handle end of message */
350         if (dws->cur_msg->state == DONE_STATE) {
351                 dws->cur_msg->status = 0;
352                 giveback(dws);
353         } else
354                 tasklet_schedule(&dws->pump_transfers);
355 }
356
357 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
358 {
359         u16 irq_status, irq_mask = 0x3f;
360         u32 int_level = dws->fifo_len / 2;
361         u32 left;
362
363         irq_status = dw_readw(dws, isr) & irq_mask;
364         /* Error handling */
365         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
366                 dw_readw(dws, txoicr);
367                 dw_readw(dws, rxoicr);
368                 dw_readw(dws, rxuicr);
369                 int_error_stop(dws, "interrupt_transfer: fifo overrun");
370                 return IRQ_HANDLED;
371         }
372
373         if (irq_status & SPI_INT_TXEI) {
374                 spi_mask_intr(dws, SPI_INT_TXEI);
375
376                 left = (dws->tx_end - dws->tx) / dws->n_bytes;
377                 left = (left > int_level) ? int_level : left;
378
379                 while (left--)
380                         dws->write(dws);
381                 dws->read(dws);
382
383                 /* Re-enable the IRQ if there is still data left to tx */
384                 if (dws->tx_end > dws->tx)
385                         spi_umask_intr(dws, SPI_INT_TXEI);
386                 else
387                         transfer_complete(dws);
388         }
389
390         return IRQ_HANDLED;
391 }
392
393 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
394 {
395         struct dw_spi *dws = dev_id;
396         u16 irq_status, irq_mask = 0x3f;
397
398         irq_status = dw_readw(dws, isr) & irq_mask;
399         if (!irq_status)
400                 return IRQ_NONE;
401
402         if (!dws->cur_msg) {
403                 spi_mask_intr(dws, SPI_INT_TXEI);
404                 /* Never fail */
405                 return IRQ_HANDLED;
406         }
407
408         return dws->transfer_handler(dws);
409 }
410
411 /* Must be called inside pump_transfers() */
412 static void poll_transfer(struct dw_spi *dws)
413 {
414         while (dws->write(dws))
415                 dws->read(dws);
416         /*
417          * There is a possibility that the last word of a transaction
418          * will be lost if data is not ready. Re-read to solve this issue.
419          */
420         dws->read(dws);
421
422         transfer_complete(dws);
423 }
424
425 static void dma_transfer(struct dw_spi *dws, int cs_change)
426 {
427 }
428
429 static void pump_transfers(unsigned long data)
430 {
431         struct dw_spi *dws = (struct dw_spi *)data;
432         struct spi_message *message = NULL;
433         struct spi_transfer *transfer = NULL;
434         struct spi_transfer *previous = NULL;
435         struct spi_device *spi = NULL;
436         struct chip_data *chip = NULL;
437         u8 bits = 0;
438         u8 imask = 0;
439         u8 cs_change = 0;
440         u16 txint_level = 0;
441         u16 clk_div = 0;
442         u32 speed = 0;
443         u32 cr0 = 0;
444
445         /* Get current state information */
446         message = dws->cur_msg;
447         transfer = dws->cur_transfer;
448         chip = dws->cur_chip;
449         spi = message->spi;
450
451         if (unlikely(!chip->clk_div))
452                 chip->clk_div = dws->max_freq / chip->speed_hz;
453
454         if (message->state == ERROR_STATE) {
455                 message->status = -EIO;
456                 goto early_exit;
457         }
458
459         /* Handle end of message */
460         if (message->state == DONE_STATE) {
461                 message->status = 0;
462                 goto early_exit;
463         }
464
465         /* Delay if requested at end of transfer*/
466         if (message->state == RUNNING_STATE) {
467                 previous = list_entry(transfer->transfer_list.prev,
468                                         struct spi_transfer,
469                                         transfer_list);
470                 if (previous->delay_usecs)
471                         udelay(previous->delay_usecs);
472         }
473
474         dws->n_bytes = chip->n_bytes;
475         dws->dma_width = chip->dma_width;
476         dws->cs_control = chip->cs_control;
477
478         dws->rx_dma = transfer->rx_dma;
479         dws->tx_dma = transfer->tx_dma;
480         dws->tx = (void *)transfer->tx_buf;
481         dws->tx_end = dws->tx + transfer->len;
482         dws->rx = transfer->rx_buf;
483         dws->rx_end = dws->rx + transfer->len;
484         dws->write = dws->tx ? chip->write : null_writer;
485         dws->read = dws->rx ? chip->read : null_reader;
486         dws->cs_change = transfer->cs_change;
487         dws->len = dws->cur_transfer->len;
488         if (chip != dws->prev_chip)
489                 cs_change = 1;
490
491         cr0 = chip->cr0;
492
493         /* Handle per transfer options for bpw and speed */
494         if (transfer->speed_hz) {
495                 speed = chip->speed_hz;
496
497                 if (transfer->speed_hz != speed) {
498                         speed = transfer->speed_hz;
499                         if (speed > dws->max_freq) {
500                                 printk(KERN_ERR "MRST SPI0: unsupported"
501                                         "freq: %dHz\n", speed);
502                                 message->status = -EIO;
503                                 goto early_exit;
504                         }
505
506                         /* clk_div doesn't support odd number */
507                         clk_div = dws->max_freq / speed;
508                         clk_div = (clk_div + 1) & 0xfffe;
509
510                         chip->speed_hz = speed;
511                         chip->clk_div = clk_div;
512                 }
513         }
514         if (transfer->bits_per_word) {
515                 bits = transfer->bits_per_word;
516
517                 switch (bits) {
518                 case 8:
519                         dws->n_bytes = 1;
520                         dws->dma_width = 1;
521                         dws->read = (dws->read != null_reader) ?
522                                         u8_reader : null_reader;
523                         dws->write = (dws->write != null_writer) ?
524                                         u8_writer : null_writer;
525                         break;
526                 case 16:
527                         dws->n_bytes = 2;
528                         dws->dma_width = 2;
529                         dws->read = (dws->read != null_reader) ?
530                                         u16_reader : null_reader;
531                         dws->write = (dws->write != null_writer) ?
532                                         u16_writer : null_writer;
533                         break;
534                 default:
535                         printk(KERN_ERR "MRST SPI0: unsupported bits:"
536                                 "%db\n", bits);
537                         message->status = -EIO;
538                         goto early_exit;
539                 }
540
541                 cr0 = (bits - 1)
542                         | (chip->type << SPI_FRF_OFFSET)
543                         | (spi->mode << SPI_MODE_OFFSET)
544                         | (chip->tmode << SPI_TMOD_OFFSET);
545         }
546         message->state = RUNNING_STATE;
547
548         /*
549          * Adjust transfer mode if necessary. Requires platform dependent
550          * chipselect mechanism.
551          */
552         if (dws->cs_control) {
553                 if (dws->rx && dws->tx)
554                         chip->tmode = SPI_TMOD_TR;
555                 else if (dws->rx)
556                         chip->tmode = SPI_TMOD_RO;
557                 else
558                         chip->tmode = SPI_TMOD_TO;
559
560                 cr0 &= ~SPI_TMOD_MASK;
561                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
562         }
563
564         /* Check if current transfer is a DMA transaction */
565         dws->dma_mapped = map_dma_buffers(dws);
566
567         /*
568          * Interrupt mode
569          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
570          */
571         if (!dws->dma_mapped && !chip->poll_mode) {
572                 int templen = dws->len / dws->n_bytes;
573                 txint_level = dws->fifo_len / 2;
574                 txint_level = (templen > txint_level) ? txint_level : templen;
575
576                 imask |= SPI_INT_TXEI;
577                 dws->transfer_handler = interrupt_transfer;
578         }
579
580         /*
581          * Reprogram registers only if
582          *      1. chip select changes
583          *      2. clk_div is changed
584          *      3. control value changes
585          */
586         if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
587                 spi_enable_chip(dws, 0);
588
589                 if (dw_readw(dws, ctrl0) != cr0)
590                         dw_writew(dws, ctrl0, cr0);
591
592                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
593                 spi_chip_sel(dws, spi->chip_select);
594
595                 /* Set the interrupt mask, for poll mode just diable all int */
596                 spi_mask_intr(dws, 0xff);
597                 if (imask)
598                         spi_umask_intr(dws, imask);
599                 if (txint_level)
600                         dw_writew(dws, txfltr, txint_level);
601
602                 spi_enable_chip(dws, 1);
603                 if (cs_change)
604                         dws->prev_chip = chip;
605         }
606
607         if (dws->dma_mapped)
608                 dma_transfer(dws, cs_change);
609
610         if (chip->poll_mode)
611                 poll_transfer(dws);
612
613         return;
614
615 early_exit:
616         giveback(dws);
617         return;
618 }
619
620 static void pump_messages(struct work_struct *work)
621 {
622         struct dw_spi *dws =
623                 container_of(work, struct dw_spi, pump_messages);
624         unsigned long flags;
625
626         /* Lock queue and check for queue work */
627         spin_lock_irqsave(&dws->lock, flags);
628         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
629                 dws->busy = 0;
630                 spin_unlock_irqrestore(&dws->lock, flags);
631                 return;
632         }
633
634         /* Make sure we are not already running a message */
635         if (dws->cur_msg) {
636                 spin_unlock_irqrestore(&dws->lock, flags);
637                 return;
638         }
639
640         /* Extract head of queue */
641         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
642         list_del_init(&dws->cur_msg->queue);
643
644         /* Initial message state*/
645         dws->cur_msg->state = START_STATE;
646         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
647                                                 struct spi_transfer,
648                                                 transfer_list);
649         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
650
651         /* Mark as busy and launch transfers */
652         tasklet_schedule(&dws->pump_transfers);
653
654         dws->busy = 1;
655         spin_unlock_irqrestore(&dws->lock, flags);
656 }
657
658 /* spi_device use this to queue in their spi_msg */
659 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
660 {
661         struct dw_spi *dws = spi_master_get_devdata(spi->master);
662         unsigned long flags;
663
664         spin_lock_irqsave(&dws->lock, flags);
665
666         if (dws->run == QUEUE_STOPPED) {
667                 spin_unlock_irqrestore(&dws->lock, flags);
668                 return -ESHUTDOWN;
669         }
670
671         msg->actual_length = 0;
672         msg->status = -EINPROGRESS;
673         msg->state = START_STATE;
674
675         list_add_tail(&msg->queue, &dws->queue);
676
677         if (dws->run == QUEUE_RUNNING && !dws->busy) {
678
679                 if (dws->cur_transfer || dws->cur_msg)
680                         queue_work(dws->workqueue,
681                                         &dws->pump_messages);
682                 else {
683                         /* If no other data transaction in air, just go */
684                         spin_unlock_irqrestore(&dws->lock, flags);
685                         pump_messages(&dws->pump_messages);
686                         return 0;
687                 }
688         }
689
690         spin_unlock_irqrestore(&dws->lock, flags);
691         return 0;
692 }
693
694 /* This may be called twice for each spi dev */
695 static int dw_spi_setup(struct spi_device *spi)
696 {
697         struct dw_spi_chip *chip_info = NULL;
698         struct chip_data *chip;
699
700         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
701                 return -EINVAL;
702
703         /* Only alloc on first setup */
704         chip = spi_get_ctldata(spi);
705         if (!chip) {
706                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
707                 if (!chip)
708                         return -ENOMEM;
709         }
710
711         /*
712          * Protocol drivers may change the chip settings, so...
713          * if chip_info exists, use it
714          */
715         chip_info = spi->controller_data;
716
717         /* chip_info doesn't always exist */
718         if (chip_info) {
719                 if (chip_info->cs_control)
720                         chip->cs_control = chip_info->cs_control;
721
722                 chip->poll_mode = chip_info->poll_mode;
723                 chip->type = chip_info->type;
724
725                 chip->rx_threshold = 0;
726                 chip->tx_threshold = 0;
727
728                 chip->enable_dma = chip_info->enable_dma;
729         }
730
731         if (spi->bits_per_word <= 8) {
732                 chip->n_bytes = 1;
733                 chip->dma_width = 1;
734                 chip->read = u8_reader;
735                 chip->write = u8_writer;
736         } else if (spi->bits_per_word <= 16) {
737                 chip->n_bytes = 2;
738                 chip->dma_width = 2;
739                 chip->read = u16_reader;
740                 chip->write = u16_writer;
741         } else {
742                 /* Never take >16b case for MRST SPIC */
743                 dev_err(&spi->dev, "invalid wordsize\n");
744                 return -EINVAL;
745         }
746         chip->bits_per_word = spi->bits_per_word;
747
748         if (!spi->max_speed_hz) {
749                 dev_err(&spi->dev, "No max speed HZ parameter\n");
750                 return -EINVAL;
751         }
752         chip->speed_hz = spi->max_speed_hz;
753
754         chip->tmode = 0; /* Tx & Rx */
755         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
756         chip->cr0 = (chip->bits_per_word - 1)
757                         | (chip->type << SPI_FRF_OFFSET)
758                         | (spi->mode  << SPI_MODE_OFFSET)
759                         | (chip->tmode << SPI_TMOD_OFFSET);
760
761         spi_set_ctldata(spi, chip);
762         return 0;
763 }
764
765 static void dw_spi_cleanup(struct spi_device *spi)
766 {
767         struct chip_data *chip = spi_get_ctldata(spi);
768         kfree(chip);
769 }
770
771 static int __devinit init_queue(struct dw_spi *dws)
772 {
773         INIT_LIST_HEAD(&dws->queue);
774         spin_lock_init(&dws->lock);
775
776         dws->run = QUEUE_STOPPED;
777         dws->busy = 0;
778
779         tasklet_init(&dws->pump_transfers,
780                         pump_transfers, (unsigned long)dws);
781
782         INIT_WORK(&dws->pump_messages, pump_messages);
783         dws->workqueue = create_singlethread_workqueue(
784                                         dev_name(dws->master->dev.parent));
785         if (dws->workqueue == NULL)
786                 return -EBUSY;
787
788         return 0;
789 }
790
791 static int start_queue(struct dw_spi *dws)
792 {
793         unsigned long flags;
794
795         spin_lock_irqsave(&dws->lock, flags);
796
797         if (dws->run == QUEUE_RUNNING || dws->busy) {
798                 spin_unlock_irqrestore(&dws->lock, flags);
799                 return -EBUSY;
800         }
801
802         dws->run = QUEUE_RUNNING;
803         dws->cur_msg = NULL;
804         dws->cur_transfer = NULL;
805         dws->cur_chip = NULL;
806         dws->prev_chip = NULL;
807         spin_unlock_irqrestore(&dws->lock, flags);
808
809         queue_work(dws->workqueue, &dws->pump_messages);
810
811         return 0;
812 }
813
814 static int stop_queue(struct dw_spi *dws)
815 {
816         unsigned long flags;
817         unsigned limit = 50;
818         int status = 0;
819
820         spin_lock_irqsave(&dws->lock, flags);
821         dws->run = QUEUE_STOPPED;
822         while (!list_empty(&dws->queue) && dws->busy && limit--) {
823                 spin_unlock_irqrestore(&dws->lock, flags);
824                 msleep(10);
825                 spin_lock_irqsave(&dws->lock, flags);
826         }
827
828         if (!list_empty(&dws->queue) || dws->busy)
829                 status = -EBUSY;
830         spin_unlock_irqrestore(&dws->lock, flags);
831
832         return status;
833 }
834
835 static int destroy_queue(struct dw_spi *dws)
836 {
837         int status;
838
839         status = stop_queue(dws);
840         if (status != 0)
841                 return status;
842         destroy_workqueue(dws->workqueue);
843         return 0;
844 }
845
846 /* Restart the controller, disable all interrupts, clean rx fifo */
847 static void spi_hw_init(struct dw_spi *dws)
848 {
849         spi_enable_chip(dws, 0);
850         spi_mask_intr(dws, 0xff);
851         spi_enable_chip(dws, 1);
852         flush(dws);
853
854         /*
855          * Try to detect the FIFO depth if not set by interface driver,
856          * the depth could be from 2 to 256 from HW spec
857          */
858         if (!dws->fifo_len) {
859                 u32 fifo;
860                 for (fifo = 2; fifo <= 257; fifo++) {
861                         dw_writew(dws, txfltr, fifo);
862                         if (fifo != dw_readw(dws, txfltr))
863                                 break;
864                 }
865
866                 dws->fifo_len = (fifo == 257) ? 0 : fifo;
867                 dw_writew(dws, txfltr, 0);
868         }
869 }
870
871 int __devinit dw_spi_add_host(struct dw_spi *dws)
872 {
873         struct spi_master *master;
874         int ret;
875
876         BUG_ON(dws == NULL);
877
878         master = spi_alloc_master(dws->parent_dev, 0);
879         if (!master) {
880                 ret = -ENOMEM;
881                 goto exit;
882         }
883
884         dws->master = master;
885         dws->type = SSI_MOTO_SPI;
886         dws->prev_chip = NULL;
887         dws->dma_inited = 0;
888         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
889
890         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
891                         "dw_spi", dws);
892         if (ret < 0) {
893                 dev_err(&master->dev, "can not get IRQ\n");
894                 goto err_free_master;
895         }
896
897         master->mode_bits = SPI_CPOL | SPI_CPHA;
898         master->bus_num = dws->bus_num;
899         master->num_chipselect = dws->num_cs;
900         master->cleanup = dw_spi_cleanup;
901         master->setup = dw_spi_setup;
902         master->transfer = dw_spi_transfer;
903
904         dws->dma_inited = 0;
905
906         /* Basic HW init */
907         spi_hw_init(dws);
908
909         /* Initial and start queue */
910         ret = init_queue(dws);
911         if (ret) {
912                 dev_err(&master->dev, "problem initializing queue\n");
913                 goto err_diable_hw;
914         }
915         ret = start_queue(dws);
916         if (ret) {
917                 dev_err(&master->dev, "problem starting queue\n");
918                 goto err_diable_hw;
919         }
920
921         spi_master_set_devdata(master, dws);
922         ret = spi_register_master(master);
923         if (ret) {
924                 dev_err(&master->dev, "problem registering spi master\n");
925                 goto err_queue_alloc;
926         }
927
928         mrst_spi_debugfs_init(dws);
929         return 0;
930
931 err_queue_alloc:
932         destroy_queue(dws);
933 err_diable_hw:
934         spi_enable_chip(dws, 0);
935         free_irq(dws->irq, dws);
936 err_free_master:
937         spi_master_put(master);
938 exit:
939         return ret;
940 }
941 EXPORT_SYMBOL(dw_spi_add_host);
942
943 void __devexit dw_spi_remove_host(struct dw_spi *dws)
944 {
945         int status = 0;
946
947         if (!dws)
948                 return;
949         mrst_spi_debugfs_remove(dws);
950
951         /* Remove the queue */
952         status = destroy_queue(dws);
953         if (status != 0)
954                 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
955                         "complete, message memory not freed\n");
956
957         spi_enable_chip(dws, 0);
958         /* Disable clk */
959         spi_set_clk(dws, 0);
960         free_irq(dws->irq, dws);
961
962         /* Disconnect from the SPI framework */
963         spi_unregister_master(dws->master);
964 }
965 EXPORT_SYMBOL(dw_spi_remove_host);
966
967 int dw_spi_suspend_host(struct dw_spi *dws)
968 {
969         int ret = 0;
970
971         ret = stop_queue(dws);
972         if (ret)
973                 return ret;
974         spi_enable_chip(dws, 0);
975         spi_set_clk(dws, 0);
976         return ret;
977 }
978 EXPORT_SYMBOL(dw_spi_suspend_host);
979
980 int dw_spi_resume_host(struct dw_spi *dws)
981 {
982         int ret;
983
984         spi_hw_init(dws);
985         ret = start_queue(dws);
986         if (ret)
987                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
988         return ret;
989 }
990 EXPORT_SYMBOL(dw_spi_resume_host);
991
992 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
993 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
994 MODULE_LICENSE("GPL v2");