[SPARC]: Fix serial console device detection.
[linux-2.6.git] / drivers / serial / sunzilog.c
1 /* sunzilog.c: Zilog serial driver for Sparc systems.
2  *
3  * Driver for Zilog serial chips found on Sun workstations and
4  * servers.  This driver could actually be made more generic.
5  *
6  * This is based on the old drivers/sbus/char/zs.c code.  A lot
7  * of code has been simply moved over directly from there but
8  * much has been rewritten.  Credits therefore go out to Eddie
9  * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
10  * work there.
11  *
12  * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net)
13  */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/major.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/circ_buf.h>
27 #include <linux/serial.h>
28 #include <linux/sysrq.h>
29 #include <linux/console.h>
30 #include <linux/spinlock.h>
31 #ifdef CONFIG_SERIO
32 #include <linux/serio.h>
33 #endif
34 #include <linux/init.h>
35
36 #include <asm/io.h>
37 #include <asm/irq.h>
38 #include <asm/prom.h>
39 #include <asm/of_device.h>
40
41 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
42 #define SUPPORT_SYSRQ
43 #endif
44
45 #include <linux/serial_core.h>
46
47 #include "suncore.h"
48 #include "sunzilog.h"
49
50 /* On 32-bit sparcs we need to delay after register accesses
51  * to accommodate sun4 systems, but we do not need to flush writes.
52  * On 64-bit sparc we only need to flush single writes to ensure
53  * completion.
54  */
55 #ifndef CONFIG_SPARC64
56 #define ZSDELAY()               udelay(5)
57 #define ZSDELAY_LONG()          udelay(20)
58 #define ZS_WSYNC(channel)       do { } while (0)
59 #else
60 #define ZSDELAY()
61 #define ZSDELAY_LONG()
62 #define ZS_WSYNC(__channel) \
63         readb(&((__channel)->control))
64 #endif
65
66 static int num_sunzilog;
67 #define NUM_SUNZILOG    num_sunzilog
68 #define NUM_CHANNELS    (NUM_SUNZILOG * 2)
69
70 #define ZS_CLOCK                4915200 /* Zilog input clock rate. */
71 #define ZS_CLOCK_DIVISOR        16      /* Divisor this driver uses. */
72
73 /*
74  * We wrap our port structure around the generic uart_port.
75  */
76 struct uart_sunzilog_port {
77         struct uart_port                port;
78
79         /* IRQ servicing chain.  */
80         struct uart_sunzilog_port       *next;
81
82         /* Current values of Zilog write registers.  */
83         unsigned char                   curregs[NUM_ZSREGS];
84
85         unsigned int                    flags;
86 #define SUNZILOG_FLAG_CONS_KEYB         0x00000001
87 #define SUNZILOG_FLAG_CONS_MOUSE        0x00000002
88 #define SUNZILOG_FLAG_IS_CONS           0x00000004
89 #define SUNZILOG_FLAG_IS_KGDB           0x00000008
90 #define SUNZILOG_FLAG_MODEM_STATUS      0x00000010
91 #define SUNZILOG_FLAG_IS_CHANNEL_A      0x00000020
92 #define SUNZILOG_FLAG_REGS_HELD         0x00000040
93 #define SUNZILOG_FLAG_TX_STOPPED        0x00000080
94 #define SUNZILOG_FLAG_TX_ACTIVE         0x00000100
95 #define SUNZILOG_FLAG_ESCC              0x00000200
96 #define SUNZILOG_FLAG_ISR_HANDLER       0x00000400
97
98         unsigned int cflag;
99
100         unsigned char                   parity_mask;
101         unsigned char                   prev_status;
102
103 #ifdef CONFIG_SERIO
104         struct serio                    serio;
105         int                             serio_open;
106 #endif
107 };
108
109 #define ZILOG_CHANNEL_FROM_PORT(PORT)   ((struct zilog_channel __iomem *)((PORT)->membase))
110 #define UART_ZILOG(PORT)                ((struct uart_sunzilog_port *)(PORT))
111
112 #define ZS_IS_KEYB(UP)  ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
113 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
114 #define ZS_IS_CONS(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
115 #define ZS_IS_KGDB(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
116 #define ZS_WANTS_MODEM_STATUS(UP)       ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
117 #define ZS_IS_CHANNEL_A(UP)     ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
118 #define ZS_REGS_HELD(UP)        ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
119 #define ZS_TX_STOPPED(UP)       ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
120 #define ZS_TX_ACTIVE(UP)        ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
121
122 /* Reading and writing Zilog8530 registers.  The delays are to make this
123  * driver work on the Sun4 which needs a settling delay after each chip
124  * register access, other machines handle this in hardware via auxiliary
125  * flip-flops which implement the settle time we do in software.
126  *
127  * The port lock must be held and local IRQs must be disabled
128  * when {read,write}_zsreg is invoked.
129  */
130 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
131                                 unsigned char reg)
132 {
133         unsigned char retval;
134
135         writeb(reg, &channel->control);
136         ZSDELAY();
137         retval = readb(&channel->control);
138         ZSDELAY();
139
140         return retval;
141 }
142
143 static void write_zsreg(struct zilog_channel __iomem *channel,
144                         unsigned char reg, unsigned char value)
145 {
146         writeb(reg, &channel->control);
147         ZSDELAY();
148         writeb(value, &channel->control);
149         ZSDELAY();
150 }
151
152 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
153 {
154         int i;
155
156         for (i = 0; i < 32; i++) {
157                 unsigned char regval;
158
159                 regval = readb(&channel->control);
160                 ZSDELAY();
161                 if (regval & Rx_CH_AV)
162                         break;
163
164                 regval = read_zsreg(channel, R1);
165                 readb(&channel->data);
166                 ZSDELAY();
167
168                 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
169                         writeb(ERR_RES, &channel->control);
170                         ZSDELAY();
171                         ZS_WSYNC(channel);
172                 }
173         }
174 }
175
176 /* This function must only be called when the TX is not busy.  The UART
177  * port lock must be held and local interrupts disabled.
178  */
179 static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
180 {
181         int i;
182         int escc;
183         unsigned char r15;
184
185         /* Let pending transmits finish.  */
186         for (i = 0; i < 1000; i++) {
187                 unsigned char stat = read_zsreg(channel, R1);
188                 if (stat & ALL_SNT)
189                         break;
190                 udelay(100);
191         }
192
193         writeb(ERR_RES, &channel->control);
194         ZSDELAY();
195         ZS_WSYNC(channel);
196
197         sunzilog_clear_fifo(channel);
198
199         /* Disable all interrupts.  */
200         write_zsreg(channel, R1,
201                     regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
202
203         /* Set parity, sync config, stop bits, and clock divisor.  */
204         write_zsreg(channel, R4, regs[R4]);
205
206         /* Set misc. TX/RX control bits.  */
207         write_zsreg(channel, R10, regs[R10]);
208
209         /* Set TX/RX controls sans the enable bits.  */
210         write_zsreg(channel, R3, regs[R3] & ~RxENAB);
211         write_zsreg(channel, R5, regs[R5] & ~TxENAB);
212
213         /* Synchronous mode config.  */
214         write_zsreg(channel, R6, regs[R6]);
215         write_zsreg(channel, R7, regs[R7]);
216
217         /* Don't mess with the interrupt vector (R2, unused by us) and
218          * master interrupt control (R9).  We make sure this is setup
219          * properly at probe time then never touch it again.
220          */
221
222         /* Disable baud generator.  */
223         write_zsreg(channel, R14, regs[R14] & ~BRENAB);
224
225         /* Clock mode control.  */
226         write_zsreg(channel, R11, regs[R11]);
227
228         /* Lower and upper byte of baud rate generator divisor.  */
229         write_zsreg(channel, R12, regs[R12]);
230         write_zsreg(channel, R13, regs[R13]);
231         
232         /* Now rewrite R14, with BRENAB (if set).  */
233         write_zsreg(channel, R14, regs[R14]);
234
235         /* External status interrupt control.  */
236         write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
237
238         /* ESCC Extension Register */
239         r15 = read_zsreg(channel, R15);
240         if (r15 & 0x01) {
241                 write_zsreg(channel, R7,  regs[R7p]);
242
243                 /* External status interrupt and FIFO control.  */
244                 write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
245                 escc = 1;
246         } else {
247                  /* Clear FIFO bit case it is an issue */
248                 regs[R15] &= ~FIFOEN;
249                 escc = 0;
250         }
251
252         /* Reset external status interrupts.  */
253         write_zsreg(channel, R0, RES_EXT_INT); /* First Latch  */
254         write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
255
256         /* Rewrite R3/R5, this time without enables masked.  */
257         write_zsreg(channel, R3, regs[R3]);
258         write_zsreg(channel, R5, regs[R5]);
259
260         /* Rewrite R1, this time without IRQ enabled masked.  */
261         write_zsreg(channel, R1, regs[R1]);
262
263         return escc;
264 }
265
266 /* Reprogram the Zilog channel HW registers with the copies found in the
267  * software state struct.  If the transmitter is busy, we defer this update
268  * until the next TX complete interrupt.  Else, we do it right now.
269  *
270  * The UART port lock must be held and local interrupts disabled.
271  */
272 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
273                                        struct zilog_channel __iomem *channel)
274 {
275         if (!ZS_REGS_HELD(up)) {
276                 if (ZS_TX_ACTIVE(up)) {
277                         up->flags |= SUNZILOG_FLAG_REGS_HELD;
278                 } else {
279                         __load_zsregs(channel, up->curregs);
280                 }
281         }
282 }
283
284 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
285 {
286         unsigned int cur_cflag = up->cflag;
287         int brg, new_baud;
288
289         up->cflag &= ~CBAUD;
290         up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
291
292         brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
293         up->curregs[R12] = (brg & 0xff);
294         up->curregs[R13] = (brg >> 8) & 0xff;
295         sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
296 }
297
298 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
299                                          unsigned char ch, int is_break)
300 {
301         if (ZS_IS_KEYB(up)) {
302                 /* Stop-A is handled by drivers/char/keyboard.c now. */
303 #ifdef CONFIG_SERIO
304                 if (up->serio_open)
305                         serio_interrupt(&up->serio, ch, 0);
306 #endif
307         } else if (ZS_IS_MOUSE(up)) {
308                 int ret = suncore_mouse_baud_detection(ch, is_break);
309
310                 switch (ret) {
311                 case 2:
312                         sunzilog_change_mouse_baud(up);
313                         /* fallthru */
314                 case 1:
315                         break;
316
317                 case 0:
318 #ifdef CONFIG_SERIO
319                         if (up->serio_open)
320                                 serio_interrupt(&up->serio, ch, 0);
321 #endif
322                         break;
323                 };
324         }
325 }
326
327 static struct tty_struct *
328 sunzilog_receive_chars(struct uart_sunzilog_port *up,
329                        struct zilog_channel __iomem *channel)
330 {
331         struct tty_struct *tty;
332         unsigned char ch, r1, flag;
333
334         tty = NULL;
335         if (up->port.info != NULL &&            /* Unopened serial console */
336             up->port.info->tty != NULL)         /* Keyboard || mouse */
337                 tty = up->port.info->tty;
338
339         for (;;) {
340
341                 r1 = read_zsreg(channel, R1);
342                 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
343                         writeb(ERR_RES, &channel->control);
344                         ZSDELAY();
345                         ZS_WSYNC(channel);
346                 }
347
348                 ch = readb(&channel->control);
349                 ZSDELAY();
350
351                 /* This funny hack depends upon BRK_ABRT not interfering
352                  * with the other bits we care about in R1.
353                  */
354                 if (ch & BRK_ABRT)
355                         r1 |= BRK_ABRT;
356
357                 if (!(ch & Rx_CH_AV))
358                         break;
359
360                 ch = readb(&channel->data);
361                 ZSDELAY();
362
363                 ch &= up->parity_mask;
364
365                 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
366                         sunzilog_kbdms_receive_chars(up, ch, 0);
367                         continue;
368                 }
369
370                 if (tty == NULL) {
371                         uart_handle_sysrq_char(&up->port, ch);
372                         continue;
373                 }
374
375                 /* A real serial line, record the character and status.  */
376                 flag = TTY_NORMAL;
377                 up->port.icount.rx++;
378                 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
379                         if (r1 & BRK_ABRT) {
380                                 r1 &= ~(PAR_ERR | CRC_ERR);
381                                 up->port.icount.brk++;
382                                 if (uart_handle_break(&up->port))
383                                         continue;
384                         }
385                         else if (r1 & PAR_ERR)
386                                 up->port.icount.parity++;
387                         else if (r1 & CRC_ERR)
388                                 up->port.icount.frame++;
389                         if (r1 & Rx_OVR)
390                                 up->port.icount.overrun++;
391                         r1 &= up->port.read_status_mask;
392                         if (r1 & BRK_ABRT)
393                                 flag = TTY_BREAK;
394                         else if (r1 & PAR_ERR)
395                                 flag = TTY_PARITY;
396                         else if (r1 & CRC_ERR)
397                                 flag = TTY_FRAME;
398                 }
399                 if (uart_handle_sysrq_char(&up->port, ch))
400                         continue;
401
402                 if (up->port.ignore_status_mask == 0xff ||
403                     (r1 & up->port.ignore_status_mask) == 0) {
404                         tty_insert_flip_char(tty, ch, flag);
405                 }
406                 if (r1 & Rx_OVR)
407                         tty_insert_flip_char(tty, 0, TTY_OVERRUN);
408         }
409
410         return tty;
411 }
412
413 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
414                                    struct zilog_channel __iomem *channel)
415 {
416         unsigned char status;
417
418         status = readb(&channel->control);
419         ZSDELAY();
420
421         writeb(RES_EXT_INT, &channel->control);
422         ZSDELAY();
423         ZS_WSYNC(channel);
424
425         if (status & BRK_ABRT) {
426                 if (ZS_IS_MOUSE(up))
427                         sunzilog_kbdms_receive_chars(up, 0, 1);
428                 if (ZS_IS_CONS(up)) {
429                         /* Wait for BREAK to deassert to avoid potentially
430                          * confusing the PROM.
431                          */
432                         while (1) {
433                                 status = readb(&channel->control);
434                                 ZSDELAY();
435                                 if (!(status & BRK_ABRT))
436                                         break;
437                         }
438                         sun_do_break();
439                         return;
440                 }
441         }
442
443         if (ZS_WANTS_MODEM_STATUS(up)) {
444                 if (status & SYNC)
445                         up->port.icount.dsr++;
446
447                 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
448                  * But it does not tell us which bit has changed, we have to keep
449                  * track of this ourselves.
450                  */
451                 if ((status ^ up->prev_status) ^ DCD)
452                         uart_handle_dcd_change(&up->port,
453                                                (status & DCD));
454                 if ((status ^ up->prev_status) ^ CTS)
455                         uart_handle_cts_change(&up->port,
456                                                (status & CTS));
457
458                 wake_up_interruptible(&up->port.info->delta_msr_wait);
459         }
460
461         up->prev_status = status;
462 }
463
464 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
465                                     struct zilog_channel __iomem *channel)
466 {
467         struct circ_buf *xmit;
468
469         if (ZS_IS_CONS(up)) {
470                 unsigned char status = readb(&channel->control);
471                 ZSDELAY();
472
473                 /* TX still busy?  Just wait for the next TX done interrupt.
474                  *
475                  * It can occur because of how we do serial console writes.  It would
476                  * be nice to transmit console writes just like we normally would for
477                  * a TTY line. (ie. buffered and TX interrupt driven).  That is not
478                  * easy because console writes cannot sleep.  One solution might be
479                  * to poll on enough port->xmit space becomming free.  -DaveM
480                  */
481                 if (!(status & Tx_BUF_EMP))
482                         return;
483         }
484
485         up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
486
487         if (ZS_REGS_HELD(up)) {
488                 __load_zsregs(channel, up->curregs);
489                 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
490         }
491
492         if (ZS_TX_STOPPED(up)) {
493                 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
494                 goto ack_tx_int;
495         }
496
497         if (up->port.x_char) {
498                 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
499                 writeb(up->port.x_char, &channel->data);
500                 ZSDELAY();
501                 ZS_WSYNC(channel);
502
503                 up->port.icount.tx++;
504                 up->port.x_char = 0;
505                 return;
506         }
507
508         if (up->port.info == NULL)
509                 goto ack_tx_int;
510         xmit = &up->port.info->xmit;
511         if (uart_circ_empty(xmit))
512                 goto ack_tx_int;
513
514         if (uart_tx_stopped(&up->port))
515                 goto ack_tx_int;
516
517         up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
518         writeb(xmit->buf[xmit->tail], &channel->data);
519         ZSDELAY();
520         ZS_WSYNC(channel);
521
522         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
523         up->port.icount.tx++;
524
525         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
526                 uart_write_wakeup(&up->port);
527
528         return;
529
530 ack_tx_int:
531         writeb(RES_Tx_P, &channel->control);
532         ZSDELAY();
533         ZS_WSYNC(channel);
534 }
535
536 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
537 {
538         struct uart_sunzilog_port *up = dev_id;
539
540         while (up) {
541                 struct zilog_channel __iomem *channel
542                         = ZILOG_CHANNEL_FROM_PORT(&up->port);
543                 struct tty_struct *tty;
544                 unsigned char r3;
545
546                 spin_lock(&up->port.lock);
547                 r3 = read_zsreg(channel, R3);
548
549                 /* Channel A */
550                 tty = NULL;
551                 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
552                         writeb(RES_H_IUS, &channel->control);
553                         ZSDELAY();
554                         ZS_WSYNC(channel);
555
556                         if (r3 & CHARxIP)
557                                 tty = sunzilog_receive_chars(up, channel);
558                         if (r3 & CHAEXT)
559                                 sunzilog_status_handle(up, channel);
560                         if (r3 & CHATxIP)
561                                 sunzilog_transmit_chars(up, channel);
562                 }
563                 spin_unlock(&up->port.lock);
564
565                 if (tty)
566                         tty_flip_buffer_push(tty);
567
568                 /* Channel B */
569                 up = up->next;
570                 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
571
572                 spin_lock(&up->port.lock);
573                 tty = NULL;
574                 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
575                         writeb(RES_H_IUS, &channel->control);
576                         ZSDELAY();
577                         ZS_WSYNC(channel);
578
579                         if (r3 & CHBRxIP)
580                                 tty = sunzilog_receive_chars(up, channel);
581                         if (r3 & CHBEXT)
582                                 sunzilog_status_handle(up, channel);
583                         if (r3 & CHBTxIP)
584                                 sunzilog_transmit_chars(up, channel);
585                 }
586                 spin_unlock(&up->port.lock);
587
588                 if (tty)
589                         tty_flip_buffer_push(tty);
590
591                 up = up->next;
592         }
593
594         return IRQ_HANDLED;
595 }
596
597 /* A convenient way to quickly get R0 status.  The caller must _not_ hold the
598  * port lock, it is acquired here.
599  */
600 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
601 {
602         struct zilog_channel __iomem *channel;
603         unsigned char status;
604
605         channel = ZILOG_CHANNEL_FROM_PORT(port);
606         status = readb(&channel->control);
607         ZSDELAY();
608
609         return status;
610 }
611
612 /* The port lock is not held.  */
613 static unsigned int sunzilog_tx_empty(struct uart_port *port)
614 {
615         unsigned long flags;
616         unsigned char status;
617         unsigned int ret;
618
619         spin_lock_irqsave(&port->lock, flags);
620
621         status = sunzilog_read_channel_status(port);
622
623         spin_unlock_irqrestore(&port->lock, flags);
624
625         if (status & Tx_BUF_EMP)
626                 ret = TIOCSER_TEMT;
627         else
628                 ret = 0;
629
630         return ret;
631 }
632
633 /* The port lock is held and interrupts are disabled.  */
634 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
635 {
636         unsigned char status;
637         unsigned int ret;
638
639         status = sunzilog_read_channel_status(port);
640
641         ret = 0;
642         if (status & DCD)
643                 ret |= TIOCM_CAR;
644         if (status & SYNC)
645                 ret |= TIOCM_DSR;
646         if (status & CTS)
647                 ret |= TIOCM_CTS;
648
649         return ret;
650 }
651
652 /* The port lock is held and interrupts are disabled.  */
653 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
654 {
655         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
656         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
657         unsigned char set_bits, clear_bits;
658
659         set_bits = clear_bits = 0;
660
661         if (mctrl & TIOCM_RTS)
662                 set_bits |= RTS;
663         else
664                 clear_bits |= RTS;
665         if (mctrl & TIOCM_DTR)
666                 set_bits |= DTR;
667         else
668                 clear_bits |= DTR;
669
670         /* NOTE: Not subject to 'transmitter active' rule.  */ 
671         up->curregs[R5] |= set_bits;
672         up->curregs[R5] &= ~clear_bits;
673         write_zsreg(channel, R5, up->curregs[R5]);
674 }
675
676 /* The port lock is held and interrupts are disabled.  */
677 static void sunzilog_stop_tx(struct uart_port *port)
678 {
679         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
680
681         up->flags |= SUNZILOG_FLAG_TX_STOPPED;
682 }
683
684 /* The port lock is held and interrupts are disabled.  */
685 static void sunzilog_start_tx(struct uart_port *port)
686 {
687         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
688         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
689         unsigned char status;
690
691         up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
692         up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
693
694         status = readb(&channel->control);
695         ZSDELAY();
696
697         /* TX busy?  Just wait for the TX done interrupt.  */
698         if (!(status & Tx_BUF_EMP))
699                 return;
700
701         /* Send the first character to jump-start the TX done
702          * IRQ sending engine.
703          */
704         if (port->x_char) {
705                 writeb(port->x_char, &channel->data);
706                 ZSDELAY();
707                 ZS_WSYNC(channel);
708
709                 port->icount.tx++;
710                 port->x_char = 0;
711         } else {
712                 struct circ_buf *xmit = &port->info->xmit;
713
714                 writeb(xmit->buf[xmit->tail], &channel->data);
715                 ZSDELAY();
716                 ZS_WSYNC(channel);
717
718                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
719                 port->icount.tx++;
720
721                 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
722                         uart_write_wakeup(&up->port);
723         }
724 }
725
726 /* The port lock is held.  */
727 static void sunzilog_stop_rx(struct uart_port *port)
728 {
729         struct uart_sunzilog_port *up = UART_ZILOG(port);
730         struct zilog_channel __iomem *channel;
731
732         if (ZS_IS_CONS(up))
733                 return;
734
735         channel = ZILOG_CHANNEL_FROM_PORT(port);
736
737         /* Disable all RX interrupts.  */
738         up->curregs[R1] &= ~RxINT_MASK;
739         sunzilog_maybe_update_regs(up, channel);
740 }
741
742 /* The port lock is held.  */
743 static void sunzilog_enable_ms(struct uart_port *port)
744 {
745         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
746         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
747         unsigned char new_reg;
748
749         new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
750         if (new_reg != up->curregs[R15]) {
751                 up->curregs[R15] = new_reg;
752
753                 /* NOTE: Not subject to 'transmitter active' rule.  */ 
754                 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
755         }
756 }
757
758 /* The port lock is not held.  */
759 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
760 {
761         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
762         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
763         unsigned char set_bits, clear_bits, new_reg;
764         unsigned long flags;
765
766         set_bits = clear_bits = 0;
767
768         if (break_state)
769                 set_bits |= SND_BRK;
770         else
771                 clear_bits |= SND_BRK;
772
773         spin_lock_irqsave(&port->lock, flags);
774
775         new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
776         if (new_reg != up->curregs[R5]) {
777                 up->curregs[R5] = new_reg;
778
779                 /* NOTE: Not subject to 'transmitter active' rule.  */ 
780                 write_zsreg(channel, R5, up->curregs[R5]);
781         }
782
783         spin_unlock_irqrestore(&port->lock, flags);
784 }
785
786 static void __sunzilog_startup(struct uart_sunzilog_port *up)
787 {
788         struct zilog_channel __iomem *channel;
789
790         channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
791         up->prev_status = readb(&channel->control);
792
793         /* Enable receiver and transmitter.  */
794         up->curregs[R3] |= RxENAB;
795         up->curregs[R5] |= TxENAB;
796
797         up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
798         sunzilog_maybe_update_regs(up, channel);
799 }
800
801 static int sunzilog_startup(struct uart_port *port)
802 {
803         struct uart_sunzilog_port *up = UART_ZILOG(port);
804         unsigned long flags;
805
806         if (ZS_IS_CONS(up))
807                 return 0;
808
809         spin_lock_irqsave(&port->lock, flags);
810         __sunzilog_startup(up);
811         spin_unlock_irqrestore(&port->lock, flags);
812         return 0;
813 }
814
815 /*
816  * The test for ZS_IS_CONS is explained by the following e-mail:
817  *****
818  * From: Russell King <rmk@arm.linux.org.uk>
819  * Date: Sun, 8 Dec 2002 10:18:38 +0000
820  *
821  * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
822  * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
823  * > and I noticed that something is not right with reference
824  * > counting in this case. It seems that when the console
825  * > is open by kernel initially, this is not accounted
826  * > as an open, and uart_startup is not called.
827  *
828  * That is correct.  We are unable to call uart_startup when the serial
829  * console is initialised because it may need to allocate memory (as
830  * request_irq does) and the memory allocators may not have been
831  * initialised.
832  *
833  * 1. initialise the port into a state where it can send characters in the
834  *    console write method.
835  *
836  * 2. don't do the actual hardware shutdown in your shutdown() method (but
837  *    do the normal software shutdown - ie, free irqs etc)
838  *****
839  */
840 static void sunzilog_shutdown(struct uart_port *port)
841 {
842         struct uart_sunzilog_port *up = UART_ZILOG(port);
843         struct zilog_channel __iomem *channel;
844         unsigned long flags;
845
846         if (ZS_IS_CONS(up))
847                 return;
848
849         spin_lock_irqsave(&port->lock, flags);
850
851         channel = ZILOG_CHANNEL_FROM_PORT(port);
852
853         /* Disable receiver and transmitter.  */
854         up->curregs[R3] &= ~RxENAB;
855         up->curregs[R5] &= ~TxENAB;
856
857         /* Disable all interrupts and BRK assertion.  */
858         up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
859         up->curregs[R5] &= ~SND_BRK;
860         sunzilog_maybe_update_regs(up, channel);
861
862         spin_unlock_irqrestore(&port->lock, flags);
863 }
864
865 /* Shared by TTY driver and serial console setup.  The port lock is held
866  * and local interrupts are disabled.
867  */
868 static void
869 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
870                        unsigned int iflag, int brg)
871 {
872
873         up->curregs[R10] = NRZ;
874         up->curregs[R11] = TCBR | RCBR;
875
876         /* Program BAUD and clock source. */
877         up->curregs[R4] &= ~XCLK_MASK;
878         up->curregs[R4] |= X16CLK;
879         up->curregs[R12] = brg & 0xff;
880         up->curregs[R13] = (brg >> 8) & 0xff;
881         up->curregs[R14] = BRSRC | BRENAB;
882
883         /* Character size, stop bits, and parity. */
884         up->curregs[R3] &= ~RxN_MASK;
885         up->curregs[R5] &= ~TxN_MASK;
886         switch (cflag & CSIZE) {
887         case CS5:
888                 up->curregs[R3] |= Rx5;
889                 up->curregs[R5] |= Tx5;
890                 up->parity_mask = 0x1f;
891                 break;
892         case CS6:
893                 up->curregs[R3] |= Rx6;
894                 up->curregs[R5] |= Tx6;
895                 up->parity_mask = 0x3f;
896                 break;
897         case CS7:
898                 up->curregs[R3] |= Rx7;
899                 up->curregs[R5] |= Tx7;
900                 up->parity_mask = 0x7f;
901                 break;
902         case CS8:
903         default:
904                 up->curregs[R3] |= Rx8;
905                 up->curregs[R5] |= Tx8;
906                 up->parity_mask = 0xff;
907                 break;
908         };
909         up->curregs[R4] &= ~0x0c;
910         if (cflag & CSTOPB)
911                 up->curregs[R4] |= SB2;
912         else
913                 up->curregs[R4] |= SB1;
914         if (cflag & PARENB)
915                 up->curregs[R4] |= PAR_ENAB;
916         else
917                 up->curregs[R4] &= ~PAR_ENAB;
918         if (!(cflag & PARODD))
919                 up->curregs[R4] |= PAR_EVEN;
920         else
921                 up->curregs[R4] &= ~PAR_EVEN;
922
923         up->port.read_status_mask = Rx_OVR;
924         if (iflag & INPCK)
925                 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
926         if (iflag & (BRKINT | PARMRK))
927                 up->port.read_status_mask |= BRK_ABRT;
928
929         up->port.ignore_status_mask = 0;
930         if (iflag & IGNPAR)
931                 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
932         if (iflag & IGNBRK) {
933                 up->port.ignore_status_mask |= BRK_ABRT;
934                 if (iflag & IGNPAR)
935                         up->port.ignore_status_mask |= Rx_OVR;
936         }
937
938         if ((cflag & CREAD) == 0)
939                 up->port.ignore_status_mask = 0xff;
940 }
941
942 /* The port lock is not held.  */
943 static void
944 sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
945                      struct ktermios *old)
946 {
947         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
948         unsigned long flags;
949         int baud, brg;
950
951         baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
952
953         spin_lock_irqsave(&up->port.lock, flags);
954
955         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
956
957         sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
958
959         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
960                 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
961         else
962                 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
963
964         up->cflag = termios->c_cflag;
965
966         sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
967
968         uart_update_timeout(port, termios->c_cflag, baud);
969
970         spin_unlock_irqrestore(&up->port.lock, flags);
971 }
972
973 static const char *sunzilog_type(struct uart_port *port)
974 {
975         struct uart_sunzilog_port *up = UART_ZILOG(port);
976
977         return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
978 }
979
980 /* We do not request/release mappings of the registers here, this
981  * happens at early serial probe time.
982  */
983 static void sunzilog_release_port(struct uart_port *port)
984 {
985 }
986
987 static int sunzilog_request_port(struct uart_port *port)
988 {
989         return 0;
990 }
991
992 /* These do not need to do anything interesting either.  */
993 static void sunzilog_config_port(struct uart_port *port, int flags)
994 {
995 }
996
997 /* We do not support letting the user mess with the divisor, IRQ, etc. */
998 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
999 {
1000         return -EINVAL;
1001 }
1002
1003 static struct uart_ops sunzilog_pops = {
1004         .tx_empty       =       sunzilog_tx_empty,
1005         .set_mctrl      =       sunzilog_set_mctrl,
1006         .get_mctrl      =       sunzilog_get_mctrl,
1007         .stop_tx        =       sunzilog_stop_tx,
1008         .start_tx       =       sunzilog_start_tx,
1009         .stop_rx        =       sunzilog_stop_rx,
1010         .enable_ms      =       sunzilog_enable_ms,
1011         .break_ctl      =       sunzilog_break_ctl,
1012         .startup        =       sunzilog_startup,
1013         .shutdown       =       sunzilog_shutdown,
1014         .set_termios    =       sunzilog_set_termios,
1015         .type           =       sunzilog_type,
1016         .release_port   =       sunzilog_release_port,
1017         .request_port   =       sunzilog_request_port,
1018         .config_port    =       sunzilog_config_port,
1019         .verify_port    =       sunzilog_verify_port,
1020 };
1021
1022 static struct uart_sunzilog_port *sunzilog_port_table;
1023 static struct zilog_layout __iomem **sunzilog_chip_regs;
1024
1025 static struct uart_sunzilog_port *sunzilog_irq_chain;
1026
1027 static struct uart_driver sunzilog_reg = {
1028         .owner          =       THIS_MODULE,
1029         .driver_name    =       "ttyS",
1030         .dev_name       =       "ttyS",
1031         .major          =       TTY_MAJOR,
1032 };
1033
1034 static int __init sunzilog_alloc_tables(void)
1035 {
1036         struct uart_sunzilog_port *up;
1037         unsigned long size;
1038         int i;
1039
1040         size = NUM_CHANNELS * sizeof(struct uart_sunzilog_port);
1041         sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1042         if (!sunzilog_port_table)
1043                 return -ENOMEM;
1044
1045         for (i = 0; i < NUM_CHANNELS; i++) {
1046                 up = &sunzilog_port_table[i];
1047
1048                 spin_lock_init(&up->port.lock);
1049
1050                 if (i == 0)
1051                         sunzilog_irq_chain = up;
1052
1053                 if (i < NUM_CHANNELS - 1)
1054                         up->next = up + 1;
1055                 else
1056                         up->next = NULL;
1057         }
1058
1059         size = NUM_SUNZILOG * sizeof(struct zilog_layout __iomem *);
1060         sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1061         if (!sunzilog_chip_regs) {
1062                 kfree(sunzilog_port_table);
1063                 sunzilog_irq_chain = NULL;
1064                 return -ENOMEM;
1065         }
1066
1067         return 0;
1068 }
1069
1070 static void sunzilog_free_tables(void)
1071 {
1072         kfree(sunzilog_port_table);
1073         sunzilog_irq_chain = NULL;
1074         kfree(sunzilog_chip_regs);
1075 }
1076
1077 #define ZS_PUT_CHAR_MAX_DELAY   2000    /* 10 ms */
1078
1079 static void sunzilog_putchar(struct uart_port *port, int ch)
1080 {
1081         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
1082         int loops = ZS_PUT_CHAR_MAX_DELAY;
1083
1084         /* This is a timed polling loop so do not switch the explicit
1085          * udelay with ZSDELAY as that is a NOP on some platforms.  -DaveM
1086          */
1087         do {
1088                 unsigned char val = readb(&channel->control);
1089                 if (val & Tx_BUF_EMP) {
1090                         ZSDELAY();
1091                         break;
1092                 }
1093                 udelay(5);
1094         } while (--loops);
1095
1096         writeb(ch, &channel->data);
1097         ZSDELAY();
1098         ZS_WSYNC(channel);
1099 }
1100
1101 #ifdef CONFIG_SERIO
1102
1103 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1104
1105 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1106 {
1107         struct uart_sunzilog_port *up = serio->port_data;
1108         unsigned long flags;
1109
1110         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1111
1112         sunzilog_putchar(&up->port, ch);
1113
1114         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1115
1116         return 0;
1117 }
1118
1119 static int sunzilog_serio_open(struct serio *serio)
1120 {
1121         struct uart_sunzilog_port *up = serio->port_data;
1122         unsigned long flags;
1123         int ret;
1124
1125         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1126         if (!up->serio_open) {
1127                 up->serio_open = 1;
1128                 ret = 0;
1129         } else
1130                 ret = -EBUSY;
1131         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1132
1133         return ret;
1134 }
1135
1136 static void sunzilog_serio_close(struct serio *serio)
1137 {
1138         struct uart_sunzilog_port *up = serio->port_data;
1139         unsigned long flags;
1140
1141         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1142         up->serio_open = 0;
1143         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1144 }
1145
1146 #endif /* CONFIG_SERIO */
1147
1148 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1149 static void
1150 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1151 {
1152         struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1153         unsigned long flags;
1154         int locked = 1;
1155
1156         local_irq_save(flags);
1157         if (up->port.sysrq) {
1158                 locked = 0;
1159         } else if (oops_in_progress) {
1160                 locked = spin_trylock(&up->port.lock);
1161         } else
1162                 spin_lock(&up->port.lock);
1163
1164         uart_console_write(&up->port, s, count, sunzilog_putchar);
1165         udelay(2);
1166
1167         if (locked)
1168                 spin_unlock(&up->port.lock);
1169         local_irq_restore(flags);
1170 }
1171
1172 static int __init sunzilog_console_setup(struct console *con, char *options)
1173 {
1174         struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1175         unsigned long flags;
1176         int baud, brg;
1177
1178         if (up->port.type != PORT_SUNZILOG)
1179                 return -1;
1180
1181         printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1182                (sunzilog_reg.minor - 64) + con->index, con->index);
1183
1184         /* Get firmware console settings.  */
1185         sunserial_console_termios(con);
1186
1187         /* Firmware console speed is limited to 150-->38400 baud so
1188          * this hackish cflag thing is OK.
1189          */
1190         switch (con->cflag & CBAUD) {
1191         case B150: baud = 150; break;
1192         case B300: baud = 300; break;
1193         case B600: baud = 600; break;
1194         case B1200: baud = 1200; break;
1195         case B2400: baud = 2400; break;
1196         case B4800: baud = 4800; break;
1197         default: case B9600: baud = 9600; break;
1198         case B19200: baud = 19200; break;
1199         case B38400: baud = 38400; break;
1200         };
1201
1202         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1203
1204         spin_lock_irqsave(&up->port.lock, flags);
1205
1206         up->curregs[R15] |= BRKIE;
1207         sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1208
1209         sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1210         __sunzilog_startup(up);
1211
1212         spin_unlock_irqrestore(&up->port.lock, flags);
1213
1214         return 0;
1215 }
1216
1217 static struct console sunzilog_console_ops = {
1218         .name   =       "ttyS",
1219         .write  =       sunzilog_console_write,
1220         .device =       uart_console_device,
1221         .setup  =       sunzilog_console_setup,
1222         .flags  =       CON_PRINTBUFFER,
1223         .index  =       -1,
1224         .data   =       &sunzilog_reg,
1225 };
1226
1227 static inline struct console *SUNZILOG_CONSOLE(void)
1228 {
1229         return &sunzilog_console_ops;
1230 }
1231
1232 #else
1233 #define SUNZILOG_CONSOLE()      (NULL)
1234 #endif
1235
1236 static void __devinit sunzilog_init_kbdms(struct uart_sunzilog_port *up, int channel)
1237 {
1238         int baud, brg;
1239
1240         if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1241                 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1242                 baud = 1200;
1243         } else {
1244                 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1245                 baud = 4800;
1246         }
1247
1248         up->curregs[R15] |= BRKIE;
1249         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1250         sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1251         sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1252         __sunzilog_startup(up);
1253 }
1254
1255 #ifdef CONFIG_SERIO
1256 static void __devinit sunzilog_register_serio(struct uart_sunzilog_port *up)
1257 {
1258         struct serio *serio = &up->serio;
1259
1260         serio->port_data = up;
1261
1262         serio->id.type = SERIO_RS232;
1263         if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1264                 serio->id.proto = SERIO_SUNKBD;
1265                 strlcpy(serio->name, "zskbd", sizeof(serio->name));
1266         } else {
1267                 serio->id.proto = SERIO_SUN;
1268                 serio->id.extra = 1;
1269                 strlcpy(serio->name, "zsms", sizeof(serio->name));
1270         }
1271         strlcpy(serio->phys,
1272                 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1273                  "zs/serio0" : "zs/serio1"),
1274                 sizeof(serio->phys));
1275
1276         serio->write = sunzilog_serio_write;
1277         serio->open = sunzilog_serio_open;
1278         serio->close = sunzilog_serio_close;
1279         serio->dev.parent = up->port.dev;
1280
1281         serio_register_port(serio);
1282 }
1283 #endif
1284
1285 static void __devinit sunzilog_init_hw(struct uart_sunzilog_port *up)
1286 {
1287         struct zilog_channel __iomem *channel;
1288         unsigned long flags;
1289         int baud, brg;
1290
1291         channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1292
1293         spin_lock_irqsave(&up->port.lock, flags);
1294         if (ZS_IS_CHANNEL_A(up)) {
1295                 write_zsreg(channel, R9, FHWRES);
1296                 ZSDELAY_LONG();
1297                 (void) read_zsreg(channel, R0);
1298         }
1299
1300         if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1301                          SUNZILOG_FLAG_CONS_MOUSE)) {
1302                 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1303                 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1304                 up->curregs[R3] = RxENAB | Rx8;
1305                 up->curregs[R5] = TxENAB | Tx8;
1306                 up->curregs[R6] = 0x00; /* SDLC Address */
1307                 up->curregs[R7] = 0x7E; /* SDLC Flag    */
1308                 up->curregs[R9] = NV;
1309                 up->curregs[R7p] = 0x00;
1310                 sunzilog_init_kbdms(up, up->port.line);
1311                 /* Only enable interrupts if an ISR handler available */
1312                 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1313                         up->curregs[R9] |= MIE;
1314                 write_zsreg(channel, R9, up->curregs[R9]);
1315         } else {
1316                 /* Normal serial TTY. */
1317                 up->parity_mask = 0xff;
1318                 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1319                 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1320                 up->curregs[R3] = RxENAB | Rx8;
1321                 up->curregs[R5] = TxENAB | Tx8;
1322                 up->curregs[R6] = 0x00; /* SDLC Address */
1323                 up->curregs[R7] = 0x7E; /* SDLC Flag    */
1324                 up->curregs[R9] = NV;
1325                 up->curregs[R10] = NRZ;
1326                 up->curregs[R11] = TCBR | RCBR;
1327                 baud = 9600;
1328                 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1329                 up->curregs[R12] = (brg & 0xff);
1330                 up->curregs[R13] = (brg >> 8) & 0xff;
1331                 up->curregs[R14] = BRSRC | BRENAB;
1332                 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1333                 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1334                 if (__load_zsregs(channel, up->curregs)) {
1335                         up->flags |= SUNZILOG_FLAG_ESCC;
1336                 }
1337                 /* Only enable interrupts if an ISR handler available */
1338                 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1339                         up->curregs[R9] |= MIE;
1340                 write_zsreg(channel, R9, up->curregs[R9]);
1341         }
1342
1343         spin_unlock_irqrestore(&up->port.lock, flags);
1344
1345 #ifdef CONFIG_SERIO
1346         if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1347                          SUNZILOG_FLAG_CONS_MOUSE))
1348                 sunzilog_register_serio(up);
1349 #endif
1350 }
1351
1352 static int zilog_irq = -1;
1353
1354 static int __devinit zs_probe(struct of_device *op, const struct of_device_id *match)
1355 {
1356         static int inst;
1357         struct uart_sunzilog_port *up;
1358         struct zilog_layout __iomem *rp;
1359         int keyboard_mouse;
1360         int err;
1361
1362         keyboard_mouse = 0;
1363         if (of_find_property(op->node, "keyboard", NULL))
1364                 keyboard_mouse = 1;
1365
1366         sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1367                                               sizeof(struct zilog_layout),
1368                                               "zs");
1369         if (!sunzilog_chip_regs[inst])
1370                 return -ENOMEM;
1371
1372         rp = sunzilog_chip_regs[inst];
1373
1374         if (zilog_irq == -1)
1375                 zilog_irq = op->irqs[0];
1376
1377         up = &sunzilog_port_table[inst * 2];
1378
1379         /* Channel A */
1380         up[0].port.mapbase = op->resource[0].start + 0x00;
1381         up[0].port.membase = (void __iomem *) &rp->channelA;
1382         up[0].port.iotype = UPIO_MEM;
1383         up[0].port.irq = op->irqs[0];
1384         up[0].port.uartclk = ZS_CLOCK;
1385         up[0].port.fifosize = 1;
1386         up[0].port.ops = &sunzilog_pops;
1387         up[0].port.type = PORT_SUNZILOG;
1388         up[0].port.flags = 0;
1389         up[0].port.line = (inst * 2) + 0;
1390         up[0].port.dev = &op->dev;
1391         up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1392         if (keyboard_mouse)
1393                 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1394         sunzilog_init_hw(&up[0]);
1395
1396         /* Channel B */
1397         up[1].port.mapbase = op->resource[0].start + 0x04;
1398         up[1].port.membase = (void __iomem *) &rp->channelB;
1399         up[1].port.iotype = UPIO_MEM;
1400         up[1].port.irq = op->irqs[0];
1401         up[1].port.uartclk = ZS_CLOCK;
1402         up[1].port.fifosize = 1;
1403         up[1].port.ops = &sunzilog_pops;
1404         up[1].port.type = PORT_SUNZILOG;
1405         up[1].port.flags = 0;
1406         up[1].port.line = (inst * 2) + 1;
1407         up[1].port.dev = &op->dev;
1408         up[1].flags |= 0;
1409         if (keyboard_mouse)
1410                 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1411         sunzilog_init_hw(&up[1]);
1412
1413         if (!keyboard_mouse) {
1414                 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->node,
1415                                             &sunzilog_reg, up[0].port.line))
1416                         up->flags |= SUNZILOG_FLAG_IS_CONS;
1417                 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1418                 if (err) {
1419                         of_iounmap(&op->resource[0],
1420                                    rp, sizeof(struct zilog_layout));
1421                         return err;
1422                 }
1423                 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->node,
1424                                             &sunzilog_reg, up[1].port.line))
1425                         up->flags |= SUNZILOG_FLAG_IS_CONS;
1426                 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1427                 if (err) {
1428                         uart_remove_one_port(&sunzilog_reg, &up[0].port);
1429                         of_iounmap(&op->resource[0],
1430                                    rp, sizeof(struct zilog_layout));
1431                         return err;
1432                 }
1433         } else {
1434                 printk(KERN_INFO "%s: Keyboard at MMIO 0x%lx (irq = %d) "
1435                        "is a %s\n",
1436                        op->dev.bus_id, up[0].port.mapbase, op->irqs[0],
1437                        sunzilog_type (&up[0].port));
1438                 printk(KERN_INFO "%s: Mouse at MMIO 0x%lx (irq = %d) "
1439                        "is a %s\n",
1440                        op->dev.bus_id, up[1].port.mapbase, op->irqs[0],
1441                        sunzilog_type (&up[1].port));
1442         }
1443
1444         dev_set_drvdata(&op->dev, &up[0]);
1445
1446         inst++;
1447
1448         return 0;
1449 }
1450
1451 static void __devexit zs_remove_one(struct uart_sunzilog_port *up)
1452 {
1453         if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1454 #ifdef CONFIG_SERIO
1455                 serio_unregister_port(&up->serio);
1456 #endif
1457         } else
1458                 uart_remove_one_port(&sunzilog_reg, &up->port);
1459 }
1460
1461 static int __devexit zs_remove(struct of_device *op)
1462 {
1463         struct uart_sunzilog_port *up = dev_get_drvdata(&op->dev);
1464         struct zilog_layout __iomem *regs;
1465
1466         zs_remove_one(&up[0]);
1467         zs_remove_one(&up[1]);
1468
1469         regs = sunzilog_chip_regs[up[0].port.line / 2];
1470         of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
1471
1472         dev_set_drvdata(&op->dev, NULL);
1473
1474         return 0;
1475 }
1476
1477 static struct of_device_id zs_match[] = {
1478         {
1479                 .name = "zs",
1480         },
1481         {},
1482 };
1483 MODULE_DEVICE_TABLE(of, zs_match);
1484
1485 static struct of_platform_driver zs_driver = {
1486         .name           = "zs",
1487         .match_table    = zs_match,
1488         .probe          = zs_probe,
1489         .remove         = __devexit_p(zs_remove),
1490 };
1491
1492 static int __init sunzilog_init(void)
1493 {
1494         struct device_node *dp;
1495         int err, uart_count;
1496         int num_keybms;
1497
1498         NUM_SUNZILOG = 0;
1499         num_keybms = 0;
1500         for_each_node_by_name(dp, "zs") {
1501                 NUM_SUNZILOG++;
1502                 if (of_find_property(dp, "keyboard", NULL))
1503                         num_keybms++;
1504         }
1505
1506         uart_count = 0;
1507         if (NUM_SUNZILOG) {
1508                 int uart_count;
1509
1510                 err = sunzilog_alloc_tables();
1511                 if (err)
1512                         goto out;
1513
1514                 uart_count = (NUM_SUNZILOG * 2) - (2 * num_keybms);
1515
1516                 sunzilog_reg.nr = uart_count;
1517                 sunzilog_reg.minor = sunserial_current_minor;
1518                 err = uart_register_driver(&sunzilog_reg);
1519                 if (err)
1520                         goto out_free_tables;
1521
1522                 sunzilog_reg.tty_driver->name_base = sunzilog_reg.minor - 64;
1523
1524                 sunserial_current_minor += uart_count;
1525         }
1526
1527         err = of_register_driver(&zs_driver, &of_bus_type);
1528         if (err)
1529                 goto out_unregister_uart;
1530
1531         if (zilog_irq != -1) {
1532                 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1533                 err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1534                                   "zs", sunzilog_irq_chain);
1535                 if (err)
1536                         goto out_unregister_driver;
1537
1538                 /* Enable Interrupts */
1539                 while (up) {
1540                         struct zilog_channel __iomem *channel;
1541
1542                         /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1543                         channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1544                         up->flags       |= SUNZILOG_FLAG_ISR_HANDLER;
1545                         up->curregs[R9] |= MIE;
1546                         write_zsreg(channel, R9, up->curregs[R9]);
1547                         up = up->next;
1548                 }
1549         }
1550
1551 out:
1552         return err;
1553
1554 out_unregister_driver:
1555         of_unregister_driver(&zs_driver);
1556
1557 out_unregister_uart:
1558         if (NUM_SUNZILOG) {
1559                 uart_unregister_driver(&sunzilog_reg);
1560                 sunzilog_reg.cons = NULL;
1561         }
1562
1563 out_free_tables:
1564         sunzilog_free_tables();
1565         goto out;
1566 }
1567
1568 static void __exit sunzilog_exit(void)
1569 {
1570         of_unregister_driver(&zs_driver);
1571
1572         if (zilog_irq != -1) {
1573                 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1574
1575                 /* Disable Interrupts */
1576                 while (up) {
1577                         struct zilog_channel __iomem *channel;
1578
1579                         /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1580                         channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1581                         up->flags       &= ~SUNZILOG_FLAG_ISR_HANDLER;
1582                         up->curregs[R9] &= ~MIE;
1583                         write_zsreg(channel, R9, up->curregs[R9]);
1584                         up = up->next;
1585                 }
1586
1587                 free_irq(zilog_irq, sunzilog_irq_chain);
1588                 zilog_irq = -1;
1589         }
1590
1591         if (NUM_SUNZILOG) {
1592                 uart_unregister_driver(&sunzilog_reg);
1593                 sunzilog_free_tables();
1594         }
1595 }
1596
1597 module_init(sunzilog_init);
1598 module_exit(sunzilog_exit);
1599
1600 MODULE_AUTHOR("David S. Miller");
1601 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1602 MODULE_VERSION("2.0");
1603 MODULE_LICENSE("GPL");