pci: use pci_ioremap_bar() in drivers/serial
[linux-2.6.git] / drivers / serial / 8250_pci.c
1 /*
2  *  linux/drivers/char/8250_pci.c
3  *
4  *  Probe module for 8250/16550-type PCI serial ports.
5  *
6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7  *
8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License.
13  */
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/tty.h>
22 #include <linux/serial_core.h>
23 #include <linux/8250_pci.h>
24 #include <linux/bitops.h>
25
26 #include <asm/byteorder.h>
27 #include <asm/io.h>
28
29 #include "8250.h"
30
31 #undef SERIAL_DEBUG_PCI
32
33 /*
34  * init function returns:
35  *  > 0 - number of ports
36  *  = 0 - use board->num_ports
37  *  < 0 - error
38  */
39 struct pci_serial_quirk {
40         u32     vendor;
41         u32     device;
42         u32     subvendor;
43         u32     subdevice;
44         int     (*init)(struct pci_dev *dev);
45         int     (*setup)(struct serial_private *,
46                          const struct pciserial_board *,
47                          struct uart_port *, int);
48         void    (*exit)(struct pci_dev *dev);
49 };
50
51 #define PCI_NUM_BAR_RESOURCES   6
52
53 struct serial_private {
54         struct pci_dev          *dev;
55         unsigned int            nr;
56         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
57         struct pci_serial_quirk *quirk;
58         int                     line[0];
59 };
60
61 static void moan_device(const char *str, struct pci_dev *dev)
62 {
63         printk(KERN_WARNING "%s: %s\n"
64                KERN_WARNING "Please send the output of lspci -vv, this\n"
65                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
66                KERN_WARNING "manufacturer and name of serial board or\n"
67                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
68                pci_name(dev), str, dev->vendor, dev->device,
69                dev->subsystem_vendor, dev->subsystem_device);
70 }
71
72 static int
73 setup_port(struct serial_private *priv, struct uart_port *port,
74            int bar, int offset, int regshift)
75 {
76         struct pci_dev *dev = priv->dev;
77         unsigned long base, len;
78
79         if (bar >= PCI_NUM_BAR_RESOURCES)
80                 return -EINVAL;
81
82         base = pci_resource_start(dev, bar);
83
84         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
85                 len =  pci_resource_len(dev, bar);
86
87                 if (!priv->remapped_bar[bar])
88                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
89                 if (!priv->remapped_bar[bar])
90                         return -ENOMEM;
91
92                 port->iotype = UPIO_MEM;
93                 port->iobase = 0;
94                 port->mapbase = base + offset;
95                 port->membase = priv->remapped_bar[bar] + offset;
96                 port->regshift = regshift;
97         } else {
98                 port->iotype = UPIO_PORT;
99                 port->iobase = base + offset;
100                 port->mapbase = 0;
101                 port->membase = NULL;
102                 port->regshift = 0;
103         }
104         return 0;
105 }
106
107 /*
108  * ADDI-DATA GmbH communication cards <info@addi-data.com>
109  */
110 static int addidata_apci7800_setup(struct serial_private *priv,
111                                 const struct pciserial_board *board,
112                                 struct uart_port *port, int idx)
113 {
114         unsigned int bar = 0, offset = board->first_offset;
115         bar = FL_GET_BASE(board->flags);
116
117         if (idx < 2) {
118                 offset += idx * board->uart_offset;
119         } else if ((idx >= 2) && (idx < 4)) {
120                 bar += 1;
121                 offset += ((idx - 2) * board->uart_offset);
122         } else if ((idx >= 4) && (idx < 6)) {
123                 bar += 2;
124                 offset += ((idx - 4) * board->uart_offset);
125         } else if (idx >= 6) {
126                 bar += 3;
127                 offset += ((idx - 6) * board->uart_offset);
128         }
129
130         return setup_port(priv, port, bar, offset, board->reg_shift);
131 }
132
133 /*
134  * AFAVLAB uses a different mixture of BARs and offsets
135  * Not that ugly ;) -- HW
136  */
137 static int
138 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
139               struct uart_port *port, int idx)
140 {
141         unsigned int bar, offset = board->first_offset;
142
143         bar = FL_GET_BASE(board->flags);
144         if (idx < 4)
145                 bar += idx;
146         else {
147                 bar = 4;
148                 offset += (idx - 4) * board->uart_offset;
149         }
150
151         return setup_port(priv, port, bar, offset, board->reg_shift);
152 }
153
154 /*
155  * HP's Remote Management Console.  The Diva chip came in several
156  * different versions.  N-class, L2000 and A500 have two Diva chips, each
157  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
158  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
159  * one Diva chip, but it has been expanded to 5 UARTs.
160  */
161 static int pci_hp_diva_init(struct pci_dev *dev)
162 {
163         int rc = 0;
164
165         switch (dev->subsystem_device) {
166         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
167         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
168         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
169         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
170                 rc = 3;
171                 break;
172         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
173                 rc = 2;
174                 break;
175         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
176                 rc = 4;
177                 break;
178         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
179         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
180                 rc = 1;
181                 break;
182         }
183
184         return rc;
185 }
186
187 /*
188  * HP's Diva chip puts the 4th/5th serial port further out, and
189  * some serial ports are supposed to be hidden on certain models.
190  */
191 static int
192 pci_hp_diva_setup(struct serial_private *priv,
193                 const struct pciserial_board *board,
194                 struct uart_port *port, int idx)
195 {
196         unsigned int offset = board->first_offset;
197         unsigned int bar = FL_GET_BASE(board->flags);
198
199         switch (priv->dev->subsystem_device) {
200         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
201                 if (idx == 3)
202                         idx++;
203                 break;
204         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
205                 if (idx > 0)
206                         idx++;
207                 if (idx > 2)
208                         idx++;
209                 break;
210         }
211         if (idx > 2)
212                 offset = 0x18;
213
214         offset += idx * board->uart_offset;
215
216         return setup_port(priv, port, bar, offset, board->reg_shift);
217 }
218
219 /*
220  * Added for EKF Intel i960 serial boards
221  */
222 static int pci_inteli960ni_init(struct pci_dev *dev)
223 {
224         unsigned long oldval;
225
226         if (!(dev->subsystem_device & 0x1000))
227                 return -ENODEV;
228
229         /* is firmware started? */
230         pci_read_config_dword(dev, 0x44, (void *)&oldval);
231         if (oldval == 0x00001000L) { /* RESET value */
232                 printk(KERN_DEBUG "Local i960 firmware missing");
233                 return -ENODEV;
234         }
235         return 0;
236 }
237
238 /*
239  * Some PCI serial cards using the PLX 9050 PCI interface chip require
240  * that the card interrupt be explicitly enabled or disabled.  This
241  * seems to be mainly needed on card using the PLX which also use I/O
242  * mapped memory.
243  */
244 static int pci_plx9050_init(struct pci_dev *dev)
245 {
246         u8 irq_config;
247         void __iomem *p;
248
249         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250                 moan_device("no memory in bar 0", dev);
251                 return 0;
252         }
253
254         irq_config = 0x41;
255         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
256             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
257                 irq_config = 0x43;
258
259         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
260             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
261                 /*
262                  * As the megawolf cards have the int pins active
263                  * high, and have 2 UART chips, both ints must be
264                  * enabled on the 9050. Also, the UARTS are set in
265                  * 16450 mode by default, so we have to enable the
266                  * 16C950 'enhanced' mode so that we can use the
267                  * deep FIFOs
268                  */
269                 irq_config = 0x5b;
270         /*
271          * enable/disable interrupts
272          */
273         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
274         if (p == NULL)
275                 return -ENOMEM;
276         writel(irq_config, p + 0x4c);
277
278         /*
279          * Read the register back to ensure that it took effect.
280          */
281         readl(p + 0x4c);
282         iounmap(p);
283
284         return 0;
285 }
286
287 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
288 {
289         u8 __iomem *p;
290
291         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292                 return;
293
294         /*
295          * disable interrupts
296          */
297         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
298         if (p != NULL) {
299                 writel(0, p + 0x4c);
300
301                 /*
302                  * Read the register back to ensure that it took effect.
303                  */
304                 readl(p + 0x4c);
305                 iounmap(p);
306         }
307 }
308
309 #define NI8420_INT_ENABLE_REG   0x38
310 #define NI8420_INT_ENABLE_BIT   0x2000
311
312 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
313 {
314         void __iomem *p;
315         unsigned long base, len;
316         unsigned int bar = 0;
317
318         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
319                 moan_device("no memory in bar", dev);
320                 return;
321         }
322
323         base = pci_resource_start(dev, bar);
324         len =  pci_resource_len(dev, bar);
325         p = ioremap_nocache(base, len);
326         if (p == NULL)
327                 return;
328
329         /* Disable the CPU Interrupt */
330         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
331                p + NI8420_INT_ENABLE_REG);
332         iounmap(p);
333 }
334
335
336 /* MITE registers */
337 #define MITE_IOWBSR1    0xc4
338 #define MITE_IOWCR1     0xf4
339 #define MITE_LCIMR1     0x08
340 #define MITE_LCIMR2     0x10
341
342 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
343
344 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
345 {
346         void __iomem *p;
347         unsigned long base, len;
348         unsigned int bar = 0;
349
350         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
351                 moan_device("no memory in bar", dev);
352                 return;
353         }
354
355         base = pci_resource_start(dev, bar);
356         len =  pci_resource_len(dev, bar);
357         p = ioremap_nocache(base, len);
358         if (p == NULL)
359                 return;
360
361         /* Disable the CPU Interrupt */
362         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
363         iounmap(p);
364 }
365
366 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
367 static int
368 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
369                 struct uart_port *port, int idx)
370 {
371         unsigned int bar, offset = board->first_offset;
372
373         bar = 0;
374
375         if (idx < 4) {
376                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
377                 offset += idx * board->uart_offset;
378         } else if (idx < 8) {
379                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
380                 offset += idx * board->uart_offset + 0xC00;
381         } else /* we have only 8 ports on PMC-OCTALPRO */
382                 return 1;
383
384         return setup_port(priv, port, bar, offset, board->reg_shift);
385 }
386
387 /*
388 * This does initialization for PMC OCTALPRO cards:
389 * maps the device memory, resets the UARTs (needed, bc
390 * if the module is removed and inserted again, the card
391 * is in the sleep mode) and enables global interrupt.
392 */
393
394 /* global control register offset for SBS PMC-OctalPro */
395 #define OCT_REG_CR_OFF          0x500
396
397 static int sbs_init(struct pci_dev *dev)
398 {
399         u8 __iomem *p;
400
401         p = pci_ioremap_bar(dev, 0);
402
403         if (p == NULL)
404                 return -ENOMEM;
405         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
406         writeb(0x10, p + OCT_REG_CR_OFF);
407         udelay(50);
408         writeb(0x0, p + OCT_REG_CR_OFF);
409
410         /* Set bit-2 (INTENABLE) of Control Register */
411         writeb(0x4, p + OCT_REG_CR_OFF);
412         iounmap(p);
413
414         return 0;
415 }
416
417 /*
418  * Disables the global interrupt of PMC-OctalPro
419  */
420
421 static void __devexit sbs_exit(struct pci_dev *dev)
422 {
423         u8 __iomem *p;
424
425         p = pci_ioremap_bar(dev, 0);
426         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
427         if (p != NULL)
428                 writeb(0, p + OCT_REG_CR_OFF);
429         iounmap(p);
430 }
431
432 /*
433  * SIIG serial cards have an PCI interface chip which also controls
434  * the UART clocking frequency. Each UART can be clocked independently
435  * (except cards equiped with 4 UARTs) and initial clocking settings
436  * are stored in the EEPROM chip. It can cause problems because this
437  * version of serial driver doesn't support differently clocked UART's
438  * on single PCI card. To prevent this, initialization functions set
439  * high frequency clocking for all UART's on given card. It is safe (I
440  * hope) because it doesn't touch EEPROM settings to prevent conflicts
441  * with other OSes (like M$ DOS).
442  *
443  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
444  *
445  * There is two family of SIIG serial cards with different PCI
446  * interface chip and different configuration methods:
447  *     - 10x cards have control registers in IO and/or memory space;
448  *     - 20x cards have control registers in standard PCI configuration space.
449  *
450  * Note: all 10x cards have PCI device ids 0x10..
451  *       all 20x cards have PCI device ids 0x20..
452  *
453  * There are also Quartet Serial cards which use Oxford Semiconductor
454  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
455  *
456  * Note: some SIIG cards are probed by the parport_serial object.
457  */
458
459 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
460 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
461
462 static int pci_siig10x_init(struct pci_dev *dev)
463 {
464         u16 data;
465         void __iomem *p;
466
467         switch (dev->device & 0xfff8) {
468         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
469                 data = 0xffdf;
470                 break;
471         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
472                 data = 0xf7ff;
473                 break;
474         default:                        /* 1S1P, 4S */
475                 data = 0xfffb;
476                 break;
477         }
478
479         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
480         if (p == NULL)
481                 return -ENOMEM;
482
483         writew(readw(p + 0x28) & data, p + 0x28);
484         readw(p + 0x28);
485         iounmap(p);
486         return 0;
487 }
488
489 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
490 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
491
492 static int pci_siig20x_init(struct pci_dev *dev)
493 {
494         u8 data;
495
496         /* Change clock frequency for the first UART. */
497         pci_read_config_byte(dev, 0x6f, &data);
498         pci_write_config_byte(dev, 0x6f, data & 0xef);
499
500         /* If this card has 2 UART, we have to do the same with second UART. */
501         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
502             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
503                 pci_read_config_byte(dev, 0x73, &data);
504                 pci_write_config_byte(dev, 0x73, data & 0xef);
505         }
506         return 0;
507 }
508
509 static int pci_siig_init(struct pci_dev *dev)
510 {
511         unsigned int type = dev->device & 0xff00;
512
513         if (type == 0x1000)
514                 return pci_siig10x_init(dev);
515         else if (type == 0x2000)
516                 return pci_siig20x_init(dev);
517
518         moan_device("Unknown SIIG card", dev);
519         return -ENODEV;
520 }
521
522 static int pci_siig_setup(struct serial_private *priv,
523                           const struct pciserial_board *board,
524                           struct uart_port *port, int idx)
525 {
526         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
527
528         if (idx > 3) {
529                 bar = 4;
530                 offset = (idx - 4) * 8;
531         }
532
533         return setup_port(priv, port, bar, offset, 0);
534 }
535
536 /*
537  * Timedia has an explosion of boards, and to avoid the PCI table from
538  * growing *huge*, we use this function to collapse some 70 entries
539  * in the PCI table into one, for sanity's and compactness's sake.
540  */
541 static const unsigned short timedia_single_port[] = {
542         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
543 };
544
545 static const unsigned short timedia_dual_port[] = {
546         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
547         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
548         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
549         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
550         0xD079, 0
551 };
552
553 static const unsigned short timedia_quad_port[] = {
554         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
555         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
556         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
557         0xB157, 0
558 };
559
560 static const unsigned short timedia_eight_port[] = {
561         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
562         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
563 };
564
565 static const struct timedia_struct {
566         int num;
567         const unsigned short *ids;
568 } timedia_data[] = {
569         { 1, timedia_single_port },
570         { 2, timedia_dual_port },
571         { 4, timedia_quad_port },
572         { 8, timedia_eight_port }
573 };
574
575 static int pci_timedia_init(struct pci_dev *dev)
576 {
577         const unsigned short *ids;
578         int i, j;
579
580         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
581                 ids = timedia_data[i].ids;
582                 for (j = 0; ids[j]; j++)
583                         if (dev->subsystem_device == ids[j])
584                                 return timedia_data[i].num;
585         }
586         return 0;
587 }
588
589 /*
590  * Timedia/SUNIX uses a mixture of BARs and offsets
591  * Ugh, this is ugly as all hell --- TYT
592  */
593 static int
594 pci_timedia_setup(struct serial_private *priv,
595                   const struct pciserial_board *board,
596                   struct uart_port *port, int idx)
597 {
598         unsigned int bar = 0, offset = board->first_offset;
599
600         switch (idx) {
601         case 0:
602                 bar = 0;
603                 break;
604         case 1:
605                 offset = board->uart_offset;
606                 bar = 0;
607                 break;
608         case 2:
609                 bar = 1;
610                 break;
611         case 3:
612                 offset = board->uart_offset;
613                 /* FALLTHROUGH */
614         case 4: /* BAR 2 */
615         case 5: /* BAR 3 */
616         case 6: /* BAR 4 */
617         case 7: /* BAR 5 */
618                 bar = idx - 2;
619         }
620
621         return setup_port(priv, port, bar, offset, board->reg_shift);
622 }
623
624 /*
625  * Some Titan cards are also a little weird
626  */
627 static int
628 titan_400l_800l_setup(struct serial_private *priv,
629                       const struct pciserial_board *board,
630                       struct uart_port *port, int idx)
631 {
632         unsigned int bar, offset = board->first_offset;
633
634         switch (idx) {
635         case 0:
636                 bar = 1;
637                 break;
638         case 1:
639                 bar = 2;
640                 break;
641         default:
642                 bar = 4;
643                 offset = (idx - 2) * board->uart_offset;
644         }
645
646         return setup_port(priv, port, bar, offset, board->reg_shift);
647 }
648
649 static int pci_xircom_init(struct pci_dev *dev)
650 {
651         msleep(100);
652         return 0;
653 }
654
655 static int pci_ni8420_init(struct pci_dev *dev)
656 {
657         void __iomem *p;
658         unsigned long base, len;
659         unsigned int bar = 0;
660
661         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
662                 moan_device("no memory in bar", dev);
663                 return 0;
664         }
665
666         base = pci_resource_start(dev, bar);
667         len =  pci_resource_len(dev, bar);
668         p = ioremap_nocache(base, len);
669         if (p == NULL)
670                 return -ENOMEM;
671
672         /* Enable CPU Interrupt */
673         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
674                p + NI8420_INT_ENABLE_REG);
675
676         iounmap(p);
677         return 0;
678 }
679
680 #define MITE_IOWBSR1_WSIZE      0xa
681 #define MITE_IOWBSR1_WIN_OFFSET 0x800
682 #define MITE_IOWBSR1_WENAB      (1 << 7)
683 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
684 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
685 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
686
687 static int pci_ni8430_init(struct pci_dev *dev)
688 {
689         void __iomem *p;
690         unsigned long base, len;
691         u32 device_window;
692         unsigned int bar = 0;
693
694         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
695                 moan_device("no memory in bar", dev);
696                 return 0;
697         }
698
699         base = pci_resource_start(dev, bar);
700         len =  pci_resource_len(dev, bar);
701         p = ioremap_nocache(base, len);
702         if (p == NULL)
703                 return -ENOMEM;
704
705         /* Set device window address and size in BAR0 */
706         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
707                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
708         writel(device_window, p + MITE_IOWBSR1);
709
710         /* Set window access to go to RAMSEL IO address space */
711         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
712                p + MITE_IOWCR1);
713
714         /* Enable IO Bus Interrupt 0 */
715         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
716
717         /* Enable CPU Interrupt */
718         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
719
720         iounmap(p);
721         return 0;
722 }
723
724 /* UART Port Control Register */
725 #define NI8430_PORTCON  0x0f
726 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
727
728 static int
729 pci_ni8430_setup(struct serial_private *priv,
730                  const struct pciserial_board *board,
731                  struct uart_port *port, int idx)
732 {
733         void __iomem *p;
734         unsigned long base, len;
735         unsigned int bar, offset = board->first_offset;
736
737         if (idx >= board->num_ports)
738                 return 1;
739
740         bar = FL_GET_BASE(board->flags);
741         offset += idx * board->uart_offset;
742
743         base = pci_resource_start(priv->dev, bar);
744         len =  pci_resource_len(priv->dev, bar);
745         p = ioremap_nocache(base, len);
746
747         /* enable the transciever */
748         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
749                p + offset + NI8430_PORTCON);
750
751         iounmap(p);
752
753         return setup_port(priv, port, bar, offset, board->reg_shift);
754 }
755
756
757 static int pci_netmos_init(struct pci_dev *dev)
758 {
759         /* subdevice 0x00PS means <P> parallel, <S> serial */
760         unsigned int num_serial = dev->subsystem_device & 0xf;
761
762         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
763                         dev->subsystem_device == 0x0299)
764                 return 0;
765
766         if (num_serial == 0)
767                 return -ENODEV;
768         return num_serial;
769 }
770
771 /*
772  * These chips are available with optionally one parallel port and up to
773  * two serial ports. Unfortunately they all have the same product id.
774  *
775  * Basic configuration is done over a region of 32 I/O ports. The base
776  * ioport is called INTA or INTC, depending on docs/other drivers.
777  *
778  * The region of the 32 I/O ports is configured in POSIO0R...
779  */
780
781 /* registers */
782 #define ITE_887x_MISCR          0x9c
783 #define ITE_887x_INTCBAR        0x78
784 #define ITE_887x_UARTBAR        0x7c
785 #define ITE_887x_PS0BAR         0x10
786 #define ITE_887x_POSIO0         0x60
787
788 /* I/O space size */
789 #define ITE_887x_IOSIZE         32
790 /* I/O space size (bits 26-24; 8 bytes = 011b) */
791 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
792 /* I/O space size (bits 26-24; 32 bytes = 101b) */
793 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
794 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
795 #define ITE_887x_POSIO_SPEED            (3 << 29)
796 /* enable IO_Space bit */
797 #define ITE_887x_POSIO_ENABLE           (1 << 31)
798
799 static int pci_ite887x_init(struct pci_dev *dev)
800 {
801         /* inta_addr are the configuration addresses of the ITE */
802         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
803                                                         0x200, 0x280, 0 };
804         int ret, i, type;
805         struct resource *iobase = NULL;
806         u32 miscr, uartbar, ioport;
807
808         /* search for the base-ioport */
809         i = 0;
810         while (inta_addr[i] && iobase == NULL) {
811                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
812                                                                 "ite887x");
813                 if (iobase != NULL) {
814                         /* write POSIO0R - speed | size | ioport */
815                         pci_write_config_dword(dev, ITE_887x_POSIO0,
816                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
817                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
818                         /* write INTCBAR - ioport */
819                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
820                                                                 inta_addr[i]);
821                         ret = inb(inta_addr[i]);
822                         if (ret != 0xff) {
823                                 /* ioport connected */
824                                 break;
825                         }
826                         release_region(iobase->start, ITE_887x_IOSIZE);
827                         iobase = NULL;
828                 }
829                 i++;
830         }
831
832         if (!inta_addr[i]) {
833                 printk(KERN_ERR "ite887x: could not find iobase\n");
834                 return -ENODEV;
835         }
836
837         /* start of undocumented type checking (see parport_pc.c) */
838         type = inb(iobase->start + 0x18) & 0x0f;
839
840         switch (type) {
841         case 0x2:       /* ITE8871 (1P) */
842         case 0xa:       /* ITE8875 (1P) */
843                 ret = 0;
844                 break;
845         case 0xe:       /* ITE8872 (2S1P) */
846                 ret = 2;
847                 break;
848         case 0x6:       /* ITE8873 (1S) */
849                 ret = 1;
850                 break;
851         case 0x8:       /* ITE8874 (2S) */
852                 ret = 2;
853                 break;
854         default:
855                 moan_device("Unknown ITE887x", dev);
856                 ret = -ENODEV;
857         }
858
859         /* configure all serial ports */
860         for (i = 0; i < ret; i++) {
861                 /* read the I/O port from the device */
862                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
863                                                                 &ioport);
864                 ioport &= 0x0000FF00;   /* the actual base address */
865                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
866                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
867                         ITE_887x_POSIO_IOSIZE_8 | ioport);
868
869                 /* write the ioport to the UARTBAR */
870                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
871                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
872                 uartbar |= (ioport << (16 * i));        /* set the ioport */
873                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
874
875                 /* get current config */
876                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
877                 /* disable interrupts (UARTx_Routing[3:0]) */
878                 miscr &= ~(0xf << (12 - 4 * i));
879                 /* activate the UART (UARTx_En) */
880                 miscr |= 1 << (23 - i);
881                 /* write new config with activated UART */
882                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
883         }
884
885         if (ret <= 0) {
886                 /* the device has no UARTs if we get here */
887                 release_region(iobase->start, ITE_887x_IOSIZE);
888         }
889
890         return ret;
891 }
892
893 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
894 {
895         u32 ioport;
896         /* the ioport is bit 0-15 in POSIO0R */
897         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
898         ioport &= 0xffff;
899         release_region(ioport, ITE_887x_IOSIZE);
900 }
901
902 /*
903  * Oxford Semiconductor Inc.
904  * Check that device is part of the Tornado range of devices, then determine
905  * the number of ports available on the device.
906  */
907 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
908 {
909         u8 __iomem *p;
910         unsigned long deviceID;
911         unsigned int  number_uarts = 0;
912
913         /* OxSemi Tornado devices are all 0xCxxx */
914         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
915             (dev->device & 0xF000) != 0xC000)
916                 return 0;
917
918         p = pci_iomap(dev, 0, 5);
919         if (p == NULL)
920                 return -ENOMEM;
921
922         deviceID = ioread32(p);
923         /* Tornado device */
924         if (deviceID == 0x07000200) {
925                 number_uarts = ioread8(p + 4);
926                 printk(KERN_DEBUG
927                         "%d ports detected on Oxford PCI Express device\n",
928                                                                 number_uarts);
929         }
930         pci_iounmap(dev, p);
931         return number_uarts;
932 }
933
934 static int
935 pci_default_setup(struct serial_private *priv,
936                   const struct pciserial_board *board,
937                   struct uart_port *port, int idx)
938 {
939         unsigned int bar, offset = board->first_offset, maxnr;
940
941         bar = FL_GET_BASE(board->flags);
942         if (board->flags & FL_BASE_BARS)
943                 bar += idx;
944         else
945                 offset += idx * board->uart_offset;
946
947         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
948                 (board->reg_shift + 3);
949
950         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
951                 return 1;
952
953         return setup_port(priv, port, bar, offset, board->reg_shift);
954 }
955
956 static int skip_tx_en_setup(struct serial_private *priv,
957                         const struct pciserial_board *board,
958                         struct uart_port *port, int idx)
959 {
960         port->flags |= UPF_NO_TXEN_TEST;
961         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
962                           "[%04x:%04x] subsystem [%04x:%04x]\n",
963                           priv->dev->vendor,
964                           priv->dev->device,
965                           priv->dev->subsystem_vendor,
966                           priv->dev->subsystem_device);
967
968         return pci_default_setup(priv, board, port, idx);
969 }
970
971 /* This should be in linux/pci_ids.h */
972 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
973 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
974 #define PCI_DEVICE_ID_OCTPRO            0x0001
975 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
976 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
977 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
978 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
979 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
980 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
981
982 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
983 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
984
985 /*
986  * Master list of serial port init/setup/exit quirks.
987  * This does not describe the general nature of the port.
988  * (ie, baud base, number and location of ports, etc)
989  *
990  * This list is ordered alphabetically by vendor then device.
991  * Specific entries must come before more generic entries.
992  */
993 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
994         /*
995         * ADDI-DATA GmbH communication cards <info@addi-data.com>
996         */
997         {
998                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
999                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1000                 .subvendor      = PCI_ANY_ID,
1001                 .subdevice      = PCI_ANY_ID,
1002                 .setup          = addidata_apci7800_setup,
1003         },
1004         /*
1005          * AFAVLAB cards - these may be called via parport_serial
1006          *  It is not clear whether this applies to all products.
1007          */
1008         {
1009                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1010                 .device         = PCI_ANY_ID,
1011                 .subvendor      = PCI_ANY_ID,
1012                 .subdevice      = PCI_ANY_ID,
1013                 .setup          = afavlab_setup,
1014         },
1015         /*
1016          * HP Diva
1017          */
1018         {
1019                 .vendor         = PCI_VENDOR_ID_HP,
1020                 .device         = PCI_DEVICE_ID_HP_DIVA,
1021                 .subvendor      = PCI_ANY_ID,
1022                 .subdevice      = PCI_ANY_ID,
1023                 .init           = pci_hp_diva_init,
1024                 .setup          = pci_hp_diva_setup,
1025         },
1026         /*
1027          * Intel
1028          */
1029         {
1030                 .vendor         = PCI_VENDOR_ID_INTEL,
1031                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1032                 .subvendor      = 0xe4bf,
1033                 .subdevice      = PCI_ANY_ID,
1034                 .init           = pci_inteli960ni_init,
1035                 .setup          = pci_default_setup,
1036         },
1037         {
1038                 .vendor         = PCI_VENDOR_ID_INTEL,
1039                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1040                 .subvendor      = PCI_ANY_ID,
1041                 .subdevice      = PCI_ANY_ID,
1042                 .setup          = skip_tx_en_setup,
1043         },
1044         {
1045                 .vendor         = PCI_VENDOR_ID_INTEL,
1046                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1047                 .subvendor      = PCI_ANY_ID,
1048                 .subdevice      = PCI_ANY_ID,
1049                 .setup          = skip_tx_en_setup,
1050         },
1051         {
1052                 .vendor         = PCI_VENDOR_ID_INTEL,
1053                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1054                 .subvendor      = PCI_ANY_ID,
1055                 .subdevice      = PCI_ANY_ID,
1056                 .setup          = skip_tx_en_setup,
1057         },
1058         /*
1059          * ITE
1060          */
1061         {
1062                 .vendor         = PCI_VENDOR_ID_ITE,
1063                 .device         = PCI_DEVICE_ID_ITE_8872,
1064                 .subvendor      = PCI_ANY_ID,
1065                 .subdevice      = PCI_ANY_ID,
1066                 .init           = pci_ite887x_init,
1067                 .setup          = pci_default_setup,
1068                 .exit           = __devexit_p(pci_ite887x_exit),
1069         },
1070         /*
1071          * National Instruments
1072          */
1073         {
1074                 .vendor         = PCI_VENDOR_ID_NI,
1075                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1076                 .subvendor      = PCI_ANY_ID,
1077                 .subdevice      = PCI_ANY_ID,
1078                 .init           = pci_ni8420_init,
1079                 .setup          = pci_default_setup,
1080                 .exit           = __devexit_p(pci_ni8420_exit),
1081         },
1082         {
1083                 .vendor         = PCI_VENDOR_ID_NI,
1084                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1085                 .subvendor      = PCI_ANY_ID,
1086                 .subdevice      = PCI_ANY_ID,
1087                 .init           = pci_ni8420_init,
1088                 .setup          = pci_default_setup,
1089                 .exit           = __devexit_p(pci_ni8420_exit),
1090         },
1091         {
1092                 .vendor         = PCI_VENDOR_ID_NI,
1093                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1094                 .subvendor      = PCI_ANY_ID,
1095                 .subdevice      = PCI_ANY_ID,
1096                 .init           = pci_ni8420_init,
1097                 .setup          = pci_default_setup,
1098                 .exit           = __devexit_p(pci_ni8420_exit),
1099         },
1100         {
1101                 .vendor         = PCI_VENDOR_ID_NI,
1102                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1103                 .subvendor      = PCI_ANY_ID,
1104                 .subdevice      = PCI_ANY_ID,
1105                 .init           = pci_ni8420_init,
1106                 .setup          = pci_default_setup,
1107                 .exit           = __devexit_p(pci_ni8420_exit),
1108         },
1109         {
1110                 .vendor         = PCI_VENDOR_ID_NI,
1111                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1112                 .subvendor      = PCI_ANY_ID,
1113                 .subdevice      = PCI_ANY_ID,
1114                 .init           = pci_ni8420_init,
1115                 .setup          = pci_default_setup,
1116                 .exit           = __devexit_p(pci_ni8420_exit),
1117         },
1118         {
1119                 .vendor         = PCI_VENDOR_ID_NI,
1120                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1121                 .subvendor      = PCI_ANY_ID,
1122                 .subdevice      = PCI_ANY_ID,
1123                 .init           = pci_ni8420_init,
1124                 .setup          = pci_default_setup,
1125                 .exit           = __devexit_p(pci_ni8420_exit),
1126         },
1127         {
1128                 .vendor         = PCI_VENDOR_ID_NI,
1129                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1130                 .subvendor      = PCI_ANY_ID,
1131                 .subdevice      = PCI_ANY_ID,
1132                 .init           = pci_ni8420_init,
1133                 .setup          = pci_default_setup,
1134                 .exit           = __devexit_p(pci_ni8420_exit),
1135         },
1136         {
1137                 .vendor         = PCI_VENDOR_ID_NI,
1138                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1139                 .subvendor      = PCI_ANY_ID,
1140                 .subdevice      = PCI_ANY_ID,
1141                 .init           = pci_ni8420_init,
1142                 .setup          = pci_default_setup,
1143                 .exit           = __devexit_p(pci_ni8420_exit),
1144         },
1145         {
1146                 .vendor         = PCI_VENDOR_ID_NI,
1147                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1148                 .subvendor      = PCI_ANY_ID,
1149                 .subdevice      = PCI_ANY_ID,
1150                 .init           = pci_ni8420_init,
1151                 .setup          = pci_default_setup,
1152                 .exit           = __devexit_p(pci_ni8420_exit),
1153         },
1154         {
1155                 .vendor         = PCI_VENDOR_ID_NI,
1156                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1157                 .subvendor      = PCI_ANY_ID,
1158                 .subdevice      = PCI_ANY_ID,
1159                 .init           = pci_ni8420_init,
1160                 .setup          = pci_default_setup,
1161                 .exit           = __devexit_p(pci_ni8420_exit),
1162         },
1163         {
1164                 .vendor         = PCI_VENDOR_ID_NI,
1165                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1166                 .subvendor      = PCI_ANY_ID,
1167                 .subdevice      = PCI_ANY_ID,
1168                 .init           = pci_ni8420_init,
1169                 .setup          = pci_default_setup,
1170                 .exit           = __devexit_p(pci_ni8420_exit),
1171         },
1172         {
1173                 .vendor         = PCI_VENDOR_ID_NI,
1174                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1175                 .subvendor      = PCI_ANY_ID,
1176                 .subdevice      = PCI_ANY_ID,
1177                 .init           = pci_ni8420_init,
1178                 .setup          = pci_default_setup,
1179                 .exit           = __devexit_p(pci_ni8420_exit),
1180         },
1181         {
1182                 .vendor         = PCI_VENDOR_ID_NI,
1183                 .device         = PCI_ANY_ID,
1184                 .subvendor      = PCI_ANY_ID,
1185                 .subdevice      = PCI_ANY_ID,
1186                 .init           = pci_ni8430_init,
1187                 .setup          = pci_ni8430_setup,
1188                 .exit           = __devexit_p(pci_ni8430_exit),
1189         },
1190         /*
1191          * Panacom
1192          */
1193         {
1194                 .vendor         = PCI_VENDOR_ID_PANACOM,
1195                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1196                 .subvendor      = PCI_ANY_ID,
1197                 .subdevice      = PCI_ANY_ID,
1198                 .init           = pci_plx9050_init,
1199                 .setup          = pci_default_setup,
1200                 .exit           = __devexit_p(pci_plx9050_exit),
1201         },
1202         {
1203                 .vendor         = PCI_VENDOR_ID_PANACOM,
1204                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1205                 .subvendor      = PCI_ANY_ID,
1206                 .subdevice      = PCI_ANY_ID,
1207                 .init           = pci_plx9050_init,
1208                 .setup          = pci_default_setup,
1209                 .exit           = __devexit_p(pci_plx9050_exit),
1210         },
1211         /*
1212          * PLX
1213          */
1214         {
1215                 .vendor         = PCI_VENDOR_ID_PLX,
1216                 .device         = PCI_DEVICE_ID_PLX_9030,
1217                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1218                 .subdevice      = PCI_ANY_ID,
1219                 .setup          = pci_default_setup,
1220         },
1221         {
1222                 .vendor         = PCI_VENDOR_ID_PLX,
1223                 .device         = PCI_DEVICE_ID_PLX_9050,
1224                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1225                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1226                 .init           = pci_plx9050_init,
1227                 .setup          = pci_default_setup,
1228                 .exit           = __devexit_p(pci_plx9050_exit),
1229         },
1230         {
1231                 .vendor         = PCI_VENDOR_ID_PLX,
1232                 .device         = PCI_DEVICE_ID_PLX_9050,
1233                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1234                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1235                 .init           = pci_plx9050_init,
1236                 .setup          = pci_default_setup,
1237                 .exit           = __devexit_p(pci_plx9050_exit),
1238         },
1239         {
1240                 .vendor         = PCI_VENDOR_ID_PLX,
1241                 .device         = PCI_DEVICE_ID_PLX_9050,
1242                 .subvendor      = PCI_VENDOR_ID_PLX,
1243                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1244                 .init           = pci_plx9050_init,
1245                 .setup          = pci_default_setup,
1246                 .exit           = __devexit_p(pci_plx9050_exit),
1247         },
1248         {
1249                 .vendor         = PCI_VENDOR_ID_PLX,
1250                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1251                 .subvendor      = PCI_VENDOR_ID_PLX,
1252                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1253                 .init           = pci_plx9050_init,
1254                 .setup          = pci_default_setup,
1255                 .exit           = __devexit_p(pci_plx9050_exit),
1256         },
1257         /*
1258          * SBS Technologies, Inc., PMC-OCTALPRO 232
1259          */
1260         {
1261                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1262                 .device         = PCI_DEVICE_ID_OCTPRO,
1263                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1264                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1265                 .init           = sbs_init,
1266                 .setup          = sbs_setup,
1267                 .exit           = __devexit_p(sbs_exit),
1268         },
1269         /*
1270          * SBS Technologies, Inc., PMC-OCTALPRO 422
1271          */
1272         {
1273                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1274                 .device         = PCI_DEVICE_ID_OCTPRO,
1275                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1276                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1277                 .init           = sbs_init,
1278                 .setup          = sbs_setup,
1279                 .exit           = __devexit_p(sbs_exit),
1280         },
1281         /*
1282          * SBS Technologies, Inc., P-Octal 232
1283          */
1284         {
1285                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1286                 .device         = PCI_DEVICE_ID_OCTPRO,
1287                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1288                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1289                 .init           = sbs_init,
1290                 .setup          = sbs_setup,
1291                 .exit           = __devexit_p(sbs_exit),
1292         },
1293         /*
1294          * SBS Technologies, Inc., P-Octal 422
1295          */
1296         {
1297                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1298                 .device         = PCI_DEVICE_ID_OCTPRO,
1299                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1300                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1301                 .init           = sbs_init,
1302                 .setup          = sbs_setup,
1303                 .exit           = __devexit_p(sbs_exit),
1304         },
1305         /*
1306          * SIIG cards - these may be called via parport_serial
1307          */
1308         {
1309                 .vendor         = PCI_VENDOR_ID_SIIG,
1310                 .device         = PCI_ANY_ID,
1311                 .subvendor      = PCI_ANY_ID,
1312                 .subdevice      = PCI_ANY_ID,
1313                 .init           = pci_siig_init,
1314                 .setup          = pci_siig_setup,
1315         },
1316         /*
1317          * Titan cards
1318          */
1319         {
1320                 .vendor         = PCI_VENDOR_ID_TITAN,
1321                 .device         = PCI_DEVICE_ID_TITAN_400L,
1322                 .subvendor      = PCI_ANY_ID,
1323                 .subdevice      = PCI_ANY_ID,
1324                 .setup          = titan_400l_800l_setup,
1325         },
1326         {
1327                 .vendor         = PCI_VENDOR_ID_TITAN,
1328                 .device         = PCI_DEVICE_ID_TITAN_800L,
1329                 .subvendor      = PCI_ANY_ID,
1330                 .subdevice      = PCI_ANY_ID,
1331                 .setup          = titan_400l_800l_setup,
1332         },
1333         /*
1334          * Timedia cards
1335          */
1336         {
1337                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1338                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1339                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1340                 .subdevice      = PCI_ANY_ID,
1341                 .init           = pci_timedia_init,
1342                 .setup          = pci_timedia_setup,
1343         },
1344         {
1345                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1346                 .device         = PCI_ANY_ID,
1347                 .subvendor      = PCI_ANY_ID,
1348                 .subdevice      = PCI_ANY_ID,
1349                 .setup          = pci_timedia_setup,
1350         },
1351         /*
1352          * Xircom cards
1353          */
1354         {
1355                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1356                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1357                 .subvendor      = PCI_ANY_ID,
1358                 .subdevice      = PCI_ANY_ID,
1359                 .init           = pci_xircom_init,
1360                 .setup          = pci_default_setup,
1361         },
1362         /*
1363          * Netmos cards - these may be called via parport_serial
1364          */
1365         {
1366                 .vendor         = PCI_VENDOR_ID_NETMOS,
1367                 .device         = PCI_ANY_ID,
1368                 .subvendor      = PCI_ANY_ID,
1369                 .subdevice      = PCI_ANY_ID,
1370                 .init           = pci_netmos_init,
1371                 .setup          = pci_default_setup,
1372         },
1373         /*
1374          * For Oxford Semiconductor and Mainpine
1375          */
1376         {
1377                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1378                 .device         = PCI_ANY_ID,
1379                 .subvendor      = PCI_ANY_ID,
1380                 .subdevice      = PCI_ANY_ID,
1381                 .init           = pci_oxsemi_tornado_init,
1382                 .setup          = pci_default_setup,
1383         },
1384         {
1385                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1386                 .device         = PCI_ANY_ID,
1387                 .subvendor      = PCI_ANY_ID,
1388                 .subdevice      = PCI_ANY_ID,
1389                 .init           = pci_oxsemi_tornado_init,
1390                 .setup          = pci_default_setup,
1391         },
1392         /*
1393          * Default "match everything" terminator entry
1394          */
1395         {
1396                 .vendor         = PCI_ANY_ID,
1397                 .device         = PCI_ANY_ID,
1398                 .subvendor      = PCI_ANY_ID,
1399                 .subdevice      = PCI_ANY_ID,
1400                 .setup          = pci_default_setup,
1401         }
1402 };
1403
1404 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1405 {
1406         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1407 }
1408
1409 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1410 {
1411         struct pci_serial_quirk *quirk;
1412
1413         for (quirk = pci_serial_quirks; ; quirk++)
1414                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1415                     quirk_id_matches(quirk->device, dev->device) &&
1416                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1417                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1418                         break;
1419         return quirk;
1420 }
1421
1422 static inline int get_pci_irq(struct pci_dev *dev,
1423                                 const struct pciserial_board *board)
1424 {
1425         if (board->flags & FL_NOIRQ)
1426                 return 0;
1427         else
1428                 return dev->irq;
1429 }
1430
1431 /*
1432  * This is the configuration table for all of the PCI serial boards
1433  * which we support.  It is directly indexed by the pci_board_num_t enum
1434  * value, which is encoded in the pci_device_id PCI probe table's
1435  * driver_data member.
1436  *
1437  * The makeup of these names are:
1438  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1439  *
1440  *  bn          = PCI BAR number
1441  *  bt          = Index using PCI BARs
1442  *  n           = number of serial ports
1443  *  baud        = baud rate
1444  *  offsetinhex = offset for each sequential port (in hex)
1445  *
1446  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1447  *
1448  * Please note: in theory if n = 1, _bt infix should make no difference.
1449  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1450  */
1451 enum pci_board_num_t {
1452         pbn_default = 0,
1453
1454         pbn_b0_1_115200,
1455         pbn_b0_2_115200,
1456         pbn_b0_4_115200,
1457         pbn_b0_5_115200,
1458         pbn_b0_8_115200,
1459
1460         pbn_b0_1_921600,
1461         pbn_b0_2_921600,
1462         pbn_b0_4_921600,
1463
1464         pbn_b0_2_1130000,
1465
1466         pbn_b0_4_1152000,
1467
1468         pbn_b0_2_1843200,
1469         pbn_b0_4_1843200,
1470
1471         pbn_b0_2_1843200_200,
1472         pbn_b0_4_1843200_200,
1473         pbn_b0_8_1843200_200,
1474
1475         pbn_b0_1_4000000,
1476
1477         pbn_b0_bt_1_115200,
1478         pbn_b0_bt_2_115200,
1479         pbn_b0_bt_8_115200,
1480
1481         pbn_b0_bt_1_460800,
1482         pbn_b0_bt_2_460800,
1483         pbn_b0_bt_4_460800,
1484
1485         pbn_b0_bt_1_921600,
1486         pbn_b0_bt_2_921600,
1487         pbn_b0_bt_4_921600,
1488         pbn_b0_bt_8_921600,
1489
1490         pbn_b1_1_115200,
1491         pbn_b1_2_115200,
1492         pbn_b1_4_115200,
1493         pbn_b1_8_115200,
1494         pbn_b1_16_115200,
1495
1496         pbn_b1_1_921600,
1497         pbn_b1_2_921600,
1498         pbn_b1_4_921600,
1499         pbn_b1_8_921600,
1500
1501         pbn_b1_2_1250000,
1502
1503         pbn_b1_bt_1_115200,
1504         pbn_b1_bt_2_115200,
1505         pbn_b1_bt_4_115200,
1506
1507         pbn_b1_bt_2_921600,
1508
1509         pbn_b1_1_1382400,
1510         pbn_b1_2_1382400,
1511         pbn_b1_4_1382400,
1512         pbn_b1_8_1382400,
1513
1514         pbn_b2_1_115200,
1515         pbn_b2_2_115200,
1516         pbn_b2_4_115200,
1517         pbn_b2_8_115200,
1518
1519         pbn_b2_1_460800,
1520         pbn_b2_4_460800,
1521         pbn_b2_8_460800,
1522         pbn_b2_16_460800,
1523
1524         pbn_b2_1_921600,
1525         pbn_b2_4_921600,
1526         pbn_b2_8_921600,
1527
1528         pbn_b2_bt_1_115200,
1529         pbn_b2_bt_2_115200,
1530         pbn_b2_bt_4_115200,
1531
1532         pbn_b2_bt_2_921600,
1533         pbn_b2_bt_4_921600,
1534
1535         pbn_b3_2_115200,
1536         pbn_b3_4_115200,
1537         pbn_b3_8_115200,
1538
1539         /*
1540          * Board-specific versions.
1541          */
1542         pbn_panacom,
1543         pbn_panacom2,
1544         pbn_panacom4,
1545         pbn_exsys_4055,
1546         pbn_plx_romulus,
1547         pbn_oxsemi,
1548         pbn_oxsemi_1_4000000,
1549         pbn_oxsemi_2_4000000,
1550         pbn_oxsemi_4_4000000,
1551         pbn_oxsemi_8_4000000,
1552         pbn_intel_i960,
1553         pbn_sgi_ioc3,
1554         pbn_computone_4,
1555         pbn_computone_6,
1556         pbn_computone_8,
1557         pbn_sbsxrsio,
1558         pbn_exar_XR17C152,
1559         pbn_exar_XR17C154,
1560         pbn_exar_XR17C158,
1561         pbn_pasemi_1682M,
1562         pbn_ni8430_2,
1563         pbn_ni8430_4,
1564         pbn_ni8430_8,
1565         pbn_ni8430_16,
1566 };
1567
1568 /*
1569  * uart_offset - the space between channels
1570  * reg_shift   - describes how the UART registers are mapped
1571  *               to PCI memory by the card.
1572  * For example IER register on SBS, Inc. PMC-OctPro is located at
1573  * offset 0x10 from the UART base, while UART_IER is defined as 1
1574  * in include/linux/serial_reg.h,
1575  * see first lines of serial_in() and serial_out() in 8250.c
1576 */
1577
1578 static struct pciserial_board pci_boards[] __devinitdata = {
1579         [pbn_default] = {
1580                 .flags          = FL_BASE0,
1581                 .num_ports      = 1,
1582                 .base_baud      = 115200,
1583                 .uart_offset    = 8,
1584         },
1585         [pbn_b0_1_115200] = {
1586                 .flags          = FL_BASE0,
1587                 .num_ports      = 1,
1588                 .base_baud      = 115200,
1589                 .uart_offset    = 8,
1590         },
1591         [pbn_b0_2_115200] = {
1592                 .flags          = FL_BASE0,
1593                 .num_ports      = 2,
1594                 .base_baud      = 115200,
1595                 .uart_offset    = 8,
1596         },
1597         [pbn_b0_4_115200] = {
1598                 .flags          = FL_BASE0,
1599                 .num_ports      = 4,
1600                 .base_baud      = 115200,
1601                 .uart_offset    = 8,
1602         },
1603         [pbn_b0_5_115200] = {
1604                 .flags          = FL_BASE0,
1605                 .num_ports      = 5,
1606                 .base_baud      = 115200,
1607                 .uart_offset    = 8,
1608         },
1609         [pbn_b0_8_115200] = {
1610                 .flags          = FL_BASE0,
1611                 .num_ports      = 8,
1612                 .base_baud      = 115200,
1613                 .uart_offset    = 8,
1614         },
1615         [pbn_b0_1_921600] = {
1616                 .flags          = FL_BASE0,
1617                 .num_ports      = 1,
1618                 .base_baud      = 921600,
1619                 .uart_offset    = 8,
1620         },
1621         [pbn_b0_2_921600] = {
1622                 .flags          = FL_BASE0,
1623                 .num_ports      = 2,
1624                 .base_baud      = 921600,
1625                 .uart_offset    = 8,
1626         },
1627         [pbn_b0_4_921600] = {
1628                 .flags          = FL_BASE0,
1629                 .num_ports      = 4,
1630                 .base_baud      = 921600,
1631                 .uart_offset    = 8,
1632         },
1633
1634         [pbn_b0_2_1130000] = {
1635                 .flags          = FL_BASE0,
1636                 .num_ports      = 2,
1637                 .base_baud      = 1130000,
1638                 .uart_offset    = 8,
1639         },
1640
1641         [pbn_b0_4_1152000] = {
1642                 .flags          = FL_BASE0,
1643                 .num_ports      = 4,
1644                 .base_baud      = 1152000,
1645                 .uart_offset    = 8,
1646         },
1647
1648         [pbn_b0_2_1843200] = {
1649                 .flags          = FL_BASE0,
1650                 .num_ports      = 2,
1651                 .base_baud      = 1843200,
1652                 .uart_offset    = 8,
1653         },
1654         [pbn_b0_4_1843200] = {
1655                 .flags          = FL_BASE0,
1656                 .num_ports      = 4,
1657                 .base_baud      = 1843200,
1658                 .uart_offset    = 8,
1659         },
1660
1661         [pbn_b0_2_1843200_200] = {
1662                 .flags          = FL_BASE0,
1663                 .num_ports      = 2,
1664                 .base_baud      = 1843200,
1665                 .uart_offset    = 0x200,
1666         },
1667         [pbn_b0_4_1843200_200] = {
1668                 .flags          = FL_BASE0,
1669                 .num_ports      = 4,
1670                 .base_baud      = 1843200,
1671                 .uart_offset    = 0x200,
1672         },
1673         [pbn_b0_8_1843200_200] = {
1674                 .flags          = FL_BASE0,
1675                 .num_ports      = 8,
1676                 .base_baud      = 1843200,
1677                 .uart_offset    = 0x200,
1678         },
1679         [pbn_b0_1_4000000] = {
1680                 .flags          = FL_BASE0,
1681                 .num_ports      = 1,
1682                 .base_baud      = 4000000,
1683                 .uart_offset    = 8,
1684         },
1685
1686         [pbn_b0_bt_1_115200] = {
1687                 .flags          = FL_BASE0|FL_BASE_BARS,
1688                 .num_ports      = 1,
1689                 .base_baud      = 115200,
1690                 .uart_offset    = 8,
1691         },
1692         [pbn_b0_bt_2_115200] = {
1693                 .flags          = FL_BASE0|FL_BASE_BARS,
1694                 .num_ports      = 2,
1695                 .base_baud      = 115200,
1696                 .uart_offset    = 8,
1697         },
1698         [pbn_b0_bt_8_115200] = {
1699                 .flags          = FL_BASE0|FL_BASE_BARS,
1700                 .num_ports      = 8,
1701                 .base_baud      = 115200,
1702                 .uart_offset    = 8,
1703         },
1704
1705         [pbn_b0_bt_1_460800] = {
1706                 .flags          = FL_BASE0|FL_BASE_BARS,
1707                 .num_ports      = 1,
1708                 .base_baud      = 460800,
1709                 .uart_offset    = 8,
1710         },
1711         [pbn_b0_bt_2_460800] = {
1712                 .flags          = FL_BASE0|FL_BASE_BARS,
1713                 .num_ports      = 2,
1714                 .base_baud      = 460800,
1715                 .uart_offset    = 8,
1716         },
1717         [pbn_b0_bt_4_460800] = {
1718                 .flags          = FL_BASE0|FL_BASE_BARS,
1719                 .num_ports      = 4,
1720                 .base_baud      = 460800,
1721                 .uart_offset    = 8,
1722         },
1723
1724         [pbn_b0_bt_1_921600] = {
1725                 .flags          = FL_BASE0|FL_BASE_BARS,
1726                 .num_ports      = 1,
1727                 .base_baud      = 921600,
1728                 .uart_offset    = 8,
1729         },
1730         [pbn_b0_bt_2_921600] = {
1731                 .flags          = FL_BASE0|FL_BASE_BARS,
1732                 .num_ports      = 2,
1733                 .base_baud      = 921600,
1734                 .uart_offset    = 8,
1735         },
1736         [pbn_b0_bt_4_921600] = {
1737                 .flags          = FL_BASE0|FL_BASE_BARS,
1738                 .num_ports      = 4,
1739                 .base_baud      = 921600,
1740                 .uart_offset    = 8,
1741         },
1742         [pbn_b0_bt_8_921600] = {
1743                 .flags          = FL_BASE0|FL_BASE_BARS,
1744                 .num_ports      = 8,
1745                 .base_baud      = 921600,
1746                 .uart_offset    = 8,
1747         },
1748
1749         [pbn_b1_1_115200] = {
1750                 .flags          = FL_BASE1,
1751                 .num_ports      = 1,
1752                 .base_baud      = 115200,
1753                 .uart_offset    = 8,
1754         },
1755         [pbn_b1_2_115200] = {
1756                 .flags          = FL_BASE1,
1757                 .num_ports      = 2,
1758                 .base_baud      = 115200,
1759                 .uart_offset    = 8,
1760         },
1761         [pbn_b1_4_115200] = {
1762                 .flags          = FL_BASE1,
1763                 .num_ports      = 4,
1764                 .base_baud      = 115200,
1765                 .uart_offset    = 8,
1766         },
1767         [pbn_b1_8_115200] = {
1768                 .flags          = FL_BASE1,
1769                 .num_ports      = 8,
1770                 .base_baud      = 115200,
1771                 .uart_offset    = 8,
1772         },
1773         [pbn_b1_16_115200] = {
1774                 .flags          = FL_BASE1,
1775                 .num_ports      = 16,
1776                 .base_baud      = 115200,
1777                 .uart_offset    = 8,
1778         },
1779
1780         [pbn_b1_1_921600] = {
1781                 .flags          = FL_BASE1,
1782                 .num_ports      = 1,
1783                 .base_baud      = 921600,
1784                 .uart_offset    = 8,
1785         },
1786         [pbn_b1_2_921600] = {
1787                 .flags          = FL_BASE1,
1788                 .num_ports      = 2,
1789                 .base_baud      = 921600,
1790                 .uart_offset    = 8,
1791         },
1792         [pbn_b1_4_921600] = {
1793                 .flags          = FL_BASE1,
1794                 .num_ports      = 4,
1795                 .base_baud      = 921600,
1796                 .uart_offset    = 8,
1797         },
1798         [pbn_b1_8_921600] = {
1799                 .flags          = FL_BASE1,
1800                 .num_ports      = 8,
1801                 .base_baud      = 921600,
1802                 .uart_offset    = 8,
1803         },
1804         [pbn_b1_2_1250000] = {
1805                 .flags          = FL_BASE1,
1806                 .num_ports      = 2,
1807                 .base_baud      = 1250000,
1808                 .uart_offset    = 8,
1809         },
1810
1811         [pbn_b1_bt_1_115200] = {
1812                 .flags          = FL_BASE1|FL_BASE_BARS,
1813                 .num_ports      = 1,
1814                 .base_baud      = 115200,
1815                 .uart_offset    = 8,
1816         },
1817         [pbn_b1_bt_2_115200] = {
1818                 .flags          = FL_BASE1|FL_BASE_BARS,
1819                 .num_ports      = 2,
1820                 .base_baud      = 115200,
1821                 .uart_offset    = 8,
1822         },
1823         [pbn_b1_bt_4_115200] = {
1824                 .flags          = FL_BASE1|FL_BASE_BARS,
1825                 .num_ports      = 4,
1826                 .base_baud      = 115200,
1827                 .uart_offset    = 8,
1828         },
1829
1830         [pbn_b1_bt_2_921600] = {
1831                 .flags          = FL_BASE1|FL_BASE_BARS,
1832                 .num_ports      = 2,
1833                 .base_baud      = 921600,
1834                 .uart_offset    = 8,
1835         },
1836
1837         [pbn_b1_1_1382400] = {
1838                 .flags          = FL_BASE1,
1839                 .num_ports      = 1,
1840                 .base_baud      = 1382400,
1841                 .uart_offset    = 8,
1842         },
1843         [pbn_b1_2_1382400] = {
1844                 .flags          = FL_BASE1,
1845                 .num_ports      = 2,
1846                 .base_baud      = 1382400,
1847                 .uart_offset    = 8,
1848         },
1849         [pbn_b1_4_1382400] = {
1850                 .flags          = FL_BASE1,
1851                 .num_ports      = 4,
1852                 .base_baud      = 1382400,
1853                 .uart_offset    = 8,
1854         },
1855         [pbn_b1_8_1382400] = {
1856                 .flags          = FL_BASE1,
1857                 .num_ports      = 8,
1858                 .base_baud      = 1382400,
1859                 .uart_offset    = 8,
1860         },
1861
1862         [pbn_b2_1_115200] = {
1863                 .flags          = FL_BASE2,
1864                 .num_ports      = 1,
1865                 .base_baud      = 115200,
1866                 .uart_offset    = 8,
1867         },
1868         [pbn_b2_2_115200] = {
1869                 .flags          = FL_BASE2,
1870                 .num_ports      = 2,
1871                 .base_baud      = 115200,
1872                 .uart_offset    = 8,
1873         },
1874         [pbn_b2_4_115200] = {
1875                 .flags          = FL_BASE2,
1876                 .num_ports      = 4,
1877                 .base_baud      = 115200,
1878                 .uart_offset    = 8,
1879         },
1880         [pbn_b2_8_115200] = {
1881                 .flags          = FL_BASE2,
1882                 .num_ports      = 8,
1883                 .base_baud      = 115200,
1884                 .uart_offset    = 8,
1885         },
1886
1887         [pbn_b2_1_460800] = {
1888                 .flags          = FL_BASE2,
1889                 .num_ports      = 1,
1890                 .base_baud      = 460800,
1891                 .uart_offset    = 8,
1892         },
1893         [pbn_b2_4_460800] = {
1894                 .flags          = FL_BASE2,
1895                 .num_ports      = 4,
1896                 .base_baud      = 460800,
1897                 .uart_offset    = 8,
1898         },
1899         [pbn_b2_8_460800] = {
1900                 .flags          = FL_BASE2,
1901                 .num_ports      = 8,
1902                 .base_baud      = 460800,
1903                 .uart_offset    = 8,
1904         },
1905         [pbn_b2_16_460800] = {
1906                 .flags          = FL_BASE2,
1907                 .num_ports      = 16,
1908                 .base_baud      = 460800,
1909                 .uart_offset    = 8,
1910          },
1911
1912         [pbn_b2_1_921600] = {
1913                 .flags          = FL_BASE2,
1914                 .num_ports      = 1,
1915                 .base_baud      = 921600,
1916                 .uart_offset    = 8,
1917         },
1918         [pbn_b2_4_921600] = {
1919                 .flags          = FL_BASE2,
1920                 .num_ports      = 4,
1921                 .base_baud      = 921600,
1922                 .uart_offset    = 8,
1923         },
1924         [pbn_b2_8_921600] = {
1925                 .flags          = FL_BASE2,
1926                 .num_ports      = 8,
1927                 .base_baud      = 921600,
1928                 .uart_offset    = 8,
1929         },
1930
1931         [pbn_b2_bt_1_115200] = {
1932                 .flags          = FL_BASE2|FL_BASE_BARS,
1933                 .num_ports      = 1,
1934                 .base_baud      = 115200,
1935                 .uart_offset    = 8,
1936         },
1937         [pbn_b2_bt_2_115200] = {
1938                 .flags          = FL_BASE2|FL_BASE_BARS,
1939                 .num_ports      = 2,
1940                 .base_baud      = 115200,
1941                 .uart_offset    = 8,
1942         },
1943         [pbn_b2_bt_4_115200] = {
1944                 .flags          = FL_BASE2|FL_BASE_BARS,
1945                 .num_ports      = 4,
1946                 .base_baud      = 115200,
1947                 .uart_offset    = 8,
1948         },
1949
1950         [pbn_b2_bt_2_921600] = {
1951                 .flags          = FL_BASE2|FL_BASE_BARS,
1952                 .num_ports      = 2,
1953                 .base_baud      = 921600,
1954                 .uart_offset    = 8,
1955         },
1956         [pbn_b2_bt_4_921600] = {
1957                 .flags          = FL_BASE2|FL_BASE_BARS,
1958                 .num_ports      = 4,
1959                 .base_baud      = 921600,
1960                 .uart_offset    = 8,
1961         },
1962
1963         [pbn_b3_2_115200] = {
1964                 .flags          = FL_BASE3,
1965                 .num_ports      = 2,
1966                 .base_baud      = 115200,
1967                 .uart_offset    = 8,
1968         },
1969         [pbn_b3_4_115200] = {
1970                 .flags          = FL_BASE3,
1971                 .num_ports      = 4,
1972                 .base_baud      = 115200,
1973                 .uart_offset    = 8,
1974         },
1975         [pbn_b3_8_115200] = {
1976                 .flags          = FL_BASE3,
1977                 .num_ports      = 8,
1978                 .base_baud      = 115200,
1979                 .uart_offset    = 8,
1980         },
1981
1982         /*
1983          * Entries following this are board-specific.
1984          */
1985
1986         /*
1987          * Panacom - IOMEM
1988          */
1989         [pbn_panacom] = {
1990                 .flags          = FL_BASE2,
1991                 .num_ports      = 2,
1992                 .base_baud      = 921600,
1993                 .uart_offset    = 0x400,
1994                 .reg_shift      = 7,
1995         },
1996         [pbn_panacom2] = {
1997                 .flags          = FL_BASE2|FL_BASE_BARS,
1998                 .num_ports      = 2,
1999                 .base_baud      = 921600,
2000                 .uart_offset    = 0x400,
2001                 .reg_shift      = 7,
2002         },
2003         [pbn_panacom4] = {
2004                 .flags          = FL_BASE2|FL_BASE_BARS,
2005                 .num_ports      = 4,
2006                 .base_baud      = 921600,
2007                 .uart_offset    = 0x400,
2008                 .reg_shift      = 7,
2009         },
2010
2011         [pbn_exsys_4055] = {
2012                 .flags          = FL_BASE2,
2013                 .num_ports      = 4,
2014                 .base_baud      = 115200,
2015                 .uart_offset    = 8,
2016         },
2017
2018         /* I think this entry is broken - the first_offset looks wrong --rmk */
2019         [pbn_plx_romulus] = {
2020                 .flags          = FL_BASE2,
2021                 .num_ports      = 4,
2022                 .base_baud      = 921600,
2023                 .uart_offset    = 8 << 2,
2024                 .reg_shift      = 2,
2025                 .first_offset   = 0x03,
2026         },
2027
2028         /*
2029          * This board uses the size of PCI Base region 0 to
2030          * signal now many ports are available
2031          */
2032         [pbn_oxsemi] = {
2033                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2034                 .num_ports      = 32,
2035                 .base_baud      = 115200,
2036                 .uart_offset    = 8,
2037         },
2038         [pbn_oxsemi_1_4000000] = {
2039                 .flags          = FL_BASE0,
2040                 .num_ports      = 1,
2041                 .base_baud      = 4000000,
2042                 .uart_offset    = 0x200,
2043                 .first_offset   = 0x1000,
2044         },
2045         [pbn_oxsemi_2_4000000] = {
2046                 .flags          = FL_BASE0,
2047                 .num_ports      = 2,
2048                 .base_baud      = 4000000,
2049                 .uart_offset    = 0x200,
2050                 .first_offset   = 0x1000,
2051         },
2052         [pbn_oxsemi_4_4000000] = {
2053                 .flags          = FL_BASE0,
2054                 .num_ports      = 4,
2055                 .base_baud      = 4000000,
2056                 .uart_offset    = 0x200,
2057                 .first_offset   = 0x1000,
2058         },
2059         [pbn_oxsemi_8_4000000] = {
2060                 .flags          = FL_BASE0,
2061                 .num_ports      = 8,
2062                 .base_baud      = 4000000,
2063                 .uart_offset    = 0x200,
2064                 .first_offset   = 0x1000,
2065         },
2066
2067
2068         /*
2069          * EKF addition for i960 Boards form EKF with serial port.
2070          * Max 256 ports.
2071          */
2072         [pbn_intel_i960] = {
2073                 .flags          = FL_BASE0,
2074                 .num_ports      = 32,
2075                 .base_baud      = 921600,
2076                 .uart_offset    = 8 << 2,
2077                 .reg_shift      = 2,
2078                 .first_offset   = 0x10000,
2079         },
2080         [pbn_sgi_ioc3] = {
2081                 .flags          = FL_BASE0|FL_NOIRQ,
2082                 .num_ports      = 1,
2083                 .base_baud      = 458333,
2084                 .uart_offset    = 8,
2085                 .reg_shift      = 0,
2086                 .first_offset   = 0x20178,
2087         },
2088
2089         /*
2090          * Computone - uses IOMEM.
2091          */
2092         [pbn_computone_4] = {
2093                 .flags          = FL_BASE0,
2094                 .num_ports      = 4,
2095                 .base_baud      = 921600,
2096                 .uart_offset    = 0x40,
2097                 .reg_shift      = 2,
2098                 .first_offset   = 0x200,
2099         },
2100         [pbn_computone_6] = {
2101                 .flags          = FL_BASE0,
2102                 .num_ports      = 6,
2103                 .base_baud      = 921600,
2104                 .uart_offset    = 0x40,
2105                 .reg_shift      = 2,
2106                 .first_offset   = 0x200,
2107         },
2108         [pbn_computone_8] = {
2109                 .flags          = FL_BASE0,
2110                 .num_ports      = 8,
2111                 .base_baud      = 921600,
2112                 .uart_offset    = 0x40,
2113                 .reg_shift      = 2,
2114                 .first_offset   = 0x200,
2115         },
2116         [pbn_sbsxrsio] = {
2117                 .flags          = FL_BASE0,
2118                 .num_ports      = 8,
2119                 .base_baud      = 460800,
2120                 .uart_offset    = 256,
2121                 .reg_shift      = 4,
2122         },
2123         /*
2124          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2125          *  Only basic 16550A support.
2126          *  XR17C15[24] are not tested, but they should work.
2127          */
2128         [pbn_exar_XR17C152] = {
2129                 .flags          = FL_BASE0,
2130                 .num_ports      = 2,
2131                 .base_baud      = 921600,
2132                 .uart_offset    = 0x200,
2133         },
2134         [pbn_exar_XR17C154] = {
2135                 .flags          = FL_BASE0,
2136                 .num_ports      = 4,
2137                 .base_baud      = 921600,
2138                 .uart_offset    = 0x200,
2139         },
2140         [pbn_exar_XR17C158] = {
2141                 .flags          = FL_BASE0,
2142                 .num_ports      = 8,
2143                 .base_baud      = 921600,
2144                 .uart_offset    = 0x200,
2145         },
2146         /*
2147          * PA Semi PWRficient PA6T-1682M on-chip UART
2148          */
2149         [pbn_pasemi_1682M] = {
2150                 .flags          = FL_BASE0,
2151                 .num_ports      = 1,
2152                 .base_baud      = 8333333,
2153         },
2154         /*
2155          * National Instruments 843x
2156          */
2157         [pbn_ni8430_16] = {
2158                 .flags          = FL_BASE0,
2159                 .num_ports      = 16,
2160                 .base_baud      = 3686400,
2161                 .uart_offset    = 0x10,
2162                 .first_offset   = 0x800,
2163         },
2164         [pbn_ni8430_8] = {
2165                 .flags          = FL_BASE0,
2166                 .num_ports      = 8,
2167                 .base_baud      = 3686400,
2168                 .uart_offset    = 0x10,
2169                 .first_offset   = 0x800,
2170         },
2171         [pbn_ni8430_4] = {
2172                 .flags          = FL_BASE0,
2173                 .num_ports      = 4,
2174                 .base_baud      = 3686400,
2175                 .uart_offset    = 0x10,
2176                 .first_offset   = 0x800,
2177         },
2178         [pbn_ni8430_2] = {
2179                 .flags          = FL_BASE0,
2180                 .num_ports      = 2,
2181                 .base_baud      = 3686400,
2182                 .uart_offset    = 0x10,
2183                 .first_offset   = 0x800,
2184         },
2185 };
2186
2187 static const struct pci_device_id softmodem_blacklist[] = {
2188         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2189 };
2190
2191 /*
2192  * Given a complete unknown PCI device, try to use some heuristics to
2193  * guess what the configuration might be, based on the pitiful PCI
2194  * serial specs.  Returns 0 on success, 1 on failure.
2195  */
2196 static int __devinit
2197 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2198 {
2199         const struct pci_device_id *blacklist;
2200         int num_iomem, num_port, first_port = -1, i;
2201
2202         /*
2203          * If it is not a communications device or the programming
2204          * interface is greater than 6, give up.
2205          *
2206          * (Should we try to make guesses for multiport serial devices
2207          * later?)
2208          */
2209         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2210              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2211             (dev->class & 0xff) > 6)
2212                 return -ENODEV;
2213
2214         /*
2215          * Do not access blacklisted devices that are known not to
2216          * feature serial ports.
2217          */
2218         for (blacklist = softmodem_blacklist;
2219              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2220              blacklist++) {
2221                 if (dev->vendor == blacklist->vendor &&
2222                     dev->device == blacklist->device)
2223                         return -ENODEV;
2224         }
2225
2226         num_iomem = num_port = 0;
2227         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2228                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2229                         num_port++;
2230                         if (first_port == -1)
2231                                 first_port = i;
2232                 }
2233                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2234                         num_iomem++;
2235         }
2236
2237         /*
2238          * If there is 1 or 0 iomem regions, and exactly one port,
2239          * use it.  We guess the number of ports based on the IO
2240          * region size.
2241          */
2242         if (num_iomem <= 1 && num_port == 1) {
2243                 board->flags = first_port;
2244                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2245                 return 0;
2246         }
2247
2248         /*
2249          * Now guess if we've got a board which indexes by BARs.
2250          * Each IO BAR should be 8 bytes, and they should follow
2251          * consecutively.
2252          */
2253         first_port = -1;
2254         num_port = 0;
2255         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2256                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2257                     pci_resource_len(dev, i) == 8 &&
2258                     (first_port == -1 || (first_port + num_port) == i)) {
2259                         num_port++;
2260                         if (first_port == -1)
2261                                 first_port = i;
2262                 }
2263         }
2264
2265         if (num_port > 1) {
2266                 board->flags = first_port | FL_BASE_BARS;
2267                 board->num_ports = num_port;
2268                 return 0;
2269         }
2270
2271         return -ENODEV;
2272 }
2273
2274 static inline int
2275 serial_pci_matches(const struct pciserial_board *board,
2276                    const struct pciserial_board *guessed)
2277 {
2278         return
2279             board->num_ports == guessed->num_ports &&
2280             board->base_baud == guessed->base_baud &&
2281             board->uart_offset == guessed->uart_offset &&
2282             board->reg_shift == guessed->reg_shift &&
2283             board->first_offset == guessed->first_offset;
2284 }
2285
2286 struct serial_private *
2287 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2288 {
2289         struct uart_port serial_port;
2290         struct serial_private *priv;
2291         struct pci_serial_quirk *quirk;
2292         int rc, nr_ports, i;
2293
2294         nr_ports = board->num_ports;
2295
2296         /*
2297          * Find an init and setup quirks.
2298          */
2299         quirk = find_quirk(dev);
2300
2301         /*
2302          * Run the new-style initialization function.
2303          * The initialization function returns:
2304          *  <0  - error
2305          *   0  - use board->num_ports
2306          *  >0  - number of ports
2307          */
2308         if (quirk->init) {
2309                 rc = quirk->init(dev);
2310                 if (rc < 0) {
2311                         priv = ERR_PTR(rc);
2312                         goto err_out;
2313                 }
2314                 if (rc)
2315                         nr_ports = rc;
2316         }
2317
2318         priv = kzalloc(sizeof(struct serial_private) +
2319                        sizeof(unsigned int) * nr_ports,
2320                        GFP_KERNEL);
2321         if (!priv) {
2322                 priv = ERR_PTR(-ENOMEM);
2323                 goto err_deinit;
2324         }
2325
2326         priv->dev = dev;
2327         priv->quirk = quirk;
2328
2329         memset(&serial_port, 0, sizeof(struct uart_port));
2330         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2331         serial_port.uartclk = board->base_baud * 16;
2332         serial_port.irq = get_pci_irq(dev, board);
2333         serial_port.dev = &dev->dev;
2334
2335         for (i = 0; i < nr_ports; i++) {
2336                 if (quirk->setup(priv, board, &serial_port, i))
2337                         break;
2338
2339 #ifdef SERIAL_DEBUG_PCI
2340                 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
2341                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2342 #endif
2343
2344                 priv->line[i] = serial8250_register_port(&serial_port);
2345                 if (priv->line[i] < 0) {
2346                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2347                         break;
2348                 }
2349         }
2350         priv->nr = i;
2351         return priv;
2352
2353 err_deinit:
2354         if (quirk->exit)
2355                 quirk->exit(dev);
2356 err_out:
2357         return priv;
2358 }
2359 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2360
2361 void pciserial_remove_ports(struct serial_private *priv)
2362 {
2363         struct pci_serial_quirk *quirk;
2364         int i;
2365
2366         for (i = 0; i < priv->nr; i++)
2367                 serial8250_unregister_port(priv->line[i]);
2368
2369         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2370                 if (priv->remapped_bar[i])
2371                         iounmap(priv->remapped_bar[i]);
2372                 priv->remapped_bar[i] = NULL;
2373         }
2374
2375         /*
2376          * Find the exit quirks.
2377          */
2378         quirk = find_quirk(priv->dev);
2379         if (quirk->exit)
2380                 quirk->exit(priv->dev);
2381
2382         kfree(priv);
2383 }
2384 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2385
2386 void pciserial_suspend_ports(struct serial_private *priv)
2387 {
2388         int i;
2389
2390         for (i = 0; i < priv->nr; i++)
2391                 if (priv->line[i] >= 0)
2392                         serial8250_suspend_port(priv->line[i]);
2393 }
2394 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2395
2396 void pciserial_resume_ports(struct serial_private *priv)
2397 {
2398         int i;
2399
2400         /*
2401          * Ensure that the board is correctly configured.
2402          */
2403         if (priv->quirk->init)
2404                 priv->quirk->init(priv->dev);
2405
2406         for (i = 0; i < priv->nr; i++)
2407                 if (priv->line[i] >= 0)
2408                         serial8250_resume_port(priv->line[i]);
2409 }
2410 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2411
2412 /*
2413  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2414  * to the arrangement of serial ports on a PCI card.
2415  */
2416 static int __devinit
2417 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2418 {
2419         struct serial_private *priv;
2420         const struct pciserial_board *board;
2421         struct pciserial_board tmp;
2422         int rc;
2423
2424         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2425                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2426                         ent->driver_data);
2427                 return -EINVAL;
2428         }
2429
2430         board = &pci_boards[ent->driver_data];
2431
2432         rc = pci_enable_device(dev);
2433         if (rc)
2434                 return rc;
2435
2436         if (ent->driver_data == pbn_default) {
2437                 /*
2438                  * Use a copy of the pci_board entry for this;
2439                  * avoid changing entries in the table.
2440                  */
2441                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2442                 board = &tmp;
2443
2444                 /*
2445                  * We matched one of our class entries.  Try to
2446                  * determine the parameters of this board.
2447                  */
2448                 rc = serial_pci_guess_board(dev, &tmp);
2449                 if (rc)
2450                         goto disable;
2451         } else {
2452                 /*
2453                  * We matched an explicit entry.  If we are able to
2454                  * detect this boards settings with our heuristic,
2455                  * then we no longer need this entry.
2456                  */
2457                 memcpy(&tmp, &pci_boards[pbn_default],
2458                        sizeof(struct pciserial_board));
2459                 rc = serial_pci_guess_board(dev, &tmp);
2460                 if (rc == 0 && serial_pci_matches(board, &tmp))
2461                         moan_device("Redundant entry in serial pci_table.",
2462                                     dev);
2463         }
2464
2465         priv = pciserial_init_ports(dev, board);
2466         if (!IS_ERR(priv)) {
2467                 pci_set_drvdata(dev, priv);
2468                 return 0;
2469         }
2470
2471         rc = PTR_ERR(priv);
2472
2473  disable:
2474         pci_disable_device(dev);
2475         return rc;
2476 }
2477
2478 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2479 {
2480         struct serial_private *priv = pci_get_drvdata(dev);
2481
2482         pci_set_drvdata(dev, NULL);
2483
2484         pciserial_remove_ports(priv);
2485
2486         pci_disable_device(dev);
2487 }
2488
2489 #ifdef CONFIG_PM
2490 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2491 {
2492         struct serial_private *priv = pci_get_drvdata(dev);
2493
2494         if (priv)
2495                 pciserial_suspend_ports(priv);
2496
2497         pci_save_state(dev);
2498         pci_set_power_state(dev, pci_choose_state(dev, state));
2499         return 0;
2500 }
2501
2502 static int pciserial_resume_one(struct pci_dev *dev)
2503 {
2504         int err;
2505         struct serial_private *priv = pci_get_drvdata(dev);
2506
2507         pci_set_power_state(dev, PCI_D0);
2508         pci_restore_state(dev);
2509
2510         if (priv) {
2511                 /*
2512                  * The device may have been disabled.  Re-enable it.
2513                  */
2514                 err = pci_enable_device(dev);
2515                 /* FIXME: We cannot simply error out here */
2516                 if (err)
2517                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2518                 pciserial_resume_ports(priv);
2519         }
2520         return 0;
2521 }
2522 #endif
2523
2524 static struct pci_device_id serial_pci_tbl[] = {
2525         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2526         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2527                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2528                 pbn_b2_8_921600 },
2529         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2530                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2531                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2532                 pbn_b1_8_1382400 },
2533         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2534                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2535                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2536                 pbn_b1_4_1382400 },
2537         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2538                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2539                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2540                 pbn_b1_2_1382400 },
2541         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2542                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2543                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2544                 pbn_b1_8_1382400 },
2545         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2546                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2547                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2548                 pbn_b1_4_1382400 },
2549         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2550                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2551                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2552                 pbn_b1_2_1382400 },
2553         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2554                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2555                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2556                 pbn_b1_8_921600 },
2557         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2558                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2559                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2560                 pbn_b1_8_921600 },
2561         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2562                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2563                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2564                 pbn_b1_4_921600 },
2565         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2566                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2567                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2568                 pbn_b1_4_921600 },
2569         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2570                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2571                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2572                 pbn_b1_2_921600 },
2573         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2574                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2575                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2576                 pbn_b1_8_921600 },
2577         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2578                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2579                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2580                 pbn_b1_8_921600 },
2581         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2582                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2583                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2584                 pbn_b1_4_921600 },
2585         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2586                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2587                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2588                 pbn_b1_2_1250000 },
2589         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2590                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2591                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2592                 pbn_b0_2_1843200 },
2593         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2594                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2595                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2596                 pbn_b0_4_1843200 },
2597         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2598                 PCI_VENDOR_ID_AFAVLAB,
2599                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2600                 pbn_b0_4_1152000 },
2601         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2602                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2603                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2604                 pbn_b0_2_1843200_200 },
2605         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2606                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2607                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2608                 pbn_b0_4_1843200_200 },
2609         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2610                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2611                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2612                 pbn_b0_8_1843200_200 },
2613         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2614                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2615                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2616                 pbn_b0_2_1843200_200 },
2617         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2618                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2619                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2620                 pbn_b0_4_1843200_200 },
2621         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2622                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2623                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2624                 pbn_b0_8_1843200_200 },
2625         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2626                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2627                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2628                 pbn_b0_2_1843200_200 },
2629         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2630                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2631                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2632                 pbn_b0_4_1843200_200 },
2633         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2634                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2635                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2636                 pbn_b0_8_1843200_200 },
2637         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2638                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2639                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2640                 pbn_b0_2_1843200_200 },
2641         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2642                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2643                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2644                 pbn_b0_4_1843200_200 },
2645         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2646                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2647                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2648                 pbn_b0_8_1843200_200 },
2649
2650         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2651                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2652                 pbn_b2_bt_1_115200 },
2653         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2654                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2655                 pbn_b2_bt_2_115200 },
2656         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2657                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2658                 pbn_b2_bt_4_115200 },
2659         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2660                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2661                 pbn_b2_bt_2_115200 },
2662         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2663                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2664                 pbn_b2_bt_4_115200 },
2665         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2666                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2667                 pbn_b2_8_115200 },
2668         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2669                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2670                 pbn_b2_8_460800 },
2671         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2672                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2673                 pbn_b2_8_115200 },
2674
2675         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2676                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2677                 pbn_b2_bt_2_115200 },
2678         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2679                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2680                 pbn_b2_bt_2_921600 },
2681         /*
2682          * VScom SPCOM800, from sl@s.pl
2683          */
2684         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2685                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2686                 pbn_b2_8_921600 },
2687         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2688                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2689                 pbn_b2_4_921600 },
2690         /* Unknown card - subdevice 0x1584 */
2691         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2692                 PCI_VENDOR_ID_PLX,
2693                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2694                 pbn_b0_4_115200 },
2695         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2696                 PCI_SUBVENDOR_ID_KEYSPAN,
2697                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2698                 pbn_panacom },
2699         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2700                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2701                 pbn_panacom4 },
2702         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2703                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2704                 pbn_panacom2 },
2705         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2706                 PCI_VENDOR_ID_ESDGMBH,
2707                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2708                 pbn_b2_4_115200 },
2709         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2710                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2711                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2712                 pbn_b2_4_460800 },
2713         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2714                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2715                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2716                 pbn_b2_8_460800 },
2717         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2718                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2719                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2720                 pbn_b2_16_460800 },
2721         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2722                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2723                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2724                 pbn_b2_16_460800 },
2725         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2726                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2727                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2728                 pbn_b2_4_460800 },
2729         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2730                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2731                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2732                 pbn_b2_8_460800 },
2733         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2734                 PCI_SUBVENDOR_ID_EXSYS,
2735                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2736                 pbn_exsys_4055 },
2737         /*
2738          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2739          * (Exoray@isys.ca)
2740          */
2741         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2742                 0x10b5, 0x106a, 0, 0,
2743                 pbn_plx_romulus },
2744         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2745                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2746                 pbn_b1_4_115200 },
2747         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2748                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2749                 pbn_b1_2_115200 },
2750         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2751                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2752                 pbn_b1_8_115200 },
2753         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2754                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2755                 pbn_b1_8_115200 },
2756         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2757                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2758                 0, 0,
2759                 pbn_b0_4_921600 },
2760         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2761                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2762                 0, 0,
2763                 pbn_b0_4_1152000 },
2764
2765                 /*
2766                  * The below card is a little controversial since it is the
2767                  * subject of a PCI vendor/device ID clash.  (See
2768                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2769                  * For now just used the hex ID 0x950a.
2770                  */
2771         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2772                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2773                 pbn_b0_2_115200 },
2774         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2775                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2776                 pbn_b0_2_1130000 },
2777         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2778                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2779                 pbn_b0_1_921600 },
2780         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2781                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2782                 pbn_b0_4_115200 },
2783         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2784                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2785                 pbn_b0_bt_2_921600 },
2786
2787         /*
2788          * Oxford Semiconductor Inc. Tornado PCI express device range.
2789          */
2790         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
2791                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2792                 pbn_b0_1_4000000 },
2793         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
2794                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2795                 pbn_b0_1_4000000 },
2796         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
2797                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2798                 pbn_oxsemi_1_4000000 },
2799         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
2800                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2801                 pbn_oxsemi_1_4000000 },
2802         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
2803                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2804                 pbn_b0_1_4000000 },
2805         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
2806                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2807                 pbn_b0_1_4000000 },
2808         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
2809                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2810                 pbn_oxsemi_1_4000000 },
2811         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
2812                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2813                 pbn_oxsemi_1_4000000 },
2814         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
2815                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2816                 pbn_b0_1_4000000 },
2817         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
2818                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2819                 pbn_b0_1_4000000 },
2820         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
2821                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2822                 pbn_b0_1_4000000 },
2823         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
2824                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2825                 pbn_b0_1_4000000 },
2826         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
2827                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2828                 pbn_oxsemi_2_4000000 },
2829         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
2830                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2831                 pbn_oxsemi_2_4000000 },
2832         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
2833                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2834                 pbn_oxsemi_4_4000000 },
2835         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
2836                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2837                 pbn_oxsemi_4_4000000 },
2838         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
2839                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2840                 pbn_oxsemi_8_4000000 },
2841         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
2842                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2843                 pbn_oxsemi_8_4000000 },
2844         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
2845                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2846                 pbn_oxsemi_1_4000000 },
2847         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
2848                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2849                 pbn_oxsemi_1_4000000 },
2850         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
2851                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2852                 pbn_oxsemi_1_4000000 },
2853         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
2854                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2855                 pbn_oxsemi_1_4000000 },
2856         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
2857                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2858                 pbn_oxsemi_1_4000000 },
2859         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
2860                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2861                 pbn_oxsemi_1_4000000 },
2862         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
2863                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2864                 pbn_oxsemi_1_4000000 },
2865         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
2866                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2867                 pbn_oxsemi_1_4000000 },
2868         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
2869                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2870                 pbn_oxsemi_1_4000000 },
2871         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
2872                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2873                 pbn_oxsemi_1_4000000 },
2874         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
2875                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2876                 pbn_oxsemi_1_4000000 },
2877         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
2878                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2879                 pbn_oxsemi_1_4000000 },
2880         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
2881                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2882                 pbn_oxsemi_1_4000000 },
2883         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
2884                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2885                 pbn_oxsemi_1_4000000 },
2886         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
2887                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2888                 pbn_oxsemi_1_4000000 },
2889         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
2890                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2891                 pbn_oxsemi_1_4000000 },
2892         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
2893                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2894                 pbn_oxsemi_1_4000000 },
2895         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
2896                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2897                 pbn_oxsemi_1_4000000 },
2898         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
2899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2900                 pbn_oxsemi_1_4000000 },
2901         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
2902                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2903                 pbn_oxsemi_1_4000000 },
2904         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
2905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2906                 pbn_oxsemi_1_4000000 },
2907         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
2908                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2909                 pbn_oxsemi_1_4000000 },
2910         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
2911                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2912                 pbn_oxsemi_1_4000000 },
2913         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
2914                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2915                 pbn_oxsemi_1_4000000 },
2916         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
2917                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2918                 pbn_oxsemi_1_4000000 },
2919         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
2920                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2921                 pbn_oxsemi_1_4000000 },
2922         /*
2923          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2924          */
2925         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2926                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2927                 pbn_oxsemi_1_4000000 },
2928         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2929                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2930                 pbn_oxsemi_2_4000000 },
2931         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2932                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2933                 pbn_oxsemi_4_4000000 },
2934         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2935                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2936                 pbn_oxsemi_8_4000000 },
2937         /*
2938          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2939          * from skokodyn@yahoo.com
2940          */
2941         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2942                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2943                 pbn_sbsxrsio },
2944         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2945                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2946                 pbn_sbsxrsio },
2947         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2948                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2949                 pbn_sbsxrsio },
2950         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2951                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2952                 pbn_sbsxrsio },
2953
2954         /*
2955          * Digitan DS560-558, from jimd@esoft.com
2956          */
2957         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2958                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2959                 pbn_b1_1_115200 },
2960
2961         /*
2962          * Titan Electronic cards
2963          *  The 400L and 800L have a custom setup quirk.
2964          */
2965         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2966                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2967                 pbn_b0_1_921600 },
2968         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2969                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2970                 pbn_b0_2_921600 },
2971         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2972                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2973                 pbn_b0_4_921600 },
2974         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2975                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2976                 pbn_b0_4_921600 },
2977         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2978                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2979                 pbn_b1_1_921600 },
2980         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2981                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2982                 pbn_b1_bt_2_921600 },
2983         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2984                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2985                 pbn_b0_bt_4_921600 },
2986         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2987                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2988                 pbn_b0_bt_8_921600 },
2989
2990         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2991                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2992                 pbn_b2_1_460800 },
2993         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2994                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2995                 pbn_b2_1_460800 },
2996         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2997                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2998                 pbn_b2_1_460800 },
2999         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3000                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3001                 pbn_b2_bt_2_921600 },
3002         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3003                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3004                 pbn_b2_bt_2_921600 },
3005         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3006                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3007                 pbn_b2_bt_2_921600 },
3008         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3009                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3010                 pbn_b2_bt_4_921600 },
3011         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3012                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3013                 pbn_b2_bt_4_921600 },
3014         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3015                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3016                 pbn_b2_bt_4_921600 },
3017         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3018                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3019                 pbn_b0_1_921600 },
3020         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3021                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3022                 pbn_b0_1_921600 },
3023         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3024                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3025                 pbn_b0_1_921600 },
3026         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3027                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3028                 pbn_b0_bt_2_921600 },
3029         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3030                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3031                 pbn_b0_bt_2_921600 },
3032         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3033                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3034                 pbn_b0_bt_2_921600 },
3035         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3036                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3037                 pbn_b0_bt_4_921600 },
3038         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3039                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3040                 pbn_b0_bt_4_921600 },
3041         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3042                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3043                 pbn_b0_bt_4_921600 },
3044         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3045                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3046                 pbn_b0_bt_8_921600 },
3047         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3048                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3049                 pbn_b0_bt_8_921600 },
3050         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3051                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3052                 pbn_b0_bt_8_921600 },
3053
3054         /*
3055          * Computone devices submitted by Doug McNash dmcnash@computone.com
3056          */
3057         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3058                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3059                 0, 0, pbn_computone_4 },
3060         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3061                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3062                 0, 0, pbn_computone_8 },
3063         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3064                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3065                 0, 0, pbn_computone_6 },
3066
3067         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3068                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3069                 pbn_oxsemi },
3070         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3071                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3072                 pbn_b0_bt_1_921600 },
3073
3074         /*
3075          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3076          */
3077         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3078                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3079                 pbn_b0_bt_8_115200 },
3080         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3081                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3082                 pbn_b0_bt_8_115200 },
3083
3084         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3085                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3086                 pbn_b0_bt_2_115200 },
3087         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3088                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3089                 pbn_b0_bt_2_115200 },
3090         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3091                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3092                 pbn_b0_bt_2_115200 },
3093         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3094                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3095                 pbn_b0_bt_4_460800 },
3096         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3097                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3098                 pbn_b0_bt_4_460800 },
3099         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3100                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3101                 pbn_b0_bt_2_460800 },
3102         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3103                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3104                 pbn_b0_bt_2_460800 },
3105         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3107                 pbn_b0_bt_2_460800 },
3108         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3109                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3110                 pbn_b0_bt_1_115200 },
3111         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3112                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3113                 pbn_b0_bt_1_460800 },
3114
3115         /*
3116          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3117          * Cards are identified by their subsystem vendor IDs, which
3118          * (in hex) match the model number.
3119          *
3120          * Note that JC140x are RS422/485 cards which require ox950
3121          * ACR = 0x10, and as such are not currently fully supported.
3122          */
3123         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3124                 0x1204, 0x0004, 0, 0,
3125                 pbn_b0_4_921600 },
3126         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3127                 0x1208, 0x0004, 0, 0,
3128                 pbn_b0_4_921600 },
3129 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3130                 0x1402, 0x0002, 0, 0,
3131                 pbn_b0_2_921600 }, */
3132 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3133                 0x1404, 0x0004, 0, 0,
3134                 pbn_b0_4_921600 }, */
3135         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3136                 0x1208, 0x0004, 0, 0,
3137                 pbn_b0_4_921600 },
3138
3139         /*
3140          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3141          */
3142         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3143                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3144                 pbn_b1_1_1382400 },
3145
3146         /*
3147          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3148          */
3149         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3150                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3151                 pbn_b1_1_1382400 },
3152
3153         /*
3154          * RAStel 2 port modem, gerg@moreton.com.au
3155          */
3156         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3157                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3158                 pbn_b2_bt_2_115200 },
3159
3160         /*
3161          * EKF addition for i960 Boards form EKF with serial port
3162          */
3163         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3164                 0xE4BF, PCI_ANY_ID, 0, 0,
3165                 pbn_intel_i960 },
3166
3167         /*
3168          * Xircom Cardbus/Ethernet combos
3169          */
3170         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3171                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3172                 pbn_b0_1_115200 },
3173         /*
3174          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3175          */
3176         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3177                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3178                 pbn_b0_1_115200 },
3179
3180         /*
3181          * Untested PCI modems, sent in from various folks...
3182          */
3183
3184         /*
3185          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3186          */
3187         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3188                 0x1048, 0x1500, 0, 0,
3189                 pbn_b1_1_115200 },
3190
3191         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3192                 0xFF00, 0, 0, 0,
3193                 pbn_sgi_ioc3 },
3194
3195         /*
3196          * HP Diva card
3197          */
3198         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3199                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3200                 pbn_b1_1_115200 },
3201         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3202                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3203                 pbn_b0_5_115200 },
3204         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3205                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3206                 pbn_b2_1_115200 },
3207
3208         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3209                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3210                 pbn_b3_2_115200 },
3211         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3212                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3213                 pbn_b3_4_115200 },
3214         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3215                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3216                 pbn_b3_8_115200 },
3217
3218         /*
3219          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3220          */
3221         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3222                 PCI_ANY_ID, PCI_ANY_ID,
3223                 0,
3224                 0, pbn_exar_XR17C152 },
3225         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3226                 PCI_ANY_ID, PCI_ANY_ID,
3227                 0,
3228                 0, pbn_exar_XR17C154 },
3229         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3230                 PCI_ANY_ID, PCI_ANY_ID,
3231                 0,
3232                 0, pbn_exar_XR17C158 },
3233
3234         /*
3235          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3236          */
3237         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3238                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239                 pbn_b0_1_115200 },
3240         /*
3241          * ITE
3242          */
3243         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3244                 PCI_ANY_ID, PCI_ANY_ID,
3245                 0, 0,
3246                 pbn_b1_bt_1_115200 },
3247
3248         /*
3249          * IntaShield IS-200
3250          */
3251         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3252                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3253                 pbn_b2_2_115200 },
3254         /*
3255          * IntaShield IS-400
3256          */
3257         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3258                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3259                 pbn_b2_4_115200 },
3260         /*
3261          * Perle PCI-RAS cards
3262          */
3263         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3264                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3265                 0, 0, pbn_b2_4_921600 },
3266         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3267                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3268                 0, 0, pbn_b2_8_921600 },
3269
3270         /*
3271          * Mainpine series cards: Fairly standard layout but fools
3272          * parts of the autodetect in some cases and uses otherwise
3273          * unmatched communications subclasses in the PCI Express case
3274          */
3275
3276         {       /* RockForceDUO */
3277                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3278                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3279                 0, 0, pbn_b0_2_115200 },
3280         {       /* RockForceQUATRO */
3281                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3282                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3283                 0, 0, pbn_b0_4_115200 },
3284         {       /* RockForceDUO+ */
3285                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3286                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3287                 0, 0, pbn_b0_2_115200 },
3288         {       /* RockForceQUATRO+ */
3289                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3290                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3291                 0, 0, pbn_b0_4_115200 },
3292         {       /* RockForce+ */
3293                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3294                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3295                 0, 0, pbn_b0_2_115200 },
3296         {       /* RockForce+ */
3297                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3298                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3299                 0, 0, pbn_b0_4_115200 },
3300         {       /* RockForceOCTO+ */
3301                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3302                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3303                 0, 0, pbn_b0_8_115200 },
3304         {       /* RockForceDUO+ */
3305                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3306                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3307                 0, 0, pbn_b0_2_115200 },
3308         {       /* RockForceQUARTRO+ */
3309                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3310                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3311                 0, 0, pbn_b0_4_115200 },
3312         {       /* RockForceOCTO+ */
3313                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3314                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3315                 0, 0, pbn_b0_8_115200 },
3316         {       /* RockForceD1 */
3317                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3318                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3319                 0, 0, pbn_b0_1_115200 },
3320         {       /* RockForceF1 */
3321                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3322                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3323                 0, 0, pbn_b0_1_115200 },
3324         {       /* RockForceD2 */
3325                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3326                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3327                 0, 0, pbn_b0_2_115200 },
3328         {       /* RockForceF2 */
3329                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3330                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3331                 0, 0, pbn_b0_2_115200 },
3332         {       /* RockForceD4 */
3333                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3334                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3335                 0, 0, pbn_b0_4_115200 },
3336         {       /* RockForceF4 */
3337                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3338                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3339                 0, 0, pbn_b0_4_115200 },
3340         {       /* RockForceD8 */
3341                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3342                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3343                 0, 0, pbn_b0_8_115200 },
3344         {       /* RockForceF8 */
3345                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3346                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3347                 0, 0, pbn_b0_8_115200 },
3348         {       /* IQ Express D1 */
3349                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3350                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3351                 0, 0, pbn_b0_1_115200 },
3352         {       /* IQ Express F1 */
3353                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3354                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3355                 0, 0, pbn_b0_1_115200 },
3356         {       /* IQ Express D2 */
3357                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3358                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3359                 0, 0, pbn_b0_2_115200 },
3360         {       /* IQ Express F2 */
3361                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3362                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3363                 0, 0, pbn_b0_2_115200 },
3364         {       /* IQ Express D4 */
3365                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3366                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3367                 0, 0, pbn_b0_4_115200 },
3368         {       /* IQ Express F4 */
3369                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3370                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3371                 0, 0, pbn_b0_4_115200 },
3372         {       /* IQ Express D8 */
3373                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3374                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3375                 0, 0, pbn_b0_8_115200 },
3376         {       /* IQ Express F8 */
3377                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3378                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3379                 0, 0, pbn_b0_8_115200 },
3380
3381
3382         /*
3383          * PA Semi PA6T-1682M on-chip UART
3384          */
3385         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3386                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3387                 pbn_pasemi_1682M },
3388
3389         /*
3390          * National Instruments
3391          */
3392         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3393                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3394                 pbn_b1_16_115200 },
3395         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3396                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3397                 pbn_b1_8_115200 },
3398         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3400                 pbn_b1_bt_4_115200 },
3401         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3402                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3403                 pbn_b1_bt_2_115200 },
3404         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3405                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3406                 pbn_b1_bt_4_115200 },
3407         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3408                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3409                 pbn_b1_bt_2_115200 },
3410         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3411                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3412                 pbn_b1_16_115200 },
3413         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3414                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3415                 pbn_b1_8_115200 },
3416         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3417                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3418                 pbn_b1_bt_4_115200 },
3419         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3420                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3421                 pbn_b1_bt_2_115200 },
3422         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3423                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3424                 pbn_b1_bt_4_115200 },
3425         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3426                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3427                 pbn_b1_bt_2_115200 },
3428         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3429                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3430                 pbn_ni8430_2 },
3431         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3432                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3433                 pbn_ni8430_2 },
3434         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3435                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3436                 pbn_ni8430_4 },
3437         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3438                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3439                 pbn_ni8430_4 },
3440         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3441                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3442                 pbn_ni8430_8 },
3443         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3444                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3445                 pbn_ni8430_8 },
3446         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3447                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3448                 pbn_ni8430_16 },
3449         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3450                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3451                 pbn_ni8430_16 },
3452         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3453                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3454                 pbn_ni8430_2 },
3455         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3456                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3457                 pbn_ni8430_2 },
3458         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3459                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3460                 pbn_ni8430_4 },
3461         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3462                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3463                 pbn_ni8430_4 },
3464
3465         /*
3466         * ADDI-DATA GmbH communication cards <info@addi-data.com>
3467         */
3468         {       PCI_VENDOR_ID_ADDIDATA,
3469                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3470                 PCI_ANY_ID,
3471                 PCI_ANY_ID,
3472                 0,
3473                 0,
3474                 pbn_b0_4_115200 },
3475
3476         {       PCI_VENDOR_ID_ADDIDATA,
3477                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3478                 PCI_ANY_ID,
3479                 PCI_ANY_ID,
3480                 0,
3481                 0,
3482                 pbn_b0_2_115200 },
3483
3484         {       PCI_VENDOR_ID_ADDIDATA,
3485                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3486                 PCI_ANY_ID,
3487                 PCI_ANY_ID,
3488                 0,
3489                 0,
3490                 pbn_b0_1_115200 },
3491
3492         {       PCI_VENDOR_ID_ADDIDATA_OLD,
3493                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3494                 PCI_ANY_ID,
3495                 PCI_ANY_ID,
3496                 0,
3497                 0,
3498                 pbn_b1_8_115200 },
3499
3500         {       PCI_VENDOR_ID_ADDIDATA,
3501                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3502                 PCI_ANY_ID,
3503                 PCI_ANY_ID,
3504                 0,
3505                 0,
3506                 pbn_b0_4_115200 },
3507
3508         {       PCI_VENDOR_ID_ADDIDATA,
3509                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3510                 PCI_ANY_ID,
3511                 PCI_ANY_ID,
3512                 0,
3513                 0,
3514                 pbn_b0_2_115200 },
3515
3516         {       PCI_VENDOR_ID_ADDIDATA,
3517                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3518                 PCI_ANY_ID,
3519                 PCI_ANY_ID,
3520                 0,
3521                 0,
3522                 pbn_b0_1_115200 },
3523
3524         {       PCI_VENDOR_ID_ADDIDATA,
3525                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3526                 PCI_ANY_ID,
3527                 PCI_ANY_ID,
3528                 0,
3529                 0,
3530                 pbn_b0_4_115200 },
3531
3532         {       PCI_VENDOR_ID_ADDIDATA,
3533                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3534                 PCI_ANY_ID,
3535                 PCI_ANY_ID,
3536                 0,
3537                 0,
3538                 pbn_b0_2_115200 },
3539
3540         {       PCI_VENDOR_ID_ADDIDATA,
3541                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3542                 PCI_ANY_ID,
3543                 PCI_ANY_ID,
3544                 0,
3545                 0,
3546                 pbn_b0_1_115200 },
3547
3548         {       PCI_VENDOR_ID_ADDIDATA,
3549                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3550                 PCI_ANY_ID,
3551                 PCI_ANY_ID,
3552                 0,
3553                 0,
3554                 pbn_b0_8_115200 },
3555
3556         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3557                 PCI_VENDOR_ID_IBM, 0x0299,
3558                 0, 0, pbn_b0_bt_2_115200 },
3559
3560         /*
3561          * These entries match devices with class COMMUNICATION_SERIAL,
3562          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3563          */
3564         {       PCI_ANY_ID, PCI_ANY_ID,
3565                 PCI_ANY_ID, PCI_ANY_ID,
3566                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3567                 0xffff00, pbn_default },
3568         {       PCI_ANY_ID, PCI_ANY_ID,
3569                 PCI_ANY_ID, PCI_ANY_ID,
3570                 PCI_CLASS_COMMUNICATION_MODEM << 8,
3571                 0xffff00, pbn_default },
3572         {       PCI_ANY_ID, PCI_ANY_ID,
3573                 PCI_ANY_ID, PCI_ANY_ID,
3574                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3575                 0xffff00, pbn_default },
3576         { 0, }
3577 };
3578
3579 static struct pci_driver serial_pci_driver = {
3580         .name           = "serial",
3581         .probe          = pciserial_init_one,
3582         .remove         = __devexit_p(pciserial_remove_one),
3583 #ifdef CONFIG_PM
3584         .suspend        = pciserial_suspend_one,
3585         .resume         = pciserial_resume_one,
3586 #endif
3587         .id_table       = serial_pci_tbl,
3588 };
3589
3590 static int __init serial8250_pci_init(void)
3591 {
3592         return pci_register_driver(&serial_pci_driver);
3593 }
3594
3595 static void __exit serial8250_pci_exit(void)
3596 {
3597         pci_unregister_driver(&serial_pci_driver);
3598 }
3599
3600 module_init(serial8250_pci_init);
3601 module_exit(serial8250_pci_exit);
3602
3603 MODULE_LICENSE("GPL");
3604 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3605 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);