2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
18 /* Ugh. Need to stop exporting this to modules. */
19 LIST_HEAD(pci_root_buses);
20 EXPORT_SYMBOL(pci_root_buses);
23 static int find_anything(struct device *dev, void *data)
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
33 int no_pci_devices(void)
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
43 EXPORT_SYMBOL(no_pci_devices);
45 #ifdef HAVE_PCI_LEGACY
47 * pci_create_legacy_files - create legacy I/O port and memory files
48 * @b: bus to create files under
50 * Some platforms allow access to legacy I/O port and ISA memory space on
51 * a per-bus basis. This routine creates the files and ties them into
52 * their associated read, write and mmap files from pci-sysfs.c
54 * On error unwind, but don't propogate the error to the caller
55 * as it is ok to set up the PCI bus without these files.
57 static void pci_create_legacy_files(struct pci_bus *b)
61 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
66 b->legacy_io->attr.name = "legacy_io";
67 b->legacy_io->size = 0xffff;
68 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
69 b->legacy_io->read = pci_read_legacy_io;
70 b->legacy_io->write = pci_write_legacy_io;
71 error = device_create_bin_file(&b->dev, b->legacy_io);
75 /* Allocated above after the legacy_io struct */
76 b->legacy_mem = b->legacy_io + 1;
77 b->legacy_mem->attr.name = "legacy_mem";
78 b->legacy_mem->size = 1024*1024;
79 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
80 b->legacy_mem->mmap = pci_mmap_legacy_mem;
81 error = device_create_bin_file(&b->dev, b->legacy_mem);
88 device_remove_bin_file(&b->dev, b->legacy_io);
93 printk(KERN_WARNING "pci: warning: could not create legacy I/O port "
94 "and ISA memory resources to sysfs\n");
98 void pci_remove_legacy_files(struct pci_bus *b)
101 device_remove_bin_file(&b->dev, b->legacy_io);
102 device_remove_bin_file(&b->dev, b->legacy_mem);
103 kfree(b->legacy_io); /* both are allocated here */
106 #else /* !HAVE_PCI_LEGACY */
107 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
108 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
109 #endif /* HAVE_PCI_LEGACY */
112 * PCI Bus Class Devices
114 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
116 struct device_attribute *attr,
122 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
124 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask):
125 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
131 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
132 struct device_attribute *attr,
135 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
138 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
139 struct device_attribute *attr,
142 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
145 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
146 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
151 static void release_pcibus_dev(struct device *dev)
153 struct pci_bus *pci_bus = to_pci_bus(dev);
156 put_device(pci_bus->bridge);
160 static struct class pcibus_class = {
162 .dev_release = &release_pcibus_dev,
165 static int __init pcibus_class_init(void)
167 return class_register(&pcibus_class);
169 postcore_initcall(pcibus_class_init);
172 * Translate the low bits of the PCI base
173 * to the resource type
175 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
177 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
178 return IORESOURCE_IO;
180 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
181 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
183 return IORESOURCE_MEM;
186 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
188 u64 size = mask & maxbase; /* Find the significant bits */
192 /* Get the lowest of them to find the decode size, and
193 from that the extent. */
194 size = (size & ~(size-1)) - 1;
196 /* base == maxbase can be valid only if the BAR has
197 already been programmed with all 1s. */
198 if (base == maxbase && ((base | size) & mask) != mask)
205 pci_bar_unknown, /* Standard PCI BAR probe */
206 pci_bar_io, /* An io port BAR */
207 pci_bar_mem32, /* A 32-bit memory BAR */
208 pci_bar_mem64, /* A 64-bit memory BAR */
211 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
213 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
214 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
218 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
220 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
221 return pci_bar_mem64;
222 return pci_bar_mem32;
226 * If the type is not unknown, we assume that the lowest bit is 'enable'.
227 * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit.
229 static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
230 struct resource *res, unsigned int pos)
234 mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
236 res->name = pci_name(dev);
238 pci_read_config_dword(dev, pos, &l);
239 pci_write_config_dword(dev, pos, mask);
240 pci_read_config_dword(dev, pos, &sz);
241 pci_write_config_dword(dev, pos, l);
244 * All bits set in sz means the device isn't working properly.
245 * If the BAR isn't implemented, all bits must be 0. If it's a
246 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
249 if (!sz || sz == 0xffffffff)
253 * I don't know how l can have all bits set. Copied from old code.
254 * Maybe it fixes a bug on some ancient platform.
259 if (type == pci_bar_unknown) {
260 type = decode_bar(res, l);
261 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
262 if (type == pci_bar_io) {
263 l &= PCI_BASE_ADDRESS_IO_MASK;
264 mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff;
266 l &= PCI_BASE_ADDRESS_MEM_MASK;
267 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
270 res->flags |= (l & IORESOURCE_ROM_ENABLE);
271 l &= PCI_ROM_ADDRESS_MASK;
272 mask = (u32)PCI_ROM_ADDRESS_MASK;
275 if (type == pci_bar_mem64) {
278 u64 mask64 = mask | (u64)~0 << 32;
280 pci_read_config_dword(dev, pos + 4, &l);
281 pci_write_config_dword(dev, pos + 4, ~0);
282 pci_read_config_dword(dev, pos + 4, &sz);
283 pci_write_config_dword(dev, pos + 4, l);
285 l64 |= ((u64)l << 32);
286 sz64 |= ((u64)sz << 32);
288 sz64 = pci_size(l64, sz64, mask64);
293 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
294 dev_err(&dev->dev, "can't handle 64-bit BAR\n");
296 } else if ((sizeof(resource_size_t) < 8) && l) {
297 /* Address above 32-bit boundary; disable the BAR */
298 pci_write_config_dword(dev, pos, 0);
299 pci_write_config_dword(dev, pos + 4, 0);
304 res->end = l64 + sz64;
305 printk(KERN_DEBUG "PCI: %s reg %x 64bit mmio: %pR\n",
306 pci_name(dev), pos, res);
309 sz = pci_size(l, sz, mask);
316 printk(KERN_DEBUG "PCI: %s reg %x %s: %pR\n",
318 (res->flags & IORESOURCE_IO) ? "io port":"32bit mmio",
323 return (type == pci_bar_mem64) ? 1 : 0;
329 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
331 unsigned int pos, reg;
333 for (pos = 0; pos < howmany; pos++) {
334 struct resource *res = &dev->resource[pos];
335 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
336 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
340 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
341 dev->rom_base_reg = rom;
342 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
343 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
344 IORESOURCE_SIZEALIGN;
345 __pci_read_base(dev, pci_bar_mem32, res, rom);
349 void __devinit pci_read_bridge_bases(struct pci_bus *child)
351 struct pci_dev *dev = child->self;
352 u8 io_base_lo, io_limit_lo;
353 u16 mem_base_lo, mem_limit_lo;
354 unsigned long base, limit;
355 struct resource *res;
358 if (!dev) /* It's a host bus, nothing to read */
361 if (dev->transparent) {
362 dev_info(&dev->dev, "transparent bridge\n");
363 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
364 child->resource[i] = child->parent->resource[i - 3];
368 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
370 res = child->resource[0];
371 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
372 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
373 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
374 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
376 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
377 u16 io_base_hi, io_limit_hi;
378 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
379 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
380 base |= (io_base_hi << 16);
381 limit |= (io_limit_hi << 16);
385 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
389 res->end = limit + 0xfff;
390 printk(KERN_DEBUG "PCI: bridge %s io port: %pR\n",
394 res = child->resource[1];
395 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
396 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
397 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
398 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
400 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
402 res->end = limit + 0xfffff;
403 printk(KERN_DEBUG "PCI: bridge %s 32bit mmio: %pR\n",
407 res = child->resource[2];
408 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
409 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
410 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
411 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
413 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
414 u32 mem_base_hi, mem_limit_hi;
415 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
416 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
419 * Some bridges set the base > limit by default, and some
420 * (broken) BIOSes do not initialize them. If we find
421 * this, just assume they are not being used.
423 if (mem_base_hi <= mem_limit_hi) {
424 #if BITS_PER_LONG == 64
425 base |= ((long) mem_base_hi) << 32;
426 limit |= ((long) mem_limit_hi) << 32;
428 if (mem_base_hi || mem_limit_hi) {
429 dev_err(&dev->dev, "can't handle 64-bit "
430 "address space for bridge\n");
437 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
439 res->end = limit + 0xfffff;
440 printk(KERN_DEBUG "PCI: bridge %s %sbit mmio pref: %pR\n",
442 (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64":"32", res);
446 static struct pci_bus * pci_alloc_bus(void)
450 b = kzalloc(sizeof(*b), GFP_KERNEL);
452 INIT_LIST_HEAD(&b->node);
453 INIT_LIST_HEAD(&b->children);
454 INIT_LIST_HEAD(&b->devices);
455 INIT_LIST_HEAD(&b->slots);
460 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
461 struct pci_dev *bridge, int busnr)
463 struct pci_bus *child;
467 * Allocate a new bus, and inherit stuff from the parent..
469 child = pci_alloc_bus();
473 child->self = bridge;
474 child->parent = parent;
475 child->ops = parent->ops;
476 child->sysdata = parent->sysdata;
477 child->bus_flags = parent->bus_flags;
478 child->bridge = get_device(&bridge->dev);
480 /* initialize some portions of the bus device, but don't register it
481 * now as the parent is not properly set up yet. This device will get
482 * registered later in pci_bus_add_devices()
484 child->dev.class = &pcibus_class;
485 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
488 * Set up the primary, secondary and subordinate
491 child->number = child->secondary = busnr;
492 child->primary = parent->secondary;
493 child->subordinate = 0xff;
495 /* Set up default resource pointers and names.. */
496 for (i = 0; i < 4; i++) {
497 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
498 child->resource[i]->name = child->name;
500 bridge->subordinate = child;
505 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
507 struct pci_bus *child;
509 child = pci_alloc_child_bus(parent, dev, busnr);
511 down_write(&pci_bus_sem);
512 list_add_tail(&child->node, &parent->children);
513 up_write(&pci_bus_sem);
518 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
520 struct pci_bus *parent = child->parent;
522 /* Attempts to fix that up are really dangerous unless
523 we're going to re-assign all bus numbers. */
524 if (!pcibios_assign_all_busses())
527 while (parent->parent && parent->subordinate < max) {
528 parent->subordinate = max;
529 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
530 parent = parent->parent;
535 * If it's a bridge, configure it and scan the bus behind it.
536 * For CardBus bridges, we don't scan behind as the devices will
537 * be handled by the bridge driver itself.
539 * We need to process bridges in two passes -- first we scan those
540 * already configured by the BIOS and after we are done with all of
541 * them, we proceed to assigning numbers to the remaining buses in
542 * order to avoid overlaps between old and new bus numbers.
544 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
546 struct pci_bus *child;
547 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
551 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
553 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
554 buses & 0xffffff, pass);
556 /* Disable MasterAbortMode during probing to avoid reporting
557 of bus errors (in some architectures) */
558 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
559 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
560 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
562 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
563 unsigned int cmax, busnr;
565 * Bus already configured by firmware, process it in the first
566 * pass and just note the configuration.
570 busnr = (buses >> 8) & 0xFF;
573 * If we already got to this bus through a different bridge,
574 * ignore it. This can happen with the i450NX chipset.
576 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
577 dev_info(&dev->dev, "bus %04x:%02x already known\n",
578 pci_domain_nr(bus), busnr);
582 child = pci_add_new_bus(bus, dev, busnr);
585 child->primary = buses & 0xFF;
586 child->subordinate = (buses >> 16) & 0xFF;
587 child->bridge_ctl = bctl;
589 cmax = pci_scan_child_bus(child);
592 if (child->subordinate > max)
593 max = child->subordinate;
596 * We need to assign a number to this bus which we always
597 * do in the second pass.
600 if (pcibios_assign_all_busses())
601 /* Temporarily disable forwarding of the
602 configuration cycles on all bridges in
603 this bus segment to avoid possible
604 conflicts in the second pass between two
605 bridges programmed with overlapping
607 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
613 pci_write_config_word(dev, PCI_STATUS, 0xffff);
615 /* Prevent assigning a bus number that already exists.
616 * This can happen when a bridge is hot-plugged */
617 if (pci_find_bus(pci_domain_nr(bus), max+1))
619 child = pci_add_new_bus(bus, dev, ++max);
620 buses = (buses & 0xff000000)
621 | ((unsigned int)(child->primary) << 0)
622 | ((unsigned int)(child->secondary) << 8)
623 | ((unsigned int)(child->subordinate) << 16);
626 * yenta.c forces a secondary latency timer of 176.
627 * Copy that behaviour here.
630 buses &= ~0xff000000;
631 buses |= CARDBUS_LATENCY_TIMER << 24;
635 * We need to blast all three values with a single write.
637 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
640 child->bridge_ctl = bctl;
642 * Adjust subordinate busnr in parent buses.
643 * We do this before scanning for children because
644 * some devices may not be detected if the bios
647 pci_fixup_parent_subordinate_busnr(child, max);
648 /* Now we can scan all subordinate buses... */
649 max = pci_scan_child_bus(child);
651 * now fix it up again since we have found
652 * the real value of max.
654 pci_fixup_parent_subordinate_busnr(child, max);
657 * For CardBus bridges, we leave 4 bus numbers
658 * as cards with a PCI-to-PCI bridge can be
661 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
662 struct pci_bus *parent = bus;
663 if (pci_find_bus(pci_domain_nr(bus),
666 while (parent->parent) {
667 if ((!pcibios_assign_all_busses()) &&
668 (parent->subordinate > max) &&
669 (parent->subordinate <= max+i)) {
672 parent = parent->parent;
676 * Often, there are two cardbus bridges
677 * -- try to leave one valid bus number
685 pci_fixup_parent_subordinate_busnr(child, max);
688 * Set the subordinate bus number to its real value.
690 child->subordinate = max;
691 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
695 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
696 pci_domain_nr(bus), child->number);
698 /* Has only triggered on CardBus, fixup is in yenta_socket */
699 while (bus->parent) {
700 if ((child->subordinate > bus->subordinate) ||
701 (child->number > bus->subordinate) ||
702 (child->number < bus->number) ||
703 (child->subordinate < bus->number)) {
704 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
705 "hidden behind%s bridge #%02x (-#%02x)\n",
706 child->number, child->subordinate,
707 (bus->number > child->subordinate &&
708 bus->subordinate < child->number) ?
709 "wholly" : "partially",
710 bus->self->transparent ? " transparent" : "",
711 bus->number, bus->subordinate);
717 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
723 * Read interrupt line and base address registers.
724 * The architecture-dependent code can tweak these, of course.
726 static void pci_read_irq(struct pci_dev *dev)
730 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
733 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
737 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
740 * pci_setup_device - fill in class and map information of a device
741 * @dev: the device structure to fill
743 * Initialize the device structure with information about the device's
744 * vendor,class,memory and IO-space addresses,IRQ lines etc.
745 * Called at initialisation of the PCI subsystem and by CardBus services.
746 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
749 static int pci_setup_device(struct pci_dev * dev)
753 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
754 dev->bus->number, PCI_SLOT(dev->devfn),
755 PCI_FUNC(dev->devfn));
757 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
758 dev->revision = class & 0xff;
759 class >>= 8; /* upper 3 bytes */
763 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n",
764 dev->vendor, dev->device, class, dev->hdr_type);
766 /* "Unknown power state" */
767 dev->current_state = PCI_UNKNOWN;
769 /* Early fixups, before probing the BARs */
770 pci_fixup_device(pci_fixup_early, dev);
771 class = dev->class >> 8;
773 switch (dev->hdr_type) { /* header type */
774 case PCI_HEADER_TYPE_NORMAL: /* standard header */
775 if (class == PCI_CLASS_BRIDGE_PCI)
778 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
779 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
780 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
783 * Do the ugly legacy mode stuff here rather than broken chip
784 * quirk code. Legacy mode ATA controllers have fixed
785 * addresses. These are not always echoed in BAR0-3, and
786 * BAR0-3 in a few cases contain junk!
788 if (class == PCI_CLASS_STORAGE_IDE) {
790 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
791 if ((progif & 1) == 0) {
792 dev->resource[0].start = 0x1F0;
793 dev->resource[0].end = 0x1F7;
794 dev->resource[0].flags = LEGACY_IO_RESOURCE;
795 dev->resource[1].start = 0x3F6;
796 dev->resource[1].end = 0x3F6;
797 dev->resource[1].flags = LEGACY_IO_RESOURCE;
799 if ((progif & 4) == 0) {
800 dev->resource[2].start = 0x170;
801 dev->resource[2].end = 0x177;
802 dev->resource[2].flags = LEGACY_IO_RESOURCE;
803 dev->resource[3].start = 0x376;
804 dev->resource[3].end = 0x376;
805 dev->resource[3].flags = LEGACY_IO_RESOURCE;
810 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
811 if (class != PCI_CLASS_BRIDGE_PCI)
813 /* The PCI-to-PCI bridge spec requires that subtractive
814 decoding (i.e. transparent) bridge must have programming
815 interface code of 0x01. */
817 dev->transparent = ((dev->class & 0xff) == 1);
818 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
821 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
822 if (class != PCI_CLASS_BRIDGE_CARDBUS)
825 pci_read_bases(dev, 1, 0);
826 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
827 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
830 default: /* unknown header */
831 dev_err(&dev->dev, "unknown header type %02x, "
832 "ignoring device\n", dev->hdr_type);
836 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
837 "type %02x)\n", class, dev->hdr_type);
838 dev->class = PCI_CLASS_NOT_DEFINED;
841 /* We found a fine healthy device, go go go... */
845 static void pci_release_capabilities(struct pci_dev *dev)
847 pci_vpd_release(dev);
851 * pci_release_dev - free a pci device structure when all users of it are finished.
852 * @dev: device that's been disconnected
854 * Will be called only by the device core when all users of this pci device are
857 static void pci_release_dev(struct device *dev)
859 struct pci_dev *pci_dev;
861 pci_dev = to_pci_dev(dev);
862 pci_release_capabilities(pci_dev);
866 static void set_pcie_port_type(struct pci_dev *pdev)
871 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
875 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
876 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
880 * pci_cfg_space_size - get the configuration space size of the PCI device.
883 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
884 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
885 * access it. Maybe we don't have a way to generate extended config space
886 * accesses, or the device is behind a reverse Express bridge. So we try
887 * reading the dword at 0x100 which must either be 0 or a valid extended
890 int pci_cfg_space_size_ext(struct pci_dev *dev)
893 int pos = PCI_CFG_SPACE_SIZE;
895 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
897 if (status == 0xffffffff)
900 return PCI_CFG_SPACE_EXP_SIZE;
903 return PCI_CFG_SPACE_SIZE;
906 int pci_cfg_space_size(struct pci_dev *dev)
911 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
913 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
917 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
918 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
922 return pci_cfg_space_size_ext(dev);
925 return PCI_CFG_SPACE_SIZE;
928 static void pci_release_bus_bridge_dev(struct device *dev)
933 struct pci_dev *alloc_pci_dev(void)
937 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
941 INIT_LIST_HEAD(&dev->bus_list);
945 EXPORT_SYMBOL(alloc_pci_dev);
948 * Read the config data for a PCI device, sanity-check it
949 * and fill in the dev structure...
951 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
954 struct pci_slot *slot;
959 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
962 /* some broken boards return 0 or ~0 if a slot is empty: */
963 if (l == 0xffffffff || l == 0x00000000 ||
964 l == 0x0000ffff || l == 0xffff0000)
967 /* Configuration request Retry Status */
968 while (l == 0xffff0001) {
971 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
973 /* Card hasn't responded in 60 seconds? Must be stuck. */
974 if (delay > 60 * 1000) {
975 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
976 "responding\n", pci_domain_nr(bus),
977 bus->number, PCI_SLOT(devfn),
983 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
986 dev = alloc_pci_dev();
991 dev->sysdata = bus->sysdata;
992 dev->dev.parent = bus->bridge;
993 dev->dev.bus = &pci_bus_type;
995 dev->hdr_type = hdr_type & 0x7f;
996 dev->multifunction = !!(hdr_type & 0x80);
997 dev->vendor = l & 0xffff;
998 dev->device = (l >> 16) & 0xffff;
999 dev->cfg_size = pci_cfg_space_size(dev);
1000 dev->error_state = pci_channel_io_normal;
1001 set_pcie_port_type(dev);
1003 list_for_each_entry(slot, &bus->slots, list)
1004 if (PCI_SLOT(devfn) == slot->number)
1007 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1008 set this higher, assuming the system even supports it. */
1009 dev->dma_mask = 0xffffffff;
1010 if (pci_setup_device(dev) < 0) {
1018 static void pci_init_capabilities(struct pci_dev *dev)
1020 /* MSI/MSI-X list */
1021 pci_msi_init_pci_dev(dev);
1023 /* Power Management */
1026 /* Vital Product Data */
1027 pci_vpd_pci22_init(dev);
1030 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1032 device_initialize(&dev->dev);
1033 dev->dev.release = pci_release_dev;
1036 dev->dev.dma_mask = &dev->dma_mask;
1037 dev->dev.dma_parms = &dev->dma_parms;
1038 dev->dev.coherent_dma_mask = 0xffffffffull;
1040 pci_set_dma_max_seg_size(dev, 65536);
1041 pci_set_dma_seg_boundary(dev, 0xffffffff);
1043 /* Fix up broken headers */
1044 pci_fixup_device(pci_fixup_header, dev);
1046 /* Initialize various capabilities */
1047 pci_init_capabilities(dev);
1050 * Add the device to our list of discovered devices
1051 * and the bus list for fixup functions, etc.
1053 down_write(&pci_bus_sem);
1054 list_add_tail(&dev->bus_list, &bus->devices);
1055 up_write(&pci_bus_sem);
1058 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1060 struct pci_dev *dev;
1062 dev = pci_scan_device(bus, devfn);
1066 pci_device_add(dev, bus);
1070 EXPORT_SYMBOL(pci_scan_single_device);
1073 * pci_scan_slot - scan a PCI slot on a bus for devices.
1074 * @bus: PCI bus to scan
1075 * @devfn: slot number to scan (must have zero function.)
1077 * Scan a PCI slot on the specified PCI bus for devices, adding
1078 * discovered devices to the @bus->devices list. New devices
1079 * will not have is_added set.
1081 int pci_scan_slot(struct pci_bus *bus, int devfn)
1086 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
1088 for (func = 0; func < 8; func++, devfn++) {
1089 struct pci_dev *dev;
1091 dev = pci_scan_single_device(bus, devfn);
1096 * If this is a single function device,
1097 * don't scan past the first function.
1099 if (!dev->multifunction) {
1101 dev->multifunction = 1;
1107 if (func == 0 && !scan_all_fns)
1112 /* only one slot has pcie device */
1113 if (bus->self && nr)
1114 pcie_aspm_init_link_state(bus->self);
1119 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1121 unsigned int devfn, pass, max = bus->secondary;
1122 struct pci_dev *dev;
1124 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1126 /* Go find them, Rover! */
1127 for (devfn = 0; devfn < 0x100; devfn += 8)
1128 pci_scan_slot(bus, devfn);
1131 * After performing arch-dependent fixup of the bus, look behind
1132 * all PCI-to-PCI bridges on this bus.
1134 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1135 pcibios_fixup_bus(bus);
1136 for (pass=0; pass < 2; pass++)
1137 list_for_each_entry(dev, &bus->devices, bus_list) {
1138 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1139 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1140 max = pci_scan_bridge(bus, dev, max, pass);
1144 * We've scanned the bus and so we know all about what's on
1145 * the other side of any bridges that may be on this bus plus
1148 * Return how far we've got finding sub-buses.
1150 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1151 pci_domain_nr(bus), bus->number, max);
1155 void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b)
1159 struct pci_bus * pci_create_bus(struct device *parent,
1160 int bus, struct pci_ops *ops, void *sysdata)
1166 b = pci_alloc_bus();
1170 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1176 b->sysdata = sysdata;
1179 if (pci_find_bus(pci_domain_nr(b), bus)) {
1180 /* If we already got to this bus through a different bridge, ignore it */
1181 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1185 down_write(&pci_bus_sem);
1186 list_add_tail(&b->node, &pci_root_buses);
1187 up_write(&pci_bus_sem);
1189 memset(dev, 0, sizeof(*dev));
1190 dev->parent = parent;
1191 dev->release = pci_release_bus_bridge_dev;
1192 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1193 error = device_register(dev);
1196 b->bridge = get_device(dev);
1199 set_dev_node(b->bridge, pcibus_to_node(b));
1201 b->dev.class = &pcibus_class;
1202 b->dev.parent = b->bridge;
1203 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1204 error = device_register(&b->dev);
1206 goto class_dev_reg_err;
1207 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1209 goto dev_create_file_err;
1211 /* Create legacy_io and legacy_mem files for this bus */
1212 pci_create_legacy_files(b);
1214 b->number = b->secondary = bus;
1215 b->resource[0] = &ioport_resource;
1216 b->resource[1] = &iomem_resource;
1218 set_pci_bus_resources_arch_default(b);
1222 dev_create_file_err:
1223 device_unregister(&b->dev);
1225 device_unregister(dev);
1227 down_write(&pci_bus_sem);
1229 up_write(&pci_bus_sem);
1236 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1237 int bus, struct pci_ops *ops, void *sysdata)
1241 b = pci_create_bus(parent, bus, ops, sysdata);
1243 b->subordinate = pci_scan_child_bus(b);
1246 EXPORT_SYMBOL(pci_scan_bus_parented);
1248 #ifdef CONFIG_HOTPLUG
1249 EXPORT_SYMBOL(pci_add_new_bus);
1250 EXPORT_SYMBOL(pci_scan_slot);
1251 EXPORT_SYMBOL(pci_scan_bridge);
1252 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1255 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1257 const struct pci_dev *a = to_pci_dev(d_a);
1258 const struct pci_dev *b = to_pci_dev(d_b);
1260 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1261 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1263 if (a->bus->number < b->bus->number) return -1;
1264 else if (a->bus->number > b->bus->number) return 1;
1266 if (a->devfn < b->devfn) return -1;
1267 else if (a->devfn > b->devfn) return 1;
1272 void __init pci_sort_breadthfirst(void)
1274 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);