rt2x00: Let rt2800lib check CONFIG_RT2X00_LIB_USB instead of CONFIG_RT2800USB
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
1 /*
2         Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10         <http://rt2x00.serialmonkey.com>
11
12         This program is free software; you can redistribute it and/or modify
13         it under the terms of the GNU General Public License as published by
14         the Free Software Foundation; either version 2 of the License, or
15         (at your option) any later version.
16
17         This program is distributed in the hope that it will be useful,
18         but WITHOUT ANY WARRANTY; without even the implied warranty of
19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20         GNU General Public License for more details.
21
22         You should have received a copy of the GNU General Public License
23         along with this program; if not, write to the
24         Free Software Foundation, Inc.,
25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26  */
27
28 /*
29         Module: rt2800pci
30         Abstract: rt2800pci device specific routines.
31         Supported chipsets: RT2800E & RT2800ED.
32  */
33
34 #include <linux/crc-ccitt.h>
35 #include <linux/delay.h>
36 #include <linux/etherdevice.h>
37 #include <linux/init.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/pci.h>
41 #include <linux/platform_device.h>
42 #include <linux/eeprom_93cx6.h>
43
44 #include "rt2x00.h"
45 #include "rt2x00pci.h"
46 #include "rt2x00soc.h"
47 #include "rt2800lib.h"
48 #include "rt2800.h"
49 #include "rt2800pci.h"
50
51 #ifdef CONFIG_RT2800PCI_PCI_MODULE
52 #define CONFIG_RT2800PCI_PCI
53 #endif
54
55 #ifdef CONFIG_RT2800PCI_SOC_MODULE
56 #define CONFIG_RT2800PCI_SOC
57 #endif
58
59 /*
60  * Allow hardware encryption to be disabled.
61  */
62 static int modparam_nohwcrypt = 1;
63 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
64 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
65
66 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
67 {
68         unsigned int i;
69         u32 reg;
70
71         for (i = 0; i < 200; i++) {
72                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
73
74                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
75                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
76                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
77                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
78                         break;
79
80                 udelay(REGISTER_BUSY_DELAY);
81         }
82
83         if (i == 200)
84                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
85
86         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
87         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
88 }
89
90 #ifdef CONFIG_RT2800PCI_SOC
91 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
92 {
93         u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
94
95         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
96 }
97 #else
98 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
99 {
100 }
101 #endif /* CONFIG_RT2800PCI_SOC */
102
103 #ifdef CONFIG_RT2800PCI_PCI
104 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
105 {
106         struct rt2x00_dev *rt2x00dev = eeprom->data;
107         u32 reg;
108
109         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
110
111         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
112         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
113         eeprom->reg_data_clock =
114             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
115         eeprom->reg_chip_select =
116             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
117 }
118
119 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
120 {
121         struct rt2x00_dev *rt2x00dev = eeprom->data;
122         u32 reg = 0;
123
124         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
125         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
126         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
127                            !!eeprom->reg_data_clock);
128         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
129                            !!eeprom->reg_chip_select);
130
131         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
132 }
133
134 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
135 {
136         struct eeprom_93cx6 eeprom;
137         u32 reg;
138
139         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
140
141         eeprom.data = rt2x00dev;
142         eeprom.register_read = rt2800pci_eepromregister_read;
143         eeprom.register_write = rt2800pci_eepromregister_write;
144         eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
145             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
146         eeprom.reg_data_in = 0;
147         eeprom.reg_data_out = 0;
148         eeprom.reg_data_clock = 0;
149         eeprom.reg_chip_select = 0;
150
151         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
152                                EEPROM_SIZE / sizeof(u16));
153 }
154
155 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
156 {
157         return rt2800_efuse_detect(rt2x00dev);
158 }
159
160 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
161 {
162         rt2800_read_eeprom_efuse(rt2x00dev);
163 }
164 #else
165 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
166 {
167 }
168
169 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
170 {
171         return 0;
172 }
173
174 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
175 {
176 }
177 #endif /* CONFIG_RT2800PCI_PCI */
178
179 /*
180  * Firmware functions
181  */
182 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
183 {
184         return FIRMWARE_RT2860;
185 }
186
187 static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
188                                     const u8 *data, const size_t len)
189 {
190         u16 fw_crc;
191         u16 crc;
192
193         /*
194          * Only support 8kb firmware files.
195          */
196         if (len != 8192)
197                 return FW_BAD_LENGTH;
198
199         /*
200          * The last 2 bytes in the firmware array are the crc checksum itself,
201          * this means that we should never pass those 2 bytes to the crc
202          * algorithm.
203          */
204         fw_crc = (data[len - 2] << 8 | data[len - 1]);
205
206         /*
207          * Use the crc ccitt algorithm.
208          * This will return the same value as the legacy driver which
209          * used bit ordering reversion on the both the firmware bytes
210          * before input input as well as on the final output.
211          * Obviously using crc ccitt directly is much more efficient.
212          */
213         crc = crc_ccitt(~0, data, len - 2);
214
215         /*
216          * There is a small difference between the crc-itu-t + bitrev and
217          * the crc-ccitt crc calculation. In the latter method the 2 bytes
218          * will be swapped, use swab16 to convert the crc to the correct
219          * value.
220          */
221         crc = swab16(crc);
222
223         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
224 }
225
226 static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
227                                    const u8 *data, const size_t len)
228 {
229         unsigned int i;
230         u32 reg;
231
232         /*
233          * Wait for stable hardware.
234          */
235         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
236                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
237                 if (reg && reg != ~0)
238                         break;
239                 msleep(1);
240         }
241
242         if (i == REGISTER_BUSY_COUNT) {
243                 ERROR(rt2x00dev, "Unstable hardware.\n");
244                 return -EBUSY;
245         }
246
247         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
248         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
249
250         /*
251          * Disable DMA, will be reenabled later when enabling
252          * the radio.
253          */
254         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
255         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
256         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
257         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
258         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
259         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
260         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
261
262         /*
263          * enable Host program ram write selection
264          */
265         reg = 0;
266         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
267         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
268
269         /*
270          * Write firmware to device.
271          */
272         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
273                                       data, len);
274
275         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
276         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
277
278         /*
279          * Wait for device to stabilize.
280          */
281         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
282                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
283                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
284                         break;
285                 msleep(1);
286         }
287
288         if (i == REGISTER_BUSY_COUNT) {
289                 ERROR(rt2x00dev, "PBF system register not ready.\n");
290                 return -EBUSY;
291         }
292
293         /*
294          * Disable interrupts
295          */
296         rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
297
298         /*
299          * Initialize BBP R/W access agent
300          */
301         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
302         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
303
304         return 0;
305 }
306
307 /*
308  * Initialization functions.
309  */
310 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
311 {
312         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
313         u32 word;
314
315         if (entry->queue->qid == QID_RX) {
316                 rt2x00_desc_read(entry_priv->desc, 1, &word);
317
318                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
319         } else {
320                 rt2x00_desc_read(entry_priv->desc, 1, &word);
321
322                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
323         }
324 }
325
326 static void rt2800pci_clear_entry(struct queue_entry *entry)
327 {
328         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
329         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
330         u32 word;
331
332         if (entry->queue->qid == QID_RX) {
333                 rt2x00_desc_read(entry_priv->desc, 0, &word);
334                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
335                 rt2x00_desc_write(entry_priv->desc, 0, word);
336
337                 rt2x00_desc_read(entry_priv->desc, 1, &word);
338                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
339                 rt2x00_desc_write(entry_priv->desc, 1, word);
340         } else {
341                 rt2x00_desc_read(entry_priv->desc, 1, &word);
342                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
343                 rt2x00_desc_write(entry_priv->desc, 1, word);
344         }
345 }
346
347 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
348 {
349         struct queue_entry_priv_pci *entry_priv;
350         u32 reg;
351
352         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
353         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
354         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
355         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
356         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
357         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
358         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
359         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
360         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
361
362         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
363         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
364
365         /*
366          * Initialize registers.
367          */
368         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
369         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
370         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
371         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
372         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
373
374         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
375         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
376         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
377         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
378         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
379
380         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
381         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
382         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
383         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
384         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
385
386         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
387         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
388         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
389         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
390         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
391
392         entry_priv = rt2x00dev->rx->entries[0].priv_data;
393         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
394         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
395         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
396         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
397
398         /*
399          * Enable global DMA configuration
400          */
401         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
402         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
403         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
404         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
405         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
406
407         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
408
409         return 0;
410 }
411
412 /*
413  * Device state switch handlers.
414  */
415 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
416                                 enum dev_state state)
417 {
418         u32 reg;
419
420         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
421         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
422                            (state == STATE_RADIO_RX_ON) ||
423                            (state == STATE_RADIO_RX_ON_LINK));
424         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
425 }
426
427 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
428                                  enum dev_state state)
429 {
430         int mask = (state == STATE_RADIO_IRQ_ON);
431         u32 reg;
432
433         /*
434          * When interrupts are being enabled, the interrupt registers
435          * should clear the register to assure a clean state.
436          */
437         if (state == STATE_RADIO_IRQ_ON) {
438                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
439                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
440         }
441
442         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
443         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
444         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
445         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
446         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
447         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
448         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
449         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
450         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
451         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
452         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
453         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
454         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
455         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
456         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
457         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
458         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
459         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
460         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
461         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
462 }
463
464 static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
465 {
466         unsigned int i;
467         u32 reg;
468
469         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
470                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
471                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
472                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
473                         return 0;
474
475                 msleep(1);
476         }
477
478         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
479         return -EACCES;
480 }
481
482 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
483 {
484         u32 reg;
485         u16 word;
486
487         /*
488          * Initialize all registers.
489          */
490         if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
491                      rt2800pci_init_queues(rt2x00dev) ||
492                      rt2800_init_registers(rt2x00dev) ||
493                      rt2800pci_wait_wpdma_ready(rt2x00dev) ||
494                      rt2800_init_bbp(rt2x00dev) ||
495                      rt2800_init_rfcsr(rt2x00dev)))
496                 return -EIO;
497
498         /*
499          * Send signal to firmware during boot time.
500          */
501         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
502
503         /*
504          * Enable RX.
505          */
506         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
507         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
508         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
509         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
510
511         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
512         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
513         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
514         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
515         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
516         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
517
518         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
519         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
520         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
521         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
522
523         /*
524          * Initialize LED control
525          */
526         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
527         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
528                               word & 0xff, (word >> 8) & 0xff);
529
530         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
531         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
532                               word & 0xff, (word >> 8) & 0xff);
533
534         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
535         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
536                               word & 0xff, (word >> 8) & 0xff);
537
538         return 0;
539 }
540
541 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
542 {
543         u32 reg;
544
545         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
546         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
547         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
548         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
549         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
550         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
551         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
552
553         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
554         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
555         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
556
557         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
558
559         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
560         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
561         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
562         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
563         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
564         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
565         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
566         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
567         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
568
569         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
570         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
571
572         /* Wait for DMA, ignore error */
573         rt2800pci_wait_wpdma_ready(rt2x00dev);
574 }
575
576 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
577                                enum dev_state state)
578 {
579         /*
580          * Always put the device to sleep (even when we intend to wakeup!)
581          * if the device is booting and wasn't asleep it will return
582          * failure when attempting to wakeup.
583          */
584         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
585
586         if (state == STATE_AWAKE) {
587                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
588                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
589         }
590
591         return 0;
592 }
593
594 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
595                                       enum dev_state state)
596 {
597         int retval = 0;
598
599         switch (state) {
600         case STATE_RADIO_ON:
601                 /*
602                  * Before the radio can be enabled, the device first has
603                  * to be woken up. After that it needs a bit of time
604                  * to be fully awake and then the radio can be enabled.
605                  */
606                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
607                 msleep(1);
608                 retval = rt2800pci_enable_radio(rt2x00dev);
609                 break;
610         case STATE_RADIO_OFF:
611                 /*
612                  * After the radio has been disabled, the device should
613                  * be put to sleep for powersaving.
614                  */
615                 rt2800pci_disable_radio(rt2x00dev);
616                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
617                 break;
618         case STATE_RADIO_RX_ON:
619         case STATE_RADIO_RX_ON_LINK:
620         case STATE_RADIO_RX_OFF:
621         case STATE_RADIO_RX_OFF_LINK:
622                 rt2800pci_toggle_rx(rt2x00dev, state);
623                 break;
624         case STATE_RADIO_IRQ_ON:
625         case STATE_RADIO_IRQ_OFF:
626                 rt2800pci_toggle_irq(rt2x00dev, state);
627                 break;
628         case STATE_DEEP_SLEEP:
629         case STATE_SLEEP:
630         case STATE_STANDBY:
631         case STATE_AWAKE:
632                 retval = rt2800pci_set_state(rt2x00dev, state);
633                 break;
634         default:
635                 retval = -ENOTSUPP;
636                 break;
637         }
638
639         if (unlikely(retval))
640                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
641                       state, retval);
642
643         return retval;
644 }
645
646 /*
647  * TX descriptor initialization
648  */
649 static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
650                                     struct sk_buff *skb,
651                                     struct txentry_desc *txdesc)
652 {
653         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
654         __le32 *txd = skbdesc->desc;
655         __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->ops->extra_tx_headroom);
656         u32 word;
657
658         /*
659          * Initialize TX Info descriptor
660          */
661         rt2x00_desc_read(txwi, 0, &word);
662         rt2x00_set_field32(&word, TXWI_W0_FRAG,
663                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
664         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
665         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
666         rt2x00_set_field32(&word, TXWI_W0_TS,
667                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
668         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
669                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
670         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
671         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
672         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
673         rt2x00_set_field32(&word, TXWI_W0_BW,
674                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
675         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
676                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
677         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
678         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
679         rt2x00_desc_write(txwi, 0, word);
680
681         rt2x00_desc_read(txwi, 1, &word);
682         rt2x00_set_field32(&word, TXWI_W1_ACK,
683                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
684         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
685                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
686         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
687         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
688                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
689                            txdesc->key_idx : 0xff);
690         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
691                            skb->len - txdesc->l2pad);
692         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
693                            skbdesc->entry->queue->qid + 1);
694         rt2x00_desc_write(txwi, 1, word);
695
696         /*
697          * Always write 0 to IV/EIV fields, hardware will insert the IV
698          * from the IVEIV register when TXD_W3_WIV is set to 0.
699          * When TXD_W3_WIV is set to 1 it will use the IV data
700          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
701          * crypto entry in the registers should be used to encrypt the frame.
702          */
703         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
704         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
705
706         /*
707          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
708          * must contains a TXWI structure + 802.11 header + padding + 802.11
709          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
710          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
711          * data. It means that LAST_SEC0 is always 0.
712          */
713
714         /*
715          * Initialize TX descriptor
716          */
717         rt2x00_desc_read(txd, 0, &word);
718         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
719         rt2x00_desc_write(txd, 0, word);
720
721         rt2x00_desc_read(txd, 1, &word);
722         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
723         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
724                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
725         rt2x00_set_field32(&word, TXD_W1_BURST,
726                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
727         rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
728                            rt2x00dev->ops->extra_tx_headroom);
729         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
730         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
731         rt2x00_desc_write(txd, 1, word);
732
733         rt2x00_desc_read(txd, 2, &word);
734         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
735                            skbdesc->skb_dma + rt2x00dev->ops->extra_tx_headroom);
736         rt2x00_desc_write(txd, 2, word);
737
738         rt2x00_desc_read(txd, 3, &word);
739         rt2x00_set_field32(&word, TXD_W3_WIV,
740                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
741         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
742         rt2x00_desc_write(txd, 3, word);
743 }
744
745 /*
746  * TX data initialization
747  */
748 static void rt2800pci_write_beacon(struct queue_entry *entry)
749 {
750         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
751         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
752         unsigned int beacon_base;
753         u32 reg;
754
755         /*
756          * Disable beaconing while we are reloading the beacon data,
757          * otherwise we might be sending out invalid data.
758          */
759         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
760         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
761         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
762
763         /*
764          * Write entire beacon with descriptor to register.
765          */
766         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
767         rt2800_register_multiwrite(rt2x00dev,
768                                       beacon_base,
769                                       skbdesc->desc, skbdesc->desc_len);
770         rt2800_register_multiwrite(rt2x00dev,
771                                       beacon_base + skbdesc->desc_len,
772                                       entry->skb->data, entry->skb->len);
773
774         /*
775          * Clean up beacon skb.
776          */
777         dev_kfree_skb_any(entry->skb);
778         entry->skb = NULL;
779 }
780
781 static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
782                                     const enum data_queue_qid queue_idx)
783 {
784         struct data_queue *queue;
785         unsigned int idx, qidx = 0;
786         u32 reg;
787
788         if (queue_idx == QID_BEACON) {
789                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
790                 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
791                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
792                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
793                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
794                         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
795                 }
796                 return;
797         }
798
799         if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
800                 return;
801
802         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
803         idx = queue->index[Q_INDEX];
804
805         if (queue_idx == QID_MGMT)
806                 qidx = 5;
807         else
808                 qidx = queue_idx;
809
810         rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
811 }
812
813 static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
814                                     const enum data_queue_qid qid)
815 {
816         u32 reg;
817
818         if (qid == QID_BEACON) {
819                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
820                 return;
821         }
822
823         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
824         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
825         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
826         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
827         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
828         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
829 }
830
831 /*
832  * RX control handlers
833  */
834 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
835                                   struct rxdone_entry_desc *rxdesc)
836 {
837         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
838         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
839         __le32 *rxd = entry_priv->desc;
840         __le32 *rxwi = (__le32 *)entry->skb->data;
841         u32 rxd3;
842         u32 rxwi0;
843         u32 rxwi1;
844         u32 rxwi2;
845         u32 rxwi3;
846
847         rt2x00_desc_read(rxd, 3, &rxd3);
848         rt2x00_desc_read(rxwi, 0, &rxwi0);
849         rt2x00_desc_read(rxwi, 1, &rxwi1);
850         rt2x00_desc_read(rxwi, 2, &rxwi2);
851         rt2x00_desc_read(rxwi, 3, &rxwi3);
852
853         if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
854                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
855
856         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
857                 /*
858                  * Unfortunately we don't know the cipher type used during
859                  * decryption. This prevents us from correct providing
860                  * correct statistics through debugfs.
861                  */
862                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
863                 rxdesc->cipher_status =
864                     rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
865         }
866
867         if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
868                 /*
869                  * Hardware has stripped IV/EIV data from 802.11 frame during
870                  * decryption. Unfortunately the descriptor doesn't contain
871                  * any fields with the EIV/IV data either, so they can't
872                  * be restored by rt2x00lib.
873                  */
874                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
875
876                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
877                         rxdesc->flags |= RX_FLAG_DECRYPTED;
878                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
879                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
880         }
881
882         if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
883                 rxdesc->dev_flags |= RXDONE_MY_BSS;
884
885         if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD))
886                 rxdesc->dev_flags |= RXDONE_L2PAD;
887
888         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
889                 rxdesc->flags |= RX_FLAG_SHORT_GI;
890
891         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
892                 rxdesc->flags |= RX_FLAG_40MHZ;
893
894         /*
895          * Detect RX rate, always use MCS as signal type.
896          */
897         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
898         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
899         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
900
901         /*
902          * Mask of 0x8 bit to remove the short preamble flag.
903          */
904         if (rxdesc->rate_mode == RATE_MODE_CCK)
905                 rxdesc->signal &= ~0x8;
906
907         rxdesc->rssi =
908             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
909              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
910
911         rxdesc->noise =
912             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
913              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
914
915         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
916
917         /*
918          * Set RX IDX in register to inform hardware that we have handled
919          * this entry and it is available for reuse again.
920          */
921         rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
922
923         /*
924          * Remove TXWI descriptor from start of buffer.
925          */
926         skb_pull(entry->skb, RXWI_DESC_SIZE);
927 }
928
929 /*
930  * Interrupt functions.
931  */
932 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
933 {
934         struct data_queue *queue;
935         struct queue_entry *entry;
936         struct queue_entry *entry_done;
937         struct queue_entry_priv_pci *entry_priv;
938         struct txdone_entry_desc txdesc;
939         u32 word;
940         u32 reg;
941         u32 old_reg;
942         unsigned int type;
943         unsigned int index;
944         u16 mcs, real_mcs;
945
946         /*
947          * During each loop we will compare the freshly read
948          * TX_STA_FIFO register value with the value read from
949          * the previous loop. If the 2 values are equal then
950          * we should stop processing because the chance it
951          * quite big that the device has been unplugged and
952          * we risk going into an endless loop.
953          */
954         old_reg = 0;
955
956         while (1) {
957                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
958                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
959                         break;
960
961                 if (old_reg == reg)
962                         break;
963                 old_reg = reg;
964
965                 /*
966                  * Skip this entry when it contains an invalid
967                  * queue identication number.
968                  */
969                 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
970                 if (type >= QID_RX)
971                         continue;
972
973                 queue = rt2x00queue_get_queue(rt2x00dev, type);
974                 if (unlikely(!queue))
975                         continue;
976
977                 /*
978                  * Skip this entry when it contains an invalid
979                  * index number.
980                  */
981                 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;
982                 if (unlikely(index >= queue->limit))
983                         continue;
984
985                 entry = &queue->entries[index];
986                 entry_priv = entry->priv_data;
987                 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
988
989                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
990                 while (entry != entry_done) {
991                         /*
992                          * Catch up.
993                          * Just report any entries we missed as failed.
994                          */
995                         WARNING(rt2x00dev,
996                                 "TX status report missed for entry %d\n",
997                                 entry_done->entry_idx);
998
999                         txdesc.flags = 0;
1000                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
1001                         txdesc.retry = 0;
1002
1003                         rt2x00lib_txdone(entry_done, &txdesc);
1004                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1005                 }
1006
1007                 /*
1008                  * Obtain the status about this packet.
1009                  */
1010                 txdesc.flags = 0;
1011                 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
1012                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1013                 else
1014                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1015
1016                 /*
1017                  * Ralink has a retry mechanism using a global fallback
1018                  * table. We setup this fallback table to try immediate
1019                  * lower rate for all rates. In the TX_STA_FIFO,
1020                  * the MCS field contains the MCS used for the successfull
1021                  * transmission. If the first transmission succeed,
1022                  * we have mcs == tx_mcs. On the second transmission,
1023                  * we have mcs = tx_mcs - 1. So the number of
1024                  * retry is (tx_mcs - mcs).
1025                  */
1026                 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1027                 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
1028                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1029                 txdesc.retry = mcs - min(mcs, real_mcs);
1030
1031                 rt2x00lib_txdone(entry, &txdesc);
1032         }
1033 }
1034
1035 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1036 {
1037         struct rt2x00_dev *rt2x00dev = dev_instance;
1038         u32 reg;
1039
1040         /* Read status and ACK all interrupts */
1041         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1042         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1043
1044         if (!reg)
1045                 return IRQ_NONE;
1046
1047         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1048                 return IRQ_HANDLED;
1049
1050         /*
1051          * 1 - Rx ring done interrupt.
1052          */
1053         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1054                 rt2x00pci_rxdone(rt2x00dev);
1055
1056         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1057                 rt2800pci_txdone(rt2x00dev);
1058
1059         return IRQ_HANDLED;
1060 }
1061
1062 /*
1063  * Device probe functions.
1064  */
1065 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1066 {
1067         /*
1068          * Read EEPROM into buffer
1069          */
1070         switch (rt2x00dev->chip.rt) {
1071         case RT2880:
1072         case RT3052:
1073                 rt2800pci_read_eeprom_soc(rt2x00dev);
1074                 break;
1075         default:
1076                 if (rt2800pci_efuse_detect(rt2x00dev))
1077                         rt2800pci_read_eeprom_efuse(rt2x00dev);
1078                 else
1079                         rt2800pci_read_eeprom_pci(rt2x00dev);
1080                 break;
1081         }
1082
1083         return rt2800_validate_eeprom(rt2x00dev);
1084 }
1085
1086 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1087         .register_read          = rt2x00pci_register_read,
1088         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
1089         .register_write         = rt2x00pci_register_write,
1090         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
1091
1092         .register_multiread     = rt2x00pci_register_multiread,
1093         .register_multiwrite    = rt2x00pci_register_multiwrite,
1094
1095         .regbusy_read           = rt2x00pci_regbusy_read,
1096 };
1097
1098 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1099 {
1100         int retval;
1101
1102         rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1103
1104         /*
1105          * Allocate eeprom data.
1106          */
1107         retval = rt2800pci_validate_eeprom(rt2x00dev);
1108         if (retval)
1109                 return retval;
1110
1111         retval = rt2800_init_eeprom(rt2x00dev);
1112         if (retval)
1113                 return retval;
1114
1115         /*
1116          * Initialize hw specifications.
1117          */
1118         retval = rt2800_probe_hw_mode(rt2x00dev);
1119         if (retval)
1120                 return retval;
1121
1122         /*
1123          * This device has multiple filters for control frames
1124          * and has a separate filter for PS Poll frames.
1125          */
1126         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1127         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1128
1129         /*
1130          * This device requires firmware.
1131          */
1132         if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
1133             !rt2x00_rt(&rt2x00dev->chip, RT3052))
1134                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1135         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1136         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1137         if (!modparam_nohwcrypt)
1138                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1139
1140         /*
1141          * Set the rssi offset.
1142          */
1143         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1144
1145         return 0;
1146 }
1147
1148 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1149         .irq_handler            = rt2800pci_interrupt,
1150         .probe_hw               = rt2800pci_probe_hw,
1151         .get_firmware_name      = rt2800pci_get_firmware_name,
1152         .check_firmware         = rt2800pci_check_firmware,
1153         .load_firmware          = rt2800pci_load_firmware,
1154         .initialize             = rt2x00pci_initialize,
1155         .uninitialize           = rt2x00pci_uninitialize,
1156         .get_entry_state        = rt2800pci_get_entry_state,
1157         .clear_entry            = rt2800pci_clear_entry,
1158         .set_device_state       = rt2800pci_set_device_state,
1159         .rfkill_poll            = rt2800_rfkill_poll,
1160         .link_stats             = rt2800_link_stats,
1161         .reset_tuner            = rt2800_reset_tuner,
1162         .link_tuner             = rt2800_link_tuner,
1163         .write_tx_desc          = rt2800pci_write_tx_desc,
1164         .write_tx_data          = rt2x00pci_write_tx_data,
1165         .write_beacon           = rt2800pci_write_beacon,
1166         .kick_tx_queue          = rt2800pci_kick_tx_queue,
1167         .kill_tx_queue          = rt2800pci_kill_tx_queue,
1168         .fill_rxdone            = rt2800pci_fill_rxdone,
1169         .config_shared_key      = rt2800_config_shared_key,
1170         .config_pairwise_key    = rt2800_config_pairwise_key,
1171         .config_filter          = rt2800_config_filter,
1172         .config_intf            = rt2800_config_intf,
1173         .config_erp             = rt2800_config_erp,
1174         .config_ant             = rt2800_config_ant,
1175         .config                 = rt2800_config,
1176 };
1177
1178 static const struct data_queue_desc rt2800pci_queue_rx = {
1179         .entry_num              = RX_ENTRIES,
1180         .data_size              = AGGREGATION_SIZE,
1181         .desc_size              = RXD_DESC_SIZE,
1182         .priv_size              = sizeof(struct queue_entry_priv_pci),
1183 };
1184
1185 static const struct data_queue_desc rt2800pci_queue_tx = {
1186         .entry_num              = TX_ENTRIES,
1187         .data_size              = AGGREGATION_SIZE,
1188         .desc_size              = TXD_DESC_SIZE,
1189         .priv_size              = sizeof(struct queue_entry_priv_pci),
1190 };
1191
1192 static const struct data_queue_desc rt2800pci_queue_bcn = {
1193         .entry_num              = 8 * BEACON_ENTRIES,
1194         .data_size              = 0, /* No DMA required for beacons */
1195         .desc_size              = TXWI_DESC_SIZE,
1196         .priv_size              = sizeof(struct queue_entry_priv_pci),
1197 };
1198
1199 static const struct rt2x00_ops rt2800pci_ops = {
1200         .name                   = KBUILD_MODNAME,
1201         .max_sta_intf           = 1,
1202         .max_ap_intf            = 8,
1203         .eeprom_size            = EEPROM_SIZE,
1204         .rf_size                = RF_SIZE,
1205         .tx_queues              = NUM_TX_QUEUES,
1206         .extra_tx_headroom      = TXWI_DESC_SIZE,
1207         .rx                     = &rt2800pci_queue_rx,
1208         .tx                     = &rt2800pci_queue_tx,
1209         .bcn                    = &rt2800pci_queue_bcn,
1210         .lib                    = &rt2800pci_rt2x00_ops,
1211         .hw                     = &rt2800_mac80211_ops,
1212 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1213         .debugfs                = &rt2800_rt2x00debug,
1214 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1215 };
1216
1217 /*
1218  * RT2800pci module information.
1219  */
1220 static struct pci_device_id rt2800pci_device_table[] = {
1221         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1222         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1223         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1224         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1225         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1226         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1227         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1228         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1229         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1230         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1231         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1232         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1233         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1234         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1235         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1236         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1237         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1238         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1239         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1240         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1241         { 0, }
1242 };
1243
1244 MODULE_AUTHOR(DRV_PROJECT);
1245 MODULE_VERSION(DRV_VERSION);
1246 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1247 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1248 #ifdef CONFIG_RT2800PCI_PCI
1249 MODULE_FIRMWARE(FIRMWARE_RT2860);
1250 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1251 #endif /* CONFIG_RT2800PCI_PCI */
1252 MODULE_LICENSE("GPL");
1253
1254 #ifdef CONFIG_RT2800PCI_SOC
1255 #if defined(CONFIG_RALINK_RT288X)
1256 __rt2x00soc_probe(RT2880, &rt2800pci_ops);
1257 #elif defined(CONFIG_RALINK_RT305X)
1258 __rt2x00soc_probe(RT3052, &rt2800pci_ops);
1259 #endif
1260
1261 static struct platform_driver rt2800soc_driver = {
1262         .driver         = {
1263                 .name           = "rt2800_wmac",
1264                 .owner          = THIS_MODULE,
1265                 .mod_name       = KBUILD_MODNAME,
1266         },
1267         .probe          = __rt2x00soc_probe,
1268         .remove         = __devexit_p(rt2x00soc_remove),
1269         .suspend        = rt2x00soc_suspend,
1270         .resume         = rt2x00soc_resume,
1271 };
1272 #endif /* CONFIG_RT2800PCI_SOC */
1273
1274 #ifdef CONFIG_RT2800PCI_PCI
1275 static struct pci_driver rt2800pci_driver = {
1276         .name           = KBUILD_MODNAME,
1277         .id_table       = rt2800pci_device_table,
1278         .probe          = rt2x00pci_probe,
1279         .remove         = __devexit_p(rt2x00pci_remove),
1280         .suspend        = rt2x00pci_suspend,
1281         .resume         = rt2x00pci_resume,
1282 };
1283 #endif /* CONFIG_RT2800PCI_PCI */
1284
1285 static int __init rt2800pci_init(void)
1286 {
1287         int ret = 0;
1288
1289 #ifdef CONFIG_RT2800PCI_SOC
1290         ret = platform_driver_register(&rt2800soc_driver);
1291         if (ret)
1292                 return ret;
1293 #endif
1294 #ifdef CONFIG_RT2800PCI_PCI
1295         ret = pci_register_driver(&rt2800pci_driver);
1296         if (ret) {
1297 #ifdef CONFIG_RT2800PCI_SOC
1298                 platform_driver_unregister(&rt2800soc_driver);
1299 #endif
1300                 return ret;
1301         }
1302 #endif
1303
1304         return ret;
1305 }
1306
1307 static void __exit rt2800pci_exit(void)
1308 {
1309 #ifdef CONFIG_RT2800PCI_PCI
1310         pci_unregister_driver(&rt2800pci_driver);
1311 #endif
1312 #ifdef CONFIG_RT2800PCI_SOC
1313         platform_driver_unregister(&rt2800soc_driver);
1314 #endif
1315 }
1316
1317 module_init(rt2800pci_init);
1318 module_exit(rt2800pci_exit);