rt2x00: convert RT2800PCI_PCI and RT2800PCI_SOC Kconfig symbols to booleans.
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
1 /*
2         Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10         <http://rt2x00.serialmonkey.com>
11
12         This program is free software; you can redistribute it and/or modify
13         it under the terms of the GNU General Public License as published by
14         the Free Software Foundation; either version 2 of the License, or
15         (at your option) any later version.
16
17         This program is distributed in the hope that it will be useful,
18         but WITHOUT ANY WARRANTY; without even the implied warranty of
19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20         GNU General Public License for more details.
21
22         You should have received a copy of the GNU General Public License
23         along with this program; if not, write to the
24         Free Software Foundation, Inc.,
25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26  */
27
28 /*
29         Module: rt2800pci
30         Abstract: rt2800pci device specific routines.
31         Supported chipsets: RT2800E & RT2800ED.
32  */
33
34 #include <linux/crc-ccitt.h>
35 #include <linux/delay.h>
36 #include <linux/etherdevice.h>
37 #include <linux/init.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/pci.h>
41 #include <linux/platform_device.h>
42 #include <linux/eeprom_93cx6.h>
43
44 #include "rt2x00.h"
45 #include "rt2x00pci.h"
46 #include "rt2x00soc.h"
47 #include "rt2800lib.h"
48 #include "rt2800.h"
49 #include "rt2800pci.h"
50
51 /*
52  * Allow hardware encryption to be disabled.
53  */
54 static int modparam_nohwcrypt = 1;
55 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
56 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57
58 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
59 {
60         unsigned int i;
61         u32 reg;
62
63         for (i = 0; i < 200; i++) {
64                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
65
66                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
67                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
68                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
69                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
70                         break;
71
72                 udelay(REGISTER_BUSY_DELAY);
73         }
74
75         if (i == 200)
76                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
77
78         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
79         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
80 }
81
82 #ifdef CONFIG_RT2800PCI_SOC
83 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
84 {
85         u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
86
87         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
88 }
89 #else
90 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
91 {
92 }
93 #endif /* CONFIG_RT2800PCI_SOC */
94
95 #ifdef CONFIG_RT2800PCI_PCI
96 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
97 {
98         struct rt2x00_dev *rt2x00dev = eeprom->data;
99         u32 reg;
100
101         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
102
103         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
104         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
105         eeprom->reg_data_clock =
106             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
107         eeprom->reg_chip_select =
108             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
109 }
110
111 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
112 {
113         struct rt2x00_dev *rt2x00dev = eeprom->data;
114         u32 reg = 0;
115
116         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
117         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
118         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
119                            !!eeprom->reg_data_clock);
120         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
121                            !!eeprom->reg_chip_select);
122
123         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
124 }
125
126 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
127 {
128         struct eeprom_93cx6 eeprom;
129         u32 reg;
130
131         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
132
133         eeprom.data = rt2x00dev;
134         eeprom.register_read = rt2800pci_eepromregister_read;
135         eeprom.register_write = rt2800pci_eepromregister_write;
136         eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
137             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
138         eeprom.reg_data_in = 0;
139         eeprom.reg_data_out = 0;
140         eeprom.reg_data_clock = 0;
141         eeprom.reg_chip_select = 0;
142
143         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
144                                EEPROM_SIZE / sizeof(u16));
145 }
146
147 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
148 {
149         return rt2800_efuse_detect(rt2x00dev);
150 }
151
152 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
153 {
154         rt2800_read_eeprom_efuse(rt2x00dev);
155 }
156 #else
157 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
158 {
159 }
160
161 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
162 {
163         return 0;
164 }
165
166 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
167 {
168 }
169 #endif /* CONFIG_RT2800PCI_PCI */
170
171 /*
172  * Firmware functions
173  */
174 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
175 {
176         return FIRMWARE_RT2860;
177 }
178
179 static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
180                                     const u8 *data, const size_t len)
181 {
182         u16 fw_crc;
183         u16 crc;
184
185         /*
186          * Only support 8kb firmware files.
187          */
188         if (len != 8192)
189                 return FW_BAD_LENGTH;
190
191         /*
192          * The last 2 bytes in the firmware array are the crc checksum itself,
193          * this means that we should never pass those 2 bytes to the crc
194          * algorithm.
195          */
196         fw_crc = (data[len - 2] << 8 | data[len - 1]);
197
198         /*
199          * Use the crc ccitt algorithm.
200          * This will return the same value as the legacy driver which
201          * used bit ordering reversion on the both the firmware bytes
202          * before input input as well as on the final output.
203          * Obviously using crc ccitt directly is much more efficient.
204          */
205         crc = crc_ccitt(~0, data, len - 2);
206
207         /*
208          * There is a small difference between the crc-itu-t + bitrev and
209          * the crc-ccitt crc calculation. In the latter method the 2 bytes
210          * will be swapped, use swab16 to convert the crc to the correct
211          * value.
212          */
213         crc = swab16(crc);
214
215         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
216 }
217
218 static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
219                                    const u8 *data, const size_t len)
220 {
221         unsigned int i;
222         u32 reg;
223
224         /*
225          * Wait for stable hardware.
226          */
227         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
228                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
229                 if (reg && reg != ~0)
230                         break;
231                 msleep(1);
232         }
233
234         if (i == REGISTER_BUSY_COUNT) {
235                 ERROR(rt2x00dev, "Unstable hardware.\n");
236                 return -EBUSY;
237         }
238
239         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
240         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
241
242         /*
243          * Disable DMA, will be reenabled later when enabling
244          * the radio.
245          */
246         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
247         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
248         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
249         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
250         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
251         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
252         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
253
254         /*
255          * enable Host program ram write selection
256          */
257         reg = 0;
258         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
259         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
260
261         /*
262          * Write firmware to device.
263          */
264         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
265                                       data, len);
266
267         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
268         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
269
270         /*
271          * Wait for device to stabilize.
272          */
273         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
274                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
275                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
276                         break;
277                 msleep(1);
278         }
279
280         if (i == REGISTER_BUSY_COUNT) {
281                 ERROR(rt2x00dev, "PBF system register not ready.\n");
282                 return -EBUSY;
283         }
284
285         /*
286          * Disable interrupts
287          */
288         rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
289
290         /*
291          * Initialize BBP R/W access agent
292          */
293         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
294         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
295
296         return 0;
297 }
298
299 /*
300  * Initialization functions.
301  */
302 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
303 {
304         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
305         u32 word;
306
307         if (entry->queue->qid == QID_RX) {
308                 rt2x00_desc_read(entry_priv->desc, 1, &word);
309
310                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
311         } else {
312                 rt2x00_desc_read(entry_priv->desc, 1, &word);
313
314                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
315         }
316 }
317
318 static void rt2800pci_clear_entry(struct queue_entry *entry)
319 {
320         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
321         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
322         u32 word;
323
324         if (entry->queue->qid == QID_RX) {
325                 rt2x00_desc_read(entry_priv->desc, 0, &word);
326                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
327                 rt2x00_desc_write(entry_priv->desc, 0, word);
328
329                 rt2x00_desc_read(entry_priv->desc, 1, &word);
330                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
331                 rt2x00_desc_write(entry_priv->desc, 1, word);
332         } else {
333                 rt2x00_desc_read(entry_priv->desc, 1, &word);
334                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
335                 rt2x00_desc_write(entry_priv->desc, 1, word);
336         }
337 }
338
339 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
340 {
341         struct queue_entry_priv_pci *entry_priv;
342         u32 reg;
343
344         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
345         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
346         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
347         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
348         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
349         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
350         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
351         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
352         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
353
354         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
355         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
356
357         /*
358          * Initialize registers.
359          */
360         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
361         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
362         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
363         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
364         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
365
366         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
367         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
368         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
369         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
370         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
371
372         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
373         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
374         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
375         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
376         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
377
378         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
379         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
380         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
381         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
382         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
383
384         entry_priv = rt2x00dev->rx->entries[0].priv_data;
385         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
386         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
387         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
388         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
389
390         /*
391          * Enable global DMA configuration
392          */
393         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
394         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
395         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
396         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
397         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
398
399         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
400
401         return 0;
402 }
403
404 /*
405  * Device state switch handlers.
406  */
407 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
408                                 enum dev_state state)
409 {
410         u32 reg;
411
412         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
413         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
414                            (state == STATE_RADIO_RX_ON) ||
415                            (state == STATE_RADIO_RX_ON_LINK));
416         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
417 }
418
419 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
420                                  enum dev_state state)
421 {
422         int mask = (state == STATE_RADIO_IRQ_ON);
423         u32 reg;
424
425         /*
426          * When interrupts are being enabled, the interrupt registers
427          * should clear the register to assure a clean state.
428          */
429         if (state == STATE_RADIO_IRQ_ON) {
430                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
431                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
432         }
433
434         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
435         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
436         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
437         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
438         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
439         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
440         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
441         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
442         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
443         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
444         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
445         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
446         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
447         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
448         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
449         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
450         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
451         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
452         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
453         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
454 }
455
456 static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
457 {
458         unsigned int i;
459         u32 reg;
460
461         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
462                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
463                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
464                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
465                         return 0;
466
467                 msleep(1);
468         }
469
470         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
471         return -EACCES;
472 }
473
474 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
475 {
476         u32 reg;
477         u16 word;
478
479         /*
480          * Initialize all registers.
481          */
482         if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
483                      rt2800pci_init_queues(rt2x00dev) ||
484                      rt2800_init_registers(rt2x00dev) ||
485                      rt2800pci_wait_wpdma_ready(rt2x00dev) ||
486                      rt2800_init_bbp(rt2x00dev) ||
487                      rt2800_init_rfcsr(rt2x00dev)))
488                 return -EIO;
489
490         /*
491          * Send signal to firmware during boot time.
492          */
493         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
494
495         /*
496          * Enable RX.
497          */
498         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
499         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
500         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
501         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
502
503         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
504         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
505         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
506         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
507         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
508         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
509
510         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
511         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
512         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
513         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
514
515         /*
516          * Initialize LED control
517          */
518         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
519         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
520                               word & 0xff, (word >> 8) & 0xff);
521
522         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
523         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
524                               word & 0xff, (word >> 8) & 0xff);
525
526         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
527         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
528                               word & 0xff, (word >> 8) & 0xff);
529
530         return 0;
531 }
532
533 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
534 {
535         u32 reg;
536
537         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
538         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
539         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
540         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
541         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
542         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
543         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
544
545         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
546         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
547         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
548
549         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
550
551         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
552         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
553         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
554         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
555         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
556         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
557         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
558         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
559         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
560
561         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
562         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
563
564         /* Wait for DMA, ignore error */
565         rt2800pci_wait_wpdma_ready(rt2x00dev);
566 }
567
568 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
569                                enum dev_state state)
570 {
571         /*
572          * Always put the device to sleep (even when we intend to wakeup!)
573          * if the device is booting and wasn't asleep it will return
574          * failure when attempting to wakeup.
575          */
576         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
577
578         if (state == STATE_AWAKE) {
579                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
580                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
581         }
582
583         return 0;
584 }
585
586 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
587                                       enum dev_state state)
588 {
589         int retval = 0;
590
591         switch (state) {
592         case STATE_RADIO_ON:
593                 /*
594                  * Before the radio can be enabled, the device first has
595                  * to be woken up. After that it needs a bit of time
596                  * to be fully awake and then the radio can be enabled.
597                  */
598                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
599                 msleep(1);
600                 retval = rt2800pci_enable_radio(rt2x00dev);
601                 break;
602         case STATE_RADIO_OFF:
603                 /*
604                  * After the radio has been disabled, the device should
605                  * be put to sleep for powersaving.
606                  */
607                 rt2800pci_disable_radio(rt2x00dev);
608                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
609                 break;
610         case STATE_RADIO_RX_ON:
611         case STATE_RADIO_RX_ON_LINK:
612         case STATE_RADIO_RX_OFF:
613         case STATE_RADIO_RX_OFF_LINK:
614                 rt2800pci_toggle_rx(rt2x00dev, state);
615                 break;
616         case STATE_RADIO_IRQ_ON:
617         case STATE_RADIO_IRQ_OFF:
618                 rt2800pci_toggle_irq(rt2x00dev, state);
619                 break;
620         case STATE_DEEP_SLEEP:
621         case STATE_SLEEP:
622         case STATE_STANDBY:
623         case STATE_AWAKE:
624                 retval = rt2800pci_set_state(rt2x00dev, state);
625                 break;
626         default:
627                 retval = -ENOTSUPP;
628                 break;
629         }
630
631         if (unlikely(retval))
632                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
633                       state, retval);
634
635         return retval;
636 }
637
638 /*
639  * TX descriptor initialization
640  */
641 static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
642                                     struct sk_buff *skb,
643                                     struct txentry_desc *txdesc)
644 {
645         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
646         __le32 *txd = skbdesc->desc;
647         __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->ops->extra_tx_headroom);
648         u32 word;
649
650         /*
651          * Initialize TX Info descriptor
652          */
653         rt2x00_desc_read(txwi, 0, &word);
654         rt2x00_set_field32(&word, TXWI_W0_FRAG,
655                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
656         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
657         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
658         rt2x00_set_field32(&word, TXWI_W0_TS,
659                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
660         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
661                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
662         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
663         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
664         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
665         rt2x00_set_field32(&word, TXWI_W0_BW,
666                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
667         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
668                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
669         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
670         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
671         rt2x00_desc_write(txwi, 0, word);
672
673         rt2x00_desc_read(txwi, 1, &word);
674         rt2x00_set_field32(&word, TXWI_W1_ACK,
675                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
676         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
677                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
678         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
679         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
680                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
681                            txdesc->key_idx : 0xff);
682         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
683                            skb->len - txdesc->l2pad);
684         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
685                            skbdesc->entry->queue->qid + 1);
686         rt2x00_desc_write(txwi, 1, word);
687
688         /*
689          * Always write 0 to IV/EIV fields, hardware will insert the IV
690          * from the IVEIV register when TXD_W3_WIV is set to 0.
691          * When TXD_W3_WIV is set to 1 it will use the IV data
692          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
693          * crypto entry in the registers should be used to encrypt the frame.
694          */
695         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
696         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
697
698         /*
699          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
700          * must contains a TXWI structure + 802.11 header + padding + 802.11
701          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
702          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
703          * data. It means that LAST_SEC0 is always 0.
704          */
705
706         /*
707          * Initialize TX descriptor
708          */
709         rt2x00_desc_read(txd, 0, &word);
710         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
711         rt2x00_desc_write(txd, 0, word);
712
713         rt2x00_desc_read(txd, 1, &word);
714         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
715         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
716                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
717         rt2x00_set_field32(&word, TXD_W1_BURST,
718                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
719         rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
720                            rt2x00dev->ops->extra_tx_headroom);
721         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
722         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
723         rt2x00_desc_write(txd, 1, word);
724
725         rt2x00_desc_read(txd, 2, &word);
726         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
727                            skbdesc->skb_dma + rt2x00dev->ops->extra_tx_headroom);
728         rt2x00_desc_write(txd, 2, word);
729
730         rt2x00_desc_read(txd, 3, &word);
731         rt2x00_set_field32(&word, TXD_W3_WIV,
732                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
733         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
734         rt2x00_desc_write(txd, 3, word);
735 }
736
737 /*
738  * TX data initialization
739  */
740 static void rt2800pci_write_beacon(struct queue_entry *entry)
741 {
742         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
743         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
744         unsigned int beacon_base;
745         u32 reg;
746
747         /*
748          * Disable beaconing while we are reloading the beacon data,
749          * otherwise we might be sending out invalid data.
750          */
751         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
752         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
753         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
754
755         /*
756          * Write entire beacon with descriptor to register.
757          */
758         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
759         rt2800_register_multiwrite(rt2x00dev,
760                                       beacon_base,
761                                       skbdesc->desc, skbdesc->desc_len);
762         rt2800_register_multiwrite(rt2x00dev,
763                                       beacon_base + skbdesc->desc_len,
764                                       entry->skb->data, entry->skb->len);
765
766         /*
767          * Clean up beacon skb.
768          */
769         dev_kfree_skb_any(entry->skb);
770         entry->skb = NULL;
771 }
772
773 static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
774                                     const enum data_queue_qid queue_idx)
775 {
776         struct data_queue *queue;
777         unsigned int idx, qidx = 0;
778         u32 reg;
779
780         if (queue_idx == QID_BEACON) {
781                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
782                 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
783                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
784                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
785                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
786                         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
787                 }
788                 return;
789         }
790
791         if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
792                 return;
793
794         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
795         idx = queue->index[Q_INDEX];
796
797         if (queue_idx == QID_MGMT)
798                 qidx = 5;
799         else
800                 qidx = queue_idx;
801
802         rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
803 }
804
805 static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
806                                     const enum data_queue_qid qid)
807 {
808         u32 reg;
809
810         if (qid == QID_BEACON) {
811                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
812                 return;
813         }
814
815         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
816         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
817         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
818         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
819         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
820         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
821 }
822
823 /*
824  * RX control handlers
825  */
826 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
827                                   struct rxdone_entry_desc *rxdesc)
828 {
829         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
830         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
831         __le32 *rxd = entry_priv->desc;
832         __le32 *rxwi = (__le32 *)entry->skb->data;
833         u32 rxd3;
834         u32 rxwi0;
835         u32 rxwi1;
836         u32 rxwi2;
837         u32 rxwi3;
838
839         rt2x00_desc_read(rxd, 3, &rxd3);
840         rt2x00_desc_read(rxwi, 0, &rxwi0);
841         rt2x00_desc_read(rxwi, 1, &rxwi1);
842         rt2x00_desc_read(rxwi, 2, &rxwi2);
843         rt2x00_desc_read(rxwi, 3, &rxwi3);
844
845         if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
846                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
847
848         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
849                 /*
850                  * Unfortunately we don't know the cipher type used during
851                  * decryption. This prevents us from correct providing
852                  * correct statistics through debugfs.
853                  */
854                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
855                 rxdesc->cipher_status =
856                     rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
857         }
858
859         if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
860                 /*
861                  * Hardware has stripped IV/EIV data from 802.11 frame during
862                  * decryption. Unfortunately the descriptor doesn't contain
863                  * any fields with the EIV/IV data either, so they can't
864                  * be restored by rt2x00lib.
865                  */
866                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
867
868                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
869                         rxdesc->flags |= RX_FLAG_DECRYPTED;
870                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
871                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
872         }
873
874         if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
875                 rxdesc->dev_flags |= RXDONE_MY_BSS;
876
877         if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD))
878                 rxdesc->dev_flags |= RXDONE_L2PAD;
879
880         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
881                 rxdesc->flags |= RX_FLAG_SHORT_GI;
882
883         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
884                 rxdesc->flags |= RX_FLAG_40MHZ;
885
886         /*
887          * Detect RX rate, always use MCS as signal type.
888          */
889         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
890         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
891         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
892
893         /*
894          * Mask of 0x8 bit to remove the short preamble flag.
895          */
896         if (rxdesc->rate_mode == RATE_MODE_CCK)
897                 rxdesc->signal &= ~0x8;
898
899         rxdesc->rssi =
900             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
901              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
902
903         rxdesc->noise =
904             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
905              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
906
907         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
908
909         /*
910          * Set RX IDX in register to inform hardware that we have handled
911          * this entry and it is available for reuse again.
912          */
913         rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
914
915         /*
916          * Remove TXWI descriptor from start of buffer.
917          */
918         skb_pull(entry->skb, RXWI_DESC_SIZE);
919 }
920
921 /*
922  * Interrupt functions.
923  */
924 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
925 {
926         struct data_queue *queue;
927         struct queue_entry *entry;
928         struct queue_entry *entry_done;
929         struct queue_entry_priv_pci *entry_priv;
930         struct txdone_entry_desc txdesc;
931         u32 word;
932         u32 reg;
933         u32 old_reg;
934         unsigned int type;
935         unsigned int index;
936         u16 mcs, real_mcs;
937
938         /*
939          * During each loop we will compare the freshly read
940          * TX_STA_FIFO register value with the value read from
941          * the previous loop. If the 2 values are equal then
942          * we should stop processing because the chance it
943          * quite big that the device has been unplugged and
944          * we risk going into an endless loop.
945          */
946         old_reg = 0;
947
948         while (1) {
949                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
950                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
951                         break;
952
953                 if (old_reg == reg)
954                         break;
955                 old_reg = reg;
956
957                 /*
958                  * Skip this entry when it contains an invalid
959                  * queue identication number.
960                  */
961                 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
962                 if (type >= QID_RX)
963                         continue;
964
965                 queue = rt2x00queue_get_queue(rt2x00dev, type);
966                 if (unlikely(!queue))
967                         continue;
968
969                 /*
970                  * Skip this entry when it contains an invalid
971                  * index number.
972                  */
973                 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;
974                 if (unlikely(index >= queue->limit))
975                         continue;
976
977                 entry = &queue->entries[index];
978                 entry_priv = entry->priv_data;
979                 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
980
981                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
982                 while (entry != entry_done) {
983                         /*
984                          * Catch up.
985                          * Just report any entries we missed as failed.
986                          */
987                         WARNING(rt2x00dev,
988                                 "TX status report missed for entry %d\n",
989                                 entry_done->entry_idx);
990
991                         txdesc.flags = 0;
992                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
993                         txdesc.retry = 0;
994
995                         rt2x00lib_txdone(entry_done, &txdesc);
996                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
997                 }
998
999                 /*
1000                  * Obtain the status about this packet.
1001                  */
1002                 txdesc.flags = 0;
1003                 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
1004                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1005                 else
1006                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1007
1008                 /*
1009                  * Ralink has a retry mechanism using a global fallback
1010                  * table. We setup this fallback table to try immediate
1011                  * lower rate for all rates. In the TX_STA_FIFO,
1012                  * the MCS field contains the MCS used for the successfull
1013                  * transmission. If the first transmission succeed,
1014                  * we have mcs == tx_mcs. On the second transmission,
1015                  * we have mcs = tx_mcs - 1. So the number of
1016                  * retry is (tx_mcs - mcs).
1017                  */
1018                 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1019                 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
1020                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1021                 txdesc.retry = mcs - min(mcs, real_mcs);
1022
1023                 rt2x00lib_txdone(entry, &txdesc);
1024         }
1025 }
1026
1027 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1028 {
1029         struct rt2x00_dev *rt2x00dev = dev_instance;
1030         u32 reg;
1031
1032         /* Read status and ACK all interrupts */
1033         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1034         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1035
1036         if (!reg)
1037                 return IRQ_NONE;
1038
1039         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1040                 return IRQ_HANDLED;
1041
1042         /*
1043          * 1 - Rx ring done interrupt.
1044          */
1045         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1046                 rt2x00pci_rxdone(rt2x00dev);
1047
1048         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1049                 rt2800pci_txdone(rt2x00dev);
1050
1051         return IRQ_HANDLED;
1052 }
1053
1054 /*
1055  * Device probe functions.
1056  */
1057 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1058 {
1059         /*
1060          * Read EEPROM into buffer
1061          */
1062         switch (rt2x00dev->chip.rt) {
1063         case RT2880:
1064         case RT3052:
1065                 rt2800pci_read_eeprom_soc(rt2x00dev);
1066                 break;
1067         default:
1068                 if (rt2800pci_efuse_detect(rt2x00dev))
1069                         rt2800pci_read_eeprom_efuse(rt2x00dev);
1070                 else
1071                         rt2800pci_read_eeprom_pci(rt2x00dev);
1072                 break;
1073         }
1074
1075         return rt2800_validate_eeprom(rt2x00dev);
1076 }
1077
1078 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1079         .register_read          = rt2x00pci_register_read,
1080         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
1081         .register_write         = rt2x00pci_register_write,
1082         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
1083
1084         .register_multiread     = rt2x00pci_register_multiread,
1085         .register_multiwrite    = rt2x00pci_register_multiwrite,
1086
1087         .regbusy_read           = rt2x00pci_regbusy_read,
1088 };
1089
1090 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1091 {
1092         int retval;
1093
1094         rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1095
1096         /*
1097          * Allocate eeprom data.
1098          */
1099         retval = rt2800pci_validate_eeprom(rt2x00dev);
1100         if (retval)
1101                 return retval;
1102
1103         retval = rt2800_init_eeprom(rt2x00dev);
1104         if (retval)
1105                 return retval;
1106
1107         /*
1108          * Initialize hw specifications.
1109          */
1110         retval = rt2800_probe_hw_mode(rt2x00dev);
1111         if (retval)
1112                 return retval;
1113
1114         /*
1115          * This device has multiple filters for control frames
1116          * and has a separate filter for PS Poll frames.
1117          */
1118         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1119         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1120
1121         /*
1122          * This device requires firmware.
1123          */
1124         if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
1125             !rt2x00_rt(&rt2x00dev->chip, RT3052))
1126                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1127         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1128         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1129         if (!modparam_nohwcrypt)
1130                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1131
1132         /*
1133          * Set the rssi offset.
1134          */
1135         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1136
1137         return 0;
1138 }
1139
1140 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1141         .irq_handler            = rt2800pci_interrupt,
1142         .probe_hw               = rt2800pci_probe_hw,
1143         .get_firmware_name      = rt2800pci_get_firmware_name,
1144         .check_firmware         = rt2800pci_check_firmware,
1145         .load_firmware          = rt2800pci_load_firmware,
1146         .initialize             = rt2x00pci_initialize,
1147         .uninitialize           = rt2x00pci_uninitialize,
1148         .get_entry_state        = rt2800pci_get_entry_state,
1149         .clear_entry            = rt2800pci_clear_entry,
1150         .set_device_state       = rt2800pci_set_device_state,
1151         .rfkill_poll            = rt2800_rfkill_poll,
1152         .link_stats             = rt2800_link_stats,
1153         .reset_tuner            = rt2800_reset_tuner,
1154         .link_tuner             = rt2800_link_tuner,
1155         .write_tx_desc          = rt2800pci_write_tx_desc,
1156         .write_tx_data          = rt2x00pci_write_tx_data,
1157         .write_beacon           = rt2800pci_write_beacon,
1158         .kick_tx_queue          = rt2800pci_kick_tx_queue,
1159         .kill_tx_queue          = rt2800pci_kill_tx_queue,
1160         .fill_rxdone            = rt2800pci_fill_rxdone,
1161         .config_shared_key      = rt2800_config_shared_key,
1162         .config_pairwise_key    = rt2800_config_pairwise_key,
1163         .config_filter          = rt2800_config_filter,
1164         .config_intf            = rt2800_config_intf,
1165         .config_erp             = rt2800_config_erp,
1166         .config_ant             = rt2800_config_ant,
1167         .config                 = rt2800_config,
1168 };
1169
1170 static const struct data_queue_desc rt2800pci_queue_rx = {
1171         .entry_num              = RX_ENTRIES,
1172         .data_size              = AGGREGATION_SIZE,
1173         .desc_size              = RXD_DESC_SIZE,
1174         .priv_size              = sizeof(struct queue_entry_priv_pci),
1175 };
1176
1177 static const struct data_queue_desc rt2800pci_queue_tx = {
1178         .entry_num              = TX_ENTRIES,
1179         .data_size              = AGGREGATION_SIZE,
1180         .desc_size              = TXD_DESC_SIZE,
1181         .priv_size              = sizeof(struct queue_entry_priv_pci),
1182 };
1183
1184 static const struct data_queue_desc rt2800pci_queue_bcn = {
1185         .entry_num              = 8 * BEACON_ENTRIES,
1186         .data_size              = 0, /* No DMA required for beacons */
1187         .desc_size              = TXWI_DESC_SIZE,
1188         .priv_size              = sizeof(struct queue_entry_priv_pci),
1189 };
1190
1191 static const struct rt2x00_ops rt2800pci_ops = {
1192         .name                   = KBUILD_MODNAME,
1193         .max_sta_intf           = 1,
1194         .max_ap_intf            = 8,
1195         .eeprom_size            = EEPROM_SIZE,
1196         .rf_size                = RF_SIZE,
1197         .tx_queues              = NUM_TX_QUEUES,
1198         .extra_tx_headroom      = TXWI_DESC_SIZE,
1199         .rx                     = &rt2800pci_queue_rx,
1200         .tx                     = &rt2800pci_queue_tx,
1201         .bcn                    = &rt2800pci_queue_bcn,
1202         .lib                    = &rt2800pci_rt2x00_ops,
1203         .hw                     = &rt2800_mac80211_ops,
1204 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1205         .debugfs                = &rt2800_rt2x00debug,
1206 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1207 };
1208
1209 /*
1210  * RT2800pci module information.
1211  */
1212 static struct pci_device_id rt2800pci_device_table[] = {
1213         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1214         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1215         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1216         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1217         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1218         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1219         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1220         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1221         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1222         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1223         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1224         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1225         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1226         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1227         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1228         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1229         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1230         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1231         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1232         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1233         { 0, }
1234 };
1235
1236 MODULE_AUTHOR(DRV_PROJECT);
1237 MODULE_VERSION(DRV_VERSION);
1238 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1239 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1240 #ifdef CONFIG_RT2800PCI_PCI
1241 MODULE_FIRMWARE(FIRMWARE_RT2860);
1242 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1243 #endif /* CONFIG_RT2800PCI_PCI */
1244 MODULE_LICENSE("GPL");
1245
1246 #ifdef CONFIG_RT2800PCI_SOC
1247 #if defined(CONFIG_RALINK_RT288X)
1248 __rt2x00soc_probe(RT2880, &rt2800pci_ops);
1249 #elif defined(CONFIG_RALINK_RT305X)
1250 __rt2x00soc_probe(RT3052, &rt2800pci_ops);
1251 #endif
1252
1253 static struct platform_driver rt2800soc_driver = {
1254         .driver         = {
1255                 .name           = "rt2800_wmac",
1256                 .owner          = THIS_MODULE,
1257                 .mod_name       = KBUILD_MODNAME,
1258         },
1259         .probe          = __rt2x00soc_probe,
1260         .remove         = __devexit_p(rt2x00soc_remove),
1261         .suspend        = rt2x00soc_suspend,
1262         .resume         = rt2x00soc_resume,
1263 };
1264 #endif /* CONFIG_RT2800PCI_SOC */
1265
1266 #ifdef CONFIG_RT2800PCI_PCI
1267 static struct pci_driver rt2800pci_driver = {
1268         .name           = KBUILD_MODNAME,
1269         .id_table       = rt2800pci_device_table,
1270         .probe          = rt2x00pci_probe,
1271         .remove         = __devexit_p(rt2x00pci_remove),
1272         .suspend        = rt2x00pci_suspend,
1273         .resume         = rt2x00pci_resume,
1274 };
1275 #endif /* CONFIG_RT2800PCI_PCI */
1276
1277 static int __init rt2800pci_init(void)
1278 {
1279         int ret = 0;
1280
1281 #ifdef CONFIG_RT2800PCI_SOC
1282         ret = platform_driver_register(&rt2800soc_driver);
1283         if (ret)
1284                 return ret;
1285 #endif
1286 #ifdef CONFIG_RT2800PCI_PCI
1287         ret = pci_register_driver(&rt2800pci_driver);
1288         if (ret) {
1289 #ifdef CONFIG_RT2800PCI_SOC
1290                 platform_driver_unregister(&rt2800soc_driver);
1291 #endif
1292                 return ret;
1293         }
1294 #endif
1295
1296         return ret;
1297 }
1298
1299 static void __exit rt2800pci_exit(void)
1300 {
1301 #ifdef CONFIG_RT2800PCI_PCI
1302         pci_unregister_driver(&rt2800pci_driver);
1303 #endif
1304 #ifdef CONFIG_RT2800PCI_SOC
1305         platform_driver_unregister(&rt2800soc_driver);
1306 #endif
1307 }
1308
1309 module_init(rt2800pci_init);
1310 module_exit(rt2800pci_exit);