a654551b73259eaa4b635b48f1f4664b86401284
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
3         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
4
5         Based on the original rt2800pci.c and rt2800usb.c.
6           Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
7           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
13           <http://rt2x00.serialmonkey.com>
14
15         This program is free software; you can redistribute it and/or modify
16         it under the terms of the GNU General Public License as published by
17         the Free Software Foundation; either version 2 of the License, or
18         (at your option) any later version.
19
20         This program is distributed in the hope that it will be useful,
21         but WITHOUT ANY WARRANTY; without even the implied warranty of
22         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23         GNU General Public License for more details.
24
25         You should have received a copy of the GNU General Public License
26         along with this program; if not, write to the
27         Free Software Foundation, Inc.,
28         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29  */
30
31 /*
32         Module: rt2800lib
33         Abstract: rt2800 generic device routines.
34  */
35
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38
39 #include "rt2x00.h"
40 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
41 #include "rt2x00usb.h"
42 #endif
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45 #include "rt2800usb.h"
46
47 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
48 MODULE_DESCRIPTION("rt2800 library");
49 MODULE_LICENSE("GPL");
50
51 /*
52  * Register access.
53  * All access to the CSR registers will go through the methods
54  * rt2800_register_read and rt2800_register_write.
55  * BBP and RF register require indirect register access,
56  * and use the CSR registers BBPCSR and RFCSR to achieve this.
57  * These indirect registers work with busy bits,
58  * and we will try maximal REGISTER_BUSY_COUNT times to access
59  * the register while taking a REGISTER_BUSY_DELAY us delay
60  * between each attampt. When the busy bit is still set at that time,
61  * the access attempt is considered to have failed,
62  * and we will print an error.
63  * The _lock versions must be used if you already hold the csr_mutex
64  */
65 #define WAIT_FOR_BBP(__dev, __reg) \
66         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
67 #define WAIT_FOR_RFCSR(__dev, __reg) \
68         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
69 #define WAIT_FOR_RF(__dev, __reg) \
70         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
71 #define WAIT_FOR_MCU(__dev, __reg) \
72         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
73                             H2M_MAILBOX_CSR_OWNER, (__reg))
74
75 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
76                              const unsigned int word, const u8 value)
77 {
78         u32 reg;
79
80         mutex_lock(&rt2x00dev->csr_mutex);
81
82         /*
83          * Wait until the BBP becomes available, afterwards we
84          * can safely write the new data into the register.
85          */
86         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
87                 reg = 0;
88                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
89                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
90                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
91                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
92                 if (rt2x00_intf_is_pci(rt2x00dev))
93                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
94
95                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
96         }
97
98         mutex_unlock(&rt2x00dev->csr_mutex);
99 }
100
101 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
102                             const unsigned int word, u8 *value)
103 {
104         u32 reg;
105
106         mutex_lock(&rt2x00dev->csr_mutex);
107
108         /*
109          * Wait until the BBP becomes available, afterwards we
110          * can safely write the read request into the register.
111          * After the data has been written, we wait until hardware
112          * returns the correct value, if at any time the register
113          * doesn't become available in time, reg will be 0xffffffff
114          * which means we return 0xff to the caller.
115          */
116         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
117                 reg = 0;
118                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
119                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
120                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
121                 if (rt2x00_intf_is_pci(rt2x00dev))
122                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
123
124                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
125
126                 WAIT_FOR_BBP(rt2x00dev, &reg);
127         }
128
129         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
130
131         mutex_unlock(&rt2x00dev->csr_mutex);
132 }
133
134 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
135                                const unsigned int word, const u8 value)
136 {
137         u32 reg;
138
139         mutex_lock(&rt2x00dev->csr_mutex);
140
141         /*
142          * Wait until the RFCSR becomes available, afterwards we
143          * can safely write the new data into the register.
144          */
145         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
146                 reg = 0;
147                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
148                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
149                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
150                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
151
152                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
153         }
154
155         mutex_unlock(&rt2x00dev->csr_mutex);
156 }
157
158 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
159                               const unsigned int word, u8 *value)
160 {
161         u32 reg;
162
163         mutex_lock(&rt2x00dev->csr_mutex);
164
165         /*
166          * Wait until the RFCSR becomes available, afterwards we
167          * can safely write the read request into the register.
168          * After the data has been written, we wait until hardware
169          * returns the correct value, if at any time the register
170          * doesn't become available in time, reg will be 0xffffffff
171          * which means we return 0xff to the caller.
172          */
173         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
174                 reg = 0;
175                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
176                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
177                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
178
179                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
180
181                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
182         }
183
184         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
185
186         mutex_unlock(&rt2x00dev->csr_mutex);
187 }
188
189 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
190                             const unsigned int word, const u32 value)
191 {
192         u32 reg;
193
194         mutex_lock(&rt2x00dev->csr_mutex);
195
196         /*
197          * Wait until the RF becomes available, afterwards we
198          * can safely write the new data into the register.
199          */
200         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
201                 reg = 0;
202                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
203                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
204                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
205                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
206
207                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
208                 rt2x00_rf_write(rt2x00dev, word, value);
209         }
210
211         mutex_unlock(&rt2x00dev->csr_mutex);
212 }
213
214 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
215                         const u8 command, const u8 token,
216                         const u8 arg0, const u8 arg1)
217 {
218         u32 reg;
219
220         /*
221          * RT2880 and RT3052 don't support MCU requests.
222          */
223         if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
224             rt2x00_rt(&rt2x00dev->chip, RT3052))
225                 return;
226
227         mutex_lock(&rt2x00dev->csr_mutex);
228
229         /*
230          * Wait until the MCU becomes available, afterwards we
231          * can safely write the new data into the register.
232          */
233         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
234                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
235                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
236                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
237                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
238                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
239
240                 reg = 0;
241                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
242                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
243         }
244
245         mutex_unlock(&rt2x00dev->csr_mutex);
246 }
247 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
248
249 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
250 const struct rt2x00debug rt2800_rt2x00debug = {
251         .owner  = THIS_MODULE,
252         .csr    = {
253                 .read           = rt2800_register_read,
254                 .write          = rt2800_register_write,
255                 .flags          = RT2X00DEBUGFS_OFFSET,
256                 .word_base      = CSR_REG_BASE,
257                 .word_size      = sizeof(u32),
258                 .word_count     = CSR_REG_SIZE / sizeof(u32),
259         },
260         .eeprom = {
261                 .read           = rt2x00_eeprom_read,
262                 .write          = rt2x00_eeprom_write,
263                 .word_base      = EEPROM_BASE,
264                 .word_size      = sizeof(u16),
265                 .word_count     = EEPROM_SIZE / sizeof(u16),
266         },
267         .bbp    = {
268                 .read           = rt2800_bbp_read,
269                 .write          = rt2800_bbp_write,
270                 .word_base      = BBP_BASE,
271                 .word_size      = sizeof(u8),
272                 .word_count     = BBP_SIZE / sizeof(u8),
273         },
274         .rf     = {
275                 .read           = rt2x00_rf_read,
276                 .write          = rt2800_rf_write,
277                 .word_base      = RF_BASE,
278                 .word_size      = sizeof(u32),
279                 .word_count     = RF_SIZE / sizeof(u32),
280         },
281 };
282 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
283 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
284
285 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
286 {
287         u32 reg;
288
289         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
290         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
291 }
292 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
293
294 #ifdef CONFIG_RT2X00_LIB_LEDS
295 static void rt2800_brightness_set(struct led_classdev *led_cdev,
296                                   enum led_brightness brightness)
297 {
298         struct rt2x00_led *led =
299             container_of(led_cdev, struct rt2x00_led, led_dev);
300         unsigned int enabled = brightness != LED_OFF;
301         unsigned int bg_mode =
302             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
303         unsigned int polarity =
304                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
305                                    EEPROM_FREQ_LED_POLARITY);
306         unsigned int ledmode =
307                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
308                                    EEPROM_FREQ_LED_MODE);
309
310         if (led->type == LED_TYPE_RADIO) {
311                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
312                                       enabled ? 0x20 : 0);
313         } else if (led->type == LED_TYPE_ASSOC) {
314                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
315                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
316         } else if (led->type == LED_TYPE_QUALITY) {
317                 /*
318                  * The brightness is divided into 6 levels (0 - 5),
319                  * The specs tell us the following levels:
320                  *      0, 1 ,3, 7, 15, 31
321                  * to determine the level in a simple way we can simply
322                  * work with bitshifting:
323                  *      (1 << level) - 1
324                  */
325                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
326                                       (1 << brightness / (LED_FULL / 6)) - 1,
327                                       polarity);
328         }
329 }
330
331 static int rt2800_blink_set(struct led_classdev *led_cdev,
332                             unsigned long *delay_on, unsigned long *delay_off)
333 {
334         struct rt2x00_led *led =
335             container_of(led_cdev, struct rt2x00_led, led_dev);
336         u32 reg;
337
338         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
339         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
340         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
341         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
342         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
343         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
344         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
345         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
346         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
347
348         return 0;
349 }
350
351 void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
352                      struct rt2x00_led *led, enum led_type type)
353 {
354         led->rt2x00dev = rt2x00dev;
355         led->type = type;
356         led->led_dev.brightness_set = rt2800_brightness_set;
357         led->led_dev.blink_set = rt2800_blink_set;
358         led->flags = LED_INITIALIZED;
359 }
360 EXPORT_SYMBOL_GPL(rt2800_init_led);
361 #endif /* CONFIG_RT2X00_LIB_LEDS */
362
363 /*
364  * Configuration handlers.
365  */
366 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
367                                     struct rt2x00lib_crypto *crypto,
368                                     struct ieee80211_key_conf *key)
369 {
370         struct mac_wcid_entry wcid_entry;
371         struct mac_iveiv_entry iveiv_entry;
372         u32 offset;
373         u32 reg;
374
375         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
376
377         rt2800_register_read(rt2x00dev, offset, &reg);
378         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
379                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
380         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
381                            (crypto->cmd == SET_KEY) * crypto->cipher);
382         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
383                            (crypto->cmd == SET_KEY) * crypto->bssidx);
384         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
385         rt2800_register_write(rt2x00dev, offset, reg);
386
387         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
388
389         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
390         if ((crypto->cipher == CIPHER_TKIP) ||
391             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
392             (crypto->cipher == CIPHER_AES))
393                 iveiv_entry.iv[3] |= 0x20;
394         iveiv_entry.iv[3] |= key->keyidx << 6;
395         rt2800_register_multiwrite(rt2x00dev, offset,
396                                       &iveiv_entry, sizeof(iveiv_entry));
397
398         offset = MAC_WCID_ENTRY(key->hw_key_idx);
399
400         memset(&wcid_entry, 0, sizeof(wcid_entry));
401         if (crypto->cmd == SET_KEY)
402                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
403         rt2800_register_multiwrite(rt2x00dev, offset,
404                                       &wcid_entry, sizeof(wcid_entry));
405 }
406
407 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
408                              struct rt2x00lib_crypto *crypto,
409                              struct ieee80211_key_conf *key)
410 {
411         struct hw_key_entry key_entry;
412         struct rt2x00_field32 field;
413         u32 offset;
414         u32 reg;
415
416         if (crypto->cmd == SET_KEY) {
417                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
418
419                 memcpy(key_entry.key, crypto->key,
420                        sizeof(key_entry.key));
421                 memcpy(key_entry.tx_mic, crypto->tx_mic,
422                        sizeof(key_entry.tx_mic));
423                 memcpy(key_entry.rx_mic, crypto->rx_mic,
424                        sizeof(key_entry.rx_mic));
425
426                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
427                 rt2800_register_multiwrite(rt2x00dev, offset,
428                                               &key_entry, sizeof(key_entry));
429         }
430
431         /*
432          * The cipher types are stored over multiple registers
433          * starting with SHARED_KEY_MODE_BASE each word will have
434          * 32 bits and contains the cipher types for 2 bssidx each.
435          * Using the correct defines correctly will cause overhead,
436          * so just calculate the correct offset.
437          */
438         field.bit_offset = 4 * (key->hw_key_idx % 8);
439         field.bit_mask = 0x7 << field.bit_offset;
440
441         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
442
443         rt2800_register_read(rt2x00dev, offset, &reg);
444         rt2x00_set_field32(&reg, field,
445                            (crypto->cmd == SET_KEY) * crypto->cipher);
446         rt2800_register_write(rt2x00dev, offset, reg);
447
448         /*
449          * Update WCID information
450          */
451         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
452
453         return 0;
454 }
455 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
456
457 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
458                                struct rt2x00lib_crypto *crypto,
459                                struct ieee80211_key_conf *key)
460 {
461         struct hw_key_entry key_entry;
462         u32 offset;
463
464         if (crypto->cmd == SET_KEY) {
465                 /*
466                  * 1 pairwise key is possible per AID, this means that the AID
467                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
468                  * last possible shared key entry.
469                  */
470                 if (crypto->aid > (256 - 32))
471                         return -ENOSPC;
472
473                 key->hw_key_idx = 32 + crypto->aid;
474
475                 memcpy(key_entry.key, crypto->key,
476                        sizeof(key_entry.key));
477                 memcpy(key_entry.tx_mic, crypto->tx_mic,
478                        sizeof(key_entry.tx_mic));
479                 memcpy(key_entry.rx_mic, crypto->rx_mic,
480                        sizeof(key_entry.rx_mic));
481
482                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
483                 rt2800_register_multiwrite(rt2x00dev, offset,
484                                               &key_entry, sizeof(key_entry));
485         }
486
487         /*
488          * Update WCID information
489          */
490         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
491
492         return 0;
493 }
494 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
495
496 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
497                           const unsigned int filter_flags)
498 {
499         u32 reg;
500
501         /*
502          * Start configuration steps.
503          * Note that the version error will always be dropped
504          * and broadcast frames will always be accepted since
505          * there is no filter for it at this time.
506          */
507         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
508         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
509                            !(filter_flags & FIF_FCSFAIL));
510         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
511                            !(filter_flags & FIF_PLCPFAIL));
512         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
513                            !(filter_flags & FIF_PROMISC_IN_BSS));
514         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
515         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
516         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
517                            !(filter_flags & FIF_ALLMULTI));
518         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
519         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
520         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
521                            !(filter_flags & FIF_CONTROL));
522         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
523                            !(filter_flags & FIF_CONTROL));
524         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
525                            !(filter_flags & FIF_CONTROL));
526         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
527                            !(filter_flags & FIF_CONTROL));
528         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
529                            !(filter_flags & FIF_CONTROL));
530         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
531                            !(filter_flags & FIF_PSPOLL));
532         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
533         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
534         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
535                            !(filter_flags & FIF_CONTROL));
536         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
537 }
538 EXPORT_SYMBOL_GPL(rt2800_config_filter);
539
540 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
541                         struct rt2x00intf_conf *conf, const unsigned int flags)
542 {
543         unsigned int beacon_base;
544         u32 reg;
545
546         if (flags & CONFIG_UPDATE_TYPE) {
547                 /*
548                  * Clear current synchronisation setup.
549                  * For the Beacon base registers we only need to clear
550                  * the first byte since that byte contains the VALID and OWNER
551                  * bits which (when set to 0) will invalidate the entire beacon.
552                  */
553                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
554                 rt2800_register_write(rt2x00dev, beacon_base, 0);
555
556                 /*
557                  * Enable synchronisation.
558                  */
559                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
560                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
561                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
562                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
563                                    (conf->sync == TSF_SYNC_BEACON));
564                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
565         }
566
567         if (flags & CONFIG_UPDATE_MAC) {
568                 reg = le32_to_cpu(conf->mac[1]);
569                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
570                 conf->mac[1] = cpu_to_le32(reg);
571
572                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
573                                               conf->mac, sizeof(conf->mac));
574         }
575
576         if (flags & CONFIG_UPDATE_BSSID) {
577                 reg = le32_to_cpu(conf->bssid[1]);
578                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
579                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
580                 conf->bssid[1] = cpu_to_le32(reg);
581
582                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
583                                               conf->bssid, sizeof(conf->bssid));
584         }
585 }
586 EXPORT_SYMBOL_GPL(rt2800_config_intf);
587
588 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
589 {
590         u32 reg;
591
592         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
593         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
594         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
595
596         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
597         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
598                            !!erp->short_preamble);
599         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
600                            !!erp->short_preamble);
601         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
602
603         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
604         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
605                            erp->cts_protection ? 2 : 0);
606         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
607
608         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
609                                  erp->basic_rates);
610         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
611
612         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
613         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
614         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
615         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
616
617         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
618         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
619         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
620         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
621         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
622         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
623         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
624
625         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
626         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
627                            erp->beacon_int * 16);
628         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
629 }
630 EXPORT_SYMBOL_GPL(rt2800_config_erp);
631
632 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
633 {
634         u8 r1;
635         u8 r3;
636
637         rt2800_bbp_read(rt2x00dev, 1, &r1);
638         rt2800_bbp_read(rt2x00dev, 3, &r3);
639
640         /*
641          * Configure the TX antenna.
642          */
643         switch ((int)ant->tx) {
644         case 1:
645                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
646                 if (rt2x00_intf_is_pci(rt2x00dev))
647                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
648                 break;
649         case 2:
650                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
651                 break;
652         case 3:
653                 /* Do nothing */
654                 break;
655         }
656
657         /*
658          * Configure the RX antenna.
659          */
660         switch ((int)ant->rx) {
661         case 1:
662                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
663                 break;
664         case 2:
665                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
666                 break;
667         case 3:
668                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
669                 break;
670         }
671
672         rt2800_bbp_write(rt2x00dev, 3, r3);
673         rt2800_bbp_write(rt2x00dev, 1, r1);
674 }
675 EXPORT_SYMBOL_GPL(rt2800_config_ant);
676
677 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
678                                    struct rt2x00lib_conf *libconf)
679 {
680         u16 eeprom;
681         short lna_gain;
682
683         if (libconf->rf.channel <= 14) {
684                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
685                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
686         } else if (libconf->rf.channel <= 64) {
687                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
688                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
689         } else if (libconf->rf.channel <= 128) {
690                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
691                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
692         } else {
693                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
694                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
695         }
696
697         rt2x00dev->lna_gain = lna_gain;
698 }
699
700 static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
701                                        struct ieee80211_conf *conf,
702                                        struct rf_channel *rf,
703                                        struct channel_info *info)
704 {
705         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
706
707         if (rt2x00dev->default_ant.tx == 1)
708                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
709
710         if (rt2x00dev->default_ant.rx == 1) {
711                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
712                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
713         } else if (rt2x00dev->default_ant.rx == 2)
714                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
715
716         if (rf->channel > 14) {
717                 /*
718                  * When TX power is below 0, we should increase it by 7 to
719                  * make it a positive value (Minumum value is -7).
720                  * However this means that values between 0 and 7 have
721                  * double meaning, and we should set a 7DBm boost flag.
722                  */
723                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
724                                    (info->tx_power1 >= 0));
725
726                 if (info->tx_power1 < 0)
727                         info->tx_power1 += 7;
728
729                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
730                                    TXPOWER_A_TO_DEV(info->tx_power1));
731
732                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
733                                    (info->tx_power2 >= 0));
734
735                 if (info->tx_power2 < 0)
736                         info->tx_power2 += 7;
737
738                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
739                                    TXPOWER_A_TO_DEV(info->tx_power2));
740         } else {
741                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
742                                    TXPOWER_G_TO_DEV(info->tx_power1));
743                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
744                                    TXPOWER_G_TO_DEV(info->tx_power2));
745         }
746
747         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
748
749         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
750         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
751         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
752         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
753
754         udelay(200);
755
756         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
757         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
758         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
759         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
760
761         udelay(200);
762
763         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
764         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
765         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
766         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
767 }
768
769 static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
770                                        struct ieee80211_conf *conf,
771                                        struct rf_channel *rf,
772                                        struct channel_info *info)
773 {
774         u8 rfcsr;
775
776         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
777         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
778
779         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
780         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
781         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
782
783         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
784         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
785                           TXPOWER_G_TO_DEV(info->tx_power1));
786         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
787
788         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
789         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
790         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
791
792         rt2800_rfcsr_write(rt2x00dev, 24,
793                               rt2x00dev->calibration[conf_is_ht40(conf)]);
794
795         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
796         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
797         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
798 }
799
800 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
801                                   struct ieee80211_conf *conf,
802                                   struct rf_channel *rf,
803                                   struct channel_info *info)
804 {
805         u32 reg;
806         unsigned int tx_pin;
807         u8 bbp;
808
809         if ((rt2x00_rt(&rt2x00dev->chip, RT3070) ||
810              rt2x00_rt(&rt2x00dev->chip, RT3090)) &&
811             (rt2x00_rf(&rt2x00dev->chip, RF2020) ||
812              rt2x00_rf(&rt2x00dev->chip, RF3020) ||
813              rt2x00_rf(&rt2x00dev->chip, RF3021) ||
814              rt2x00_rf(&rt2x00dev->chip, RF3022)))
815                 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
816         else
817                 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info);
818
819         /*
820          * Change BBP settings
821          */
822         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
823         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
824         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
825         rt2800_bbp_write(rt2x00dev, 86, 0);
826
827         if (rf->channel <= 14) {
828                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
829                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
830                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
831                 } else {
832                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
833                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
834                 }
835         } else {
836                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
837
838                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
839                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
840                 else
841                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
842         }
843
844         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
845         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
846         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
847         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
848         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
849
850         tx_pin = 0;
851
852         /* Turn on unused PA or LNA when not using 1T or 1R */
853         if (rt2x00dev->default_ant.tx != 1) {
854                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
855                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
856         }
857
858         /* Turn on unused PA or LNA when not using 1T or 1R */
859         if (rt2x00dev->default_ant.rx != 1) {
860                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
861                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
862         }
863
864         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
865         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
866         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
867         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
868         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
869         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
870
871         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
872
873         rt2800_bbp_read(rt2x00dev, 4, &bbp);
874         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
875         rt2800_bbp_write(rt2x00dev, 4, bbp);
876
877         rt2800_bbp_read(rt2x00dev, 3, &bbp);
878         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
879         rt2800_bbp_write(rt2x00dev, 3, bbp);
880
881         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
882                 if (conf_is_ht40(conf)) {
883                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
884                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
885                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
886                 } else {
887                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
888                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
889                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
890                 }
891         }
892
893         msleep(1);
894 }
895
896 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
897                                   const int txpower)
898 {
899         u32 reg;
900         u32 value = TXPOWER_G_TO_DEV(txpower);
901         u8 r1;
902
903         rt2800_bbp_read(rt2x00dev, 1, &r1);
904         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
905         rt2800_bbp_write(rt2x00dev, 1, r1);
906
907         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
908         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
909         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
910         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
911         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
912         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
913         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
914         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
915         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
916         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
917
918         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
919         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
920         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
921         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
922         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
923         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
924         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
925         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
926         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
927         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
928
929         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
930         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
931         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
932         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
933         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
934         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
935         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
936         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
937         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
938         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
939
940         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
941         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
942         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
943         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
944         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
945         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
946         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
947         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
948         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
949         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
950
951         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
952         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
953         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
954         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
955         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
956         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
957 }
958
959 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
960                                       struct rt2x00lib_conf *libconf)
961 {
962         u32 reg;
963
964         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
965         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
966                            libconf->conf->short_frame_max_tx_count);
967         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
968                            libconf->conf->long_frame_max_tx_count);
969         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
970         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
971         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
972         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
973         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
974 }
975
976 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
977                              struct rt2x00lib_conf *libconf)
978 {
979         enum dev_state state =
980             (libconf->conf->flags & IEEE80211_CONF_PS) ?
981                 STATE_SLEEP : STATE_AWAKE;
982         u32 reg;
983
984         if (state == STATE_SLEEP) {
985                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
986
987                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
988                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
989                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
990                                    libconf->conf->listen_interval - 1);
991                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
992                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
993
994                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
995         } else {
996                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
997
998                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
999                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1000                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1001                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1002                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1003         }
1004 }
1005
1006 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1007                    struct rt2x00lib_conf *libconf,
1008                    const unsigned int flags)
1009 {
1010         /* Always recalculate LNA gain before changing configuration */
1011         rt2800_config_lna_gain(rt2x00dev, libconf);
1012
1013         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1014                 rt2800_config_channel(rt2x00dev, libconf->conf,
1015                                       &libconf->rf, &libconf->channel);
1016         if (flags & IEEE80211_CONF_CHANGE_POWER)
1017                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1018         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1019                 rt2800_config_retry_limit(rt2x00dev, libconf);
1020         if (flags & IEEE80211_CONF_CHANGE_PS)
1021                 rt2800_config_ps(rt2x00dev, libconf);
1022 }
1023 EXPORT_SYMBOL_GPL(rt2800_config);
1024
1025 /*
1026  * Link tuning
1027  */
1028 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1029 {
1030         u32 reg;
1031
1032         /*
1033          * Update FCS error count from register.
1034          */
1035         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1036         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1037 }
1038 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1039
1040 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1041 {
1042         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1043                 if (rt2x00_intf_is_usb(rt2x00dev) &&
1044                     rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1045                         return 0x1c + (2 * rt2x00dev->lna_gain);
1046                 else
1047                         return 0x2e + rt2x00dev->lna_gain;
1048         }
1049
1050         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1051                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1052         else
1053                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1054 }
1055
1056 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1057                                   struct link_qual *qual, u8 vgc_level)
1058 {
1059         if (qual->vgc_level != vgc_level) {
1060                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1061                 qual->vgc_level = vgc_level;
1062                 qual->vgc_level_reg = vgc_level;
1063         }
1064 }
1065
1066 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1067 {
1068         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1069 }
1070 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1071
1072 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1073                        const u32 count)
1074 {
1075         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1076                 return;
1077
1078         /*
1079          * When RSSI is better then -80 increase VGC level with 0x10
1080          */
1081         rt2800_set_vgc(rt2x00dev, qual,
1082                        rt2800_get_default_vgc(rt2x00dev) +
1083                        ((qual->rssi > -80) * 0x10));
1084 }
1085 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1086
1087 /*
1088  * Initialization functions.
1089  */
1090 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1091 {
1092         u32 reg;
1093         unsigned int i;
1094
1095         if (rt2x00_intf_is_usb(rt2x00dev)) {
1096                 /*
1097                  * Wait until BBP and RF are ready.
1098                  */
1099                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1100                         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1101                         if (reg && reg != ~0)
1102                                 break;
1103                         msleep(1);
1104                 }
1105
1106                 if (i == REGISTER_BUSY_COUNT) {
1107                         ERROR(rt2x00dev, "Unstable hardware.\n");
1108                         return -EBUSY;
1109                 }
1110
1111                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1112                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1113                                       reg & ~0x00002000);
1114         } else if (rt2x00_intf_is_pci(rt2x00dev))
1115                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1116
1117         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1118         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1119         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1120         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1121
1122         if (rt2x00_intf_is_usb(rt2x00dev)) {
1123                 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1124 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1125                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1126                                             USB_MODE_RESET, REGISTER_TIMEOUT);
1127 #endif
1128         }
1129
1130         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1131
1132         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1133         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1134         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1135         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1136         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1137         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1138
1139         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1140         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1141         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1142         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1143         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1144         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1145
1146         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1147         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1148
1149         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1150
1151         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1152         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1153         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1154         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1155         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1156         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1157         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1158         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1159
1160         if (rt2x00_intf_is_usb(rt2x00dev) &&
1161             rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1162                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1163                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1164                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1165         } else {
1166                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1167                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1168         }
1169
1170         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1171         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1172         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1173         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1174         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1175         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1176         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1177         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1178         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1179         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1180
1181         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1182         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1183         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1184         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1185
1186         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1187         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1188         if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1189             rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1190                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1191         else
1192                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1193         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1194         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1195         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1196
1197         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1198
1199         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1200         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1201         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1202         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1203         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1204         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1205         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1206
1207         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1208         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1209         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1210         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1211         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1212         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1213         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1214         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1215         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1216         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1217         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1218
1219         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1220         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1221         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1222         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1223         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1224         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1225         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1226         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1227         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1228         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1229         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1230
1231         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1232         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1233         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1234         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1235         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1236         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1237         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1238         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1239         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1240         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1241         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1242
1243         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1244         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1245         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1246         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1247         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1248         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1249         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1250         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1251         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1252         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1253         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1254
1255         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1256         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1257         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1258         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1259         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1260         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1261         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1262         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1263         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1264         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1265         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1266
1267         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1268         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1269         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1270         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1271         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1272         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1273         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1274         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1275         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1276         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1277         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1278
1279         if (rt2x00_intf_is_usb(rt2x00dev)) {
1280                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1281
1282                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1283                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1284                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1285                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1286                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1287                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1288                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1289                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1290                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1291                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1292                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1293         }
1294
1295         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1296         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1297
1298         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1299         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1300         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1301                            IEEE80211_MAX_RTS_THRESHOLD);
1302         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1303         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1304
1305         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1306         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1307
1308         /*
1309          * ASIC will keep garbage value after boot, clear encryption keys.
1310          */
1311         for (i = 0; i < 4; i++)
1312                 rt2800_register_write(rt2x00dev,
1313                                          SHARED_KEY_MODE_ENTRY(i), 0);
1314
1315         for (i = 0; i < 256; i++) {
1316                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1317                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1318                                               wcid, sizeof(wcid));
1319
1320                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1321                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1322         }
1323
1324         /*
1325          * Clear all beacons
1326          * For the Beacon base registers we only need to clear
1327          * the first byte since that byte contains the VALID and OWNER
1328          * bits which (when set to 0) will invalidate the entire beacon.
1329          */
1330         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1331         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1332         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1333         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1334         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1335         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1336         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1337         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1338
1339         if (rt2x00_intf_is_usb(rt2x00dev)) {
1340                 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1341                 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1342                 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1343         }
1344
1345         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1346         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1347         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1348         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1349         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1350         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1351         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1352         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1353         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1354         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1355
1356         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1357         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1358         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1359         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1360         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1361         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1362         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1363         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1364         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1365         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1366
1367         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1368         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1369         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1370         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1371         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1372         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1373         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1374         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1375         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1376         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1377
1378         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1379         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1380         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1381         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1382         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1383         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1384
1385         /*
1386          * We must clear the error counters.
1387          * These registers are cleared on read,
1388          * so we may pass a useless variable to store the value.
1389          */
1390         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1391         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1392         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1393         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1394         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1395         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1396
1397         return 0;
1398 }
1399 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1400
1401 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1402 {
1403         unsigned int i;
1404         u32 reg;
1405
1406         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1407                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1408                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1409                         return 0;
1410
1411                 udelay(REGISTER_BUSY_DELAY);
1412         }
1413
1414         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1415         return -EACCES;
1416 }
1417
1418 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1419 {
1420         unsigned int i;
1421         u8 value;
1422
1423         /*
1424          * BBP was enabled after firmware was loaded,
1425          * but we need to reactivate it now.
1426          */
1427         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1428         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1429         msleep(1);
1430
1431         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1432                 rt2800_bbp_read(rt2x00dev, 0, &value);
1433                 if ((value != 0xff) && (value != 0x00))
1434                         return 0;
1435                 udelay(REGISTER_BUSY_DELAY);
1436         }
1437
1438         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1439         return -EACCES;
1440 }
1441
1442 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1443 {
1444         unsigned int i;
1445         u16 eeprom;
1446         u8 reg_id;
1447         u8 value;
1448
1449         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1450                      rt2800_wait_bbp_ready(rt2x00dev)))
1451                 return -EACCES;
1452
1453         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1454         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1455         rt2800_bbp_write(rt2x00dev, 69, 0x12);
1456         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1457         rt2800_bbp_write(rt2x00dev, 73, 0x10);
1458         rt2800_bbp_write(rt2x00dev, 81, 0x37);
1459         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1460         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1461         rt2800_bbp_write(rt2x00dev, 84, 0x99);
1462         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1463         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1464         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1465         rt2800_bbp_write(rt2x00dev, 103, 0x00);
1466         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1467
1468         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1469                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1470                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1471         }
1472
1473         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1474                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1475
1476         if (rt2x00_intf_is_usb(rt2x00dev) &&
1477             rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1478                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1479                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1480                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1481         }
1482
1483         if (rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1484                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1485                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1486                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1487         }
1488
1489         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1490                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1491
1492                 if (eeprom != 0xffff && eeprom != 0x0000) {
1493                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1494                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1495                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1496                 }
1497         }
1498
1499         return 0;
1500 }
1501 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1502
1503 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1504                                 bool bw40, u8 rfcsr24, u8 filter_target)
1505 {
1506         unsigned int i;
1507         u8 bbp;
1508         u8 rfcsr;
1509         u8 passband;
1510         u8 stopband;
1511         u8 overtuned = 0;
1512
1513         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1514
1515         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1516         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1517         rt2800_bbp_write(rt2x00dev, 4, bbp);
1518
1519         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1520         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1521         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1522
1523         /*
1524          * Set power & frequency of passband test tone
1525          */
1526         rt2800_bbp_write(rt2x00dev, 24, 0);
1527
1528         for (i = 0; i < 100; i++) {
1529                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1530                 msleep(1);
1531
1532                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1533                 if (passband)
1534                         break;
1535         }
1536
1537         /*
1538          * Set power & frequency of stopband test tone
1539          */
1540         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1541
1542         for (i = 0; i < 100; i++) {
1543                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1544                 msleep(1);
1545
1546                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1547
1548                 if ((passband - stopband) <= filter_target) {
1549                         rfcsr24++;
1550                         overtuned += ((passband - stopband) == filter_target);
1551                 } else
1552                         break;
1553
1554                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1555         }
1556
1557         rfcsr24 -= !!overtuned;
1558
1559         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1560         return rfcsr24;
1561 }
1562
1563 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1564 {
1565         u8 rfcsr;
1566         u8 bbp;
1567
1568         if (rt2x00_intf_is_usb(rt2x00dev) &&
1569             rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1570                 return 0;
1571
1572         if (rt2x00_intf_is_pci(rt2x00dev)) {
1573                 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1574                     !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1575                     !rt2x00_rf(&rt2x00dev->chip, RF3022))
1576                         return 0;
1577         }
1578
1579         /*
1580          * Init RF calibration.
1581          */
1582         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1583         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1584         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1585         msleep(1);
1586         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1587         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1588
1589         if (rt2x00_intf_is_usb(rt2x00dev)) {
1590                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1591                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1592                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1593                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1594                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1595                 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1596                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1597                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1598                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1599                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1600                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1601                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1602                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1603                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1604                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1605                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1606                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1607                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1608                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1609                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1610         } else if (rt2x00_intf_is_pci(rt2x00dev)) {
1611                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1612                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1613                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1614                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1615                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1616                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1617                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1618                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1619                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1620                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1621                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1622                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1623                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1624                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1625                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1626                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1627                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1628                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1629                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1630                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1631                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1632                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1633                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1634                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1635                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1636                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1637                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1638                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1639                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1640                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1641         }
1642
1643         /*
1644          * Set RX Filter calibration for 20MHz and 40MHz
1645          */
1646         rt2x00dev->calibration[0] =
1647             rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1648         rt2x00dev->calibration[1] =
1649             rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1650
1651         /*
1652          * Set back to initial state
1653          */
1654         rt2800_bbp_write(rt2x00dev, 24, 0);
1655
1656         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1657         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1658         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1659
1660         /*
1661          * set BBP back to BW20
1662          */
1663         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1664         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1665         rt2800_bbp_write(rt2x00dev, 4, bbp);
1666
1667         return 0;
1668 }
1669 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1670
1671 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1672 {
1673         u32 reg;
1674
1675         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1676
1677         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1678 }
1679 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1680
1681 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1682 {
1683         u32 reg;
1684
1685         mutex_lock(&rt2x00dev->csr_mutex);
1686
1687         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
1688         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1689         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1690         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
1691         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
1692
1693         /* Wait until the EEPROM has been loaded */
1694         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
1695
1696         /* Apparently the data is read from end to start */
1697         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
1698                                         (u32 *)&rt2x00dev->eeprom[i]);
1699         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
1700                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
1701         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
1702                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
1703         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
1704                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
1705
1706         mutex_unlock(&rt2x00dev->csr_mutex);
1707 }
1708
1709 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
1710 {
1711         unsigned int i;
1712
1713         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
1714                 rt2800_efuse_read(rt2x00dev, i);
1715 }
1716 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
1717
1718 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1719 {
1720         u16 word;
1721         u8 *mac;
1722         u8 default_lna_gain;
1723
1724         /*
1725          * Start validation of the data that has been read.
1726          */
1727         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1728         if (!is_valid_ether_addr(mac)) {
1729                 random_ether_addr(mac);
1730                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1731         }
1732
1733         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1734         if (word == 0xffff) {
1735                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1736                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1737                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1738                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1739                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1740         } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
1741                 /*
1742                  * There is a max of 2 RX streams for RT28x0 series
1743                  */
1744                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1745                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1746                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1747         }
1748
1749         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1750         if (word == 0xffff) {
1751                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
1752                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
1753                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1754                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1755                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1756                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
1757                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
1758                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
1759                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
1760                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
1761                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1762                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1763         }
1764
1765         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1766         if ((word & 0x00ff) == 0x00ff) {
1767                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1768                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1769                                    LED_MODE_TXRX_ACTIVITY);
1770                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1771                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1772                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1773                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1774                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1775                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1776         }
1777
1778         /*
1779          * During the LNA validation we are going to use
1780          * lna0 as correct value. Note that EEPROM_LNA
1781          * is never validated.
1782          */
1783         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1784         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1785
1786         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1787         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1788                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1789         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1790                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1791         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1792
1793         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1794         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1795                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1796         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1797             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1798                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1799                                    default_lna_gain);
1800         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1801
1802         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1803         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1804                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1805         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1806                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1807         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1808
1809         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1810         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1811                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1812         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1813             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1814                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1815                                    default_lna_gain);
1816         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1817
1818         return 0;
1819 }
1820 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
1821
1822 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1823 {
1824         u32 reg;
1825         u16 value;
1826         u16 eeprom;
1827
1828         /*
1829          * Read EEPROM word for configuration.
1830          */
1831         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1832
1833         /*
1834          * Identify RF chipset.
1835          */
1836         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1837         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1838
1839         rt2x00_set_chip_rf(rt2x00dev, value, reg);
1840
1841         if (rt2x00_intf_is_usb(rt2x00dev)) {
1842                 struct rt2x00_chip *chip = &rt2x00dev->chip;
1843
1844                 /*
1845                  * The check for rt2860 is not a typo, some rt2870 hardware
1846                  * identifies itself as rt2860 in the CSR register.
1847                  */
1848                 if (rt2x00_check_rev(chip, 0xfff00000, 0x28600000) ||
1849                     rt2x00_check_rev(chip, 0xfff00000, 0x28700000) ||
1850                     rt2x00_check_rev(chip, 0xfff00000, 0x28800000)) {
1851                         rt2x00_set_chip_rt(rt2x00dev, RT2870);
1852                 } else if (rt2x00_check_rev(chip, 0xffff0000, 0x30700000)) {
1853                         rt2x00_set_chip_rt(rt2x00dev, RT3070);
1854                 } else {
1855                         ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1856                         return -ENODEV;
1857                 }
1858         }
1859         rt2x00_print_chip(rt2x00dev);
1860
1861         if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
1862             !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
1863             !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
1864             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
1865             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1866             !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
1867             !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1868             !rt2x00_rf(&rt2x00dev->chip, RF3022)) {
1869                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1870                 return -ENODEV;
1871         }
1872
1873         /*
1874          * Identify default antenna configuration.
1875          */
1876         rt2x00dev->default_ant.tx =
1877             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
1878         rt2x00dev->default_ant.rx =
1879             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
1880
1881         /*
1882          * Read frequency offset and RF programming sequence.
1883          */
1884         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1885         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1886
1887         /*
1888          * Read external LNA informations.
1889          */
1890         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1891
1892         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1893                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1894         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1895                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1896
1897         /*
1898          * Detect if this device has an hardware controlled radio.
1899          */
1900         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
1901                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1902
1903         /*
1904          * Store led settings, for correct led behaviour.
1905          */
1906 #ifdef CONFIG_RT2X00_LIB_LEDS
1907         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1908         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1909         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
1910
1911         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
1912 #endif /* CONFIG_RT2X00_LIB_LEDS */
1913
1914         return 0;
1915 }
1916 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
1917
1918 /*
1919  * RF value list for rt28x0
1920  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1921  */
1922 static const struct rf_channel rf_vals[] = {
1923         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1924         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1925         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1926         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1927         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1928         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1929         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1930         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1931         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1932         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1933         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1934         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1935         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1936         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1937
1938         /* 802.11 UNI / HyperLan 2 */
1939         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1940         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1941         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1942         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1943         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1944         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1945         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1946         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1947         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1948         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1949         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1950         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1951
1952         /* 802.11 HyperLan 2 */
1953         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1954         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1955         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1956         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1957         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1958         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1959         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1960         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1961         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
1962         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
1963         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
1964         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
1965         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
1966         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
1967         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
1968         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
1969
1970         /* 802.11 UNII */
1971         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
1972         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
1973         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
1974         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
1975         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
1976         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
1977         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
1978         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
1979         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
1980         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
1981         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
1982
1983         /* 802.11 Japan */
1984         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
1985         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
1986         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
1987         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
1988         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
1989         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
1990         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
1991 };
1992
1993 /*
1994  * RF value list for rt3070
1995  * Supports: 2.4 GHz
1996  */
1997 static const struct rf_channel rf_vals_302x[] = {
1998         {1,  241, 2, 2 },
1999         {2,  241, 2, 7 },
2000         {3,  242, 2, 2 },
2001         {4,  242, 2, 7 },
2002         {5,  243, 2, 2 },
2003         {6,  243, 2, 7 },
2004         {7,  244, 2, 2 },
2005         {8,  244, 2, 7 },
2006         {9,  245, 2, 2 },
2007         {10, 245, 2, 7 },
2008         {11, 246, 2, 2 },
2009         {12, 246, 2, 7 },
2010         {13, 247, 2, 2 },
2011         {14, 248, 2, 4 },
2012 };
2013
2014 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2015 {
2016         struct rt2x00_chip *chip = &rt2x00dev->chip;
2017         struct hw_mode_spec *spec = &rt2x00dev->spec;
2018         struct channel_info *info;
2019         char *tx_power1;
2020         char *tx_power2;
2021         unsigned int i;
2022         u16 eeprom;
2023
2024         /*
2025          * Disable powersaving as default on PCI devices.
2026          */
2027         if (rt2x00_intf_is_pci(rt2x00dev))
2028                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2029
2030         /*
2031          * Initialize all hw fields.
2032          */
2033         rt2x00dev->hw->flags =
2034             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2035             IEEE80211_HW_SIGNAL_DBM |
2036             IEEE80211_HW_SUPPORTS_PS |
2037             IEEE80211_HW_PS_NULLFUNC_STACK;
2038
2039         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2040         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2041                                 rt2x00_eeprom_addr(rt2x00dev,
2042                                                    EEPROM_MAC_ADDR_0));
2043
2044         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2045
2046         /*
2047          * Initialize hw_mode information.
2048          */
2049         spec->supported_bands = SUPPORT_BAND_2GHZ;
2050         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2051
2052         if (rt2x00_rf(chip, RF2820) ||
2053             rt2x00_rf(chip, RF2720) ||
2054             (rt2x00_intf_is_pci(rt2x00dev) && rt2x00_rf(chip, RF3052))) {
2055                 spec->num_channels = 14;
2056                 spec->channels = rf_vals;
2057         } else if (rt2x00_rf(chip, RF2850) || rt2x00_rf(chip, RF2750)) {
2058                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2059                 spec->num_channels = ARRAY_SIZE(rf_vals);
2060                 spec->channels = rf_vals;
2061         } else if (rt2x00_rf(chip, RF3020) ||
2062                    rt2x00_rf(chip, RF2020) ||
2063                    rt2x00_rf(chip, RF3021) ||
2064                    rt2x00_rf(chip, RF3022)) {
2065                 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2066                 spec->channels = rf_vals_302x;
2067         }
2068
2069         /*
2070          * Initialize HT information.
2071          */
2072         if (!rt2x00_rf(chip, RF2020))
2073                 spec->ht.ht_supported = true;
2074         else
2075                 spec->ht.ht_supported = false;
2076
2077         spec->ht.cap =
2078             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2079             IEEE80211_HT_CAP_GRN_FLD |
2080             IEEE80211_HT_CAP_SGI_20 |
2081             IEEE80211_HT_CAP_SGI_40 |
2082             IEEE80211_HT_CAP_TX_STBC |
2083             IEEE80211_HT_CAP_RX_STBC;
2084         spec->ht.ampdu_factor = 3;
2085         spec->ht.ampdu_density = 4;
2086         spec->ht.mcs.tx_params =
2087             IEEE80211_HT_MCS_TX_DEFINED |
2088             IEEE80211_HT_MCS_TX_RX_DIFF |
2089             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2090                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2091
2092         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2093         case 3:
2094                 spec->ht.mcs.rx_mask[2] = 0xff;
2095         case 2:
2096                 spec->ht.mcs.rx_mask[1] = 0xff;
2097         case 1:
2098                 spec->ht.mcs.rx_mask[0] = 0xff;
2099                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2100                 break;
2101         }
2102
2103         /*
2104          * Create channel information array
2105          */
2106         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2107         if (!info)
2108                 return -ENOMEM;
2109
2110         spec->channels_info = info;
2111
2112         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2113         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2114
2115         for (i = 0; i < 14; i++) {
2116                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2117                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2118         }
2119
2120         if (spec->num_channels > 14) {
2121                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2122                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2123
2124                 for (i = 14; i < spec->num_channels; i++) {
2125                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2126                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2127                 }
2128         }
2129
2130         return 0;
2131 }
2132 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2133
2134 /*
2135  * IEEE80211 stack callback functions.
2136  */
2137 static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2138                                 u32 *iv32, u16 *iv16)
2139 {
2140         struct rt2x00_dev *rt2x00dev = hw->priv;
2141         struct mac_iveiv_entry iveiv_entry;
2142         u32 offset;
2143
2144         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2145         rt2800_register_multiread(rt2x00dev, offset,
2146                                       &iveiv_entry, sizeof(iveiv_entry));
2147
2148         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2149         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2150 }
2151
2152 static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2153 {
2154         struct rt2x00_dev *rt2x00dev = hw->priv;
2155         u32 reg;
2156         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2157
2158         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2159         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2160         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2161
2162         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2163         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2164         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2165
2166         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2167         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2168         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2169
2170         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2171         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2172         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2173
2174         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2175         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2176         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2177
2178         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2179         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2180         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2181
2182         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2183         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2184         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2185
2186         return 0;
2187 }
2188
2189 static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2190                           const struct ieee80211_tx_queue_params *params)
2191 {
2192         struct rt2x00_dev *rt2x00dev = hw->priv;
2193         struct data_queue *queue;
2194         struct rt2x00_field32 field;
2195         int retval;
2196         u32 reg;
2197         u32 offset;
2198
2199         /*
2200          * First pass the configuration through rt2x00lib, that will
2201          * update the queue settings and validate the input. After that
2202          * we are free to update the registers based on the value
2203          * in the queue parameter.
2204          */
2205         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2206         if (retval)
2207                 return retval;
2208
2209         /*
2210          * We only need to perform additional register initialization
2211          * for WMM queues/
2212          */
2213         if (queue_idx >= 4)
2214                 return 0;
2215
2216         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2217
2218         /* Update WMM TXOP register */
2219         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2220         field.bit_offset = (queue_idx & 1) * 16;
2221         field.bit_mask = 0xffff << field.bit_offset;
2222
2223         rt2800_register_read(rt2x00dev, offset, &reg);
2224         rt2x00_set_field32(&reg, field, queue->txop);
2225         rt2800_register_write(rt2x00dev, offset, reg);
2226
2227         /* Update WMM registers */
2228         field.bit_offset = queue_idx * 4;
2229         field.bit_mask = 0xf << field.bit_offset;
2230
2231         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2232         rt2x00_set_field32(&reg, field, queue->aifs);
2233         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2234
2235         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2236         rt2x00_set_field32(&reg, field, queue->cw_min);
2237         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2238
2239         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2240         rt2x00_set_field32(&reg, field, queue->cw_max);
2241         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2242
2243         /* Update EDCA registers */
2244         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2245
2246         rt2800_register_read(rt2x00dev, offset, &reg);
2247         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2248         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2249         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2250         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2251         rt2800_register_write(rt2x00dev, offset, reg);
2252
2253         return 0;
2254 }
2255
2256 static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2257 {
2258         struct rt2x00_dev *rt2x00dev = hw->priv;
2259         u64 tsf;
2260         u32 reg;
2261
2262         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2263         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2264         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2265         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2266
2267         return tsf;
2268 }
2269
2270 const struct ieee80211_ops rt2800_mac80211_ops = {
2271         .tx                     = rt2x00mac_tx,
2272         .start                  = rt2x00mac_start,
2273         .stop                   = rt2x00mac_stop,
2274         .add_interface          = rt2x00mac_add_interface,
2275         .remove_interface       = rt2x00mac_remove_interface,
2276         .config                 = rt2x00mac_config,
2277         .configure_filter       = rt2x00mac_configure_filter,
2278         .set_tim                = rt2x00mac_set_tim,
2279         .set_key                = rt2x00mac_set_key,
2280         .get_stats              = rt2x00mac_get_stats,
2281         .get_tkip_seq           = rt2800_get_tkip_seq,
2282         .set_rts_threshold      = rt2800_set_rts_threshold,
2283         .bss_info_changed       = rt2x00mac_bss_info_changed,
2284         .conf_tx                = rt2800_conf_tx,
2285         .get_tx_stats           = rt2x00mac_get_tx_stats,
2286         .get_tsf                = rt2800_get_tsf,
2287         .rfkill_poll            = rt2x00mac_rfkill_poll,
2288 };
2289 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);