qla3xxx: bugfix: Fix VLAN rx completion handling.
[linux-2.6.git] / drivers / net / qla3xxx.c
1 /*
2  * QLogic QLA3xxx NIC HBA Driver
3  * Copyright (c)  2003-2006 QLogic Corporation
4  *
5  * See LICENSE.qla3xxx for copyright and licensing details.
6  */
7
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/dmapool.h>
18 #include <linux/mempool.h>
19 #include <linux/spinlock.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/ip.h>
25 #include <linux/in.h>
26 #include <linux/if_arp.h>
27 #include <linux/if_ether.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/skbuff.h>
32 #include <linux/rtnetlink.h>
33 #include <linux/if_vlan.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
36 #include <linux/mm.h>
37
38 #include "qla3xxx.h"
39
40 #define DRV_NAME        "qla3xxx"
41 #define DRV_STRING      "QLogic ISP3XXX Network Driver"
42 #define DRV_VERSION     "v2.03.00-k4"
43 #define PFX             DRV_NAME " "
44
45 static const char ql3xxx_driver_name[] = DRV_NAME;
46 static const char ql3xxx_driver_version[] = DRV_VERSION;
47
48 MODULE_AUTHOR("QLogic Corporation");
49 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
50 MODULE_LICENSE("GPL");
51 MODULE_VERSION(DRV_VERSION);
52
53 static const u32 default_msg
54     = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
55     | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
56
57 static int debug = -1;          /* defaults above */
58 module_param(debug, int, 0);
59 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
60
61 static int msi;
62 module_param(msi, int, 0);
63 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
64
65 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
66         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
67         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
68         /* required last entry */
69         {0,}
70 };
71
72 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
73
74 /*
75  *  These are the known PHY's which are used
76  */
77 typedef enum {
78    PHY_TYPE_UNKNOWN   = 0,
79    PHY_VITESSE_VSC8211,
80    PHY_AGERE_ET1011C,
81    MAX_PHY_DEV_TYPES
82 } PHY_DEVICE_et;
83
84 typedef struct {
85         PHY_DEVICE_et phyDevice; 
86         u32             phyIdOUI;
87         u16             phyIdModel;
88         char            *name;
89 } PHY_DEVICE_INFO_t;
90
91 static const PHY_DEVICE_INFO_t PHY_DEVICES[] =
92         {{PHY_TYPE_UNKNOWN,    0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
93          {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
94          {PHY_AGERE_ET1011C,   0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
95 };
96
97
98 /*
99  * Caller must take hw_lock.
100  */
101 static int ql_sem_spinlock(struct ql3_adapter *qdev,
102                             u32 sem_mask, u32 sem_bits)
103 {
104         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
105         u32 value;
106         unsigned int seconds = 3;
107
108         do {
109                 writel((sem_mask | sem_bits),
110                        &port_regs->CommonRegs.semaphoreReg);
111                 value = readl(&port_regs->CommonRegs.semaphoreReg);
112                 if ((value & (sem_mask >> 16)) == sem_bits)
113                         return 0;
114                 ssleep(1);
115         } while(--seconds);
116         return -1;
117 }
118
119 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
120 {
121         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
122         writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
123         readl(&port_regs->CommonRegs.semaphoreReg);
124 }
125
126 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
127 {
128         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
129         u32 value;
130
131         writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
132         value = readl(&port_regs->CommonRegs.semaphoreReg);
133         return ((value & (sem_mask >> 16)) == sem_bits);
134 }
135
136 /*
137  * Caller holds hw_lock.
138  */
139 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
140 {
141         int i = 0;
142
143         while (1) {
144                 if (!ql_sem_lock(qdev,
145                                  QL_DRVR_SEM_MASK,
146                                  (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
147                                   * 2) << 1)) {
148                         if (i < 10) {
149                                 ssleep(1);
150                                 i++;
151                         } else {
152                                 printk(KERN_ERR PFX "%s: Timed out waiting for "
153                                        "driver lock...\n",
154                                        qdev->ndev->name);
155                                 return 0;
156                         }
157                 } else {
158                         printk(KERN_DEBUG PFX
159                                "%s: driver lock acquired.\n",
160                                qdev->ndev->name);
161                         return 1;
162                 }
163         }
164 }
165
166 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
167 {
168         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
169
170         writel(((ISP_CONTROL_NP_MASK << 16) | page),
171                         &port_regs->CommonRegs.ispControlStatus);
172         readl(&port_regs->CommonRegs.ispControlStatus);
173         qdev->current_page = page;
174 }
175
176 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
177                               u32 __iomem * reg)
178 {
179         u32 value;
180         unsigned long hw_flags;
181
182         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
183         value = readl(reg);
184         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
185
186         return value;
187 }
188
189 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
190                               u32 __iomem * reg)
191 {
192         return readl(reg);
193 }
194
195 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
196 {
197         u32 value;
198         unsigned long hw_flags;
199
200         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
201
202         if (qdev->current_page != 0)
203                 ql_set_register_page(qdev,0);
204         value = readl(reg);
205
206         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
207         return value;
208 }
209
210 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
211 {
212         if (qdev->current_page != 0)
213                 ql_set_register_page(qdev,0);
214         return readl(reg);
215 }
216
217 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
218                                 u32 __iomem *reg, u32 value)
219 {
220         unsigned long hw_flags;
221
222         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
223         writel(value, reg);
224         readl(reg);
225         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
226         return;
227 }
228
229 static void ql_write_common_reg(struct ql3_adapter *qdev,
230                                 u32 __iomem *reg, u32 value)
231 {
232         writel(value, reg);
233         readl(reg);
234         return;
235 }
236
237 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
238                                 u32 __iomem *reg, u32 value)
239 {
240         writel(value, reg);
241         readl(reg);
242         udelay(1);
243         return;
244 }
245
246 static void ql_write_page0_reg(struct ql3_adapter *qdev,
247                                u32 __iomem *reg, u32 value)
248 {
249         if (qdev->current_page != 0)
250                 ql_set_register_page(qdev,0);
251         writel(value, reg);
252         readl(reg);
253         return;
254 }
255
256 /*
257  * Caller holds hw_lock. Only called during init.
258  */
259 static void ql_write_page1_reg(struct ql3_adapter *qdev,
260                                u32 __iomem *reg, u32 value)
261 {
262         if (qdev->current_page != 1)
263                 ql_set_register_page(qdev,1);
264         writel(value, reg);
265         readl(reg);
266         return;
267 }
268
269 /*
270  * Caller holds hw_lock. Only called during init.
271  */
272 static void ql_write_page2_reg(struct ql3_adapter *qdev,
273                                u32 __iomem *reg, u32 value)
274 {
275         if (qdev->current_page != 2)
276                 ql_set_register_page(qdev,2);
277         writel(value, reg);
278         readl(reg);
279         return;
280 }
281
282 static void ql_disable_interrupts(struct ql3_adapter *qdev)
283 {
284         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
285
286         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
287                             (ISP_IMR_ENABLE_INT << 16));
288
289 }
290
291 static void ql_enable_interrupts(struct ql3_adapter *qdev)
292 {
293         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
294
295         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
296                             ((0xff << 16) | ISP_IMR_ENABLE_INT));
297
298 }
299
300 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
301                                             struct ql_rcv_buf_cb *lrg_buf_cb)
302 {
303         dma_addr_t map;
304         int err;
305         lrg_buf_cb->next = NULL;
306
307         if (qdev->lrg_buf_free_tail == NULL) {  /* The list is empty  */
308                 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
309         } else {
310                 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
311                 qdev->lrg_buf_free_tail = lrg_buf_cb;
312         }
313
314         if (!lrg_buf_cb->skb) {
315                 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
316                                                    qdev->lrg_buffer_len);
317                 if (unlikely(!lrg_buf_cb->skb)) {
318                         printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
319                                qdev->ndev->name);
320                         qdev->lrg_buf_skb_check++;
321                 } else {
322                         /*
323                          * We save some space to copy the ethhdr from first
324                          * buffer
325                          */
326                         skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
327                         map = pci_map_single(qdev->pdev,
328                                              lrg_buf_cb->skb->data,
329                                              qdev->lrg_buffer_len -
330                                              QL_HEADER_SPACE,
331                                              PCI_DMA_FROMDEVICE);
332                         err = pci_dma_mapping_error(map);
333                         if(err) {
334                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n", 
335                                        qdev->ndev->name, err);
336                                 dev_kfree_skb(lrg_buf_cb->skb);
337                                 lrg_buf_cb->skb = NULL;
338
339                                 qdev->lrg_buf_skb_check++;
340                                 return;
341                         }
342
343                         lrg_buf_cb->buf_phy_addr_low =
344                             cpu_to_le32(LS_64BITS(map));
345                         lrg_buf_cb->buf_phy_addr_high =
346                             cpu_to_le32(MS_64BITS(map));
347                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
348                         pci_unmap_len_set(lrg_buf_cb, maplen,
349                                           qdev->lrg_buffer_len -
350                                           QL_HEADER_SPACE);
351                 }
352         }
353
354         qdev->lrg_buf_free_count++;
355 }
356
357 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
358                                                            *qdev)
359 {
360         struct ql_rcv_buf_cb *lrg_buf_cb;
361
362         if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
363                 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
364                         qdev->lrg_buf_free_tail = NULL;
365                 qdev->lrg_buf_free_count--;
366         }
367
368         return lrg_buf_cb;
369 }
370
371 static u32 addrBits = EEPROM_NO_ADDR_BITS;
372 static u32 dataBits = EEPROM_NO_DATA_BITS;
373
374 static void fm93c56a_deselect(struct ql3_adapter *qdev);
375 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
376                             unsigned short *value);
377
378 /*
379  * Caller holds hw_lock.
380  */
381 static void fm93c56a_select(struct ql3_adapter *qdev)
382 {
383         struct ql3xxx_port_registers __iomem *port_regs =
384                         qdev->mem_map_registers;
385
386         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
387         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
388                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
389         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
390                             ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
391 }
392
393 /*
394  * Caller holds hw_lock.
395  */
396 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
397 {
398         int i;
399         u32 mask;
400         u32 dataBit;
401         u32 previousBit;
402         struct ql3xxx_port_registers __iomem *port_regs =
403                         qdev->mem_map_registers;
404
405         /* Clock in a zero, then do the start bit */
406         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
407                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
408                             AUBURN_EEPROM_DO_1);
409         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
410                             ISP_NVRAM_MASK | qdev->
411                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
412                             AUBURN_EEPROM_CLK_RISE);
413         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
414                             ISP_NVRAM_MASK | qdev->
415                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
416                             AUBURN_EEPROM_CLK_FALL);
417
418         mask = 1 << (FM93C56A_CMD_BITS - 1);
419         /* Force the previous data bit to be different */
420         previousBit = 0xffff;
421         for (i = 0; i < FM93C56A_CMD_BITS; i++) {
422                 dataBit =
423                     (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
424                 if (previousBit != dataBit) {
425                         /*
426                          * If the bit changed, then change the DO state to
427                          * match
428                          */
429                         ql_write_nvram_reg(qdev,
430                                             &port_regs->CommonRegs.
431                                             serialPortInterfaceReg,
432                                             ISP_NVRAM_MASK | qdev->
433                                             eeprom_cmd_data | dataBit);
434                         previousBit = dataBit;
435                 }
436                 ql_write_nvram_reg(qdev,
437                                     &port_regs->CommonRegs.
438                                     serialPortInterfaceReg,
439                                     ISP_NVRAM_MASK | qdev->
440                                     eeprom_cmd_data | dataBit |
441                                     AUBURN_EEPROM_CLK_RISE);
442                 ql_write_nvram_reg(qdev,
443                                     &port_regs->CommonRegs.
444                                     serialPortInterfaceReg,
445                                     ISP_NVRAM_MASK | qdev->
446                                     eeprom_cmd_data | dataBit |
447                                     AUBURN_EEPROM_CLK_FALL);
448                 cmd = cmd << 1;
449         }
450
451         mask = 1 << (addrBits - 1);
452         /* Force the previous data bit to be different */
453         previousBit = 0xffff;
454         for (i = 0; i < addrBits; i++) {
455                 dataBit =
456                     (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
457                     AUBURN_EEPROM_DO_0;
458                 if (previousBit != dataBit) {
459                         /*
460                          * If the bit changed, then change the DO state to
461                          * match
462                          */
463                         ql_write_nvram_reg(qdev,
464                                             &port_regs->CommonRegs.
465                                             serialPortInterfaceReg,
466                                             ISP_NVRAM_MASK | qdev->
467                                             eeprom_cmd_data | dataBit);
468                         previousBit = dataBit;
469                 }
470                 ql_write_nvram_reg(qdev,
471                                     &port_regs->CommonRegs.
472                                     serialPortInterfaceReg,
473                                     ISP_NVRAM_MASK | qdev->
474                                     eeprom_cmd_data | dataBit |
475                                     AUBURN_EEPROM_CLK_RISE);
476                 ql_write_nvram_reg(qdev,
477                                     &port_regs->CommonRegs.
478                                     serialPortInterfaceReg,
479                                     ISP_NVRAM_MASK | qdev->
480                                     eeprom_cmd_data | dataBit |
481                                     AUBURN_EEPROM_CLK_FALL);
482                 eepromAddr = eepromAddr << 1;
483         }
484 }
485
486 /*
487  * Caller holds hw_lock.
488  */
489 static void fm93c56a_deselect(struct ql3_adapter *qdev)
490 {
491         struct ql3xxx_port_registers __iomem *port_regs =
492                         qdev->mem_map_registers;
493         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
494         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
495                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
496 }
497
498 /*
499  * Caller holds hw_lock.
500  */
501 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
502 {
503         int i;
504         u32 data = 0;
505         u32 dataBit;
506         struct ql3xxx_port_registers __iomem *port_regs =
507                         qdev->mem_map_registers;
508
509         /* Read the data bits */
510         /* The first bit is a dummy.  Clock right over it. */
511         for (i = 0; i < dataBits; i++) {
512                 ql_write_nvram_reg(qdev,
513                                     &port_regs->CommonRegs.
514                                     serialPortInterfaceReg,
515                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
516                                     AUBURN_EEPROM_CLK_RISE);
517                 ql_write_nvram_reg(qdev,
518                                     &port_regs->CommonRegs.
519                                     serialPortInterfaceReg,
520                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
521                                     AUBURN_EEPROM_CLK_FALL);
522                 dataBit =
523                     (ql_read_common_reg
524                      (qdev,
525                       &port_regs->CommonRegs.
526                       serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
527                 data = (data << 1) | dataBit;
528         }
529         *value = (u16) data;
530 }
531
532 /*
533  * Caller holds hw_lock.
534  */
535 static void eeprom_readword(struct ql3_adapter *qdev,
536                             u32 eepromAddr, unsigned short *value)
537 {
538         fm93c56a_select(qdev);
539         fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
540         fm93c56a_datain(qdev, value);
541         fm93c56a_deselect(qdev);
542 }
543
544 static void ql_swap_mac_addr(u8 * macAddress)
545 {
546 #ifdef __BIG_ENDIAN
547         u8 temp;
548         temp = macAddress[0];
549         macAddress[0] = macAddress[1];
550         macAddress[1] = temp;
551         temp = macAddress[2];
552         macAddress[2] = macAddress[3];
553         macAddress[3] = temp;
554         temp = macAddress[4];
555         macAddress[4] = macAddress[5];
556         macAddress[5] = temp;
557 #endif
558 }
559
560 static int ql_get_nvram_params(struct ql3_adapter *qdev)
561 {
562         u16 *pEEPROMData;
563         u16 checksum = 0;
564         u32 index;
565         unsigned long hw_flags;
566
567         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
568
569         pEEPROMData = (u16 *) & qdev->nvram_data;
570         qdev->eeprom_cmd_data = 0;
571         if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
572                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
573                          2) << 10)) {
574                 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
575                         __func__);
576                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
577                 return -1;
578         }
579
580         for (index = 0; index < EEPROM_SIZE; index++) {
581                 eeprom_readword(qdev, index, pEEPROMData);
582                 checksum += *pEEPROMData;
583                 pEEPROMData++;
584         }
585         ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
586
587         if (checksum != 0) {
588                 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
589                        qdev->ndev->name, checksum);
590                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
591                 return -1;
592         }
593
594         /*
595          * We have a problem with endianness for the MAC addresses
596          * and the two 8-bit values version, and numPorts.  We
597          * have to swap them on big endian systems.
598          */
599         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
600         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
601         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
602         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
603         pEEPROMData = (u16 *) & qdev->nvram_data.version;
604         *pEEPROMData = le16_to_cpu(*pEEPROMData);
605
606         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
607         return checksum;
608 }
609
610 static const u32 PHYAddr[2] = {
611         PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
612 };
613
614 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
615 {
616         struct ql3xxx_port_registers __iomem *port_regs =
617                         qdev->mem_map_registers;
618         u32 temp;
619         int count = 1000;
620
621         while (count) {
622                 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
623                 if (!(temp & MAC_MII_STATUS_BSY))
624                         return 0;
625                 udelay(10);
626                 count--;
627         }
628         return -1;
629 }
630
631 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
632 {
633         struct ql3xxx_port_registers __iomem *port_regs =
634                         qdev->mem_map_registers;
635         u32 scanControl;
636
637         if (qdev->numPorts > 1) {
638                 /* Auto scan will cycle through multiple ports */
639                 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
640         } else {
641                 scanControl = MAC_MII_CONTROL_SC;
642         }
643
644         /*
645          * Scan register 1 of PHY/PETBI,
646          * Set up to scan both devices
647          * The autoscan starts from the first register, completes
648          * the last one before rolling over to the first
649          */
650         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
651                            PHYAddr[0] | MII_SCAN_REGISTER);
652
653         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
654                            (scanControl) |
655                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
656 }
657
658 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
659 {
660         u8 ret;
661         struct ql3xxx_port_registers __iomem *port_regs =
662                                         qdev->mem_map_registers;
663
664         /* See if scan mode is enabled before we turn it off */
665         if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
666             (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
667                 /* Scan is enabled */
668                 ret = 1;
669         } else {
670                 /* Scan is disabled */
671                 ret = 0;
672         }
673
674         /*
675          * When disabling scan mode you must first change the MII register
676          * address
677          */
678         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
679                            PHYAddr[0] | MII_SCAN_REGISTER);
680
681         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
682                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
683                              MAC_MII_CONTROL_RC) << 16));
684
685         return ret;
686 }
687
688 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
689                                u16 regAddr, u16 value, u32 phyAddr)
690 {
691         struct ql3xxx_port_registers __iomem *port_regs =
692                         qdev->mem_map_registers;
693         u8 scanWasEnabled;
694
695         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
696
697         if (ql_wait_for_mii_ready(qdev)) {
698                 if (netif_msg_link(qdev))
699                         printk(KERN_WARNING PFX
700                                "%s Timed out waiting for management port to "
701                                "get free before issuing command.\n",
702                                qdev->ndev->name);
703                 return -1;
704         }
705
706         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
707                            phyAddr | regAddr);
708
709         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
710
711         /* Wait for write to complete 9/10/04 SJP */
712         if (ql_wait_for_mii_ready(qdev)) {
713                 if (netif_msg_link(qdev))
714                         printk(KERN_WARNING PFX
715                                "%s: Timed out waiting for management port to"
716                                "get free before issuing command.\n",
717                                qdev->ndev->name);
718                 return -1;
719         }
720
721         if (scanWasEnabled)
722                 ql_mii_enable_scan_mode(qdev);
723
724         return 0;
725 }
726
727 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
728                               u16 * value, u32 phyAddr)
729 {
730         struct ql3xxx_port_registers __iomem *port_regs =
731                         qdev->mem_map_registers;
732         u8 scanWasEnabled;
733         u32 temp;
734
735         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
736
737         if (ql_wait_for_mii_ready(qdev)) {
738                 if (netif_msg_link(qdev))
739                         printk(KERN_WARNING PFX
740                                "%s: Timed out waiting for management port to "
741                                "get free before issuing command.\n",
742                                qdev->ndev->name);
743                 return -1;
744         }
745
746         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
747                            phyAddr | regAddr);
748
749         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
750                            (MAC_MII_CONTROL_RC << 16));
751
752         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
753                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
754
755         /* Wait for the read to complete */
756         if (ql_wait_for_mii_ready(qdev)) {
757                 if (netif_msg_link(qdev))
758                         printk(KERN_WARNING PFX
759                                "%s: Timed out waiting for management port to "
760                                "get free after issuing command.\n",
761                                qdev->ndev->name);
762                 return -1;
763         }
764
765         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
766         *value = (u16) temp;
767
768         if (scanWasEnabled)
769                 ql_mii_enable_scan_mode(qdev);
770
771         return 0;
772 }
773
774 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
775 {
776         struct ql3xxx_port_registers __iomem *port_regs =
777                         qdev->mem_map_registers;
778
779         ql_mii_disable_scan_mode(qdev);
780
781         if (ql_wait_for_mii_ready(qdev)) {
782                 if (netif_msg_link(qdev))
783                         printk(KERN_WARNING PFX
784                                "%s: Timed out waiting for management port to "
785                                "get free before issuing command.\n",
786                                qdev->ndev->name);
787                 return -1;
788         }
789
790         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
791                            qdev->PHYAddr | regAddr);
792
793         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
794
795         /* Wait for write to complete. */
796         if (ql_wait_for_mii_ready(qdev)) {
797                 if (netif_msg_link(qdev))
798                         printk(KERN_WARNING PFX
799                                "%s: Timed out waiting for management port to "
800                                "get free before issuing command.\n",
801                                qdev->ndev->name);
802                 return -1;
803         }
804
805         ql_mii_enable_scan_mode(qdev);
806
807         return 0;
808 }
809
810 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
811 {
812         u32 temp;
813         struct ql3xxx_port_registers __iomem *port_regs =
814                         qdev->mem_map_registers;
815
816         ql_mii_disable_scan_mode(qdev);
817
818         if (ql_wait_for_mii_ready(qdev)) {
819                 if (netif_msg_link(qdev))
820                         printk(KERN_WARNING PFX
821                                "%s: Timed out waiting for management port to "
822                                "get free before issuing command.\n",
823                                qdev->ndev->name);
824                 return -1;
825         }
826
827         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
828                            qdev->PHYAddr | regAddr);
829
830         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
831                            (MAC_MII_CONTROL_RC << 16));
832
833         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
834                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
835
836         /* Wait for the read to complete */
837         if (ql_wait_for_mii_ready(qdev)) {
838                 if (netif_msg_link(qdev))
839                         printk(KERN_WARNING PFX
840                                "%s: Timed out waiting for management port to "
841                                "get free before issuing command.\n",
842                                qdev->ndev->name);
843                 return -1;
844         }
845
846         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
847         *value = (u16) temp;
848
849         ql_mii_enable_scan_mode(qdev);
850
851         return 0;
852 }
853
854 static void ql_petbi_reset(struct ql3_adapter *qdev)
855 {
856         ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
857 }
858
859 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
860 {
861         u16 reg;
862
863         /* Enable Auto-negotiation sense */
864         ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
865         reg |= PETBI_TBI_AUTO_SENSE;
866         ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
867
868         ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
869                          PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
870
871         ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
872                          PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
873                          PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
874
875 }
876
877 static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
878 {
879         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
880                             PHYAddr[qdev->mac_index]);
881 }
882
883 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
884 {
885         u16 reg;
886
887         /* Enable Auto-negotiation sense */
888         ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg, 
889                            PHYAddr[qdev->mac_index]);
890         reg |= PETBI_TBI_AUTO_SENSE;
891         ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, 
892                             PHYAddr[qdev->mac_index]);
893
894         ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
895                             PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, 
896                             PHYAddr[qdev->mac_index]);
897
898         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
899                             PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
900                             PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
901                             PHYAddr[qdev->mac_index]);
902 }
903
904 static void ql_petbi_init(struct ql3_adapter *qdev)
905 {
906         ql_petbi_reset(qdev);
907         ql_petbi_start_neg(qdev);
908 }
909
910 static void ql_petbi_init_ex(struct ql3_adapter *qdev)
911 {
912         ql_petbi_reset_ex(qdev);
913         ql_petbi_start_neg_ex(qdev);
914 }
915
916 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
917 {
918         u16 reg;
919
920         if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
921                 return 0;
922
923         return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
924 }
925
926 static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
927 {
928         printk(KERN_INFO "%s: enabling Agere specific PHY\n", qdev->ndev->name);
929         /* power down device bit 11 = 1 */
930         ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
931         /* enable diagnostic mode bit 2 = 1 */
932         ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
933         /* 1000MB amplitude adjust (see Agere errata) */
934         ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
935         /* 1000MB amplitude adjust (see Agere errata) */
936         ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
937         /* 100MB amplitude adjust (see Agere errata) */
938         ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
939         /* 100MB amplitude adjust (see Agere errata) */
940         ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
941         /* 10MB amplitude adjust (see Agere errata) */
942         ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
943         /* 10MB amplitude adjust (see Agere errata) */
944         ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
945         /* point to hidden reg 0x2806 */
946         ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
947         /* Write new PHYAD w/bit 5 set */
948         ql_mii_write_reg_ex(qdev, 0x11, 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
949         /* 
950          * Disable diagnostic mode bit 2 = 0
951          * Power up device bit 11 = 0
952          * Link up (on) and activity (blink)
953          */
954         ql_mii_write_reg(qdev, 0x12, 0x840a);
955         ql_mii_write_reg(qdev, 0x00, 0x1140);
956         ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
957 }
958
959 static PHY_DEVICE_et getPhyType (struct ql3_adapter *qdev, 
960                                  u16 phyIdReg0, u16 phyIdReg1)
961 {
962         PHY_DEVICE_et result = PHY_TYPE_UNKNOWN;
963         u32   oui;     
964         u16   model;
965         int i;   
966
967         if (phyIdReg0 == 0xffff) {
968                 return result;
969         }
970    
971         if (phyIdReg1 == 0xffff) {
972                 return result;
973         }
974
975         /* oui is split between two registers */
976         oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
977
978         model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
979
980         /* Scan table for this PHY */
981         for(i = 0; i < MAX_PHY_DEV_TYPES; i++) {
982                 if ((oui == PHY_DEVICES[i].phyIdOUI) && (model == PHY_DEVICES[i].phyIdModel))
983                 {
984                         result = PHY_DEVICES[i].phyDevice;
985
986                         printk(KERN_INFO "%s: Phy: %s\n",
987                                 qdev->ndev->name, PHY_DEVICES[i].name);
988                         
989                         break;
990                 }
991         }
992
993         return result;
994 }
995
996 static int ql_phy_get_speed(struct ql3_adapter *qdev)
997 {
998         u16 reg;
999
1000         switch(qdev->phyType) {
1001         case PHY_AGERE_ET1011C:
1002         {
1003                 if (ql_mii_read_reg(qdev, 0x1A, &reg) < 0)
1004                         return 0;
1005
1006                 reg = (reg >> 8) & 3;
1007                 break;
1008         }
1009         default:
1010         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1011                 return 0;
1012
1013         reg = (((reg & 0x18) >> 3) & 3);
1014         }
1015
1016         switch(reg) {
1017                 case 2:
1018                 return SPEED_1000;
1019                 case 1:
1020                 return SPEED_100;
1021                 case 0:
1022                 return SPEED_10;
1023                 default:
1024                 return -1;
1025         }
1026 }
1027
1028 static int ql_is_full_dup(struct ql3_adapter *qdev)
1029 {
1030         u16 reg;
1031
1032         switch(qdev->phyType) {
1033         case PHY_AGERE_ET1011C:
1034         {
1035                 if (ql_mii_read_reg(qdev, 0x1A, &reg))
1036                         return 0;
1037                         
1038                 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
1039         }
1040         case PHY_VITESSE_VSC8211:
1041         default:
1042         {
1043                 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1044                         return 0;
1045                 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
1046         }
1047         }
1048 }
1049
1050 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
1051 {
1052         u16 reg;
1053
1054         if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
1055                 return 0;
1056
1057         return (reg & PHY_NEG_PAUSE) != 0;
1058 }
1059
1060 static int PHY_Setup(struct ql3_adapter *qdev)
1061 {
1062         u16   reg1;
1063         u16   reg2;
1064         bool  agereAddrChangeNeeded = false;
1065         u32 miiAddr = 0;
1066         int err;
1067
1068         /*  Determine the PHY we are using by reading the ID's */
1069         err = ql_mii_read_reg(qdev, PHY_ID_0_REG, &reg1);
1070         if(err != 0) {
1071                 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1072                        qdev->ndev->name);
1073                 return err;
1074         }
1075
1076         err = ql_mii_read_reg(qdev, PHY_ID_1_REG, &reg2);
1077         if(err != 0) {
1078                 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1079                        qdev->ndev->name);
1080                 return err;
1081         }
1082
1083         /*  Check if we have a Agere PHY */
1084         if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
1085
1086                 /* Determine which MII address we should be using 
1087                    determined by the index of the card */
1088                 if (qdev->mac_index == 0) {
1089                         miiAddr = MII_AGERE_ADDR_1;
1090                 } else {
1091                         miiAddr = MII_AGERE_ADDR_2;
1092                 }
1093       
1094                 err =ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, &reg1, miiAddr);
1095                 if(err != 0) {
1096                         printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1097                                qdev->ndev->name);
1098                         return err; 
1099                 }
1100
1101                 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, &reg2, miiAddr);
1102                 if(err != 0) {
1103                         printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1104                                qdev->ndev->name);
1105                         return err;
1106                 }
1107    
1108                 /*  We need to remember to initialize the Agere PHY */
1109                 agereAddrChangeNeeded = true; 
1110         }
1111
1112         /*  Determine the particular PHY we have on board to apply
1113             PHY specific initializations */
1114         qdev->phyType = getPhyType(qdev, reg1, reg2);
1115
1116         if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1117                 /* need this here so address gets changed */
1118                 phyAgereSpecificInit(qdev, miiAddr);  
1119         } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1120                 printk(KERN_ERR "%s: PHY is unknown\n", qdev->ndev->name);
1121                 return -EIO;
1122         }
1123
1124         return 0;
1125 }
1126
1127 /*
1128  * Caller holds hw_lock.
1129  */
1130 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1131 {
1132         struct ql3xxx_port_registers __iomem *port_regs =
1133                         qdev->mem_map_registers;
1134         u32 value;
1135
1136         if (enable)
1137                 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1138         else
1139                 value = (MAC_CONFIG_REG_PE << 16);
1140
1141         if (qdev->mac_index)
1142                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1143         else
1144                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1145 }
1146
1147 /*
1148  * Caller holds hw_lock.
1149  */
1150 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1151 {
1152         struct ql3xxx_port_registers __iomem *port_regs =
1153                         qdev->mem_map_registers;
1154         u32 value;
1155
1156         if (enable)
1157                 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1158         else
1159                 value = (MAC_CONFIG_REG_SR << 16);
1160
1161         if (qdev->mac_index)
1162                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1163         else
1164                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1165 }
1166
1167 /*
1168  * Caller holds hw_lock.
1169  */
1170 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1171 {
1172         struct ql3xxx_port_registers __iomem *port_regs =
1173                         qdev->mem_map_registers;
1174         u32 value;
1175
1176         if (enable)
1177                 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1178         else
1179                 value = (MAC_CONFIG_REG_GM << 16);
1180
1181         if (qdev->mac_index)
1182                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1183         else
1184                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1185 }
1186
1187 /*
1188  * Caller holds hw_lock.
1189  */
1190 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1191 {
1192         struct ql3xxx_port_registers __iomem *port_regs =
1193                         qdev->mem_map_registers;
1194         u32 value;
1195
1196         if (enable)
1197                 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1198         else
1199                 value = (MAC_CONFIG_REG_FD << 16);
1200
1201         if (qdev->mac_index)
1202                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1203         else
1204                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1205 }
1206
1207 /*
1208  * Caller holds hw_lock.
1209  */
1210 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1211 {
1212         struct ql3xxx_port_registers __iomem *port_regs =
1213                         qdev->mem_map_registers;
1214         u32 value;
1215
1216         if (enable)
1217                 value =
1218                     ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1219                      ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1220         else
1221                 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1222
1223         if (qdev->mac_index)
1224                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1225         else
1226                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1227 }
1228
1229 /*
1230  * Caller holds hw_lock.
1231  */
1232 static int ql_is_fiber(struct ql3_adapter *qdev)
1233 {
1234         struct ql3xxx_port_registers __iomem *port_regs =
1235                         qdev->mem_map_registers;
1236         u32 bitToCheck = 0;
1237         u32 temp;
1238
1239         switch (qdev->mac_index) {
1240         case 0:
1241                 bitToCheck = PORT_STATUS_SM0;
1242                 break;
1243         case 1:
1244                 bitToCheck = PORT_STATUS_SM1;
1245                 break;
1246         }
1247
1248         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1249         return (temp & bitToCheck) != 0;
1250 }
1251
1252 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1253 {
1254         u16 reg;
1255         ql_mii_read_reg(qdev, 0x00, &reg);
1256         return (reg & 0x1000) != 0;
1257 }
1258
1259 /*
1260  * Caller holds hw_lock.
1261  */
1262 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1263 {
1264         struct ql3xxx_port_registers __iomem *port_regs =
1265                         qdev->mem_map_registers;
1266         u32 bitToCheck = 0;
1267         u32 temp;
1268
1269         switch (qdev->mac_index) {
1270         case 0:
1271                 bitToCheck = PORT_STATUS_AC0;
1272                 break;
1273         case 1:
1274                 bitToCheck = PORT_STATUS_AC1;
1275                 break;
1276         }
1277
1278         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1279         if (temp & bitToCheck) {
1280                 if (netif_msg_link(qdev))
1281                         printk(KERN_INFO PFX
1282                                "%s: Auto-Negotiate complete.\n",
1283                                qdev->ndev->name);
1284                 return 1;
1285         } else {
1286                 if (netif_msg_link(qdev))
1287                         printk(KERN_WARNING PFX
1288                                "%s: Auto-Negotiate incomplete.\n",
1289                                qdev->ndev->name);
1290                 return 0;
1291         }
1292 }
1293
1294 /*
1295  *  ql_is_neg_pause() returns 1 if pause was negotiated to be on
1296  */
1297 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1298 {
1299         if (ql_is_fiber(qdev))
1300                 return ql_is_petbi_neg_pause(qdev);
1301         else
1302                 return ql_is_phy_neg_pause(qdev);
1303 }
1304
1305 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1306 {
1307         struct ql3xxx_port_registers __iomem *port_regs =
1308                         qdev->mem_map_registers;
1309         u32 bitToCheck = 0;
1310         u32 temp;
1311
1312         switch (qdev->mac_index) {
1313         case 0:
1314                 bitToCheck = PORT_STATUS_AE0;
1315                 break;
1316         case 1:
1317                 bitToCheck = PORT_STATUS_AE1;
1318                 break;
1319         }
1320         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1321         return (temp & bitToCheck) != 0;
1322 }
1323
1324 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1325 {
1326         if (ql_is_fiber(qdev))
1327                 return SPEED_1000;
1328         else
1329                 return ql_phy_get_speed(qdev);
1330 }
1331
1332 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1333 {
1334         if (ql_is_fiber(qdev))
1335                 return 1;
1336         else
1337                 return ql_is_full_dup(qdev);
1338 }
1339
1340 /*
1341  * Caller holds hw_lock.
1342  */
1343 static int ql_link_down_detect(struct ql3_adapter *qdev)
1344 {
1345         struct ql3xxx_port_registers __iomem *port_regs =
1346                         qdev->mem_map_registers;
1347         u32 bitToCheck = 0;
1348         u32 temp;
1349
1350         switch (qdev->mac_index) {
1351         case 0:
1352                 bitToCheck = ISP_CONTROL_LINK_DN_0;
1353                 break;
1354         case 1:
1355                 bitToCheck = ISP_CONTROL_LINK_DN_1;
1356                 break;
1357         }
1358
1359         temp =
1360             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1361         return (temp & bitToCheck) != 0;
1362 }
1363
1364 /*
1365  * Caller holds hw_lock.
1366  */
1367 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1368 {
1369         struct ql3xxx_port_registers __iomem *port_regs =
1370                         qdev->mem_map_registers;
1371
1372         switch (qdev->mac_index) {
1373         case 0:
1374                 ql_write_common_reg(qdev,
1375                                     &port_regs->CommonRegs.ispControlStatus,
1376                                     (ISP_CONTROL_LINK_DN_0) |
1377                                     (ISP_CONTROL_LINK_DN_0 << 16));
1378                 break;
1379
1380         case 1:
1381                 ql_write_common_reg(qdev,
1382                                     &port_regs->CommonRegs.ispControlStatus,
1383                                     (ISP_CONTROL_LINK_DN_1) |
1384                                     (ISP_CONTROL_LINK_DN_1 << 16));
1385                 break;
1386
1387         default:
1388                 return 1;
1389         }
1390
1391         return 0;
1392 }
1393
1394 /*
1395  * Caller holds hw_lock.
1396  */
1397 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1398 {
1399         struct ql3xxx_port_registers __iomem *port_regs =
1400                         qdev->mem_map_registers;
1401         u32 bitToCheck = 0;
1402         u32 temp;
1403
1404         switch (qdev->mac_index) {
1405         case 0:
1406                 bitToCheck = PORT_STATUS_F1_ENABLED;
1407                 break;
1408         case 1:
1409                 bitToCheck = PORT_STATUS_F3_ENABLED;
1410                 break;
1411         default:
1412                 break;
1413         }
1414
1415         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1416         if (temp & bitToCheck) {
1417                 if (netif_msg_link(qdev))
1418                         printk(KERN_DEBUG PFX
1419                                "%s: is not link master.\n", qdev->ndev->name);
1420                 return 0;
1421         } else {
1422                 if (netif_msg_link(qdev))
1423                         printk(KERN_DEBUG PFX
1424                                "%s: is link master.\n", qdev->ndev->name);
1425                 return 1;
1426         }
1427 }
1428
1429 static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1430 {
1431         ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, 
1432                             PHYAddr[qdev->mac_index]);
1433 }
1434
1435 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1436 {
1437         u16 reg;
1438         u16 portConfiguration;
1439
1440         if(qdev->phyType == PHY_AGERE_ET1011C) {
1441                 /* turn off external loopback */
1442                 ql_mii_write_reg(qdev, 0x13, 0x0000); 
1443         }
1444
1445         if(qdev->mac_index == 0)
1446                 portConfiguration = qdev->nvram_data.macCfg_port0.portConfiguration;
1447         else
1448                 portConfiguration = qdev->nvram_data.macCfg_port1.portConfiguration;
1449
1450         /*  Some HBA's in the field are set to 0 and they need to
1451             be reinterpreted with a default value */
1452         if(portConfiguration == 0)
1453                 portConfiguration = PORT_CONFIG_DEFAULT;
1454
1455         /* Set the 1000 advertisements */
1456         ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, &reg, 
1457                            PHYAddr[qdev->mac_index]);
1458         reg &= ~PHY_GIG_ALL_PARAMS;
1459
1460         if(portConfiguration & 
1461            PORT_CONFIG_FULL_DUPLEX_ENABLED &
1462            PORT_CONFIG_1000MB_SPEED) {
1463                 reg |= PHY_GIG_ADV_1000F;
1464         }
1465          
1466         if(portConfiguration & 
1467            PORT_CONFIG_HALF_DUPLEX_ENABLED &
1468            PORT_CONFIG_1000MB_SPEED) {
1469                 reg |= PHY_GIG_ADV_1000H;
1470         }
1471
1472         ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg, 
1473                             PHYAddr[qdev->mac_index]);
1474
1475         /* Set the 10/100 & pause negotiation advertisements */
1476         ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, &reg,
1477                            PHYAddr[qdev->mac_index]);
1478         reg &= ~PHY_NEG_ALL_PARAMS;
1479
1480         if(portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1481                 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1482
1483         if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1484                 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1485                         reg |= PHY_NEG_ADV_100F;
1486                 
1487                 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1488                         reg |= PHY_NEG_ADV_10F;
1489         }
1490
1491         if(portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1492                 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1493                         reg |= PHY_NEG_ADV_100H;
1494                 
1495                 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1496                         reg |= PHY_NEG_ADV_10H;
1497         }
1498
1499         if(portConfiguration &
1500            PORT_CONFIG_1000MB_SPEED) {
1501                 reg |= 1;       
1502         }
1503
1504         ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg, 
1505                             PHYAddr[qdev->mac_index]);
1506
1507         ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, PHYAddr[qdev->mac_index]);
1508         
1509         ql_mii_write_reg_ex(qdev, CONTROL_REG, 
1510                             reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1511                             PHYAddr[qdev->mac_index]);
1512 }
1513
1514 static void ql_phy_init_ex(struct ql3_adapter *qdev)
1515 {
1516         ql_phy_reset_ex(qdev);
1517         PHY_Setup(qdev);
1518         ql_phy_start_neg_ex(qdev);
1519 }
1520
1521 /*
1522  * Caller holds hw_lock.
1523  */
1524 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1525 {
1526         struct ql3xxx_port_registers __iomem *port_regs =
1527                         qdev->mem_map_registers;
1528         u32 bitToCheck = 0;
1529         u32 temp, linkState;
1530
1531         switch (qdev->mac_index) {
1532         case 0:
1533                 bitToCheck = PORT_STATUS_UP0;
1534                 break;
1535         case 1:
1536                 bitToCheck = PORT_STATUS_UP1;
1537                 break;
1538         }
1539         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1540         if (temp & bitToCheck) {
1541                 linkState = LS_UP;
1542         } else {
1543                 linkState = LS_DOWN;
1544                 if (netif_msg_link(qdev))
1545                         printk(KERN_WARNING PFX
1546                                "%s: Link is down.\n", qdev->ndev->name);
1547         }
1548         return linkState;
1549 }
1550
1551 static int ql_port_start(struct ql3_adapter *qdev)
1552 {
1553         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1554                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1555                          2) << 7)) {
1556                 printk(KERN_ERR "%s: Could not get hw lock for GIO\n",
1557                        qdev->ndev->name);
1558                 return -1;
1559         }
1560
1561         if (ql_is_fiber(qdev)) {
1562                 ql_petbi_init(qdev);
1563         } else {
1564                 /* Copper port */
1565                 ql_phy_init_ex(qdev);
1566         }
1567
1568         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1569         return 0;
1570 }
1571
1572 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1573 {
1574
1575         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1576                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1577                          2) << 7))
1578                 return -1;
1579
1580         if (!ql_auto_neg_error(qdev)) {
1581                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1582                         /* configure the MAC */
1583                         if (netif_msg_link(qdev))
1584                                 printk(KERN_DEBUG PFX
1585                                        "%s: Configuring link.\n",
1586                                        qdev->ndev->
1587                                        name);
1588                         ql_mac_cfg_soft_reset(qdev, 1);
1589                         ql_mac_cfg_gig(qdev,
1590                                        (ql_get_link_speed
1591                                         (qdev) ==
1592                                         SPEED_1000));
1593                         ql_mac_cfg_full_dup(qdev,
1594                                             ql_is_link_full_dup
1595                                             (qdev));
1596                         ql_mac_cfg_pause(qdev,
1597                                          ql_is_neg_pause
1598                                          (qdev));
1599                         ql_mac_cfg_soft_reset(qdev, 0);
1600
1601                         /* enable the MAC */
1602                         if (netif_msg_link(qdev))
1603                                 printk(KERN_DEBUG PFX
1604                                        "%s: Enabling mac.\n",
1605                                        qdev->ndev->
1606                                                name);
1607                         ql_mac_enable(qdev, 1);
1608                 }
1609
1610                 if (netif_msg_link(qdev))
1611                         printk(KERN_DEBUG PFX
1612                                "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1613                                qdev->ndev->name);
1614                 qdev->port_link_state = LS_UP;
1615                 netif_start_queue(qdev->ndev);
1616                 netif_carrier_on(qdev->ndev);
1617                 if (netif_msg_link(qdev))
1618                         printk(KERN_INFO PFX
1619                                "%s: Link is up at %d Mbps, %s duplex.\n",
1620                                qdev->ndev->name,
1621                                ql_get_link_speed(qdev),
1622                                ql_is_link_full_dup(qdev)
1623                                ? "full" : "half");
1624
1625         } else {        /* Remote error detected */
1626
1627                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1628                         if (netif_msg_link(qdev))
1629                                 printk(KERN_DEBUG PFX
1630                                        "%s: Remote error detected. "
1631                                        "Calling ql_port_start().\n",
1632                                        qdev->ndev->
1633                                        name);
1634                         /*
1635                          * ql_port_start() is shared code and needs
1636                          * to lock the PHY on it's own.
1637                          */
1638                         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1639                         if(ql_port_start(qdev)) {/* Restart port */
1640                                 return -1;
1641                         } else
1642                                 return 0;
1643                 }
1644         }
1645         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1646         return 0;
1647 }
1648
1649 static void ql_link_state_machine(struct ql3_adapter *qdev)
1650 {
1651         u32 curr_link_state;
1652         unsigned long hw_flags;
1653
1654         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1655
1656         curr_link_state = ql_get_link_state(qdev);
1657
1658         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1659                 if (netif_msg_link(qdev))
1660                         printk(KERN_INFO PFX
1661                                "%s: Reset in progress, skip processing link "
1662                                "state.\n", qdev->ndev->name);
1663
1664                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);               
1665                 return;
1666         }
1667
1668         switch (qdev->port_link_state) {
1669         default:
1670                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1671                         ql_port_start(qdev);
1672                 }
1673                 qdev->port_link_state = LS_DOWN;
1674                 /* Fall Through */
1675
1676         case LS_DOWN:
1677                 if (netif_msg_link(qdev))
1678                         printk(KERN_DEBUG PFX
1679                                "%s: port_link_state = LS_DOWN.\n",
1680                                qdev->ndev->name);
1681                 if (curr_link_state == LS_UP) {
1682                         if (netif_msg_link(qdev))
1683                                 printk(KERN_DEBUG PFX
1684                                        "%s: curr_link_state = LS_UP.\n",
1685                                        qdev->ndev->name);
1686                         if (ql_is_auto_neg_complete(qdev))
1687                                 ql_finish_auto_neg(qdev);
1688
1689                         if (qdev->port_link_state == LS_UP)
1690                                 ql_link_down_detect_clear(qdev);
1691
1692                 }
1693                 break;
1694
1695         case LS_UP:
1696                 /*
1697                  * See if the link is currently down or went down and came
1698                  * back up
1699                  */
1700                 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1701                         if (netif_msg_link(qdev))
1702                                 printk(KERN_INFO PFX "%s: Link is down.\n",
1703                                        qdev->ndev->name);
1704                         qdev->port_link_state = LS_DOWN;
1705                 }
1706                 break;
1707         }
1708         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1709 }
1710
1711 /*
1712  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1713  */
1714 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1715 {
1716         if (ql_this_adapter_controls_port(qdev))
1717                 set_bit(QL_LINK_MASTER,&qdev->flags);
1718         else
1719                 clear_bit(QL_LINK_MASTER,&qdev->flags);
1720 }
1721
1722 /*
1723  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1724  */
1725 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1726 {
1727         ql_mii_enable_scan_mode(qdev);
1728
1729         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1730                 if (ql_this_adapter_controls_port(qdev))
1731                         ql_petbi_init_ex(qdev);
1732         } else {
1733                 if (ql_this_adapter_controls_port(qdev))
1734                         ql_phy_init_ex(qdev);
1735         }
1736 }
1737
1738 /*
1739  * MII_Setup needs to be called before taking the PHY out of reset so that the
1740  * management interface clock speed can be set properly.  It would be better if
1741  * we had a way to disable MDC until after the PHY is out of reset, but we
1742  * don't have that capability.
1743  */
1744 static int ql_mii_setup(struct ql3_adapter *qdev)
1745 {
1746         u32 reg;
1747         struct ql3xxx_port_registers __iomem *port_regs =
1748                         qdev->mem_map_registers;
1749
1750         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1751                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1752                          2) << 7))
1753                 return -1;
1754
1755         if (qdev->device_id == QL3032_DEVICE_ID)
1756                 ql_write_page0_reg(qdev, 
1757                         &port_regs->macMIIMgmtControlReg, 0x0f00000);
1758
1759         /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1760         reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1761
1762         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1763                            reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1764
1765         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1766         return 0;
1767 }
1768
1769 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1770 {
1771         u32 supported;
1772
1773         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1774                 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1775                     | SUPPORTED_Autoneg;
1776         } else {
1777                 supported = SUPPORTED_10baseT_Half
1778                     | SUPPORTED_10baseT_Full
1779                     | SUPPORTED_100baseT_Half
1780                     | SUPPORTED_100baseT_Full
1781                     | SUPPORTED_1000baseT_Half
1782                     | SUPPORTED_1000baseT_Full
1783                     | SUPPORTED_Autoneg | SUPPORTED_TP;
1784         }
1785
1786         return supported;
1787 }
1788
1789 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1790 {
1791         int status;
1792         unsigned long hw_flags;
1793         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1794         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1795                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1796                          2) << 7)) {
1797                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1798                 return 0;
1799         }
1800         status = ql_is_auto_cfg(qdev);
1801         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1802         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1803         return status;
1804 }
1805
1806 static u32 ql_get_speed(struct ql3_adapter *qdev)
1807 {
1808         u32 status;
1809         unsigned long hw_flags;
1810         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1811         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1812                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1813                          2) << 7)) {
1814                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1815                 return 0;
1816         }
1817         status = ql_get_link_speed(qdev);
1818         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1819         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1820         return status;
1821 }
1822
1823 static int ql_get_full_dup(struct ql3_adapter *qdev)
1824 {
1825         int status;
1826         unsigned long hw_flags;
1827         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1828         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1829                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1830                          2) << 7)) {
1831                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1832                 return 0;
1833         }
1834         status = ql_is_link_full_dup(qdev);
1835         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1836         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1837         return status;
1838 }
1839
1840
1841 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1842 {
1843         struct ql3_adapter *qdev = netdev_priv(ndev);
1844
1845         ecmd->transceiver = XCVR_INTERNAL;
1846         ecmd->supported = ql_supported_modes(qdev);
1847
1848         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1849                 ecmd->port = PORT_FIBRE;
1850         } else {
1851                 ecmd->port = PORT_TP;
1852                 ecmd->phy_address = qdev->PHYAddr;
1853         }
1854         ecmd->advertising = ql_supported_modes(qdev);
1855         ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1856         ecmd->speed = ql_get_speed(qdev);
1857         ecmd->duplex = ql_get_full_dup(qdev);
1858         return 0;
1859 }
1860
1861 static void ql_get_drvinfo(struct net_device *ndev,
1862                            struct ethtool_drvinfo *drvinfo)
1863 {
1864         struct ql3_adapter *qdev = netdev_priv(ndev);
1865         strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1866         strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1867         strncpy(drvinfo->fw_version, "N/A", 32);
1868         strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1869         drvinfo->n_stats = 0;
1870         drvinfo->testinfo_len = 0;
1871         drvinfo->regdump_len = 0;
1872         drvinfo->eedump_len = 0;
1873 }
1874
1875 static u32 ql_get_msglevel(struct net_device *ndev)
1876 {
1877         struct ql3_adapter *qdev = netdev_priv(ndev);
1878         return qdev->msg_enable;
1879 }
1880
1881 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1882 {
1883         struct ql3_adapter *qdev = netdev_priv(ndev);
1884         qdev->msg_enable = value;
1885 }
1886
1887 static void ql_get_pauseparam(struct net_device *ndev,
1888                               struct ethtool_pauseparam *pause)
1889 {
1890         struct ql3_adapter *qdev = netdev_priv(ndev);
1891         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1892
1893         u32 reg;
1894         if(qdev->mac_index == 0)
1895                 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1896         else
1897                 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1898
1899         pause->autoneg  = ql_get_auto_cfg_status(qdev);
1900         pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1901         pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1902 }
1903
1904 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1905         .get_settings = ql_get_settings,
1906         .get_drvinfo = ql_get_drvinfo,
1907         .get_link = ethtool_op_get_link,
1908         .get_msglevel = ql_get_msglevel,
1909         .set_msglevel = ql_set_msglevel,
1910         .get_pauseparam = ql_get_pauseparam,
1911 };
1912
1913 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1914 {
1915         struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1916         dma_addr_t map;
1917         int err;
1918
1919         while (lrg_buf_cb) {
1920                 if (!lrg_buf_cb->skb) {
1921                         lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1922                                                            qdev->lrg_buffer_len);
1923                         if (unlikely(!lrg_buf_cb->skb)) {
1924                                 printk(KERN_DEBUG PFX
1925                                        "%s: Failed netdev_alloc_skb().\n",
1926                                        qdev->ndev->name);
1927                                 break;
1928                         } else {
1929                                 /*
1930                                  * We save some space to copy the ethhdr from
1931                                  * first buffer
1932                                  */
1933                                 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1934                                 map = pci_map_single(qdev->pdev,
1935                                                      lrg_buf_cb->skb->data,
1936                                                      qdev->lrg_buffer_len -
1937                                                      QL_HEADER_SPACE,
1938                                                      PCI_DMA_FROMDEVICE);
1939
1940                                 err = pci_dma_mapping_error(map);
1941                                 if(err) {
1942                                         printk(KERN_ERR "%s: PCI mapping failed with error: %d\n", 
1943                                                qdev->ndev->name, err);
1944                                         dev_kfree_skb(lrg_buf_cb->skb);
1945                                         lrg_buf_cb->skb = NULL;
1946                                         break;
1947                                 }
1948
1949
1950                                 lrg_buf_cb->buf_phy_addr_low =
1951                                     cpu_to_le32(LS_64BITS(map));
1952                                 lrg_buf_cb->buf_phy_addr_high =
1953                                     cpu_to_le32(MS_64BITS(map));
1954                                 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1955                                 pci_unmap_len_set(lrg_buf_cb, maplen,
1956                                                   qdev->lrg_buffer_len -
1957                                                   QL_HEADER_SPACE);
1958                                 --qdev->lrg_buf_skb_check;
1959                                 if (!qdev->lrg_buf_skb_check)
1960                                         return 1;
1961                         }
1962                 }
1963                 lrg_buf_cb = lrg_buf_cb->next;
1964         }
1965         return 0;
1966 }
1967
1968 /*
1969  * Caller holds hw_lock.
1970  */
1971 static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1972 {
1973         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1974         if (qdev->small_buf_release_cnt >= 16) {
1975                 while (qdev->small_buf_release_cnt >= 16) {
1976                         qdev->small_buf_q_producer_index++;
1977
1978                         if (qdev->small_buf_q_producer_index ==
1979                             NUM_SBUFQ_ENTRIES)
1980                                 qdev->small_buf_q_producer_index = 0;
1981                         qdev->small_buf_release_cnt -= 8;
1982                 }
1983                 wmb();
1984                 writel(qdev->small_buf_q_producer_index,
1985                         &port_regs->CommonRegs.rxSmallQProducerIndex);
1986         }
1987 }
1988
1989 /*
1990  * Caller holds hw_lock.
1991  */
1992 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1993 {
1994         struct bufq_addr_element *lrg_buf_q_ele;
1995         int i;
1996         struct ql_rcv_buf_cb *lrg_buf_cb;
1997         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1998
1999         if ((qdev->lrg_buf_free_count >= 8)
2000             && (qdev->lrg_buf_release_cnt >= 16)) {
2001
2002                 if (qdev->lrg_buf_skb_check)
2003                         if (!ql_populate_free_queue(qdev))
2004                                 return;
2005
2006                 lrg_buf_q_ele = qdev->lrg_buf_next_free;
2007
2008                 while ((qdev->lrg_buf_release_cnt >= 16)
2009                        && (qdev->lrg_buf_free_count >= 8)) {
2010
2011                         for (i = 0; i < 8; i++) {
2012                                 lrg_buf_cb =
2013                                     ql_get_from_lrg_buf_free_list(qdev);
2014                                 lrg_buf_q_ele->addr_high =
2015                                     lrg_buf_cb->buf_phy_addr_high;
2016                                 lrg_buf_q_ele->addr_low =
2017                                     lrg_buf_cb->buf_phy_addr_low;
2018                                 lrg_buf_q_ele++;
2019
2020                                 qdev->lrg_buf_release_cnt--;
2021                         }
2022
2023                         qdev->lrg_buf_q_producer_index++;
2024
2025                         if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
2026                                 qdev->lrg_buf_q_producer_index = 0;
2027
2028                         if (qdev->lrg_buf_q_producer_index ==
2029                             (qdev->num_lbufq_entries - 1)) {
2030                                 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
2031                         }
2032                 }
2033                 wmb();
2034                 qdev->lrg_buf_next_free = lrg_buf_q_ele;
2035                 writel(qdev->lrg_buf_q_producer_index,
2036                         &port_regs->CommonRegs.rxLargeQProducerIndex);
2037         }
2038 }
2039
2040 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
2041                                    struct ob_mac_iocb_rsp *mac_rsp)
2042 {
2043         struct ql_tx_buf_cb *tx_cb;
2044         int i;
2045         int retval = 0;
2046
2047         if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2048                 printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
2049         }
2050         
2051         tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
2052
2053         /*  Check the transmit response flags for any errors */
2054         if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2055                 printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
2056
2057                 qdev->stats.tx_errors++;
2058                 retval = -EIO;
2059                 goto frame_not_sent;
2060         }
2061
2062         if(tx_cb->seg_count == 0) {
2063                 printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
2064
2065                 qdev->stats.tx_errors++;
2066                 retval = -EIO;
2067                 goto invalid_seg_count;
2068         }
2069
2070         pci_unmap_single(qdev->pdev,
2071                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
2072                          pci_unmap_len(&tx_cb->map[0], maplen),
2073                          PCI_DMA_TODEVICE);
2074         tx_cb->seg_count--;
2075         if (tx_cb->seg_count) {
2076                 for (i = 1; i < tx_cb->seg_count; i++) {
2077                         pci_unmap_page(qdev->pdev,
2078                                        pci_unmap_addr(&tx_cb->map[i],
2079                                                       mapaddr),
2080                                        pci_unmap_len(&tx_cb->map[i], maplen),
2081                                        PCI_DMA_TODEVICE);
2082                 }
2083         }
2084         qdev->stats.tx_packets++;
2085         qdev->stats.tx_bytes += tx_cb->skb->len;
2086
2087 frame_not_sent:
2088         dev_kfree_skb_irq(tx_cb->skb);
2089         tx_cb->skb = NULL;
2090
2091 invalid_seg_count:
2092         atomic_inc(&qdev->tx_count);
2093 }
2094
2095 static void ql_get_sbuf(struct ql3_adapter *qdev)
2096 {
2097         if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
2098                 qdev->small_buf_index = 0;
2099         qdev->small_buf_release_cnt++;
2100 }
2101
2102 static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
2103 {
2104         struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
2105         lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
2106         qdev->lrg_buf_release_cnt++;
2107         if (++qdev->lrg_buf_index == qdev->num_large_buffers)
2108                 qdev->lrg_buf_index = 0;
2109         return(lrg_buf_cb);
2110 }
2111
2112 /*
2113  * The difference between 3022 and 3032 for inbound completions:
2114  * 3022 uses two buffers per completion.  The first buffer contains 
2115  * (some) header info, the second the remainder of the headers plus 
2116  * the data.  For this chip we reserve some space at the top of the 
2117  * receive buffer so that the header info in buffer one can be 
2118  * prepended to the buffer two.  Buffer two is the sent up while 
2119  * buffer one is returned to the hardware to be reused.
2120  * 3032 receives all of it's data and headers in one buffer for a 
2121  * simpler process.  3032 also supports checksum verification as
2122  * can be seen in ql_process_macip_rx_intr().
2123  */
2124 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2125                                    struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2126 {
2127         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2128         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2129         struct sk_buff *skb;
2130         u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2131
2132         /*
2133          * Get the inbound address list (small buffer).
2134          */
2135         ql_get_sbuf(qdev);
2136
2137         if (qdev->device_id == QL3022_DEVICE_ID)
2138                 lrg_buf_cb1 = ql_get_lbuf(qdev);
2139
2140         /* start of second buffer */
2141         lrg_buf_cb2 = ql_get_lbuf(qdev);
2142         skb = lrg_buf_cb2->skb;
2143
2144         qdev->stats.rx_packets++;
2145         qdev->stats.rx_bytes += length;
2146
2147         skb_put(skb, length);
2148         pci_unmap_single(qdev->pdev,
2149                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
2150                          pci_unmap_len(lrg_buf_cb2, maplen),
2151                          PCI_DMA_FROMDEVICE);
2152         prefetch(skb->data);
2153         skb->ip_summed = CHECKSUM_NONE;
2154         skb->protocol = eth_type_trans(skb, qdev->ndev);
2155
2156         netif_receive_skb(skb);
2157         qdev->ndev->last_rx = jiffies;
2158         lrg_buf_cb2->skb = NULL;
2159
2160         if (qdev->device_id == QL3022_DEVICE_ID)
2161                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2162         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2163 }
2164
2165 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2166                                      struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2167 {
2168         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2169         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2170         struct sk_buff *skb1 = NULL, *skb2;
2171         struct net_device *ndev = qdev->ndev;
2172         u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2173         u16 size = 0;
2174
2175         /*
2176          * Get the inbound address list (small buffer).
2177          */
2178
2179         ql_get_sbuf(qdev);
2180
2181         if (qdev->device_id == QL3022_DEVICE_ID) {
2182                 /* start of first buffer on 3022 */
2183                 lrg_buf_cb1 = ql_get_lbuf(qdev);
2184                 skb1 = lrg_buf_cb1->skb;
2185                 size = ETH_HLEN;
2186                 if (*((u16 *) skb1->data) != 0xFFFF)
2187                         size += VLAN_ETH_HLEN - ETH_HLEN;
2188         }
2189
2190         /* start of second buffer */
2191         lrg_buf_cb2 = ql_get_lbuf(qdev);
2192         skb2 = lrg_buf_cb2->skb;
2193
2194         skb_put(skb2, length);  /* Just the second buffer length here. */
2195         pci_unmap_single(qdev->pdev,
2196                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
2197                          pci_unmap_len(lrg_buf_cb2, maplen),
2198                          PCI_DMA_FROMDEVICE);
2199         prefetch(skb2->data);
2200
2201         skb2->ip_summed = CHECKSUM_NONE;
2202         if (qdev->device_id == QL3022_DEVICE_ID) {
2203                 /*
2204                  * Copy the ethhdr from first buffer to second. This
2205                  * is necessary for 3022 IP completions.
2206                  */
2207                 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2208                                                  skb_push(skb2, size), size);
2209         } else {
2210                 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2211                 if (checksum & 
2212                         (IB_IP_IOCB_RSP_3032_ICE | 
2213                          IB_IP_IOCB_RSP_3032_CE)) { 
2214                         printk(KERN_ERR
2215                                "%s: Bad checksum for this %s packet, checksum = %x.\n",
2216                                __func__,
2217                                ((checksum & 
2218                                 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
2219                                 "UDP"),checksum);
2220                 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2221                                 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2222                                 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2223                         skb2->ip_summed = CHECKSUM_UNNECESSARY;
2224                 }
2225         }
2226         skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2227
2228         netif_receive_skb(skb2);
2229         qdev->stats.rx_packets++;
2230         qdev->stats.rx_bytes += length;
2231         ndev->last_rx = jiffies;
2232         lrg_buf_cb2->skb = NULL;
2233
2234         if (qdev->device_id == QL3022_DEVICE_ID)
2235                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2236         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2237 }
2238
2239 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
2240                           int *tx_cleaned, int *rx_cleaned, int work_to_do)
2241 {
2242         struct net_rsp_iocb *net_rsp;
2243         struct net_device *ndev = qdev->ndev;
2244         int work_done = 0;
2245
2246         /* While there are entries in the completion queue. */
2247         while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2248                 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
2249
2250                 net_rsp = qdev->rsp_current;
2251                 rmb();
2252                 /*
2253                  * Fix 4032 chipe undocumented "feature" where bit-8 is set if the
2254                  * inbound completion is for a VLAN.
2255                  */
2256                 if (qdev->device_id == QL3032_DEVICE_ID)
2257                         net_rsp->opcode &= 0x7f;
2258                 switch (net_rsp->opcode) {
2259
2260                 case OPCODE_OB_MAC_IOCB_FN0:
2261                 case OPCODE_OB_MAC_IOCB_FN2:
2262                         ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2263                                                net_rsp);
2264                         (*tx_cleaned)++;
2265                         break;
2266
2267                 case OPCODE_IB_MAC_IOCB:
2268                 case OPCODE_IB_3032_MAC_IOCB:
2269                         ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2270                                                net_rsp);
2271                         (*rx_cleaned)++;
2272                         break;
2273
2274                 case OPCODE_IB_IP_IOCB:
2275                 case OPCODE_IB_3032_IP_IOCB:
2276                         ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2277                                                  net_rsp);
2278                         (*rx_cleaned)++;
2279                         break;
2280                 default:
2281                         {
2282                                 u32 *tmp = (u32 *) net_rsp;
2283                                 printk(KERN_ERR PFX
2284                                        "%s: Hit default case, not "
2285                                        "handled!\n"
2286                                        "        dropping the packet, opcode = "
2287                                        "%x.\n",
2288                                        ndev->name, net_rsp->opcode);
2289                                 printk(KERN_ERR PFX
2290                                        "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
2291                                        (unsigned long int)tmp[0],
2292                                        (unsigned long int)tmp[1],
2293                                        (unsigned long int)tmp[2],
2294                                        (unsigned long int)tmp[3]);
2295                         }
2296                 }
2297
2298                 qdev->rsp_consumer_index++;
2299
2300                 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2301                         qdev->rsp_consumer_index = 0;
2302                         qdev->rsp_current = qdev->rsp_q_virt_addr;
2303                 } else {
2304                         qdev->rsp_current++;
2305                 }
2306
2307                 work_done = *tx_cleaned + *rx_cleaned;
2308         }
2309
2310         return work_done;
2311 }
2312
2313 static int ql_poll(struct net_device *ndev, int *budget)
2314 {
2315         struct ql3_adapter *qdev = netdev_priv(ndev);
2316         int work_to_do = min(*budget, ndev->quota);
2317         int rx_cleaned = 0, tx_cleaned = 0;
2318         unsigned long hw_flags;
2319         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2320
2321         if (!netif_carrier_ok(ndev))
2322                 goto quit_polling;
2323
2324         ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
2325         *budget -= rx_cleaned;
2326         ndev->quota -= rx_cleaned;
2327
2328         if( tx_cleaned + rx_cleaned != work_to_do ||
2329             !netif_running(ndev)) {
2330 quit_polling:
2331                 netif_rx_complete(ndev);
2332
2333                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2334                 ql_update_small_bufq_prod_index(qdev);
2335                 ql_update_lrg_bufq_prod_index(qdev);
2336                 writel(qdev->rsp_consumer_index,
2337                             &port_regs->CommonRegs.rspQConsumerIndex);
2338                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2339
2340                 ql_enable_interrupts(qdev);
2341                 return 0;
2342         }
2343         return 1;
2344 }
2345
2346 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2347 {
2348
2349         struct net_device *ndev = dev_id;
2350         struct ql3_adapter *qdev = netdev_priv(ndev);
2351         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2352         u32 value;
2353         int handled = 1;
2354         u32 var;
2355
2356         port_regs = qdev->mem_map_registers;
2357
2358         value =
2359             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2360
2361         if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2362                 spin_lock(&qdev->adapter_lock);
2363                 netif_stop_queue(qdev->ndev);
2364                 netif_carrier_off(qdev->ndev);
2365                 ql_disable_interrupts(qdev);
2366                 qdev->port_link_state = LS_DOWN;
2367                 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2368
2369                 if (value & ISP_CONTROL_FE) {
2370                         /*
2371                          * Chip Fatal Error.
2372                          */
2373                         var =
2374                             ql_read_page0_reg_l(qdev,
2375                                               &port_regs->PortFatalErrStatus);
2376                         printk(KERN_WARNING PFX
2377                                "%s: Resetting chip. PortFatalErrStatus "
2378                                "register = 0x%x\n", ndev->name, var);
2379                         set_bit(QL_RESET_START,&qdev->flags) ;
2380                 } else {
2381                         /*
2382                          * Soft Reset Requested.
2383                          */
2384                         set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2385                         printk(KERN_ERR PFX
2386                                "%s: Another function issued a reset to the "
2387                                "chip. ISR value = %x.\n", ndev->name, value);
2388                 }
2389                 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2390                 spin_unlock(&qdev->adapter_lock);
2391         } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2392                 ql_disable_interrupts(qdev);
2393                 if (likely(netif_rx_schedule_prep(ndev))) {
2394                         __netif_rx_schedule(ndev);
2395                 }
2396         } else {
2397                 return IRQ_NONE;
2398         }
2399
2400         return IRQ_RETVAL(handled);
2401 }
2402
2403 /*
2404  * Get the total number of segments needed for the 
2405  * given number of fragments.  This is necessary because
2406  * outbound address lists (OAL) will be used when more than
2407  * two frags are given.  Each address list has 5 addr/len 
2408  * pairs.  The 5th pair in each AOL is used to  point to
2409  * the next AOL if more frags are coming.  
2410  * That is why the frags:segment count  ratio is not linear.
2411  */
2412 static int ql_get_seg_count(struct ql3_adapter *qdev,
2413                             unsigned short frags)
2414 {
2415         if (qdev->device_id == QL3022_DEVICE_ID)
2416                 return 1;
2417
2418         switch(frags) {
2419         case 0: return 1;       /* just the skb->data seg */
2420         case 1: return 2;       /* skb->data + 1 frag */
2421         case 2: return 3;       /* skb->data + 2 frags */
2422         case 3: return 5;       /* skb->data + 1 frag + 1 AOL containting 2 frags */
2423         case 4: return 6;
2424         case 5: return 7;
2425         case 6: return 8;
2426         case 7: return 10;
2427         case 8: return 11;
2428         case 9: return 12;
2429         case 10: return 13;
2430         case 11: return 15;
2431         case 12: return 16;
2432         case 13: return 17;
2433         case 14: return 18;
2434         case 15: return 20;
2435         case 16: return 21;
2436         case 17: return 22;
2437         case 18: return 23;
2438         }
2439         return -1;
2440 }
2441
2442 static void ql_hw_csum_setup(const struct sk_buff *skb,
2443                              struct ob_mac_iocb_req *mac_iocb_ptr)
2444 {
2445         const struct iphdr *ip = ip_hdr(skb);
2446
2447         mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2448         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2449
2450         if (ip->protocol == IPPROTO_TCP) {
2451                 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2452                         OB_3032MAC_IOCB_REQ_IC;
2453         } else {
2454                 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2455                         OB_3032MAC_IOCB_REQ_IC;
2456         }
2457
2458 }
2459
2460 /*
2461  * Map the buffers for this transmit.  This will return
2462  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2463  */
2464 static int ql_send_map(struct ql3_adapter *qdev,
2465                                 struct ob_mac_iocb_req *mac_iocb_ptr,
2466                                 struct ql_tx_buf_cb *tx_cb,
2467                                 struct sk_buff *skb)
2468 {
2469         struct oal *oal;
2470         struct oal_entry *oal_entry;
2471         int len = skb_headlen(skb);
2472         dma_addr_t map;
2473         int err;
2474         int completed_segs, i;
2475         int seg_cnt, seg = 0;
2476         int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2477
2478         seg_cnt = tx_cb->seg_count;
2479         /*
2480          * Map the skb buffer first.
2481          */
2482         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2483
2484         err = pci_dma_mapping_error(map);
2485         if(err) {
2486                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n", 
2487                        qdev->ndev->name, err);
2488
2489                 return NETDEV_TX_BUSY;
2490         }
2491         
2492         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2493         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2494         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2495         oal_entry->len = cpu_to_le32(len);
2496         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2497         pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2498         seg++;
2499
2500         if (seg_cnt == 1) {
2501                 /* Terminate the last segment. */
2502                 oal_entry->len =
2503                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2504         } else {
2505                 oal = tx_cb->oal;
2506                 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2507                         skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2508                         oal_entry++;
2509                         if ((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2510                             (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2511                             (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2512                             (seg == 17 && seg_cnt > 18)) {
2513                                 /* Continuation entry points to outbound address list. */
2514                                 map = pci_map_single(qdev->pdev, oal,
2515                                                      sizeof(struct oal),
2516                                                      PCI_DMA_TODEVICE);
2517
2518                                 err = pci_dma_mapping_error(map);
2519                                 if(err) {
2520
2521                                         printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n", 
2522                                                qdev->ndev->name, err);
2523                                         goto map_error;
2524                                 }
2525
2526                                 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2527                                 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2528                                 oal_entry->len =
2529                                     cpu_to_le32(sizeof(struct oal) |
2530                                                 OAL_CONT_ENTRY);
2531                                 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2532                                                    map);
2533                                 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2534                                                   sizeof(struct oal));
2535                                 oal_entry = (struct oal_entry *)oal;
2536                                 oal++;
2537                                 seg++;
2538                         }
2539
2540                         map =
2541                             pci_map_page(qdev->pdev, frag->page,
2542                                          frag->page_offset, frag->size,
2543                                          PCI_DMA_TODEVICE);
2544
2545                         err = pci_dma_mapping_error(map);
2546                         if(err) {
2547                                 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n", 
2548                                        qdev->ndev->name, err);
2549                                 goto map_error;
2550                         }
2551
2552                         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2553                         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2554                         oal_entry->len = cpu_to_le32(frag->size);
2555                         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2556                         pci_unmap_len_set(&tx_cb->map[seg], maplen,
2557                                           frag->size);
2558                 }
2559                 /* Terminate the last segment. */
2560                 oal_entry->len =
2561                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2562         }
2563
2564         return NETDEV_TX_OK;
2565
2566 map_error:
2567         /* A PCI mapping failed and now we will need to back out
2568          * We need to traverse through the oal's and associated pages which 
2569          * have been mapped and now we must unmap them to clean up properly
2570          */
2571         
2572         seg = 1;
2573         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2574         oal = tx_cb->oal;
2575         for (i=0; i<completed_segs; i++,seg++) {
2576                 oal_entry++;
2577
2578                 if((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2579                    (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2580                    (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2581                    (seg == 17 && seg_cnt > 18)) {
2582                         pci_unmap_single(qdev->pdev,
2583                                 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2584                                 pci_unmap_len(&tx_cb->map[seg], maplen),
2585                                  PCI_DMA_TODEVICE);
2586                         oal++;
2587                         seg++;
2588                 }
2589
2590                 pci_unmap_page(qdev->pdev,
2591                                pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2592                                pci_unmap_len(&tx_cb->map[seg], maplen),
2593                                PCI_DMA_TODEVICE);
2594         }
2595
2596         pci_unmap_single(qdev->pdev,
2597                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
2598                          pci_unmap_addr(&tx_cb->map[0], maplen),
2599                          PCI_DMA_TODEVICE);
2600
2601         return NETDEV_TX_BUSY;
2602
2603 }
2604
2605 /*
2606  * The difference between 3022 and 3032 sends:
2607  * 3022 only supports a simple single segment transmission.
2608  * 3032 supports checksumming and scatter/gather lists (fragments).
2609  * The 3032 supports sglists by using the 3 addr/len pairs (ALP) 
2610  * in the IOCB plus a chain of outbound address lists (OAL) that 
2611  * each contain 5 ALPs.  The last ALP of the IOCB (3rd) or OAL (5th) 
2612  * will used to point to an OAL when more ALP entries are required.  
2613  * The IOCB is always the top of the chain followed by one or more 
2614  * OALs (when necessary).
2615  */
2616 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2617 {
2618         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2619         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2620         struct ql_tx_buf_cb *tx_cb;
2621         u32 tot_len = skb->len;
2622         struct ob_mac_iocb_req *mac_iocb_ptr;
2623
2624         if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2625                 return NETDEV_TX_BUSY;
2626         }
2627         
2628         tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2629         if((tx_cb->seg_count = ql_get_seg_count(qdev,
2630                                                 (skb_shinfo(skb)->nr_frags))) == -1) {
2631                 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2632                 return NETDEV_TX_OK;
2633         }
2634         
2635         mac_iocb_ptr = tx_cb->queue_entry;
2636         memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2637         mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2638         mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2639         mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2640         mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2641         mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2642         tx_cb->skb = skb;
2643         if (qdev->device_id == QL3032_DEVICE_ID &&
2644             skb->ip_summed == CHECKSUM_PARTIAL)
2645                 ql_hw_csum_setup(skb, mac_iocb_ptr);
2646         
2647         if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2648                 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2649                 return NETDEV_TX_BUSY;
2650         }
2651         
2652         wmb();
2653         qdev->req_producer_index++;
2654         if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2655                 qdev->req_producer_index = 0;
2656         wmb();
2657         ql_write_common_reg_l(qdev,
2658                             &port_regs->CommonRegs.reqQProducerIndex,
2659                             qdev->req_producer_index);
2660
2661         ndev->trans_start = jiffies;
2662         if (netif_msg_tx_queued(qdev))
2663                 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2664                        ndev->name, qdev->req_producer_index, skb->len);
2665
2666         atomic_dec(&qdev->tx_count);
2667         return NETDEV_TX_OK;
2668 }
2669
2670 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2671 {
2672         qdev->req_q_size =
2673             (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2674
2675         qdev->req_q_virt_addr =
2676             pci_alloc_consistent(qdev->pdev,
2677                                  (size_t) qdev->req_q_size,
2678                                  &qdev->req_q_phy_addr);
2679
2680         if ((qdev->req_q_virt_addr == NULL) ||
2681             LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2682                 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2683                        qdev->ndev->name);
2684                 return -ENOMEM;
2685         }
2686
2687         qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2688
2689         qdev->rsp_q_virt_addr =
2690             pci_alloc_consistent(qdev->pdev,
2691                                  (size_t) qdev->rsp_q_size,
2692                                  &qdev->rsp_q_phy_addr);
2693
2694         if ((qdev->rsp_q_virt_addr == NULL) ||
2695             LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2696                 printk(KERN_ERR PFX
2697                        "%s: rspQ allocation failed\n",
2698                        qdev->ndev->name);
2699                 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2700                                     qdev->req_q_virt_addr,
2701                                     qdev->req_q_phy_addr);
2702                 return -ENOMEM;
2703         }
2704
2705         set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2706
2707         return 0;
2708 }
2709
2710 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2711 {
2712         if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2713                 printk(KERN_INFO PFX
2714                        "%s: Already done.\n", qdev->ndev->name);
2715                 return;
2716         }
2717
2718         pci_free_consistent(qdev->pdev,
2719                             qdev->req_q_size,
2720                             qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2721
2722         qdev->req_q_virt_addr = NULL;
2723
2724         pci_free_consistent(qdev->pdev,
2725                             qdev->rsp_q_size,
2726                             qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2727
2728         qdev->rsp_q_virt_addr = NULL;
2729
2730         clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2731 }
2732
2733 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2734 {
2735         /* Create Large Buffer Queue */
2736         qdev->lrg_buf_q_size =
2737             qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2738         if (qdev->lrg_buf_q_size < PAGE_SIZE)
2739                 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2740         else
2741                 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2742
2743         qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2744         if (qdev->lrg_buf == NULL) {
2745                 printk(KERN_ERR PFX
2746                        "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2747                 return -ENOMEM;
2748         }
2749         
2750         qdev->lrg_buf_q_alloc_virt_addr =
2751             pci_alloc_consistent(qdev->pdev,
2752                                  qdev->lrg_buf_q_alloc_size,
2753                                  &qdev->lrg_buf_q_alloc_phy_addr);
2754
2755         if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2756                 printk(KERN_ERR PFX
2757                        "%s: lBufQ failed\n", qdev->ndev->name);
2758                 return -ENOMEM;
2759         }
2760         qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2761         qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2762
2763         /* Create Small Buffer Queue */
2764         qdev->small_buf_q_size =
2765             NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2766         if (qdev->small_buf_q_size < PAGE_SIZE)
2767                 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2768         else
2769                 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2770
2771         qdev->small_buf_q_alloc_virt_addr =
2772             pci_alloc_consistent(qdev->pdev,
2773                                  qdev->small_buf_q_alloc_size,
2774                                  &qdev->small_buf_q_alloc_phy_addr);
2775
2776         if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2777                 printk(KERN_ERR PFX
2778                        "%s: Small Buffer Queue allocation failed.\n",
2779                        qdev->ndev->name);
2780                 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2781                                     qdev->lrg_buf_q_alloc_virt_addr,
2782                                     qdev->lrg_buf_q_alloc_phy_addr);
2783                 return -ENOMEM;
2784         }
2785
2786         qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2787         qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2788         set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2789         return 0;
2790 }
2791
2792 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2793 {
2794         if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2795                 printk(KERN_INFO PFX
2796                        "%s: Already done.\n", qdev->ndev->name);
2797                 return;
2798         }
2799         if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2800         pci_free_consistent(qdev->pdev,
2801                             qdev->lrg_buf_q_alloc_size,
2802                             qdev->lrg_buf_q_alloc_virt_addr,
2803                             qdev->lrg_buf_q_alloc_phy_addr);
2804
2805         qdev->lrg_buf_q_virt_addr = NULL;
2806
2807         pci_free_consistent(qdev->pdev,
2808                             qdev->small_buf_q_alloc_size,
2809                             qdev->small_buf_q_alloc_virt_addr,
2810                             qdev->small_buf_q_alloc_phy_addr);
2811
2812         qdev->small_buf_q_virt_addr = NULL;
2813
2814         clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2815 }
2816
2817 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2818 {
2819         int i;
2820         struct bufq_addr_element *small_buf_q_entry;
2821
2822         /* Currently we allocate on one of memory and use it for smallbuffers */
2823         qdev->small_buf_total_size =
2824             (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2825              QL_SMALL_BUFFER_SIZE);
2826
2827         qdev->small_buf_virt_addr =
2828             pci_alloc_consistent(qdev->pdev,
2829                                  qdev->small_buf_total_size,
2830                                  &qdev->small_buf_phy_addr);
2831
2832         if (qdev->small_buf_virt_addr == NULL) {
2833                 printk(KERN_ERR PFX
2834                        "%s: Failed to get small buffer memory.\n",
2835                        qdev->ndev->name);
2836                 return -ENOMEM;
2837         }
2838
2839         qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2840         qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2841
2842         small_buf_q_entry = qdev->small_buf_q_virt_addr;
2843
2844         /* Initialize the small buffer queue. */
2845         for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2846                 small_buf_q_entry->addr_high =
2847                     cpu_to_le32(qdev->small_buf_phy_addr_high);
2848                 small_buf_q_entry->addr_low =
2849                     cpu_to_le32(qdev->small_buf_phy_addr_low +
2850                                 (i * QL_SMALL_BUFFER_SIZE));
2851                 small_buf_q_entry++;
2852         }
2853         qdev->small_buf_index = 0;
2854         set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2855         return 0;
2856 }
2857
2858 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2859 {
2860         if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2861                 printk(KERN_INFO PFX
2862                        "%s: Already done.\n", qdev->ndev->name);
2863                 return;
2864         }
2865         if (qdev->small_buf_virt_addr != NULL) {
2866                 pci_free_consistent(qdev->pdev,
2867                                     qdev->small_buf_total_size,
2868                                     qdev->small_buf_virt_addr,
2869                                     qdev->small_buf_phy_addr);
2870
2871                 qdev->small_buf_virt_addr = NULL;
2872         }
2873 }
2874
2875 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2876 {
2877         int i = 0;
2878         struct ql_rcv_buf_cb *lrg_buf_cb;
2879
2880         for (i = 0; i < qdev->num_large_buffers; i++) {
2881                 lrg_buf_cb = &qdev->lrg_buf[i];
2882                 if (lrg_buf_cb->skb) {
2883                         dev_kfree_skb(lrg_buf_cb->skb);
2884                         pci_unmap_single(qdev->pdev,
2885                                          pci_unmap_addr(lrg_buf_cb, mapaddr),
2886                                          pci_unmap_len(lrg_buf_cb, maplen),
2887                                          PCI_DMA_FROMDEVICE);
2888                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2889                 } else {
2890                         break;
2891                 }
2892         }
2893 }
2894
2895 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2896 {
2897         int i;
2898         struct ql_rcv_buf_cb *lrg_buf_cb;
2899         struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2900
2901         for (i = 0; i < qdev->num_large_buffers; i++) {
2902                 lrg_buf_cb = &qdev->lrg_buf[i];
2903                 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2904                 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2905                 buf_addr_ele++;
2906         }
2907         qdev->lrg_buf_index = 0;
2908         qdev->lrg_buf_skb_check = 0;
2909 }
2910
2911 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2912 {
2913         int i;
2914         struct ql_rcv_buf_cb *lrg_buf_cb;
2915         struct sk_buff *skb;
2916         dma_addr_t map;
2917         int err;
2918
2919         for (i = 0; i < qdev->num_large_buffers; i++) {
2920                 skb = netdev_alloc_skb(qdev->ndev,
2921                                        qdev->lrg_buffer_len);
2922                 if (unlikely(!skb)) {
2923                         /* Better luck next round */
2924                         printk(KERN_ERR PFX
2925                                "%s: large buff alloc failed, "
2926                                "for %d bytes at index %d.\n",
2927                                qdev->ndev->name,
2928                                qdev->lrg_buffer_len * 2, i);
2929                         ql_free_large_buffers(qdev);
2930                         return -ENOMEM;
2931                 } else {
2932
2933                         lrg_buf_cb = &qdev->lrg_buf[i];
2934                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2935                         lrg_buf_cb->index = i;
2936                         lrg_buf_cb->skb = skb;
2937                         /*
2938                          * We save some space to copy the ethhdr from first
2939                          * buffer
2940                          */
2941                         skb_reserve(skb, QL_HEADER_SPACE);
2942                         map = pci_map_single(qdev->pdev,
2943                                              skb->data,
2944                                              qdev->lrg_buffer_len -
2945                                              QL_HEADER_SPACE,
2946                                              PCI_DMA_FROMDEVICE);
2947
2948                         err = pci_dma_mapping_error(map);
2949                         if(err) {
2950                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2951                                        qdev->ndev->name, err);
2952                                 ql_free_large_buffers(qdev);
2953                                 return -ENOMEM;
2954                         }
2955
2956                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2957                         pci_unmap_len_set(lrg_buf_cb, maplen,
2958                                           qdev->lrg_buffer_len -
2959                                           QL_HEADER_SPACE);
2960                         lrg_buf_cb->buf_phy_addr_low =
2961                             cpu_to_le32(LS_64BITS(map));
2962                         lrg_buf_cb->buf_phy_addr_high =
2963                             cpu_to_le32(MS_64BITS(map));
2964                 }
2965         }
2966         return 0;
2967 }
2968
2969 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2970 {
2971         struct ql_tx_buf_cb *tx_cb;
2972         int i;
2973
2974         tx_cb = &qdev->tx_buf[0];
2975         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2976                 if (tx_cb->oal) {
2977                         kfree(tx_cb->oal);
2978                         tx_cb->oal = NULL;
2979                 }
2980                 tx_cb++;
2981         }
2982 }
2983
2984 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2985 {
2986         struct ql_tx_buf_cb *tx_cb;
2987         int i;
2988         struct ob_mac_iocb_req *req_q_curr =
2989                                         qdev->req_q_virt_addr;
2990
2991         /* Create free list of transmit buffers */
2992         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2993
2994                 tx_cb = &qdev->tx_buf[i];
2995                 tx_cb->skb = NULL;
2996                 tx_cb->queue_entry = req_q_curr;
2997                 req_q_curr++;
2998                 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2999                 if (tx_cb->oal == NULL)
3000                         return -1;
3001         }
3002         return 0;
3003 }
3004
3005 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
3006 {
3007         if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
3008                 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
3009                 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
3010         }
3011         else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
3012                 /*
3013                  * Bigger buffers, so less of them.
3014                  */
3015                 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
3016                 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
3017         } else {
3018                 printk(KERN_ERR PFX
3019                        "%s: Invalid mtu size.  Only 1500 and 9000 are accepted.\n",
3020                        qdev->ndev->name);
3021                 return -ENOMEM;
3022         }
3023         qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
3024         qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
3025         qdev->max_frame_size =
3026             (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
3027
3028         /*
3029          * First allocate a page of shared memory and use it for shadow
3030          * locations of Network Request Queue Consumer Address Register and
3031          * Network Completion Queue Producer Index Register
3032          */
3033         qdev->shadow_reg_virt_addr =
3034             pci_alloc_consistent(qdev->pdev,
3035                                  PAGE_SIZE, &qdev->shadow_reg_phy_addr);
3036
3037         if (qdev->shadow_reg_virt_addr != NULL) {
3038                 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
3039                 qdev->req_consumer_index_phy_addr_high =
3040                     MS_64BITS(qdev->shadow_reg_phy_addr);
3041                 qdev->req_consumer_index_phy_addr_low =
3042                     LS_64BITS(qdev->shadow_reg_phy_addr);
3043
3044                 qdev->prsp_producer_index =
3045                     (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
3046                 qdev->rsp_producer_index_phy_addr_high =
3047                     qdev->req_consumer_index_phy_addr_high;
3048                 qdev->rsp_producer_index_phy_addr_low =
3049                     qdev->req_consumer_index_phy_addr_low + 8;
3050         } else {
3051                 printk(KERN_ERR PFX
3052                        "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
3053                 return -ENOMEM;
3054         }
3055
3056         if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
3057                 printk(KERN_ERR PFX
3058                        "%s: ql_alloc_net_req_rsp_queues failed.\n",
3059                        qdev->ndev->name);
3060                 goto err_req_rsp;
3061         }
3062
3063         if (ql_alloc_buffer_queues(qdev) != 0) {
3064                 printk(KERN_ERR PFX
3065                        "%s: ql_alloc_buffer_queues failed.\n",
3066                        qdev->ndev->name);
3067                 goto err_buffer_queues;
3068         }
3069
3070         if (ql_alloc_small_buffers(qdev) != 0) {
3071                 printk(KERN_ERR PFX
3072                        "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
3073                 goto err_small_buffers;
3074         }
3075
3076         if (ql_alloc_large_buffers(qdev) != 0) {
3077                 printk(KERN_ERR PFX
3078                        "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
3079                 goto err_small_buffers;
3080         }
3081
3082         /* Initialize the large buffer queue. */
3083         ql_init_large_buffers(qdev);
3084         if (ql_create_send_free_list(qdev))
3085                 goto err_free_list;
3086
3087         qdev->rsp_current = qdev->rsp_q_virt_addr;
3088
3089         return 0;
3090 err_free_list:
3091         ql_free_send_free_list(qdev);
3092 err_small_buffers:
3093         ql_free_buffer_queues(qdev);
3094 err_buffer_queues:
3095         ql_free_net_req_rsp_queues(qdev);
3096 err_req_rsp:
3097         pci_free_consistent(qdev->pdev,
3098                             PAGE_SIZE,
3099                             qdev->shadow_reg_virt_addr,
3100                             qdev->shadow_reg_phy_addr);
3101
3102         return -ENOMEM;
3103 }
3104
3105 static void ql_free_mem_resources(struct ql3_adapter *qdev)
3106 {
3107         ql_free_send_free_list(qdev);
3108         ql_free_large_buffers(qdev);
3109         ql_free_small_buffers(qdev);
3110         ql_free_buffer_queues(qdev);
3111         ql_free_net_req_rsp_queues(qdev);
3112         if (qdev->shadow_reg_virt_addr != NULL) {
3113                 pci_free_consistent(qdev->pdev,
3114                                     PAGE_SIZE,
3115                                     qdev->shadow_reg_virt_addr,
3116                                     qdev->shadow_reg_phy_addr);
3117                 qdev->shadow_reg_virt_addr = NULL;
3118         }
3119 }
3120
3121 static int ql_init_misc_registers(struct ql3_adapter *qdev)
3122 {
3123         struct ql3xxx_local_ram_registers __iomem *local_ram =
3124             (void __iomem *)qdev->mem_map_registers;
3125
3126         if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
3127                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3128                          2) << 4))
3129                 return -1;
3130
3131         ql_write_page2_reg(qdev,
3132                            &local_ram->bufletSize, qdev->nvram_data.bufletSize);
3133
3134         ql_write_page2_reg(qdev,
3135                            &local_ram->maxBufletCount,
3136                            qdev->nvram_data.bufletCount);
3137
3138         ql_write_page2_reg(qdev,
3139                            &local_ram->freeBufletThresholdLow,
3140                            (qdev->nvram_data.tcpWindowThreshold25 << 16) |
3141                            (qdev->nvram_data.tcpWindowThreshold0));
3142
3143         ql_write_page2_reg(qdev,
3144                            &local_ram->freeBufletThresholdHigh,
3145                            qdev->nvram_data.tcpWindowThreshold50);
3146
3147         ql_write_page2_reg(qdev,
3148                            &local_ram->ipHashTableBase,
3149                            (qdev->nvram_data.ipHashTableBaseHi << 16) |
3150                            qdev->nvram_data.ipHashTableBaseLo);
3151         ql_write_page2_reg(qdev,
3152                            &local_ram->ipHashTableCount,
3153                            qdev->nvram_data.ipHashTableSize);
3154         ql_write_page2_reg(qdev,
3155                            &local_ram->tcpHashTableBase,
3156                            (qdev->nvram_data.tcpHashTableBaseHi << 16) |
3157                            qdev->nvram_data.tcpHashTableBaseLo);
3158         ql_write_page2_reg(qdev,
3159                            &local_ram->tcpHashTableCount,
3160                            qdev->nvram_data.tcpHashTableSize);
3161         ql_write_page2_reg(qdev,
3162                            &local_ram->ncbBase,
3163                            (qdev->nvram_data.ncbTableBaseHi << 16) |
3164                            qdev->nvram_data.ncbTableBaseLo);
3165         ql_write_page2_reg(qdev,
3166                            &local_ram->maxNcbCount,
3167                            qdev->nvram_data.ncbTableSize);
3168         ql_write_page2_reg(qdev,
3169                            &local_ram->drbBase,
3170                            (qdev->nvram_data.drbTableBaseHi << 16) |
3171                            qdev->nvram_data.drbTableBaseLo);
3172         ql_write_page2_reg(qdev,
3173                            &local_ram->maxDrbCount,
3174                            qdev->nvram_data.drbTableSize);
3175         ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3176         return 0;
3177 }
3178
3179 static int ql_adapter_initialize(struct ql3_adapter *qdev)
3180 {
3181         u32 value;
3182         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3183         struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3184                                                 (void __iomem *)port_regs;
3185         u32 delay = 10;
3186         int status = 0;
3187
3188         if(ql_mii_setup(qdev))
3189                 return -1;
3190
3191         /* Bring out PHY out of reset */
3192         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3193                             (ISP_SERIAL_PORT_IF_WE |
3194                              (ISP_SERIAL_PORT_IF_WE << 16)));
3195
3196         qdev->port_link_state = LS_DOWN;
3197         netif_carrier_off(qdev->ndev);
3198
3199         /* V2 chip fix for ARS-39168. */
3200         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3201                             (ISP_SERIAL_PORT_IF_SDE |
3202                              (ISP_SERIAL_PORT_IF_SDE << 16)));
3203
3204         /* Request Queue Registers */
3205         *((u32 *) (qdev->preq_consumer_index)) = 0;
3206         atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
3207         qdev->req_producer_index = 0;
3208
3209         ql_write_page1_reg(qdev,
3210                            &hmem_regs->reqConsumerIndexAddrHigh,
3211                            qdev->req_consumer_index_phy_addr_high);
3212         ql_write_page1_reg(qdev,
3213                            &hmem_regs->reqConsumerIndexAddrLow,
3214                            qdev->req_consumer_index_phy_addr_low);
3215
3216         ql_write_page1_reg(qdev,
3217                            &hmem_regs->reqBaseAddrHigh,
3218                            MS_64BITS(qdev->req_q_phy_addr));
3219         ql_write_page1_reg(qdev,
3220                            &hmem_regs->reqBaseAddrLow,
3221                            LS_64BITS(qdev->req_q_phy_addr));
3222         ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3223
3224         /* Response Queue Registers */
3225         *((u16 *) (qdev->prsp_producer_index)) = 0;
3226         qdev->rsp_consumer_index = 0;
3227         qdev->rsp_current = qdev->rsp_q_virt_addr;
3228
3229         ql_write_page1_reg(qdev,
3230                            &hmem_regs->rspProducerIndexAddrHigh,
3231                            qdev->rsp_producer_index_phy_addr_high);
3232
3233         ql_write_page1_reg(qdev,
3234                            &hmem_regs->rspProducerIndexAddrLow,
3235                            qdev->rsp_producer_index_phy_addr_low);
3236
3237         ql_write_page1_reg(qdev,
3238                            &hmem_regs->rspBaseAddrHigh,
3239                            MS_64BITS(qdev->rsp_q_phy_addr));
3240
3241         ql_write_page1_reg(qdev,
3242                            &hmem_regs->rspBaseAddrLow,
3243                            LS_64BITS(qdev->rsp_q_phy_addr));
3244
3245         ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3246
3247         /* Large Buffer Queue */
3248         ql_write_page1_reg(qdev,
3249                            &hmem_regs->rxLargeQBaseAddrHigh,
3250                            MS_64BITS(qdev->lrg_buf_q_phy_addr));
3251
3252         ql_write_page1_reg(qdev,
3253                            &hmem_regs->rxLargeQBaseAddrLow,
3254                            LS_64BITS(qdev->lrg_buf_q_phy_addr));
3255
3256         ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
3257
3258         ql_write_page1_reg(qdev,
3259                            &hmem_regs->rxLargeBufferLength,
3260                            qdev->lrg_buffer_len);
3261
3262         /* Small Buffer Queue */
3263         ql_write_page1_reg(qdev,
3264                            &hmem_regs->rxSmallQBaseAddrHigh,
3265                            MS_64BITS(qdev->small_buf_q_phy_addr));
3266
3267         ql_write_page1_reg(qdev,
3268                            &hmem_regs->rxSmallQBaseAddrLow,
3269                            LS_64BITS(qdev->small_buf_q_phy_addr));
3270
3271         ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3272         ql_write_page1_reg(qdev,
3273                            &hmem_regs->rxSmallBufferLength,
3274                            QL_SMALL_BUFFER_SIZE);
3275
3276         qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3277         qdev->small_buf_release_cnt = 8;
3278         qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3279         qdev->lrg_buf_release_cnt = 8;
3280         qdev->lrg_buf_next_free =
3281             (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3282         qdev->small_buf_index = 0;
3283         qdev->lrg_buf_index = 0;
3284         qdev->lrg_buf_free_count = 0;
3285         qdev->lrg_buf_free_head = NULL;
3286         qdev->lrg_buf_free_tail = NULL;
3287
3288         ql_write_common_reg(qdev,
3289                             &port_regs->CommonRegs.
3290                             rxSmallQProducerIndex,
3291                             qdev->small_buf_q_producer_index);
3292         ql_write_common_reg(qdev,
3293                             &port_regs->CommonRegs.
3294                             rxLargeQProducerIndex,
3295                             qdev->lrg_buf_q_producer_index);
3296
3297         /*
3298          * Find out if the chip has already been initialized.  If it has, then
3299          * we skip some of the initialization.
3300          */
3301         clear_bit(QL_LINK_MASTER, &qdev->flags);
3302         value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3303         if ((value & PORT_STATUS_IC) == 0) {
3304
3305                 /* Chip has not been configured yet, so let it rip. */
3306                 if(ql_init_misc_registers(qdev)) {
3307                         status = -1;
3308                         goto out;
3309                 }
3310
3311                 value = qdev->nvram_data.tcpMaxWindowSize;
3312                 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3313
3314                 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3315
3316                 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3317                                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3318                                  * 2) << 13)) {
3319                         status = -1;
3320                         goto out;
3321                 }
3322                 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3323                 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3324                                    (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3325                                      16) | (INTERNAL_CHIP_SD |
3326                                             INTERNAL_CHIP_WE)));
3327                 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3328         }
3329
3330         if (qdev->mac_index)
3331                 ql_write_page0_reg(qdev,
3332                                    &port_regs->mac1MaxFrameLengthReg,
3333                                    qdev->max_frame_size);
3334         else
3335                 ql_write_page0_reg(qdev,
3336                                            &port_regs->mac0MaxFrameLengthReg,
3337                                            qdev->max_frame_size);
3338
3339         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3340                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3341                          2) << 7)) {
3342                 status = -1;
3343                 goto out;
3344         }
3345
3346         PHY_Setup(qdev);
3347         ql_init_scan_mode(qdev);
3348         ql_get_phy_owner(qdev);
3349
3350         /* Load the MAC Configuration */
3351
3352         /* Program lower 32 bits of the MAC address */
3353         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3354                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3355         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3356                            ((qdev->ndev->dev_addr[2] << 24)
3357                             | (qdev->ndev->dev_addr[3] << 16)
3358                             | (qdev->ndev->dev_addr[4] << 8)
3359                             | qdev->ndev->dev_addr[5]));
3360
3361         /* Program top 16 bits of the MAC address */
3362         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3363                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3364         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3365                            ((qdev->ndev->dev_addr[0] << 8)
3366                             | qdev->ndev->dev_addr[1]));
3367
3368         /* Enable Primary MAC */
3369         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3370                            ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3371                             MAC_ADDR_INDIRECT_PTR_REG_PE));
3372
3373         /* Clear Primary and Secondary IP addresses */
3374         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3375                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3376                             (qdev->mac_index << 2)));
3377         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3378
3379         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3380                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3381                             ((qdev->mac_index << 2) + 1)));
3382         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3383
3384         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3385
3386         /* Indicate Configuration Complete */
3387         ql_write_page0_reg(qdev,
3388                            &port_regs->portControl,
3389                            ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3390
3391         do {
3392                 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3393                 if (value & PORT_STATUS_IC)
3394                         break;
3395                 msleep(500);
3396         } while (--delay);
3397
3398         if (delay == 0) {
3399                 printk(KERN_ERR PFX
3400                        "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3401                 status = -1;
3402                 goto out;
3403         }
3404
3405         /* Enable Ethernet Function */
3406         if (qdev->device_id == QL3032_DEVICE_ID) {
3407                 value =
3408                     (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3409                      QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3410                         QL3032_PORT_CONTROL_ET);
3411                 ql_write_page0_reg(qdev, &port_regs->functionControl,
3412                                    ((value << 16) | value));
3413         } else {
3414                 value =
3415                     (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3416                      PORT_CONTROL_HH);
3417                 ql_write_page0_reg(qdev, &port_regs->portControl,
3418                                    ((value << 16) | value));
3419         }
3420
3421
3422 out:
3423         return status;
3424 }
3425
3426 /*
3427  * Caller holds hw_lock.
3428  */
3429 static int ql_adapter_reset(struct ql3_adapter *qdev)
3430 {
3431         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3432         int status = 0;
3433         u16 value;
3434         int max_wait_time;
3435
3436         set_bit(QL_RESET_ACTIVE, &qdev->flags);
3437         clear_bit(QL_RESET_DONE, &qdev->flags);
3438
3439         /*
3440          * Issue soft reset to chip.
3441          */
3442         printk(KERN_DEBUG PFX
3443                "%s: Issue soft reset to chip.\n",
3444                qdev->ndev->name);
3445         ql_write_common_reg(qdev,
3446                             &port_regs->CommonRegs.ispControlStatus,
3447                             ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3448
3449         /* Wait 3 seconds for reset to complete. */
3450         printk(KERN_DEBUG PFX
3451                "%s: Wait 10 milliseconds for reset to complete.\n",
3452                qdev->ndev->name);
3453
3454         /* Wait until the firmware tells us the Soft Reset is done */
3455         max_wait_time = 5;
3456         do {
3457                 value =
3458                     ql_read_common_reg(qdev,
3459                                        &port_regs->CommonRegs.ispControlStatus);
3460                 if ((value & ISP_CONTROL_SR) == 0)
3461                         break;
3462
3463                 ssleep(1);
3464         } while ((--max_wait_time));
3465
3466         /*
3467          * Also, make sure that the Network Reset Interrupt bit has been
3468          * cleared after the soft reset has taken place.
3469          */
3470         value =
3471             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3472         if (value & ISP_CONTROL_RI) {
3473                 printk(KERN_DEBUG PFX
3474                        "ql_adapter_reset: clearing RI after reset.\n");
3475                 ql_write_common_reg(qdev,
3476                                     &port_regs->CommonRegs.
3477                                     ispControlStatus,
3478                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3479         }
3480
3481         if (max_wait_time == 0) {
3482                 /* Issue Force Soft Reset */
3483                 ql_write_common_reg(qdev,
3484                                     &port_regs->CommonRegs.
3485                                     ispControlStatus,
3486                                     ((ISP_CONTROL_FSR << 16) |
3487                                      ISP_CONTROL_FSR));
3488                 /*
3489                  * Wait until the firmware tells us the Force Soft Reset is
3490                  * done
3491                  */
3492                 max_wait_time = 5;
3493                 do {
3494                         value =
3495                             ql_read_common_reg(qdev,
3496                                                &port_regs->CommonRegs.
3497                                                ispControlStatus);
3498                         if ((value & ISP_CONTROL_FSR) == 0) {
3499                                 break;
3500                         }
3501                         ssleep(1);
3502                 } while ((--max_wait_time));
3503         }
3504         if (max_wait_time == 0)
3505                 status = 1;
3506
3507         clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3508         set_bit(QL_RESET_DONE, &qdev->flags);
3509         return status;
3510 }
3511
3512 static void ql_set_mac_info(struct ql3_adapter *qdev)
3513 {
3514         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3515         u32 value, port_status;
3516         u8 func_number;
3517
3518         /* Get the function number */
3519         value =
3520             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3521         func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3522         port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3523         switch (value & ISP_CONTROL_FN_MASK) {
3524         case ISP_CONTROL_FN0_NET:
3525                 qdev->mac_index = 0;
3526                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3527                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3528                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3529                 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3530                 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3531                 if (port_status & PORT_STATUS_SM0)
3532                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3533                 else
3534                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3535                 break;
3536
3537         case ISP_CONTROL_FN1_NET:
3538                 qdev->mac_index = 1;
3539                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3540                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3541                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3542                 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3543                 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3544                 if (port_status & PORT_STATUS_SM1)
3545                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3546                 else
3547                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3548                 break;
3549
3550         case ISP_CONTROL_FN0_SCSI:
3551         case ISP_CONTROL_FN1_SCSI:
3552         default:
3553                 printk(KERN_DEBUG PFX
3554                        "%s: Invalid function number, ispControlStatus = 0x%x\n",
3555                        qdev->ndev->name,value);
3556                 break;
3557         }
3558         qdev->numPorts = qdev->nvram_data.numPorts;
3559 }
3560
3561 static void ql_display_dev_info(struct net_device *ndev)
3562 {
3563         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3564         struct pci_dev *pdev = qdev->pdev;
3565
3566         printk(KERN_INFO PFX
3567                "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3568                DRV_NAME, qdev->index, qdev->chip_rev_id,
3569                (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3570                qdev->pci_slot);
3571         printk(KERN_INFO PFX
3572                "%s Interface.\n",
3573                test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3574
3575         /*
3576          * Print PCI bus width/type.
3577          */
3578         printk(KERN_INFO PFX
3579                "Bus interface is %s %s.\n",
3580                ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3581                ((qdev->pci_x) ? "PCI-X" : "PCI"));
3582
3583         printk(KERN_INFO PFX
3584                "mem  IO base address adjusted = 0x%p\n",
3585                qdev->mem_map_registers);
3586         printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3587
3588         if (netif_msg_probe(qdev))
3589                 printk(KERN_INFO PFX
3590                        "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3591                        ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
3592                        ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3593                        ndev->dev_addr[5]);
3594 }
3595
3596 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3597 {
3598         struct net_device *ndev = qdev->ndev;
3599         int retval = 0;
3600
3601         netif_stop_queue(ndev);
3602         netif_carrier_off(ndev);
3603
3604         clear_bit(QL_ADAPTER_UP,&qdev->flags);
3605         clear_bit(QL_LINK_MASTER,&qdev->flags);
3606
3607         ql_disable_interrupts(qdev);
3608
3609         free_irq(qdev->pdev->irq, ndev);
3610
3611         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3612                 printk(KERN_INFO PFX
3613                        "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3614                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3615                 pci_disable_msi(qdev->pdev);
3616         }
3617
3618         del_timer_sync(&qdev->adapter_timer);
3619
3620         netif_poll_disable(ndev);
3621
3622         if (do_reset) {
3623                 int soft_reset;
3624                 unsigned long hw_flags;
3625
3626                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3627                 if (ql_wait_for_drvr_lock(qdev)) {
3628                         if ((soft_reset = ql_adapter_reset(qdev))) {
3629                                 printk(KERN_ERR PFX
3630                                        "%s: ql_adapter_reset(%d) FAILED!\n",
3631                                        ndev->name, qdev->index);
3632                         }
3633                         printk(KERN_ERR PFX
3634                                 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3635                 } else {
3636                         printk(KERN_ERR PFX
3637                                "%s: Could not acquire driver lock to do "
3638                                "reset!\n", ndev->name);
3639                         retval = -1;
3640                 }
3641                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3642         }
3643         ql_free_mem_resources(qdev);
3644         return retval;
3645 }
3646
3647 static int ql_adapter_up(struct ql3_adapter *qdev)
3648 {
3649         struct net_device *ndev = qdev->ndev;
3650         int err;
3651         unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3652         unsigned long hw_flags;
3653
3654         if (ql_alloc_mem_resources(qdev)) {
3655                 printk(KERN_ERR PFX
3656                        "%s Unable to  allocate buffers.\n", ndev->name);
3657                 return -ENOMEM;
3658         }
3659
3660         if (qdev->msi) {
3661                 if (pci_enable_msi(qdev->pdev)) {
3662                         printk(KERN_ERR PFX
3663                                "%s: User requested MSI, but MSI failed to "
3664                                "initialize.  Continuing without MSI.\n",
3665                                qdev->ndev->name);
3666                         qdev->msi = 0;
3667                 } else {
3668                         printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3669                         set_bit(QL_MSI_ENABLED,&qdev->flags);
3670                         irq_flags &= ~IRQF_SHARED;
3671                 }
3672         }
3673
3674         if ((err = request_irq(qdev->pdev->irq,
3675                                ql3xxx_isr,
3676                                irq_flags, ndev->name, ndev))) {
3677                 printk(KERN_ERR PFX
3678                        "%s: Failed to reserve interrupt %d already in use.\n",
3679                        ndev->name, qdev->pdev->irq);
3680                 goto err_irq;
3681         }
3682
3683         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3684
3685         if ((err = ql_wait_for_drvr_lock(qdev))) {
3686                 if ((err = ql_adapter_initialize(qdev))) {
3687                         printk(KERN_ERR PFX
3688                                "%s: Unable to initialize adapter.\n",
3689                                ndev->name);
3690                         goto err_init;
3691                 }
3692                 printk(KERN_ERR PFX
3693                                 "%s: Releaseing driver lock.\n",ndev->name);
3694                 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3695         } else {
3696                 printk(KERN_ERR PFX
3697                        "%s: Could not aquire driver lock.\n",
3698                        ndev->name);
3699                 goto err_lock;
3700         }
3701
3702         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3703
3704         set_bit(QL_ADAPTER_UP,&qdev->flags);
3705
3706         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3707
3708         netif_poll_enable(ndev);
3709         ql_enable_interrupts(qdev);
3710         return 0;
3711
3712 err_init:
3713         ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3714 err_lock:
3715         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3716         free_irq(qdev->pdev->irq, ndev);
3717 err_irq:
3718         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3719                 printk(KERN_INFO PFX
3720                        "%s: calling pci_disable_msi().\n",
3721                        qdev->ndev->name);
3722                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3723                 pci_disable_msi(qdev->pdev);
3724         }
3725         return err;
3726 }
3727
3728 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3729 {
3730         if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3731                 printk(KERN_ERR PFX
3732                                 "%s: Driver up/down cycle failed, "
3733                                 "closing device\n",qdev->ndev->name);
3734                 dev_close(qdev->ndev);
3735                 return -1;
3736         }
3737         return 0;
3738 }
3739
3740 static int ql3xxx_close(struct net_device *ndev)
3741 {
3742         struct ql3_adapter *qdev = netdev_priv(ndev);
3743
3744         /*
3745          * Wait for device to recover from a reset.
3746          * (Rarely happens, but possible.)
3747          */
3748         while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3749                 msleep(50);
3750
3751         ql_adapter_down(qdev,QL_DO_RESET);
3752         return 0;
3753 }
3754
3755 static int ql3xxx_open(struct net_device *ndev)
3756 {
3757         struct ql3_adapter *qdev = netdev_priv(ndev);
3758         return (ql_adapter_up(qdev));
3759 }
3760
3761 static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3762 {
3763         struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3764         return &qdev->stats;
3765 }
3766
3767 static void ql3xxx_set_multicast_list(struct net_device *ndev)
3768 {
3769         /*
3770          * We are manually parsing the list in the net_device structure.
3771          */
3772         return;
3773 }
3774
3775 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3776 {
3777         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3778         struct ql3xxx_port_registers __iomem *port_regs =
3779                         qdev->mem_map_registers;
3780         struct sockaddr *addr = p;
3781         unsigned long hw_flags;
3782
3783         if (netif_running(ndev))
3784                 return -EBUSY;
3785
3786         if (!is_valid_ether_addr(addr->sa_data))
3787                 return -EADDRNOTAVAIL;
3788
3789         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3790
3791         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3792         /* Program lower 32 bits of the MAC address */
3793         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3794                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3795         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3796                            ((ndev->dev_addr[2] << 24) | (ndev->
3797                                                          dev_addr[3] << 16) |
3798                             (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3799
3800         /* Program top 16 bits of the MAC address */
3801         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3802                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3803         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3804                            ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3805         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3806
3807         return 0;
3808 }
3809
3810 static void ql3xxx_tx_timeout(struct net_device *ndev)
3811 {
3812         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3813
3814         printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3815         /*
3816          * Stop the queues, we've got a problem.
3817          */
3818         netif_stop_queue(ndev);
3819
3820         /*
3821          * Wake up the worker to process this event.
3822          */
3823         queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3824 }
3825
3826 static void ql_reset_work(struct work_struct *work)
3827 {
3828         struct ql3_adapter *qdev =
3829                 container_of(work, struct ql3_adapter, reset_work.work);
3830         struct net_device *ndev = qdev->ndev;
3831         u32 value;
3832         struct ql_tx_buf_cb *tx_cb;
3833         int max_wait_time, i;
3834         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3835         unsigned long hw_flags;
3836
3837         if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3838                 clear_bit(QL_LINK_MASTER,&qdev->flags);
3839
3840                 /*
3841                  * Loop through the active list and return the skb.
3842                  */
3843                 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3844                         int j;
3845                         tx_cb = &qdev->tx_buf[i];
3846                         if (tx_cb->skb) {
3847                                 printk(KERN_DEBUG PFX
3848                                        "%s: Freeing lost SKB.\n",
3849                                        qdev->ndev->name);
3850                                 pci_unmap_single(qdev->pdev,
3851                                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
3852                                          pci_unmap_len(&tx_cb->map[0], maplen),
3853                                          PCI_DMA_TODEVICE);
3854                                 for(j=1;j<tx_cb->seg_count;j++) {
3855                                         pci_unmap_page(qdev->pdev,
3856                                                pci_unmap_addr(&tx_cb->map[j],mapaddr),
3857                                                pci_unmap_len(&tx_cb->map[j],maplen),
3858                                                PCI_DMA_TODEVICE);
3859                                 }
3860                                 dev_kfree_skb(tx_cb->skb);
3861                                 tx_cb->skb = NULL;
3862                         }
3863                 }
3864
3865                 printk(KERN_ERR PFX
3866                        "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3867                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3868                 ql_write_common_reg(qdev,
3869                                     &port_regs->CommonRegs.
3870                                     ispControlStatus,
3871                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3872                 /*
3873                  * Wait the for Soft Reset to Complete.
3874                  */
3875                 max_wait_time = 10;
3876                 do {
3877                         value = ql_read_common_reg(qdev,
3878                                                    &port_regs->CommonRegs.
3879
3880                                                    ispControlStatus);
3881                         if ((value & ISP_CONTROL_SR) == 0) {
3882                                 printk(KERN_DEBUG PFX
3883                                        "%s: reset completed.\n",
3884                                        qdev->ndev->name);
3885                                 break;
3886                         }
3887
3888                         if (value & ISP_CONTROL_RI) {
3889                                 printk(KERN_DEBUG PFX
3890                                        "%s: clearing NRI after reset.\n",
3891                                        qdev->ndev->name);
3892                                 ql_write_common_reg(qdev,
3893                                                     &port_regs->
3894                                                     CommonRegs.
3895                                                     ispControlStatus,
3896                                                     ((ISP_CONTROL_RI <<
3897                                                       16) | ISP_CONTROL_RI));
3898                         }
3899
3900                         ssleep(1);
3901                 } while (--max_wait_time);
3902                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3903
3904                 if (value & ISP_CONTROL_SR) {
3905
3906                         /*
3907                          * Set the reset flags and clear the board again.
3908                          * Nothing else to do...
3909                          */
3910                         printk(KERN_ERR PFX
3911                                "%s: Timed out waiting for reset to "
3912                                "complete.\n", ndev->name);
3913                         printk(KERN_ERR PFX
3914                                "%s: Do a reset.\n", ndev->name);
3915                         clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3916                         clear_bit(QL_RESET_START,&qdev->flags);
3917                         ql_cycle_adapter(qdev,QL_DO_RESET);
3918                         return;
3919                 }
3920
3921                 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3922                 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3923                 clear_bit(QL_RESET_START,&qdev->flags);
3924                 ql_cycle_adapter(qdev,QL_NO_RESET);
3925         }
3926 }
3927
3928 static void ql_tx_timeout_work(struct work_struct *work)
3929 {
3930         struct ql3_adapter *qdev =
3931                 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3932
3933         ql_cycle_adapter(qdev, QL_DO_RESET);
3934 }
3935
3936 static void ql_get_board_info(struct ql3_adapter *qdev)
3937 {
3938         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3939         u32 value;
3940
3941         value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3942
3943         qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3944         if (value & PORT_STATUS_64)
3945                 qdev->pci_width = 64;
3946         else
3947                 qdev->pci_width = 32;
3948         if (value & PORT_STATUS_X)
3949                 qdev->pci_x = 1;
3950         else
3951                 qdev->pci_x = 0;
3952         qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3953 }
3954
3955 static void ql3xxx_timer(unsigned long ptr)
3956 {
3957         struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3958
3959         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3960                 printk(KERN_DEBUG PFX
3961                        "%s: Reset in progress.\n",
3962                        qdev->ndev->name);
3963                 goto end;
3964         }
3965
3966         ql_link_state_machine(qdev);
3967
3968         /* Restart timer on 2 second interval. */
3969 end:
3970         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3971 }
3972
3973 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3974                                   const struct pci_device_id *pci_entry)
3975 {
3976         struct net_device *ndev = NULL;
3977         struct ql3_adapter *qdev = NULL;
3978         static int cards_found = 0;
3979         int pci_using_dac, err;
3980
3981         err = pci_enable_device(pdev);
3982         if (err) {
3983                 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3984                        pci_name(pdev));
3985                 goto err_out;
3986         }
3987
3988         err = pci_request_regions(pdev, DRV_NAME);
3989         if (err) {
3990                 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3991                        pci_name(pdev));
3992                 goto err_out_disable_pdev;
3993         }
3994
3995         pci_set_master(pdev);
3996
3997         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3998                 pci_using_dac = 1;
3999                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4000         } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
4001                 pci_using_dac = 0;
4002                 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
4003         }
4004
4005         if (err) {
4006                 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
4007                        pci_name(pdev));
4008                 goto err_out_free_regions;
4009         }
4010
4011         ndev = alloc_etherdev(sizeof(struct ql3_adapter));
4012         if (!ndev) {
4013                 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
4014                        pci_name(pdev));
4015                 err = -ENOMEM;
4016                 goto err_out_free_regions;
4017         }
4018
4019         SET_MODULE_OWNER(ndev);
4020         SET_NETDEV_DEV(ndev, &pdev->dev);
4021
4022         pci_set_drvdata(pdev, ndev);
4023
4024         qdev = netdev_priv(ndev);
4025         qdev->index = cards_found;
4026         qdev->ndev = ndev;
4027         qdev->pdev = pdev;
4028         qdev->device_id = pci_entry->device;
4029         qdev->port_link_state = LS_DOWN;
4030         if (msi)
4031                 qdev->msi = 1;
4032
4033         qdev->msg_enable = netif_msg_init(debug, default_msg);
4034
4035         if (pci_using_dac)
4036                 ndev->features |= NETIF_F_HIGHDMA;
4037         if (qdev->device_id == QL3032_DEVICE_ID)
4038                 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
4039
4040         qdev->mem_map_registers =
4041             ioremap_nocache(pci_resource_start(pdev, 1),
4042                             pci_resource_len(qdev->pdev, 1));
4043         if (!qdev->mem_map_registers) {
4044                 printk(KERN_ERR PFX "%s: cannot map device registers\n",
4045                        pci_name(pdev));
4046                 err = -EIO;
4047                 goto err_out_free_ndev;
4048         }
4049
4050         spin_lock_init(&qdev->adapter_lock);
4051         spin_lock_init(&qdev->hw_lock);
4052
4053         /* Set driver entry points */
4054         ndev->open = ql3xxx_open;
4055         ndev->hard_start_xmit = ql3xxx_send;
4056         ndev->stop = ql3xxx_close;
4057         ndev->get_stats = ql3xxx_get_stats;
4058         ndev->set_multicast_list = ql3xxx_set_multicast_list;
4059         SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
4060         ndev->set_mac_address = ql3xxx_set_mac_address;
4061         ndev->tx_timeout = ql3xxx_tx_timeout;
4062         ndev->watchdog_timeo = 5 * HZ;
4063
4064         ndev->poll = &ql_poll;
4065         ndev->weight = 64;
4066
4067         ndev->irq = pdev->irq;
4068
4069         /* make sure the EEPROM is good */
4070         if (ql_get_nvram_params(qdev)) {
4071                 printk(KERN_ALERT PFX
4072                        "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
4073                        qdev->index);
4074                 err = -EIO;
4075                 goto err_out_iounmap;
4076         }
4077
4078         ql_set_mac_info(qdev);
4079
4080         /* Validate and set parameters */
4081         if (qdev->mac_index) {
4082                 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
4083                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
4084                        ETH_ALEN);
4085         } else {
4086                 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
4087                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
4088                        ETH_ALEN);
4089         }
4090         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
4091
4092         ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
4093
4094         /* Turn off support for multicasting */
4095         ndev->flags &= ~IFF_MULTICAST;
4096
4097         /* Record PCI bus information. */
4098         ql_get_board_info(qdev);
4099
4100         /*
4101          * Set the Maximum Memory Read Byte Count value. We do this to handle
4102          * jumbo frames.
4103          */
4104         if (qdev->pci_x) {
4105                 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
4106         }
4107
4108         err = register_netdev(ndev);
4109         if (err) {
4110                 printk(KERN_ERR PFX "%s: cannot register net device\n",
4111                        pci_name(pdev));
4112                 goto err_out_iounmap;
4113         }
4114
4115         /* we're going to reset, so assume we have no link for now */
4116
4117         netif_carrier_off(ndev);
4118         netif_stop_queue(ndev);
4119
4120         qdev->workqueue = create_singlethread_workqueue(ndev->name);
4121         INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
4122         INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
4123
4124         init_timer(&qdev->adapter_timer);
4125         qdev->adapter_timer.function = ql3xxx_timer;
4126         qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
4127         qdev->adapter_timer.data = (unsigned long)qdev;
4128
4129         if(!cards_found) {
4130                 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
4131                 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
4132                    DRV_NAME, DRV_VERSION);
4133         }
4134         ql_display_dev_info(ndev);
4135
4136         cards_found++;
4137         return 0;
4138
4139 err_out_iounmap:
4140         iounmap(qdev->mem_map_registers);
4141 err_out_free_ndev:
4142         free_netdev(ndev);
4143 err_out_free_regions:
4144         pci_release_regions(pdev);
4145 err_out_disable_pdev:
4146         pci_disable_device(pdev);
4147         pci_set_drvdata(pdev, NULL);
4148 err_out:
4149         return err;
4150 }
4151
4152 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
4153 {
4154         struct net_device *ndev = pci_get_drvdata(pdev);
4155         struct ql3_adapter *qdev = netdev_priv(ndev);
4156
4157         unregister_netdev(ndev);
4158         qdev = netdev_priv(ndev);
4159
4160         ql_disable_interrupts(qdev);
4161
4162         if (qdev->workqueue) {
4163                 cancel_delayed_work(&qdev->reset_work);
4164                 cancel_delayed_work(&qdev->tx_timeout_work);
4165                 destroy_workqueue(qdev->workqueue);
4166                 qdev->workqueue = NULL;
4167         }
4168
4169         iounmap(qdev->mem_map_registers);
4170         pci_release_regions(pdev);
4171         pci_set_drvdata(pdev, NULL);
4172         free_netdev(ndev);
4173 }
4174
4175 static struct pci_driver ql3xxx_driver = {
4176
4177         .name = DRV_NAME,
4178         .id_table = ql3xxx_pci_tbl,
4179         .probe = ql3xxx_probe,
4180         .remove = __devexit_p(ql3xxx_remove),
4181 };
4182
4183 static int __init ql3xxx_init_module(void)
4184 {
4185         return pci_register_driver(&ql3xxx_driver);
4186 }
4187
4188 static void __exit ql3xxx_exit(void)
4189 {
4190         pci_unregister_driver(&ql3xxx_driver);
4191 }
4192
4193 module_init(ql3xxx_init_module);
4194 module_exit(ql3xxx_exit);