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[linux-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2010 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <scsi/fc/fc_fcoe.h>
44
45 #include "ixgbe.h"
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb_82599.h"
48 #include "ixgbe_sriov.h"
49
50 char ixgbe_driver_name[] = "ixgbe";
51 static const char ixgbe_driver_string[] =
52                               "Intel(R) 10 Gigabit PCI Express Network Driver";
53
54 #define DRV_VERSION "2.0.44-k2"
55 const char ixgbe_driver_version[] = DRV_VERSION;
56 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
57
58 static const struct ixgbe_info *ixgbe_info_tbl[] = {
59         [board_82598] = &ixgbe_82598_info,
60         [board_82599] = &ixgbe_82599_info,
61 };
62
63 /* ixgbe_pci_tbl - PCI Device ID Table
64  *
65  * Wildcard entries (PCI_ANY_ID) should come last
66  * Last entry must be all 0s
67  *
68  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69  *   Class, Class Mask, private data (not used) }
70  */
71 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
73          board_82598 },
74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
75          board_82598 },
76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
77          board_82598 },
78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
79          board_82598 },
80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
81          board_82598 },
82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
83          board_82598 },
84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
85          board_82598 },
86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
87          board_82598 },
88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
89          board_82598 },
90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
91          board_82598 },
92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
93          board_82598 },
94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
95          board_82598 },
96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
97          board_82599 },
98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
99          board_82599 },
100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
101          board_82599 },
102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
103          board_82599 },
104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
105          board_82599 },
106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
107          board_82599 },
108         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
109          board_82599 },
110         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
111          board_82599 },
112
113         /* required last entry */
114         {0, }
115 };
116 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
117
118 #ifdef CONFIG_IXGBE_DCA
119 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
120                             void *p);
121 static struct notifier_block dca_notifier = {
122         .notifier_call = ixgbe_notify_dca,
123         .next          = NULL,
124         .priority      = 0
125 };
126 #endif
127
128 #ifdef CONFIG_PCI_IOV
129 static unsigned int max_vfs;
130 module_param(max_vfs, uint, 0);
131 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
132                  "per physical function");
133 #endif /* CONFIG_PCI_IOV */
134
135 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
136 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
137 MODULE_LICENSE("GPL");
138 MODULE_VERSION(DRV_VERSION);
139
140 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
141
142 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
143 {
144         struct ixgbe_hw *hw = &adapter->hw;
145         u32 gcr;
146         u32 gpie;
147         u32 vmdctl;
148
149 #ifdef CONFIG_PCI_IOV
150         /* disable iov and allow time for transactions to clear */
151         pci_disable_sriov(adapter->pdev);
152 #endif
153
154         /* turn off device IOV mode */
155         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
156         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
157         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
158         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
159         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
160         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
161
162         /* set default pool back to 0 */
163         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
164         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
165         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
166
167         /* take a breather then clean up driver data */
168         msleep(100);
169         if (adapter->vfinfo)
170                 kfree(adapter->vfinfo);
171         adapter->vfinfo = NULL;
172
173         adapter->num_vfs = 0;
174         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
175 }
176
177 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
178 {
179         u32 ctrl_ext;
180
181         /* Let firmware take over control of h/w */
182         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
183         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
184                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
185 }
186
187 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
188 {
189         u32 ctrl_ext;
190
191         /* Let firmware know the driver has taken over */
192         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
193         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
194                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
195 }
196
197 /*
198  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
199  * @adapter: pointer to adapter struct
200  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
201  * @queue: queue to map the corresponding interrupt to
202  * @msix_vector: the vector to map to the corresponding queue
203  *
204  */
205 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
206                            u8 queue, u8 msix_vector)
207 {
208         u32 ivar, index;
209         struct ixgbe_hw *hw = &adapter->hw;
210         switch (hw->mac.type) {
211         case ixgbe_mac_82598EB:
212                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
213                 if (direction == -1)
214                         direction = 0;
215                 index = (((direction * 64) + queue) >> 2) & 0x1F;
216                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
217                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
218                 ivar |= (msix_vector << (8 * (queue & 0x3)));
219                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
220                 break;
221         case ixgbe_mac_82599EB:
222                 if (direction == -1) {
223                         /* other causes */
224                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
225                         index = ((queue & 1) * 8);
226                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
227                         ivar &= ~(0xFF << index);
228                         ivar |= (msix_vector << index);
229                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
230                         break;
231                 } else {
232                         /* tx or rx causes */
233                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
234                         index = ((16 * (queue & 1)) + (8 * direction));
235                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
236                         ivar &= ~(0xFF << index);
237                         ivar |= (msix_vector << index);
238                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
239                         break;
240                 }
241         default:
242                 break;
243         }
244 }
245
246 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
247                                           u64 qmask)
248 {
249         u32 mask;
250
251         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
252                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
253                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
254         } else {
255                 mask = (qmask & 0xFFFFFFFF);
256                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
257                 mask = (qmask >> 32);
258                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
259         }
260 }
261
262 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
263                                              struct ixgbe_tx_buffer
264                                              *tx_buffer_info)
265 {
266         if (tx_buffer_info->dma) {
267                 if (tx_buffer_info->mapped_as_page)
268                         pci_unmap_page(adapter->pdev,
269                                        tx_buffer_info->dma,
270                                        tx_buffer_info->length,
271                                        PCI_DMA_TODEVICE);
272                 else
273                         pci_unmap_single(adapter->pdev,
274                                          tx_buffer_info->dma,
275                                          tx_buffer_info->length,
276                                          PCI_DMA_TODEVICE);
277                 tx_buffer_info->dma = 0;
278         }
279         if (tx_buffer_info->skb) {
280                 dev_kfree_skb_any(tx_buffer_info->skb);
281                 tx_buffer_info->skb = NULL;
282         }
283         tx_buffer_info->time_stamp = 0;
284         /* tx_buffer_info must be completely set up in the transmit path */
285 }
286
287 /**
288  * ixgbe_tx_is_paused - check if the tx ring is paused
289  * @adapter: the ixgbe adapter
290  * @tx_ring: the corresponding tx_ring
291  *
292  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
293  * corresponding TC of this tx_ring when checking TFCS.
294  *
295  * Returns : true if paused
296  */
297 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
298                                       struct ixgbe_ring *tx_ring)
299 {
300         u32 txoff = IXGBE_TFCS_TXOFF;
301
302 #ifdef CONFIG_IXGBE_DCB
303         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
304                 int tc;
305                 int reg_idx = tx_ring->reg_idx;
306                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
307
308                 switch (adapter->hw.mac.type) {
309                 case ixgbe_mac_82598EB:
310                         tc = reg_idx >> 2;
311                         txoff = IXGBE_TFCS_TXOFF0;
312                         break;
313                 case ixgbe_mac_82599EB:
314                         tc = 0;
315                         txoff = IXGBE_TFCS_TXOFF;
316                         if (dcb_i == 8) {
317                                 /* TC0, TC1 */
318                                 tc = reg_idx >> 5;
319                                 if (tc == 2) /* TC2, TC3 */
320                                         tc += (reg_idx - 64) >> 4;
321                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
322                                         tc += 1 + ((reg_idx - 96) >> 3);
323                         } else if (dcb_i == 4) {
324                                 /* TC0, TC1 */
325                                 tc = reg_idx >> 6;
326                                 if (tc == 1) {
327                                         tc += (reg_idx - 64) >> 5;
328                                         if (tc == 2) /* TC2, TC3 */
329                                                 tc += (reg_idx - 96) >> 4;
330                                 }
331                         }
332                         break;
333                 default:
334                         tc = 0;
335                 }
336                 txoff <<= tc;
337         }
338 #endif
339         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
340 }
341
342 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
343                                        struct ixgbe_ring *tx_ring,
344                                        unsigned int eop)
345 {
346         struct ixgbe_hw *hw = &adapter->hw;
347
348         /* Detect a transmit hang in hardware, this serializes the
349          * check with the clearing of time_stamp and movement of eop */
350         adapter->detect_tx_hung = false;
351         if (tx_ring->tx_buffer_info[eop].time_stamp &&
352             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
353             !ixgbe_tx_is_paused(adapter, tx_ring)) {
354                 /* detected Tx unit hang */
355                 union ixgbe_adv_tx_desc *tx_desc;
356                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
357                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
358                         "  Tx Queue             <%d>\n"
359                         "  TDH, TDT             <%x>, <%x>\n"
360                         "  next_to_use          <%x>\n"
361                         "  next_to_clean        <%x>\n"
362                         "tx_buffer_info[next_to_clean]\n"
363                         "  time_stamp           <%lx>\n"
364                         "  jiffies              <%lx>\n",
365                         tx_ring->queue_index,
366                         IXGBE_READ_REG(hw, tx_ring->head),
367                         IXGBE_READ_REG(hw, tx_ring->tail),
368                         tx_ring->next_to_use, eop,
369                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
370                 return true;
371         }
372
373         return false;
374 }
375
376 #define IXGBE_MAX_TXD_PWR       14
377 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
378
379 /* Tx Descriptors needed, worst case */
380 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
381                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
382 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
383         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
384
385 static void ixgbe_tx_timeout(struct net_device *netdev);
386
387 /**
388  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
389  * @q_vector: structure containing interrupt and ring information
390  * @tx_ring: tx ring to clean
391  **/
392 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
393                                struct ixgbe_ring *tx_ring)
394 {
395         struct ixgbe_adapter *adapter = q_vector->adapter;
396         struct net_device *netdev = adapter->netdev;
397         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
398         struct ixgbe_tx_buffer *tx_buffer_info;
399         unsigned int i, eop, count = 0;
400         unsigned int total_bytes = 0, total_packets = 0;
401
402         i = tx_ring->next_to_clean;
403         eop = tx_ring->tx_buffer_info[i].next_to_watch;
404         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
405
406         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
407                (count < tx_ring->work_limit)) {
408                 bool cleaned = false;
409                 for ( ; !cleaned; count++) {
410                         struct sk_buff *skb;
411                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
412                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
413                         cleaned = (i == eop);
414                         skb = tx_buffer_info->skb;
415
416                         if (cleaned && skb) {
417                                 unsigned int segs, bytecount;
418                                 unsigned int hlen = skb_headlen(skb);
419
420                                 /* gso_segs is currently only valid for tcp */
421                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
422 #ifdef IXGBE_FCOE
423                                 /* adjust for FCoE Sequence Offload */
424                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
425                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
426                                     skb_is_gso(skb)) {
427                                         hlen = skb_transport_offset(skb) +
428                                                 sizeof(struct fc_frame_header) +
429                                                 sizeof(struct fcoe_crc_eof);
430                                         segs = DIV_ROUND_UP(skb->len - hlen,
431                                                 skb_shinfo(skb)->gso_size);
432                                 }
433 #endif /* IXGBE_FCOE */
434                                 /* multiply data chunks by size of headers */
435                                 bytecount = ((segs - 1) * hlen) + skb->len;
436                                 total_packets += segs;
437                                 total_bytes += bytecount;
438                         }
439
440                         ixgbe_unmap_and_free_tx_resource(adapter,
441                                                          tx_buffer_info);
442
443                         tx_desc->wb.status = 0;
444
445                         i++;
446                         if (i == tx_ring->count)
447                                 i = 0;
448                 }
449
450                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
451                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
452         }
453
454         tx_ring->next_to_clean = i;
455
456 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
457         if (unlikely(count && netif_carrier_ok(netdev) &&
458                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
459                 /* Make sure that anybody stopping the queue after this
460                  * sees the new next_to_clean.
461                  */
462                 smp_mb();
463                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
464                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
465                         netif_wake_subqueue(netdev, tx_ring->queue_index);
466                         ++tx_ring->restart_queue;
467                 }
468         }
469
470         if (adapter->detect_tx_hung) {
471                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
472                         /* schedule immediate reset if we believe we hung */
473                         DPRINTK(PROBE, INFO,
474                                 "tx hang %d detected, resetting adapter\n",
475                                 adapter->tx_timeout_count + 1);
476                         ixgbe_tx_timeout(adapter->netdev);
477                 }
478         }
479
480         /* re-arm the interrupt */
481         if (count >= tx_ring->work_limit)
482                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
483
484         tx_ring->total_bytes += total_bytes;
485         tx_ring->total_packets += total_packets;
486         tx_ring->stats.packets += total_packets;
487         tx_ring->stats.bytes += total_bytes;
488         return (count < tx_ring->work_limit);
489 }
490
491 #ifdef CONFIG_IXGBE_DCA
492 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
493                                 struct ixgbe_ring *rx_ring)
494 {
495         u32 rxctrl;
496         int cpu = get_cpu();
497         int q = rx_ring - adapter->rx_ring;
498
499         if (rx_ring->cpu != cpu) {
500                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
501                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
502                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
503                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
504                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
505                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
506                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
507                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
508                 }
509                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
510                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
511                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
512                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
513                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
514                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
515                 rx_ring->cpu = cpu;
516         }
517         put_cpu();
518 }
519
520 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
521                                 struct ixgbe_ring *tx_ring)
522 {
523         u32 txctrl;
524         int cpu = get_cpu();
525         int q = tx_ring - adapter->tx_ring;
526         struct ixgbe_hw *hw = &adapter->hw;
527
528         if (tx_ring->cpu != cpu) {
529                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
530                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
531                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
532                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
533                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
534                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
535                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
536                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
537                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
538                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
539                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
540                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
541                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
542                 }
543                 tx_ring->cpu = cpu;
544         }
545         put_cpu();
546 }
547
548 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
549 {
550         int i;
551
552         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
553                 return;
554
555         /* always use CB2 mode, difference is masked in the CB driver */
556         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
557
558         for (i = 0; i < adapter->num_tx_queues; i++) {
559                 adapter->tx_ring[i].cpu = -1;
560                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
561         }
562         for (i = 0; i < adapter->num_rx_queues; i++) {
563                 adapter->rx_ring[i].cpu = -1;
564                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
565         }
566 }
567
568 static int __ixgbe_notify_dca(struct device *dev, void *data)
569 {
570         struct net_device *netdev = dev_get_drvdata(dev);
571         struct ixgbe_adapter *adapter = netdev_priv(netdev);
572         unsigned long event = *(unsigned long *)data;
573
574         switch (event) {
575         case DCA_PROVIDER_ADD:
576                 /* if we're already enabled, don't do it again */
577                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
578                         break;
579                 if (dca_add_requester(dev) == 0) {
580                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
581                         ixgbe_setup_dca(adapter);
582                         break;
583                 }
584                 /* Fall Through since DCA is disabled. */
585         case DCA_PROVIDER_REMOVE:
586                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
587                         dca_remove_requester(dev);
588                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
589                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
590                 }
591                 break;
592         }
593
594         return 0;
595 }
596
597 #endif /* CONFIG_IXGBE_DCA */
598 /**
599  * ixgbe_receive_skb - Send a completed packet up the stack
600  * @adapter: board private structure
601  * @skb: packet to send up
602  * @status: hardware indication of status of receive
603  * @rx_ring: rx descriptor ring (for a specific queue) to setup
604  * @rx_desc: rx descriptor
605  **/
606 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
607                               struct sk_buff *skb, u8 status,
608                               struct ixgbe_ring *ring,
609                               union ixgbe_adv_rx_desc *rx_desc)
610 {
611         struct ixgbe_adapter *adapter = q_vector->adapter;
612         struct napi_struct *napi = &q_vector->napi;
613         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
614         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
615
616         skb_record_rx_queue(skb, ring->queue_index);
617         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
618                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
619                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
620                 else
621                         napi_gro_receive(napi, skb);
622         } else {
623                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
624                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
625                 else
626                         netif_rx(skb);
627         }
628 }
629
630 /**
631  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
632  * @adapter: address of board private structure
633  * @status_err: hardware indication of status of receive
634  * @skb: skb currently being received and modified
635  **/
636 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
637                                      union ixgbe_adv_rx_desc *rx_desc,
638                                      struct sk_buff *skb)
639 {
640         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
641
642         skb->ip_summed = CHECKSUM_NONE;
643
644         /* Rx csum disabled */
645         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
646                 return;
647
648         /* if IP and error */
649         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
650             (status_err & IXGBE_RXDADV_ERR_IPE)) {
651                 adapter->hw_csum_rx_error++;
652                 return;
653         }
654
655         if (!(status_err & IXGBE_RXD_STAT_L4CS))
656                 return;
657
658         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
659                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
660
661                 /*
662                  * 82599 errata, UDP frames with a 0 checksum can be marked as
663                  * checksum errors.
664                  */
665                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
666                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
667                         return;
668
669                 adapter->hw_csum_rx_error++;
670                 return;
671         }
672
673         /* It must be a TCP or UDP packet with a valid checksum */
674         skb->ip_summed = CHECKSUM_UNNECESSARY;
675 }
676
677 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
678                                          struct ixgbe_ring *rx_ring, u32 val)
679 {
680         /*
681          * Force memory writes to complete before letting h/w
682          * know there are new descriptors to fetch.  (Only
683          * applicable for weak-ordered memory model archs,
684          * such as IA-64).
685          */
686         wmb();
687         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
688 }
689
690 /**
691  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
692  * @adapter: address of board private structure
693  **/
694 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
695                                    struct ixgbe_ring *rx_ring,
696                                    int cleaned_count)
697 {
698         struct pci_dev *pdev = adapter->pdev;
699         union ixgbe_adv_rx_desc *rx_desc;
700         struct ixgbe_rx_buffer *bi;
701         unsigned int i;
702
703         i = rx_ring->next_to_use;
704         bi = &rx_ring->rx_buffer_info[i];
705
706         while (cleaned_count--) {
707                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
708
709                 if (!bi->page_dma &&
710                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
711                         if (!bi->page) {
712                                 bi->page = alloc_page(GFP_ATOMIC);
713                                 if (!bi->page) {
714                                         adapter->alloc_rx_page_failed++;
715                                         goto no_buffers;
716                                 }
717                                 bi->page_offset = 0;
718                         } else {
719                                 /* use a half page if we're re-using */
720                                 bi->page_offset ^= (PAGE_SIZE / 2);
721                         }
722
723                         bi->page_dma = pci_map_page(pdev, bi->page,
724                                                     bi->page_offset,
725                                                     (PAGE_SIZE / 2),
726                                                     PCI_DMA_FROMDEVICE);
727                 }
728
729                 if (!bi->skb) {
730                         struct sk_buff *skb;
731                         /* netdev_alloc_skb reserves 32 bytes up front!! */
732                         uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
733                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
734
735                         if (!skb) {
736                                 adapter->alloc_rx_buff_failed++;
737                                 goto no_buffers;
738                         }
739
740                         /* advance the data pointer to the next cache line */
741                         skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
742                                           - skb->data));
743
744                         bi->skb = skb;
745                         bi->dma = pci_map_single(pdev, skb->data,
746                                                  rx_ring->rx_buf_len,
747                                                  PCI_DMA_FROMDEVICE);
748                 }
749                 /* Refresh the desc even if buffer_addrs didn't change because
750                  * each write-back erases this info. */
751                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
752                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
753                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
754                 } else {
755                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
756                 }
757
758                 i++;
759                 if (i == rx_ring->count)
760                         i = 0;
761                 bi = &rx_ring->rx_buffer_info[i];
762         }
763
764 no_buffers:
765         if (rx_ring->next_to_use != i) {
766                 rx_ring->next_to_use = i;
767                 if (i-- == 0)
768                         i = (rx_ring->count - 1);
769
770                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
771         }
772 }
773
774 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
775 {
776         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
777 }
778
779 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
780 {
781         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
782 }
783
784 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
785 {
786         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
787                 IXGBE_RXDADV_RSCCNT_MASK) >>
788                 IXGBE_RXDADV_RSCCNT_SHIFT;
789 }
790
791 /**
792  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
793  * @skb: pointer to the last skb in the rsc queue
794  * @count: pointer to number of packets coalesced in this context
795  *
796  * This function changes a queue full of hw rsc buffers into a completed
797  * packet.  It uses the ->prev pointers to find the first packet and then
798  * turns it into the frag list owner.
799  **/
800 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
801                                                         u64 *count)
802 {
803         unsigned int frag_list_size = 0;
804
805         while (skb->prev) {
806                 struct sk_buff *prev = skb->prev;
807                 frag_list_size += skb->len;
808                 skb->prev = NULL;
809                 skb = prev;
810                 *count += 1;
811         }
812
813         skb_shinfo(skb)->frag_list = skb->next;
814         skb->next = NULL;
815         skb->len += frag_list_size;
816         skb->data_len += frag_list_size;
817         skb->truesize += frag_list_size;
818         return skb;
819 }
820
821 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
822                                struct ixgbe_ring *rx_ring,
823                                int *work_done, int work_to_do)
824 {
825         struct ixgbe_adapter *adapter = q_vector->adapter;
826         struct net_device *netdev = adapter->netdev;
827         struct pci_dev *pdev = adapter->pdev;
828         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
829         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
830         struct sk_buff *skb;
831         unsigned int i, rsc_count = 0;
832         u32 len, staterr;
833         u16 hdr_info;
834         bool cleaned = false;
835         int cleaned_count = 0;
836         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
837 #ifdef IXGBE_FCOE
838         int ddp_bytes = 0;
839 #endif /* IXGBE_FCOE */
840
841         i = rx_ring->next_to_clean;
842         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
843         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
844         rx_buffer_info = &rx_ring->rx_buffer_info[i];
845
846         while (staterr & IXGBE_RXD_STAT_DD) {
847                 u32 upper_len = 0;
848                 if (*work_done >= work_to_do)
849                         break;
850                 (*work_done)++;
851
852                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
853                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
854                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
855                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
856                         if (len > IXGBE_RX_HDR_SIZE)
857                                 len = IXGBE_RX_HDR_SIZE;
858                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
859                 } else {
860                         len = le16_to_cpu(rx_desc->wb.upper.length);
861                 }
862
863                 cleaned = true;
864                 skb = rx_buffer_info->skb;
865                 prefetch(skb->data);
866                 rx_buffer_info->skb = NULL;
867
868                 if (rx_buffer_info->dma) {
869                         pci_unmap_single(pdev, rx_buffer_info->dma,
870                                          rx_ring->rx_buf_len,
871                                          PCI_DMA_FROMDEVICE);
872                         rx_buffer_info->dma = 0;
873                         skb_put(skb, len);
874                 }
875
876                 if (upper_len) {
877                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
878                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
879                         rx_buffer_info->page_dma = 0;
880                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
881                                            rx_buffer_info->page,
882                                            rx_buffer_info->page_offset,
883                                            upper_len);
884
885                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
886                             (page_count(rx_buffer_info->page) != 1))
887                                 rx_buffer_info->page = NULL;
888                         else
889                                 get_page(rx_buffer_info->page);
890
891                         skb->len += upper_len;
892                         skb->data_len += upper_len;
893                         skb->truesize += upper_len;
894                 }
895
896                 i++;
897                 if (i == rx_ring->count)
898                         i = 0;
899
900                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
901                 prefetch(next_rxd);
902                 cleaned_count++;
903
904                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
905                         rsc_count = ixgbe_get_rsc_count(rx_desc);
906
907                 if (rsc_count) {
908                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
909                                      IXGBE_RXDADV_NEXTP_SHIFT;
910                         next_buffer = &rx_ring->rx_buffer_info[nextp];
911                 } else {
912                         next_buffer = &rx_ring->rx_buffer_info[i];
913                 }
914
915                 if (staterr & IXGBE_RXD_STAT_EOP) {
916                         if (skb->prev)
917                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
918                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
919                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
920                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
921                                 else
922                                         rx_ring->rsc_count++;
923                                 rx_ring->rsc_flush++;
924                         }
925                         rx_ring->stats.packets++;
926                         rx_ring->stats.bytes += skb->len;
927                 } else {
928                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
929                                 rx_buffer_info->skb = next_buffer->skb;
930                                 rx_buffer_info->dma = next_buffer->dma;
931                                 next_buffer->skb = skb;
932                                 next_buffer->dma = 0;
933                         } else {
934                                 skb->next = next_buffer->skb;
935                                 skb->next->prev = skb;
936                         }
937                         rx_ring->non_eop_descs++;
938                         goto next_desc;
939                 }
940
941                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
942                         dev_kfree_skb_irq(skb);
943                         goto next_desc;
944                 }
945
946                 ixgbe_rx_checksum(adapter, rx_desc, skb);
947
948                 /* probably a little skewed due to removing CRC */
949                 total_rx_bytes += skb->len;
950                 total_rx_packets++;
951
952                 skb->protocol = eth_type_trans(skb, adapter->netdev);
953 #ifdef IXGBE_FCOE
954                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
955                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
956                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
957                         if (!ddp_bytes)
958                                 goto next_desc;
959                 }
960 #endif /* IXGBE_FCOE */
961                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
962
963 next_desc:
964                 rx_desc->wb.upper.status_error = 0;
965
966                 /* return some buffers to hardware, one at a time is too slow */
967                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
968                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
969                         cleaned_count = 0;
970                 }
971
972                 /* use prefetched values */
973                 rx_desc = next_rxd;
974                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
975
976                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
977         }
978
979         rx_ring->next_to_clean = i;
980         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
981
982         if (cleaned_count)
983                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
984
985 #ifdef IXGBE_FCOE
986         /* include DDPed FCoE data */
987         if (ddp_bytes > 0) {
988                 unsigned int mss;
989
990                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
991                         sizeof(struct fc_frame_header) -
992                         sizeof(struct fcoe_crc_eof);
993                 if (mss > 512)
994                         mss &= ~511;
995                 total_rx_bytes += ddp_bytes;
996                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
997         }
998 #endif /* IXGBE_FCOE */
999
1000         rx_ring->total_packets += total_rx_packets;
1001         rx_ring->total_bytes += total_rx_bytes;
1002         netdev->stats.rx_bytes += total_rx_bytes;
1003         netdev->stats.rx_packets += total_rx_packets;
1004
1005         return cleaned;
1006 }
1007
1008 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1009 /**
1010  * ixgbe_configure_msix - Configure MSI-X hardware
1011  * @adapter: board private structure
1012  *
1013  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1014  * interrupts.
1015  **/
1016 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1017 {
1018         struct ixgbe_q_vector *q_vector;
1019         int i, j, q_vectors, v_idx, r_idx;
1020         u32 mask;
1021
1022         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1023
1024         /*
1025          * Populate the IVAR table and set the ITR values to the
1026          * corresponding register.
1027          */
1028         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1029                 q_vector = adapter->q_vector[v_idx];
1030                 /* XXX for_each_bit(...) */
1031                 r_idx = find_first_bit(q_vector->rxr_idx,
1032                                        adapter->num_rx_queues);
1033
1034                 for (i = 0; i < q_vector->rxr_count; i++) {
1035                         j = adapter->rx_ring[r_idx].reg_idx;
1036                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1037                         r_idx = find_next_bit(q_vector->rxr_idx,
1038                                               adapter->num_rx_queues,
1039                                               r_idx + 1);
1040                 }
1041                 r_idx = find_first_bit(q_vector->txr_idx,
1042                                        adapter->num_tx_queues);
1043
1044                 for (i = 0; i < q_vector->txr_count; i++) {
1045                         j = adapter->tx_ring[r_idx].reg_idx;
1046                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1047                         r_idx = find_next_bit(q_vector->txr_idx,
1048                                               adapter->num_tx_queues,
1049                                               r_idx + 1);
1050                 }
1051
1052                 if (q_vector->txr_count && !q_vector->rxr_count)
1053                         /* tx only */
1054                         q_vector->eitr = adapter->tx_eitr_param;
1055                 else if (q_vector->rxr_count)
1056                         /* rx or mixed */
1057                         q_vector->eitr = adapter->rx_eitr_param;
1058
1059                 ixgbe_write_eitr(q_vector);
1060         }
1061
1062         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1063                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1064                                v_idx);
1065         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1066                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1067         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1068
1069         /* set up to autoclear timer, and the vectors */
1070         mask = IXGBE_EIMS_ENABLE_MASK;
1071         if (adapter->num_vfs)
1072                 mask &= ~(IXGBE_EIMS_OTHER |
1073                           IXGBE_EIMS_MAILBOX |
1074                           IXGBE_EIMS_LSC);
1075         else
1076                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1077         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1078 }
1079
1080 enum latency_range {
1081         lowest_latency = 0,
1082         low_latency = 1,
1083         bulk_latency = 2,
1084         latency_invalid = 255
1085 };
1086
1087 /**
1088  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1089  * @adapter: pointer to adapter
1090  * @eitr: eitr setting (ints per sec) to give last timeslice
1091  * @itr_setting: current throttle rate in ints/second
1092  * @packets: the number of packets during this measurement interval
1093  * @bytes: the number of bytes during this measurement interval
1094  *
1095  *      Stores a new ITR value based on packets and byte
1096  *      counts during the last interrupt.  The advantage of per interrupt
1097  *      computation is faster updates and more accurate ITR for the current
1098  *      traffic pattern.  Constants in this function were computed
1099  *      based on theoretical maximum wire speed and thresholds were set based
1100  *      on testing data as well as attempting to minimize response time
1101  *      while increasing bulk throughput.
1102  *      this functionality is controlled by the InterruptThrottleRate module
1103  *      parameter (see ixgbe_param.c)
1104  **/
1105 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1106                            u32 eitr, u8 itr_setting,
1107                            int packets, int bytes)
1108 {
1109         unsigned int retval = itr_setting;
1110         u32 timepassed_us;
1111         u64 bytes_perint;
1112
1113         if (packets == 0)
1114                 goto update_itr_done;
1115
1116
1117         /* simple throttlerate management
1118          *    0-20MB/s lowest (100000 ints/s)
1119          *   20-100MB/s low   (20000 ints/s)
1120          *  100-1249MB/s bulk (8000 ints/s)
1121          */
1122         /* what was last interrupt timeslice? */
1123         timepassed_us = 1000000/eitr;
1124         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1125
1126         switch (itr_setting) {
1127         case lowest_latency:
1128                 if (bytes_perint > adapter->eitr_low)
1129                         retval = low_latency;
1130                 break;
1131         case low_latency:
1132                 if (bytes_perint > adapter->eitr_high)
1133                         retval = bulk_latency;
1134                 else if (bytes_perint <= adapter->eitr_low)
1135                         retval = lowest_latency;
1136                 break;
1137         case bulk_latency:
1138                 if (bytes_perint <= adapter->eitr_high)
1139                         retval = low_latency;
1140                 break;
1141         }
1142
1143 update_itr_done:
1144         return retval;
1145 }
1146
1147 /**
1148  * ixgbe_write_eitr - write EITR register in hardware specific way
1149  * @q_vector: structure containing interrupt and ring information
1150  *
1151  * This function is made to be called by ethtool and by the driver
1152  * when it needs to update EITR registers at runtime.  Hardware
1153  * specific quirks/differences are taken care of here.
1154  */
1155 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1156 {
1157         struct ixgbe_adapter *adapter = q_vector->adapter;
1158         struct ixgbe_hw *hw = &adapter->hw;
1159         int v_idx = q_vector->v_idx;
1160         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1161
1162         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1163                 /* must write high and low 16 bits to reset counter */
1164                 itr_reg |= (itr_reg << 16);
1165         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1166                 /*
1167                  * set the WDIS bit to not clear the timer bits and cause an
1168                  * immediate assertion of the interrupt
1169                  */
1170                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1171         }
1172         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1173 }
1174
1175 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1176 {
1177         struct ixgbe_adapter *adapter = q_vector->adapter;
1178         u32 new_itr;
1179         u8 current_itr, ret_itr;
1180         int i, r_idx;
1181         struct ixgbe_ring *rx_ring, *tx_ring;
1182
1183         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1184         for (i = 0; i < q_vector->txr_count; i++) {
1185                 tx_ring = &(adapter->tx_ring[r_idx]);
1186                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1187                                            q_vector->tx_itr,
1188                                            tx_ring->total_packets,
1189                                            tx_ring->total_bytes);
1190                 /* if the result for this queue would decrease interrupt
1191                  * rate for this vector then use that result */
1192                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1193                                     q_vector->tx_itr - 1 : ret_itr);
1194                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1195                                       r_idx + 1);
1196         }
1197
1198         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1199         for (i = 0; i < q_vector->rxr_count; i++) {
1200                 rx_ring = &(adapter->rx_ring[r_idx]);
1201                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1202                                            q_vector->rx_itr,
1203                                            rx_ring->total_packets,
1204                                            rx_ring->total_bytes);
1205                 /* if the result for this queue would decrease interrupt
1206                  * rate for this vector then use that result */
1207                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1208                                     q_vector->rx_itr - 1 : ret_itr);
1209                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1210                                       r_idx + 1);
1211         }
1212
1213         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1214
1215         switch (current_itr) {
1216         /* counts and packets in update_itr are dependent on these numbers */
1217         case lowest_latency:
1218                 new_itr = 100000;
1219                 break;
1220         case low_latency:
1221                 new_itr = 20000; /* aka hwitr = ~200 */
1222                 break;
1223         case bulk_latency:
1224         default:
1225                 new_itr = 8000;
1226                 break;
1227         }
1228
1229         if (new_itr != q_vector->eitr) {
1230                 /* do an exponential smoothing */
1231                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1232
1233                 /* save the algorithm value here, not the smoothed one */
1234                 q_vector->eitr = new_itr;
1235
1236                 ixgbe_write_eitr(q_vector);
1237         }
1238
1239         return;
1240 }
1241
1242 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1243 {
1244         struct ixgbe_hw *hw = &adapter->hw;
1245
1246         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1247             (eicr & IXGBE_EICR_GPI_SDP1)) {
1248                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1249                 /* write to clear the interrupt */
1250                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1251         }
1252 }
1253
1254 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1255 {
1256         struct ixgbe_hw *hw = &adapter->hw;
1257
1258         if (eicr & IXGBE_EICR_GPI_SDP1) {
1259                 /* Clear the interrupt */
1260                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1261                 schedule_work(&adapter->multispeed_fiber_task);
1262         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1263                 /* Clear the interrupt */
1264                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1265                 schedule_work(&adapter->sfp_config_module_task);
1266         } else {
1267                 /* Interrupt isn't for us... */
1268                 return;
1269         }
1270 }
1271
1272 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1273 {
1274         struct ixgbe_hw *hw = &adapter->hw;
1275
1276         adapter->lsc_int++;
1277         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1278         adapter->link_check_timeout = jiffies;
1279         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1280                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1281                 IXGBE_WRITE_FLUSH(hw);
1282                 schedule_work(&adapter->watchdog_task);
1283         }
1284 }
1285
1286 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1287 {
1288         struct net_device *netdev = data;
1289         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1290         struct ixgbe_hw *hw = &adapter->hw;
1291         u32 eicr;
1292
1293         /*
1294          * Workaround for Silicon errata.  Use clear-by-write instead
1295          * of clear-by-read.  Reading with EICS will return the
1296          * interrupt causes without clearing, which later be done
1297          * with the write to EICR.
1298          */
1299         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1300         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1301
1302         if (eicr & IXGBE_EICR_LSC)
1303                 ixgbe_check_lsc(adapter);
1304
1305         if (eicr & IXGBE_EICR_MAILBOX)
1306                 ixgbe_msg_task(adapter);
1307
1308         if (hw->mac.type == ixgbe_mac_82598EB)
1309                 ixgbe_check_fan_failure(adapter, eicr);
1310
1311         if (hw->mac.type == ixgbe_mac_82599EB) {
1312                 ixgbe_check_sfp_event(adapter, eicr);
1313
1314                 /* Handle Flow Director Full threshold interrupt */
1315                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1316                         int i;
1317                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1318                         /* Disable transmits before FDIR Re-initialization */
1319                         netif_tx_stop_all_queues(netdev);
1320                         for (i = 0; i < adapter->num_tx_queues; i++) {
1321                                 struct ixgbe_ring *tx_ring =
1322                                                            &adapter->tx_ring[i];
1323                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1324                                                        &tx_ring->reinit_state))
1325                                         schedule_work(&adapter->fdir_reinit_task);
1326                         }
1327                 }
1328         }
1329         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1330                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1331
1332         return IRQ_HANDLED;
1333 }
1334
1335 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1336                                            u64 qmask)
1337 {
1338         u32 mask;
1339
1340         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1341                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1342                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1343         } else {
1344                 mask = (qmask & 0xFFFFFFFF);
1345                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1346                 mask = (qmask >> 32);
1347                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1348         }
1349         /* skip the flush */
1350 }
1351
1352 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1353                                             u64 qmask)
1354 {
1355         u32 mask;
1356
1357         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1358                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1359                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1360         } else {
1361                 mask = (qmask & 0xFFFFFFFF);
1362                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1363                 mask = (qmask >> 32);
1364                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1365         }
1366         /* skip the flush */
1367 }
1368
1369 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1370 {
1371         struct ixgbe_q_vector *q_vector = data;
1372         struct ixgbe_adapter  *adapter = q_vector->adapter;
1373         struct ixgbe_ring     *tx_ring;
1374         int i, r_idx;
1375
1376         if (!q_vector->txr_count)
1377                 return IRQ_HANDLED;
1378
1379         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1380         for (i = 0; i < q_vector->txr_count; i++) {
1381                 tx_ring = &(adapter->tx_ring[r_idx]);
1382                 tx_ring->total_bytes = 0;
1383                 tx_ring->total_packets = 0;
1384                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1385                                       r_idx + 1);
1386         }
1387
1388         /* EIAM disabled interrupts (on this vector) for us */
1389         napi_schedule(&q_vector->napi);
1390
1391         return IRQ_HANDLED;
1392 }
1393
1394 /**
1395  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1396  * @irq: unused
1397  * @data: pointer to our q_vector struct for this interrupt vector
1398  **/
1399 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1400 {
1401         struct ixgbe_q_vector *q_vector = data;
1402         struct ixgbe_adapter  *adapter = q_vector->adapter;
1403         struct ixgbe_ring  *rx_ring;
1404         int r_idx;
1405         int i;
1406
1407         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1408         for (i = 0;  i < q_vector->rxr_count; i++) {
1409                 rx_ring = &(adapter->rx_ring[r_idx]);
1410                 rx_ring->total_bytes = 0;
1411                 rx_ring->total_packets = 0;
1412                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1413                                       r_idx + 1);
1414         }
1415
1416         if (!q_vector->rxr_count)
1417                 return IRQ_HANDLED;
1418
1419         /* disable interrupts on this vector only */
1420         /* EIAM disabled interrupts (on this vector) for us */
1421         napi_schedule(&q_vector->napi);
1422
1423         return IRQ_HANDLED;
1424 }
1425
1426 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1427 {
1428         struct ixgbe_q_vector *q_vector = data;
1429         struct ixgbe_adapter  *adapter = q_vector->adapter;
1430         struct ixgbe_ring  *ring;
1431         int r_idx;
1432         int i;
1433
1434         if (!q_vector->txr_count && !q_vector->rxr_count)
1435                 return IRQ_HANDLED;
1436
1437         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1438         for (i = 0; i < q_vector->txr_count; i++) {
1439                 ring = &(adapter->tx_ring[r_idx]);
1440                 ring->total_bytes = 0;
1441                 ring->total_packets = 0;
1442                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1443                                       r_idx + 1);
1444         }
1445
1446         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1447         for (i = 0; i < q_vector->rxr_count; i++) {
1448                 ring = &(adapter->rx_ring[r_idx]);
1449                 ring->total_bytes = 0;
1450                 ring->total_packets = 0;
1451                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1452                                       r_idx + 1);
1453         }
1454
1455         /* EIAM disabled interrupts (on this vector) for us */
1456         napi_schedule(&q_vector->napi);
1457
1458         return IRQ_HANDLED;
1459 }
1460
1461 /**
1462  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1463  * @napi: napi struct with our devices info in it
1464  * @budget: amount of work driver is allowed to do this pass, in packets
1465  *
1466  * This function is optimized for cleaning one queue only on a single
1467  * q_vector!!!
1468  **/
1469 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1470 {
1471         struct ixgbe_q_vector *q_vector =
1472                                container_of(napi, struct ixgbe_q_vector, napi);
1473         struct ixgbe_adapter *adapter = q_vector->adapter;
1474         struct ixgbe_ring *rx_ring = NULL;
1475         int work_done = 0;
1476         long r_idx;
1477
1478         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1479         rx_ring = &(adapter->rx_ring[r_idx]);
1480 #ifdef CONFIG_IXGBE_DCA
1481         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1482                 ixgbe_update_rx_dca(adapter, rx_ring);
1483 #endif
1484
1485         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1486
1487         /* If all Rx work done, exit the polling mode */
1488         if (work_done < budget) {
1489                 napi_complete(napi);
1490                 if (adapter->rx_itr_setting & 1)
1491                         ixgbe_set_itr_msix(q_vector);
1492                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1493                         ixgbe_irq_enable_queues(adapter,
1494                                                 ((u64)1 << q_vector->v_idx));
1495         }
1496
1497         return work_done;
1498 }
1499
1500 /**
1501  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1502  * @napi: napi struct with our devices info in it
1503  * @budget: amount of work driver is allowed to do this pass, in packets
1504  *
1505  * This function will clean more than one rx queue associated with a
1506  * q_vector.
1507  **/
1508 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1509 {
1510         struct ixgbe_q_vector *q_vector =
1511                                container_of(napi, struct ixgbe_q_vector, napi);
1512         struct ixgbe_adapter *adapter = q_vector->adapter;
1513         struct ixgbe_ring *ring = NULL;
1514         int work_done = 0, i;
1515         long r_idx;
1516         bool tx_clean_complete = true;
1517
1518         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1519         for (i = 0; i < q_vector->txr_count; i++) {
1520                 ring = &(adapter->tx_ring[r_idx]);
1521 #ifdef CONFIG_IXGBE_DCA
1522                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1523                         ixgbe_update_tx_dca(adapter, ring);
1524 #endif
1525                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1526                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1527                                       r_idx + 1);
1528         }
1529
1530         /* attempt to distribute budget to each queue fairly, but don't allow
1531          * the budget to go below 1 because we'll exit polling */
1532         budget /= (q_vector->rxr_count ?: 1);
1533         budget = max(budget, 1);
1534         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1535         for (i = 0; i < q_vector->rxr_count; i++) {
1536                 ring = &(adapter->rx_ring[r_idx]);
1537 #ifdef CONFIG_IXGBE_DCA
1538                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1539                         ixgbe_update_rx_dca(adapter, ring);
1540 #endif
1541                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1542                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1543                                       r_idx + 1);
1544         }
1545
1546         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1547         ring = &(adapter->rx_ring[r_idx]);
1548         /* If all Rx work done, exit the polling mode */
1549         if (work_done < budget) {
1550                 napi_complete(napi);
1551                 if (adapter->rx_itr_setting & 1)
1552                         ixgbe_set_itr_msix(q_vector);
1553                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1554                         ixgbe_irq_enable_queues(adapter,
1555                                                 ((u64)1 << q_vector->v_idx));
1556                 return 0;
1557         }
1558
1559         return work_done;
1560 }
1561
1562 /**
1563  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1564  * @napi: napi struct with our devices info in it
1565  * @budget: amount of work driver is allowed to do this pass, in packets
1566  *
1567  * This function is optimized for cleaning one queue only on a single
1568  * q_vector!!!
1569  **/
1570 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1571 {
1572         struct ixgbe_q_vector *q_vector =
1573                                container_of(napi, struct ixgbe_q_vector, napi);
1574         struct ixgbe_adapter *adapter = q_vector->adapter;
1575         struct ixgbe_ring *tx_ring = NULL;
1576         int work_done = 0;
1577         long r_idx;
1578
1579         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1580         tx_ring = &(adapter->tx_ring[r_idx]);
1581 #ifdef CONFIG_IXGBE_DCA
1582         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1583                 ixgbe_update_tx_dca(adapter, tx_ring);
1584 #endif
1585
1586         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1587                 work_done = budget;
1588
1589         /* If all Tx work done, exit the polling mode */
1590         if (work_done < budget) {
1591                 napi_complete(napi);
1592                 if (adapter->tx_itr_setting & 1)
1593                         ixgbe_set_itr_msix(q_vector);
1594                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1595                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1596         }
1597
1598         return work_done;
1599 }
1600
1601 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1602                                      int r_idx)
1603 {
1604         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1605
1606         set_bit(r_idx, q_vector->rxr_idx);
1607         q_vector->rxr_count++;
1608 }
1609
1610 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1611                                      int t_idx)
1612 {
1613         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1614
1615         set_bit(t_idx, q_vector->txr_idx);
1616         q_vector->txr_count++;
1617 }
1618
1619 /**
1620  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1621  * @adapter: board private structure to initialize
1622  * @vectors: allotted vector count for descriptor rings
1623  *
1624  * This function maps descriptor rings to the queue-specific vectors
1625  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1626  * one vector per ring/queue, but on a constrained vector budget, we
1627  * group the rings as "efficiently" as possible.  You would add new
1628  * mapping configurations in here.
1629  **/
1630 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1631                                       int vectors)
1632 {
1633         int v_start = 0;
1634         int rxr_idx = 0, txr_idx = 0;
1635         int rxr_remaining = adapter->num_rx_queues;
1636         int txr_remaining = adapter->num_tx_queues;
1637         int i, j;
1638         int rqpv, tqpv;
1639         int err = 0;
1640
1641         /* No mapping required if MSI-X is disabled. */
1642         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1643                 goto out;
1644
1645         /*
1646          * The ideal configuration...
1647          * We have enough vectors to map one per queue.
1648          */
1649         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1650                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1651                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1652
1653                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1654                         map_vector_to_txq(adapter, v_start, txr_idx);
1655
1656                 goto out;
1657         }
1658
1659         /*
1660          * If we don't have enough vectors for a 1-to-1
1661          * mapping, we'll have to group them so there are
1662          * multiple queues per vector.
1663          */
1664         /* Re-adjusting *qpv takes care of the remainder. */
1665         for (i = v_start; i < vectors; i++) {
1666                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1667                 for (j = 0; j < rqpv; j++) {
1668                         map_vector_to_rxq(adapter, i, rxr_idx);
1669                         rxr_idx++;
1670                         rxr_remaining--;
1671                 }
1672         }
1673         for (i = v_start; i < vectors; i++) {
1674                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1675                 for (j = 0; j < tqpv; j++) {
1676                         map_vector_to_txq(adapter, i, txr_idx);
1677                         txr_idx++;
1678                         txr_remaining--;
1679                 }
1680         }
1681
1682 out:
1683         return err;
1684 }
1685
1686 /**
1687  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1688  * @adapter: board private structure
1689  *
1690  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1691  * interrupts from the kernel.
1692  **/
1693 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1694 {
1695         struct net_device *netdev = adapter->netdev;
1696         irqreturn_t (*handler)(int, void *);
1697         int i, vector, q_vectors, err;
1698         int ri=0, ti=0;
1699
1700         /* Decrement for Other and TCP Timer vectors */
1701         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1702
1703         /* Map the Tx/Rx rings to the vectors we were allotted. */
1704         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1705         if (err)
1706                 goto out;
1707
1708 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1709                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1710                          &ixgbe_msix_clean_many)
1711         for (vector = 0; vector < q_vectors; vector++) {
1712                 handler = SET_HANDLER(adapter->q_vector[vector]);
1713
1714                 if(handler == &ixgbe_msix_clean_rx) {
1715                         sprintf(adapter->name[vector], "%s-%s-%d",
1716                                 netdev->name, "rx", ri++);
1717                 }
1718                 else if(handler == &ixgbe_msix_clean_tx) {
1719                         sprintf(adapter->name[vector], "%s-%s-%d",
1720                                 netdev->name, "tx", ti++);
1721                 }
1722                 else
1723                         sprintf(adapter->name[vector], "%s-%s-%d",
1724                                 netdev->name, "TxRx", vector);
1725
1726                 err = request_irq(adapter->msix_entries[vector].vector,
1727                                   handler, 0, adapter->name[vector],
1728                                   adapter->q_vector[vector]);
1729                 if (err) {
1730                         DPRINTK(PROBE, ERR,
1731                                 "request_irq failed for MSIX interrupt "
1732                                 "Error: %d\n", err);
1733                         goto free_queue_irqs;
1734                 }
1735         }
1736
1737         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1738         err = request_irq(adapter->msix_entries[vector].vector,
1739                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1740         if (err) {
1741                 DPRINTK(PROBE, ERR,
1742                         "request_irq for msix_lsc failed: %d\n", err);
1743                 goto free_queue_irqs;
1744         }
1745
1746         return 0;
1747
1748 free_queue_irqs:
1749         for (i = vector - 1; i >= 0; i--)
1750                 free_irq(adapter->msix_entries[--vector].vector,
1751                          adapter->q_vector[i]);
1752         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1753         pci_disable_msix(adapter->pdev);
1754         kfree(adapter->msix_entries);
1755         adapter->msix_entries = NULL;
1756 out:
1757         return err;
1758 }
1759
1760 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1761 {
1762         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1763         u8 current_itr;
1764         u32 new_itr = q_vector->eitr;
1765         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1766         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1767
1768         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1769                                             q_vector->tx_itr,
1770                                             tx_ring->total_packets,
1771                                             tx_ring->total_bytes);
1772         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1773                                             q_vector->rx_itr,
1774                                             rx_ring->total_packets,
1775                                             rx_ring->total_bytes);
1776
1777         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1778
1779         switch (current_itr) {
1780         /* counts and packets in update_itr are dependent on these numbers */
1781         case lowest_latency:
1782                 new_itr = 100000;
1783                 break;
1784         case low_latency:
1785                 new_itr = 20000; /* aka hwitr = ~200 */
1786                 break;
1787         case bulk_latency:
1788                 new_itr = 8000;
1789                 break;
1790         default:
1791                 break;
1792         }
1793
1794         if (new_itr != q_vector->eitr) {
1795                 /* do an exponential smoothing */
1796                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1797
1798                 /* save the algorithm value here, not the smoothed one */
1799                 q_vector->eitr = new_itr;
1800
1801                 ixgbe_write_eitr(q_vector);
1802         }
1803
1804         return;
1805 }
1806
1807 /**
1808  * ixgbe_irq_enable - Enable default interrupt generation settings
1809  * @adapter: board private structure
1810  **/
1811 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1812 {
1813         u32 mask;
1814
1815         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1816         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1817                 mask |= IXGBE_EIMS_GPI_SDP1;
1818         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1819                 mask |= IXGBE_EIMS_ECC;
1820                 mask |= IXGBE_EIMS_GPI_SDP1;
1821                 mask |= IXGBE_EIMS_GPI_SDP2;
1822                 if (adapter->num_vfs)
1823                         mask |= IXGBE_EIMS_MAILBOX;
1824         }
1825         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1826             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1827                 mask |= IXGBE_EIMS_FLOW_DIR;
1828
1829         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1830         ixgbe_irq_enable_queues(adapter, ~0);
1831         IXGBE_WRITE_FLUSH(&adapter->hw);
1832
1833         if (adapter->num_vfs > 32) {
1834                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1835                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1836         }
1837 }
1838
1839 /**
1840  * ixgbe_intr - legacy mode Interrupt Handler
1841  * @irq: interrupt number
1842  * @data: pointer to a network interface device structure
1843  **/
1844 static irqreturn_t ixgbe_intr(int irq, void *data)
1845 {
1846         struct net_device *netdev = data;
1847         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1848         struct ixgbe_hw *hw = &adapter->hw;
1849         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1850         u32 eicr;
1851
1852         /*
1853          * Workaround for silicon errata.  Mask the interrupts
1854          * before the read of EICR.
1855          */
1856         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1857
1858         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1859          * therefore no explict interrupt disable is necessary */
1860         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1861         if (!eicr) {
1862                 /* shared interrupt alert!
1863                  * make sure interrupts are enabled because the read will
1864                  * have disabled interrupts due to EIAM */
1865                 ixgbe_irq_enable(adapter);
1866                 return IRQ_NONE;        /* Not our interrupt */
1867         }
1868
1869         if (eicr & IXGBE_EICR_LSC)
1870                 ixgbe_check_lsc(adapter);
1871
1872         if (hw->mac.type == ixgbe_mac_82599EB)
1873                 ixgbe_check_sfp_event(adapter, eicr);
1874
1875         ixgbe_check_fan_failure(adapter, eicr);
1876
1877         if (napi_schedule_prep(&(q_vector->napi))) {
1878                 adapter->tx_ring[0].total_packets = 0;
1879                 adapter->tx_ring[0].total_bytes = 0;
1880                 adapter->rx_ring[0].total_packets = 0;
1881                 adapter->rx_ring[0].total_bytes = 0;
1882                 /* would disable interrupts here but EIAM disabled it */
1883                 __napi_schedule(&(q_vector->napi));
1884         }
1885
1886         return IRQ_HANDLED;
1887 }
1888
1889 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1890 {
1891         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1892
1893         for (i = 0; i < q_vectors; i++) {
1894                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1895                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1896                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1897                 q_vector->rxr_count = 0;
1898                 q_vector->txr_count = 0;
1899         }
1900 }
1901
1902 /**
1903  * ixgbe_request_irq - initialize interrupts
1904  * @adapter: board private structure
1905  *
1906  * Attempts to configure interrupts using the best available
1907  * capabilities of the hardware and kernel.
1908  **/
1909 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1910 {
1911         struct net_device *netdev = adapter->netdev;
1912         int err;
1913
1914         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1915                 err = ixgbe_request_msix_irqs(adapter);
1916         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1917                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
1918                                   netdev->name, netdev);
1919         } else {
1920                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
1921                                   netdev->name, netdev);
1922         }
1923
1924         if (err)
1925                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1926
1927         return err;
1928 }
1929
1930 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1931 {
1932         struct net_device *netdev = adapter->netdev;
1933
1934         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1935                 int i, q_vectors;
1936
1937                 q_vectors = adapter->num_msix_vectors;
1938
1939                 i = q_vectors - 1;
1940                 free_irq(adapter->msix_entries[i].vector, netdev);
1941
1942                 i--;
1943                 for (; i >= 0; i--) {
1944                         free_irq(adapter->msix_entries[i].vector,
1945                                  adapter->q_vector[i]);
1946                 }
1947
1948                 ixgbe_reset_q_vectors(adapter);
1949         } else {
1950                 free_irq(adapter->pdev->irq, netdev);
1951         }
1952 }
1953
1954 /**
1955  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1956  * @adapter: board private structure
1957  **/
1958 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1959 {
1960         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1961                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1962         } else {
1963                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1964                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1965                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1966                 if (adapter->num_vfs > 32)
1967                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
1968         }
1969         IXGBE_WRITE_FLUSH(&adapter->hw);
1970         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1971                 int i;
1972                 for (i = 0; i < adapter->num_msix_vectors; i++)
1973                         synchronize_irq(adapter->msix_entries[i].vector);
1974         } else {
1975                 synchronize_irq(adapter->pdev->irq);
1976         }
1977 }
1978
1979 /**
1980  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1981  *
1982  **/
1983 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1984 {
1985         struct ixgbe_hw *hw = &adapter->hw;
1986
1987         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1988                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1989
1990         ixgbe_set_ivar(adapter, 0, 0, 0);
1991         ixgbe_set_ivar(adapter, 1, 0, 0);
1992
1993         map_vector_to_rxq(adapter, 0, 0);
1994         map_vector_to_txq(adapter, 0, 0);
1995
1996         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1997 }
1998
1999 /**
2000  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2001  * @adapter: board private structure
2002  *
2003  * Configure the Tx unit of the MAC after a reset.
2004  **/
2005 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2006 {
2007         u64 tdba;
2008         struct ixgbe_hw *hw = &adapter->hw;
2009         u32 i, j, tdlen, txctrl;
2010
2011         /* Setup the HW Tx Head and Tail descriptor pointers */
2012         for (i = 0; i < adapter->num_tx_queues; i++) {
2013                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
2014                 j = ring->reg_idx;
2015                 tdba = ring->dma;
2016                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2017                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2018                                 (tdba & DMA_BIT_MASK(32)));
2019                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2020                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2021                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2022                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2023                 adapter->tx_ring[i].head = IXGBE_TDH(j);
2024                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
2025                 /*
2026                  * Disable Tx Head Writeback RO bit, since this hoses
2027                  * bookkeeping if things aren't delivered in order.
2028                  */
2029                 switch (hw->mac.type) {
2030                 case ixgbe_mac_82598EB:
2031                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2032                         break;
2033                 case ixgbe_mac_82599EB:
2034                 default:
2035                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2036                         break;
2037                 }
2038                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2039                 switch (hw->mac.type) {
2040                 case ixgbe_mac_82598EB:
2041                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2042                         break;
2043                 case ixgbe_mac_82599EB:
2044                 default:
2045                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2046                         break;
2047                 }
2048         }
2049
2050         if (hw->mac.type == ixgbe_mac_82599EB) {
2051                 u32 rttdcs;
2052                 u32 mask;
2053
2054                 /* disable the arbiter while setting MTQC */
2055                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2056                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2057                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2058
2059                 /* set transmit pool layout */
2060                 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2061                 switch (adapter->flags & mask) {
2062
2063                 case (IXGBE_FLAG_SRIOV_ENABLED):
2064                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2065                                         (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2066                         break;
2067
2068                 case (IXGBE_FLAG_DCB_ENABLED):
2069                         /* We enable 8 traffic classes, DCB only */
2070                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2071                                       (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2072                         break;
2073
2074                 default:
2075                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2076                         break;
2077                 }
2078
2079                 /* re-eable the arbiter */
2080                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2081                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2082         }
2083 }
2084
2085 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2086
2087 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2088                                    struct ixgbe_ring *rx_ring)
2089 {
2090         u32 srrctl;
2091         int index;
2092         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2093
2094         index = rx_ring->reg_idx;
2095         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2096                 unsigned long mask;
2097                 mask = (unsigned long) feature[RING_F_RSS].mask;
2098                 index = index & mask;
2099         }
2100         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2101
2102         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2103         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2104
2105         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2106                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2107
2108         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2109 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2110                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2111 #else
2112                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2113 #endif
2114                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2115         } else {
2116                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2117                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2118                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2119         }
2120
2121         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2122 }
2123
2124 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2125 {
2126         u32 mrqc = 0;
2127         int mask;
2128
2129         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2130                 return mrqc;
2131
2132         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2133 #ifdef CONFIG_IXGBE_DCB
2134                                  | IXGBE_FLAG_DCB_ENABLED
2135 #endif
2136                                  | IXGBE_FLAG_SRIOV_ENABLED
2137                                 );
2138
2139         switch (mask) {
2140         case (IXGBE_FLAG_RSS_ENABLED):
2141                 mrqc = IXGBE_MRQC_RSSEN;
2142                 break;
2143         case (IXGBE_FLAG_SRIOV_ENABLED):
2144                 mrqc = IXGBE_MRQC_VMDQEN;
2145                 break;
2146 #ifdef CONFIG_IXGBE_DCB
2147         case (IXGBE_FLAG_DCB_ENABLED):
2148                 mrqc = IXGBE_MRQC_RT8TCEN;
2149                 break;
2150 #endif /* CONFIG_IXGBE_DCB */
2151         default:
2152                 break;
2153         }
2154
2155         return mrqc;
2156 }
2157
2158 /**
2159  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2160  * @adapter:    address of board private structure
2161  * @index:      index of ring to set
2162  **/
2163 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2164 {
2165         struct ixgbe_ring *rx_ring;
2166         struct ixgbe_hw *hw = &adapter->hw;
2167         int j;
2168         u32 rscctrl;
2169         int rx_buf_len;
2170
2171         rx_ring = &adapter->rx_ring[index];
2172         j = rx_ring->reg_idx;
2173         rx_buf_len = rx_ring->rx_buf_len;
2174         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2175         rscctrl |= IXGBE_RSCCTL_RSCEN;
2176         /*
2177          * we must limit the number of descriptors so that the
2178          * total size of max desc * buf_len is not greater
2179          * than 65535
2180          */
2181         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2182 #if (MAX_SKB_FRAGS > 16)
2183                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2184 #elif (MAX_SKB_FRAGS > 8)
2185                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2186 #elif (MAX_SKB_FRAGS > 4)
2187                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2188 #else
2189                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2190 #endif
2191         } else {
2192                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2193                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2194                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2195                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2196                 else
2197                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2198         }
2199         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2200 }
2201
2202 /**
2203  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2204  * @adapter: board private structure
2205  *
2206  * Configure the Rx unit of the MAC after a reset.
2207  **/
2208 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2209 {
2210         u64 rdba;
2211         struct ixgbe_hw *hw = &adapter->hw;
2212         struct ixgbe_ring *rx_ring;
2213         struct net_device *netdev = adapter->netdev;
2214         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2215         int i, j;
2216         u32 rdlen, rxctrl, rxcsum;
2217         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2218                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2219                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2220         u32 fctrl, hlreg0;
2221         u32 reta = 0, mrqc = 0;
2222         u32 rdrxctl;
2223         int rx_buf_len;
2224
2225         /* Decide whether to use packet split mode or not */
2226         /* Do not use packet split if we're in SR-IOV Mode */
2227         if (!adapter->num_vfs)
2228                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2229
2230         /* Set the RX buffer length according to the mode */
2231         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2232                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2233                 if (hw->mac.type == ixgbe_mac_82599EB) {
2234                         /* PSRTYPE must be initialized in 82599 */
2235                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2236                                       IXGBE_PSRTYPE_UDPHDR |
2237                                       IXGBE_PSRTYPE_IPV4HDR |
2238                                       IXGBE_PSRTYPE_IPV6HDR |
2239                                       IXGBE_PSRTYPE_L2HDR;
2240                         IXGBE_WRITE_REG(hw,
2241                                         IXGBE_PSRTYPE(adapter->num_vfs),
2242                                         psrtype);
2243                 }
2244         } else {
2245                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2246                     (netdev->mtu <= ETH_DATA_LEN))
2247                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2248                 else
2249                         rx_buf_len = ALIGN(max_frame, 1024);
2250         }
2251
2252         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2253         fctrl |= IXGBE_FCTRL_BAM;
2254         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2255         fctrl |= IXGBE_FCTRL_PMCF;
2256         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2257
2258         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2259         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2260                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2261         else
2262                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2263 #ifdef IXGBE_FCOE
2264         if (netdev->features & NETIF_F_FCOE_MTU)
2265                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2266 #endif
2267         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2268
2269         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2270         /* disable receives while setting up the descriptors */
2271         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2272         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2273
2274         /*
2275          * Setup the HW Rx Head and Tail Descriptor Pointers and
2276          * the Base and Length of the Rx Descriptor Ring
2277          */
2278         for (i = 0; i < adapter->num_rx_queues; i++) {
2279                 rx_ring = &adapter->rx_ring[i];
2280                 rdba = rx_ring->dma;
2281                 j = rx_ring->reg_idx;
2282                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2283                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2284                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2285                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2286                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2287                 rx_ring->head = IXGBE_RDH(j);
2288                 rx_ring->tail = IXGBE_RDT(j);
2289                 rx_ring->rx_buf_len = rx_buf_len;
2290
2291                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2292                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2293                 else
2294                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2295
2296 #ifdef IXGBE_FCOE
2297                 if (netdev->features & NETIF_F_FCOE_MTU) {
2298                         struct ixgbe_ring_feature *f;
2299                         f = &adapter->ring_feature[RING_F_FCOE];
2300                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2301                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2302                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2303                                         rx_ring->rx_buf_len =
2304                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2305                         }
2306                 }
2307
2308 #endif /* IXGBE_FCOE */
2309                 ixgbe_configure_srrctl(adapter, rx_ring);
2310         }
2311
2312         if (hw->mac.type == ixgbe_mac_82598EB) {
2313                 /*
2314                  * For VMDq support of different descriptor types or
2315                  * buffer sizes through the use of multiple SRRCTL
2316                  * registers, RDRXCTL.MVMEN must be set to 1
2317                  *
2318                  * also, the manual doesn't mention it clearly but DCA hints
2319                  * will only use queue 0's tags unless this bit is set.  Side
2320                  * effects of setting this bit are only that SRRCTL must be
2321                  * fully programmed [0..15]
2322                  */
2323                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2324                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2325                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2326         }
2327
2328         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2329                 u32 vt_reg_bits;
2330                 u32 reg_offset, vf_shift;
2331                 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2332                 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2333                         | IXGBE_VT_CTL_REPLEN;
2334                 vt_reg_bits |= (adapter->num_vfs <<
2335                                 IXGBE_VT_CTL_POOL_SHIFT);
2336                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2337                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2338
2339                 vf_shift = adapter->num_vfs % 32;
2340                 reg_offset = adapter->num_vfs / 32;
2341                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2342                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2343                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2344                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2345                 /* Enable only the PF's pool for Tx/Rx */
2346                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2347                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2348                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2349                 ixgbe_set_vmolr(hw, adapter->num_vfs);
2350         }
2351
2352         /* Program MRQC for the distribution of queues */
2353         mrqc = ixgbe_setup_mrqc(adapter);
2354
2355         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2356                 /* Fill out redirection table */
2357                 for (i = 0, j = 0; i < 128; i++, j++) {
2358                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2359                                 j = 0;
2360                         /* reta = 4-byte sliding window of
2361                          * 0x00..(indices-1)(indices-1)00..etc. */
2362                         reta = (reta << 8) | (j * 0x11);
2363                         if ((i & 3) == 3)
2364                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2365                 }
2366
2367                 /* Fill out hash function seeds */
2368                 for (i = 0; i < 10; i++)
2369                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2370
2371                 if (hw->mac.type == ixgbe_mac_82598EB)
2372                         mrqc |= IXGBE_MRQC_RSSEN;
2373                     /* Perform hash on these packet types */
2374                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2375                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2376                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2377                       | IXGBE_MRQC_RSS_FIELD_IPV6
2378                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2379                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2380         }
2381         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2382
2383         if (adapter->num_vfs) {
2384                 u32 reg;
2385
2386                 /* Map PF MAC address in RAR Entry 0 to first pool
2387                  * following VFs */
2388                 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2389
2390                 /* Set up VF register offsets for selected VT Mode, i.e.
2391                  * 64 VFs for SR-IOV */
2392                 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2393                 reg |= IXGBE_GCR_EXT_SRIOV;
2394                 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2395         }
2396
2397         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2398
2399         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2400             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2401                 /* Disable indicating checksum in descriptor, enables
2402                  * RSS hash */
2403                 rxcsum |= IXGBE_RXCSUM_PCSD;
2404         }
2405         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2406                 /* Enable IPv4 payload checksum for UDP fragments
2407                  * if PCSD is not set */
2408                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2409         }
2410
2411         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2412
2413         if (hw->mac.type == ixgbe_mac_82599EB) {
2414                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2415                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2416                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2417                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2418         }
2419
2420         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2421                 /* Enable 82599 HW-RSC */
2422                 for (i = 0; i < adapter->num_rx_queues; i++)
2423                         ixgbe_configure_rscctl(adapter, i);
2424
2425                 /* Disable RSC for ACK packets */
2426                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2427                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2428         }
2429 }
2430
2431 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2432 {
2433         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2434         struct ixgbe_hw *hw = &adapter->hw;
2435         int pool_ndx = adapter->num_vfs;
2436
2437         /* add VID to filter table */
2438         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2439 }
2440
2441 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2442 {
2443         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2444         struct ixgbe_hw *hw = &adapter->hw;
2445         int pool_ndx = adapter->num_vfs;
2446
2447         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2448                 ixgbe_irq_disable(adapter);
2449
2450         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2451
2452         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2453                 ixgbe_irq_enable(adapter);
2454
2455         /* remove VID from filter table */
2456         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2457 }
2458
2459 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2460                                    struct vlan_group *grp)
2461 {
2462         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2463         u32 ctrl;
2464         int i, j;
2465
2466         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2467                 ixgbe_irq_disable(adapter);
2468         adapter->vlgrp = grp;
2469
2470         /*
2471          * For a DCB driver, always enable VLAN tag stripping so we can
2472          * still receive traffic from a DCB-enabled host even if we're
2473          * not in DCB mode.
2474          */
2475         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2476
2477         /* Disable CFI check */
2478         ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2479
2480         /* enable VLAN tag stripping */
2481         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2482                 ctrl |= IXGBE_VLNCTRL_VME;
2483         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2484                 for (i = 0; i < adapter->num_rx_queues; i++) {
2485                         u32 ctrl;
2486                         j = adapter->rx_ring[i].reg_idx;
2487                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2488                         ctrl |= IXGBE_RXDCTL_VME;
2489                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2490                 }
2491         }
2492
2493         IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2494
2495         ixgbe_vlan_rx_add_vid(netdev, 0);
2496
2497         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2498                 ixgbe_irq_enable(adapter);
2499 }
2500
2501 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2502 {
2503         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2504
2505         if (adapter->vlgrp) {
2506                 u16 vid;
2507                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2508                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2509                                 continue;
2510                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2511                 }
2512         }
2513 }
2514
2515 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2516 {
2517         struct dev_mc_list *mc_ptr;
2518         u8 *addr = *mc_addr_ptr;
2519         *vmdq = 0;
2520
2521         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2522         if (mc_ptr->next)
2523                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2524         else
2525                 *mc_addr_ptr = NULL;
2526
2527         return addr;
2528 }
2529
2530 /**
2531  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2532  * @netdev: network interface device structure
2533  *
2534  * The set_rx_method entry point is called whenever the unicast/multicast
2535  * address list or the network interface flags are updated.  This routine is
2536  * responsible for configuring the hardware for proper unicast, multicast and
2537  * promiscuous mode.
2538  **/
2539 void ixgbe_set_rx_mode(struct net_device *netdev)
2540 {
2541         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2542         struct ixgbe_hw *hw = &adapter->hw;
2543         u32 fctrl, vlnctrl;
2544         u8 *addr_list = NULL;
2545         int addr_count = 0;
2546
2547         /* Check for Promiscuous and All Multicast modes */
2548
2549         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2550         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2551
2552         if (netdev->flags & IFF_PROMISC) {
2553                 hw->addr_ctrl.user_set_promisc = 1;
2554                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2555                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2556         } else {
2557                 if (netdev->flags & IFF_ALLMULTI) {
2558                         fctrl |= IXGBE_FCTRL_MPE;
2559                         fctrl &= ~IXGBE_FCTRL_UPE;
2560                 } else {
2561                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2562                 }
2563                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2564                 hw->addr_ctrl.user_set_promisc = 0;
2565         }
2566
2567         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2568         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2569
2570         /* reprogram secondary unicast list */
2571         hw->mac.ops.update_uc_addr_list(hw, netdev);
2572
2573         /* reprogram multicast list */
2574         addr_count = netdev->mc_count;
2575         if (addr_count)
2576                 addr_list = netdev->mc_list->dmi_addr;
2577         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2578                                         ixgbe_addr_list_itr);
2579         if (adapter->num_vfs)
2580                 ixgbe_restore_vf_multicasts(adapter);
2581 }
2582
2583 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2584 {
2585         int q_idx;
2586         struct ixgbe_q_vector *q_vector;
2587         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2588
2589         /* legacy and MSI only use one vector */
2590         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2591                 q_vectors = 1;
2592
2593         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2594                 struct napi_struct *napi;
2595                 q_vector = adapter->q_vector[q_idx];
2596                 napi = &q_vector->napi;
2597                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2598                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2599                                 if (q_vector->txr_count == 1)
2600                                         napi->poll = &ixgbe_clean_txonly;
2601                                 else if (q_vector->rxr_count == 1)
2602                                         napi->poll = &ixgbe_clean_rxonly;
2603                         }
2604                 }
2605
2606                 napi_enable(napi);
2607         }
2608 }
2609
2610 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2611 {
2612         int q_idx;
2613         struct ixgbe_q_vector *q_vector;
2614         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2615
2616         /* legacy and MSI only use one vector */
2617         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2618                 q_vectors = 1;
2619
2620         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2621                 q_vector = adapter->q_vector[q_idx];
2622                 napi_disable(&q_vector->napi);
2623         }
2624 }
2625
2626 #ifdef CONFIG_IXGBE_DCB
2627 /*
2628  * ixgbe_configure_dcb - Configure DCB hardware
2629  * @adapter: ixgbe adapter struct
2630  *
2631  * This is called by the driver on open to configure the DCB hardware.
2632  * This is also called by the gennetlink interface when reconfiguring
2633  * the DCB state.
2634  */
2635 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2636 {
2637         struct ixgbe_hw *hw = &adapter->hw;
2638         u32 txdctl, vlnctrl;
2639         int i, j;
2640
2641         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2642         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2643         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2644
2645         /* reconfigure the hardware */
2646         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2647
2648         for (i = 0; i < adapter->num_tx_queues; i++) {
2649                 j = adapter->tx_ring[i].reg_idx;
2650                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2651                 /* PThresh workaround for Tx hang with DFP enabled. */
2652                 txdctl |= 32;
2653                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2654         }
2655         /* Enable VLAN tag insert/strip */
2656         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2657         if (hw->mac.type == ixgbe_mac_82598EB) {
2658                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2659                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2660                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2661         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2662                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2663                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2664                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2665                 for (i = 0; i < adapter->num_rx_queues; i++) {
2666                         j = adapter->rx_ring[i].reg_idx;
2667                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2668                         vlnctrl |= IXGBE_RXDCTL_VME;
2669                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2670                 }
2671         }
2672         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2673 }
2674
2675 #endif
2676 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2677 {
2678         struct net_device *netdev = adapter->netdev;
2679         struct ixgbe_hw *hw = &adapter->hw;
2680         int i;
2681
2682         ixgbe_set_rx_mode(netdev);
2683
2684         ixgbe_restore_vlan(adapter);
2685 #ifdef CONFIG_IXGBE_DCB
2686         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2687                 if (hw->mac.type == ixgbe_mac_82598EB)
2688                         netif_set_gso_max_size(netdev, 32768);
2689                 else
2690                         netif_set_gso_max_size(netdev, 65536);
2691                 ixgbe_configure_dcb(adapter);
2692         } else {
2693                 netif_set_gso_max_size(netdev, 65536);
2694         }
2695 #else
2696         netif_set_gso_max_size(netdev, 65536);
2697 #endif
2698
2699 #ifdef IXGBE_FCOE
2700         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2701                 ixgbe_configure_fcoe(adapter);
2702
2703 #endif /* IXGBE_FCOE */
2704         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2705                 for (i = 0; i < adapter->num_tx_queues; i++)
2706                         adapter->tx_ring[i].atr_sample_rate =
2707                                                        adapter->atr_sample_rate;
2708                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2709         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2710                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2711         }
2712
2713         ixgbe_configure_tx(adapter);
2714         ixgbe_configure_rx(adapter);
2715         for (i = 0; i < adapter->num_rx_queues; i++)
2716                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2717                                        (adapter->rx_ring[i].count - 1));
2718 }
2719
2720 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2721 {
2722         switch (hw->phy.type) {
2723         case ixgbe_phy_sfp_avago:
2724         case ixgbe_phy_sfp_ftl:
2725         case ixgbe_phy_sfp_intel:
2726         case ixgbe_phy_sfp_unknown:
2727         case ixgbe_phy_tw_tyco:
2728         case ixgbe_phy_tw_unknown:
2729                 return true;
2730         default:
2731                 return false;
2732         }
2733 }
2734
2735 /**
2736  * ixgbe_sfp_link_config - set up SFP+ link
2737  * @adapter: pointer to private adapter struct
2738  **/
2739 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2740 {
2741         struct ixgbe_hw *hw = &adapter->hw;
2742
2743                 if (hw->phy.multispeed_fiber) {
2744                         /*
2745                          * In multispeed fiber setups, the device may not have
2746                          * had a physical connection when the driver loaded.
2747                          * If that's the case, the initial link configuration
2748                          * couldn't get the MAC into 10G or 1G mode, so we'll
2749                          * never have a link status change interrupt fire.
2750                          * We need to try and force an autonegotiation
2751                          * session, then bring up link.
2752                          */
2753                         hw->mac.ops.setup_sfp(hw);
2754                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2755                                 schedule_work(&adapter->multispeed_fiber_task);
2756                 } else {
2757                         /*
2758                          * Direct Attach Cu and non-multispeed fiber modules
2759                          * still need to be configured properly prior to
2760                          * attempting link.
2761                          */
2762                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2763                                 schedule_work(&adapter->sfp_config_module_task);
2764                 }
2765 }
2766
2767 /**
2768  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2769  * @hw: pointer to private hardware struct
2770  *
2771  * Returns 0 on success, negative on failure
2772  **/
2773 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2774 {
2775         u32 autoneg;
2776         bool negotiation, link_up = false;
2777         u32 ret = IXGBE_ERR_LINK_SETUP;
2778
2779         if (hw->mac.ops.check_link)
2780                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2781
2782         if (ret)
2783                 goto link_cfg_out;
2784
2785         if (hw->mac.ops.get_link_capabilities)
2786                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2787         if (ret)
2788                 goto link_cfg_out;
2789
2790         if (hw->mac.ops.setup_link)
2791                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2792 link_cfg_out:
2793         return ret;
2794 }
2795
2796 #define IXGBE_MAX_RX_DESC_POLL 10
2797 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2798                                               int rxr)
2799 {
2800         int j = adapter->rx_ring[rxr].reg_idx;
2801         int k;
2802
2803         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2804                 if (IXGBE_READ_REG(&adapter->hw,
2805                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2806                         break;
2807                 else
2808                         msleep(1);
2809         }
2810         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2811                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2812                         "not set within the polling period\n", rxr);
2813         }
2814         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2815                               (adapter->rx_ring[rxr].count - 1));
2816 }
2817
2818 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2819 {
2820         struct net_device *netdev = adapter->netdev;
2821         struct ixgbe_hw *hw = &adapter->hw;
2822         int i, j = 0;
2823         int num_rx_rings = adapter->num_rx_queues;
2824         int err;
2825         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2826         u32 txdctl, rxdctl, mhadd;
2827         u32 dmatxctl;
2828         u32 gpie;
2829         u32 ctrl_ext;
2830
2831         ixgbe_get_hw_control(adapter);
2832
2833         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2834             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2835                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2836                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2837                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2838                 } else {
2839                         /* MSI only */
2840                         gpie = 0;
2841                 }
2842                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2843                         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2844                         gpie |= IXGBE_GPIE_VTMODE_64;
2845                 }
2846                 /* XXX: to interrupt immediately for EICS writes, enable this */
2847                 /* gpie |= IXGBE_GPIE_EIMEN; */
2848                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2849         }
2850
2851         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2852                 /*
2853                  * use EIAM to auto-mask when MSI-X interrupt is asserted
2854                  * this saves a register write for every interrupt
2855                  */
2856                 switch (hw->mac.type) {
2857                 case ixgbe_mac_82598EB:
2858                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2859                         break;
2860                 default:
2861                 case ixgbe_mac_82599EB:
2862                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2863                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2864                         break;
2865                 }
2866         } else {
2867                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2868                  * specifically only auto mask tx and rx interrupts */
2869                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2870         }
2871
2872         /* Enable fan failure interrupt if media type is copper */
2873         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2874                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2875                 gpie |= IXGBE_SDP1_GPIEN;
2876                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2877         }
2878
2879         if (hw->mac.type == ixgbe_mac_82599EB) {
2880                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2881                 gpie |= IXGBE_SDP1_GPIEN;
2882                 gpie |= IXGBE_SDP2_GPIEN;
2883                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2884         }
2885
2886 #ifdef IXGBE_FCOE
2887         /* adjust max frame to be able to do baby jumbo for FCoE */
2888         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2889             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2890                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2891
2892 #endif /* IXGBE_FCOE */
2893         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2894         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2895                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2896                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2897
2898                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2899         }
2900
2901         for (i = 0; i < adapter->num_tx_queues; i++) {
2902                 j = adapter->tx_ring[i].reg_idx;
2903                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2904                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2905                 txdctl |= (8 << 16);
2906                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2907         }
2908
2909         if (hw->mac.type == ixgbe_mac_82599EB) {
2910                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2911                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2912                 dmatxctl |= IXGBE_DMATXCTL_TE;
2913                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2914         }
2915         for (i = 0; i < adapter->num_tx_queues; i++) {
2916                 j = adapter->tx_ring[i].reg_idx;
2917                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2918                 txdctl |= IXGBE_TXDCTL_ENABLE;
2919                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2920                 if (hw->mac.type == ixgbe_mac_82599EB) {
2921                         int wait_loop = 10;
2922                         /* poll for Tx Enable ready */
2923                         do {
2924                                 msleep(1);
2925                                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2926                         } while (--wait_loop &&
2927                                  !(txdctl & IXGBE_TXDCTL_ENABLE));
2928                         if (!wait_loop)
2929                                 DPRINTK(DRV, ERR, "Could not enable "
2930                                         "Tx Queue %d\n", j);
2931                 }
2932         }
2933
2934         for (i = 0; i < num_rx_rings; i++) {
2935                 j = adapter->rx_ring[i].reg_idx;
2936                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2937                 /* enable PTHRESH=32 descriptors (half the internal cache)
2938                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2939                  * this also removes a pesky rx_no_buffer_count increment */
2940                 rxdctl |= 0x0020;
2941                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2942                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2943                 if (hw->mac.type == ixgbe_mac_82599EB)
2944                         ixgbe_rx_desc_queue_enable(adapter, i);
2945         }
2946         /* enable all receives */
2947         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2948         if (hw->mac.type == ixgbe_mac_82598EB)
2949                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2950         else
2951                 rxdctl |= IXGBE_RXCTRL_RXEN;
2952         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2953
2954         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2955                 ixgbe_configure_msix(adapter);
2956         else
2957                 ixgbe_configure_msi_and_legacy(adapter);
2958
2959         clear_bit(__IXGBE_DOWN, &adapter->state);
2960         ixgbe_napi_enable_all(adapter);
2961
2962         /* clear any pending interrupts, may auto mask */
2963         IXGBE_READ_REG(hw, IXGBE_EICR);
2964
2965         ixgbe_irq_enable(adapter);
2966
2967         /*
2968          * If this adapter has a fan, check to see if we had a failure
2969          * before we enabled the interrupt.
2970          */
2971         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2972                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2973                 if (esdp & IXGBE_ESDP_SDP1)
2974                         DPRINTK(DRV, CRIT,
2975                                 "Fan has stopped, replace the adapter\n");
2976         }
2977
2978         /*
2979          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2980          * arrived before interrupts were enabled but after probe.  Such
2981          * devices wouldn't have their type identified yet. We need to
2982          * kick off the SFP+ module setup first, then try to bring up link.
2983          * If we're not hot-pluggable SFP+, we just need to configure link
2984          * and bring it up.
2985          */
2986         if (hw->phy.type == ixgbe_phy_unknown) {
2987                 err = hw->phy.ops.identify(hw);
2988                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2989                         /*
2990                          * Take the device down and schedule the sfp tasklet
2991                          * which will unregister_netdev and log it.
2992                          */
2993                         ixgbe_down(adapter);
2994                         schedule_work(&adapter->sfp_config_module_task);
2995                         return err;
2996                 }
2997         }
2998
2999         if (ixgbe_is_sfp(hw)) {
3000                 ixgbe_sfp_link_config(adapter);
3001         } else {
3002                 err = ixgbe_non_sfp_link_config(hw);
3003                 if (err)
3004                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3005         }
3006
3007         for (i = 0; i < adapter->num_tx_queues; i++)
3008                 set_bit(__IXGBE_FDIR_INIT_DONE,
3009                         &(adapter->tx_ring[i].reinit_state));
3010
3011         /* enable transmits */
3012         netif_tx_start_all_queues(netdev);
3013
3014         /* bring the link up in the watchdog, this could race with our first
3015          * link up interrupt but shouldn't be a problem */
3016         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3017         adapter->link_check_timeout = jiffies;
3018         mod_timer(&adapter->watchdog_timer, jiffies);
3019
3020         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3021         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3022         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3023         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3024
3025         return 0;
3026 }
3027
3028 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3029 {
3030         WARN_ON(in_interrupt());
3031         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3032                 msleep(1);
3033         ixgbe_down(adapter);
3034         ixgbe_up(adapter);
3035         clear_bit(__IXGBE_RESETTING, &adapter->state);
3036 }
3037
3038 int ixgbe_up(struct ixgbe_adapter *adapter)
3039 {
3040         /* hardware has been reset, we need to reload some things */
3041         ixgbe_configure(adapter);
3042
3043         return ixgbe_up_complete(adapter);
3044 }
3045
3046 void ixgbe_reset(struct ixgbe_adapter *adapter)
3047 {
3048         struct ixgbe_hw *hw = &adapter->hw;
3049         int err;
3050
3051         err = hw->mac.ops.init_hw(hw);
3052         switch (err) {
3053         case 0:
3054         case IXGBE_ERR_SFP_NOT_PRESENT:
3055                 break;
3056         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3057                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3058                 break;
3059         case IXGBE_ERR_EEPROM_VERSION:
3060                 /* We are running on a pre-production device, log a warning */
3061                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3062                          "adapter/LOM.  Please be aware there may be issues "
3063                          "associated with your hardware.  If you are "
3064                          "experiencing problems please contact your Intel or "
3065                          "hardware representative who provided you with this "
3066                          "hardware.\n");
3067                 break;
3068         default:
3069                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3070         }
3071
3072         /* reprogram the RAR[0] in case user changed it. */
3073         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3074                             IXGBE_RAH_AV);
3075 }
3076
3077 /**
3078  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3079  * @adapter: board private structure
3080  * @rx_ring: ring to free buffers from
3081  **/
3082 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3083                                 struct ixgbe_ring *rx_ring)
3084 {
3085         struct pci_dev *pdev = adapter->pdev;
3086         unsigned long size;
3087         unsigned int i;
3088
3089         /* Free all the Rx ring sk_buffs */
3090
3091         for (i = 0; i < rx_ring->count; i++) {
3092                 struct ixgbe_rx_buffer *rx_buffer_info;
3093
3094                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3095                 if (rx_buffer_info->dma) {
3096                         pci_unmap_single(pdev, rx_buffer_info->dma,
3097                                          rx_ring->rx_buf_len,
3098                                          PCI_DMA_FROMDEVICE);
3099                         rx_buffer_info->dma = 0;
3100                 }
3101                 if (rx_buffer_info->skb) {
3102                         struct sk_buff *skb = rx_buffer_info->skb;
3103                         rx_buffer_info->skb = NULL;
3104                         do {
3105                                 struct sk_buff *this = skb;
3106                                 skb = skb->prev;
3107                                 dev_kfree_skb(this);
3108                         } while (skb);
3109                 }
3110                 if (!rx_buffer_info->page)
3111                         continue;
3112                 if (rx_buffer_info->page_dma) {
3113                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
3114                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3115                         rx_buffer_info->page_dma = 0;
3116                 }
3117                 put_page(rx_buffer_info->page);
3118                 rx_buffer_info->page = NULL;
3119                 rx_buffer_info->page_offset = 0;
3120         }
3121
3122         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3123         memset(rx_ring->rx_buffer_info, 0, size);
3124
3125         /* Zero out the descriptor ring */
3126         memset(rx_ring->desc, 0, rx_ring->size);
3127
3128         rx_ring->next_to_clean = 0;
3129         rx_ring->next_to_use = 0;
3130
3131         if (rx_ring->head)
3132                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3133         if (rx_ring->tail)
3134                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3135 }
3136
3137 /**
3138  * ixgbe_clean_tx_ring - Free Tx Buffers
3139  * @adapter: board private structure
3140  * @tx_ring: ring to be cleaned
3141  **/
3142 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3143                                 struct ixgbe_ring *tx_ring)
3144 {
3145         struct ixgbe_tx_buffer *tx_buffer_info;
3146         unsigned long size;
3147         unsigned int i;
3148
3149         /* Free all the Tx ring sk_buffs */
3150
3151         for (i = 0; i < tx_ring->count; i++) {
3152                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3153                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3154         }
3155
3156         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3157         memset(tx_ring->tx_buffer_info, 0, size);
3158
3159         /* Zero out the descriptor ring */
3160         memset(tx_ring->desc, 0, tx_ring->size);
3161
3162         tx_ring->next_to_use = 0;
3163         tx_ring->next_to_clean = 0;
3164
3165         if (tx_ring->head)
3166                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3167         if (tx_ring->tail)
3168                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3169 }
3170
3171 /**
3172  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3173  * @adapter: board private structure
3174  **/
3175 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3176 {
3177         int i;
3178
3179         for (i = 0; i < adapter->num_rx_queues; i++)
3180                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
3181 }
3182
3183 /**
3184  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3185  * @adapter: board private structure
3186  **/
3187 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3188 {
3189         int i;
3190
3191         for (i = 0; i < adapter->num_tx_queues; i++)
3192                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
3193 }
3194
3195 void ixgbe_down(struct ixgbe_adapter *adapter)
3196 {
3197         struct net_device *netdev = adapter->netdev;
3198         struct ixgbe_hw *hw = &adapter->hw;
3199         u32 rxctrl;
3200         u32 txdctl;
3201         int i, j;
3202
3203         /* signal that we are down to the interrupt handler */
3204         set_bit(__IXGBE_DOWN, &adapter->state);
3205
3206         /* disable receive for all VFs and wait one second */
3207         if (adapter->num_vfs) {
3208                 for (i = 0 ; i < adapter->num_vfs; i++)
3209                         adapter->vfinfo[i].clear_to_send = 0;
3210
3211                 /* ping all the active vfs to let them know we are going down */
3212                 ixgbe_ping_all_vfs(adapter);
3213                 /* Disable all VFTE/VFRE TX/RX */
3214                 ixgbe_disable_tx_rx(adapter);
3215         }
3216
3217         /* disable receives */
3218         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3219         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3220
3221         netif_tx_disable(netdev);
3222
3223         IXGBE_WRITE_FLUSH(hw);
3224         msleep(10);
3225
3226         netif_tx_stop_all_queues(netdev);
3227
3228         ixgbe_irq_disable(adapter);
3229
3230         ixgbe_napi_disable_all(adapter);
3231
3232         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3233         del_timer_sync(&adapter->sfp_timer);
3234         del_timer_sync(&adapter->watchdog_timer);
3235         cancel_work_sync(&adapter->watchdog_task);
3236
3237         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3238             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3239                 cancel_work_sync(&adapter->fdir_reinit_task);
3240
3241         /* disable transmits in the hardware now that interrupts are off */
3242         for (i = 0; i < adapter->num_tx_queues; i++) {
3243                 j = adapter->tx_ring[i].reg_idx;
3244                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3245                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3246                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3247         }
3248         /* Disable the Tx DMA engine on 82599 */
3249         if (hw->mac.type == ixgbe_mac_82599EB)
3250                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3251                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3252                                  ~IXGBE_DMATXCTL_TE));
3253
3254         netif_carrier_off(netdev);
3255
3256         if (!pci_channel_offline(adapter->pdev))
3257                 ixgbe_reset(adapter);
3258         ixgbe_clean_all_tx_rings(adapter);
3259         ixgbe_clean_all_rx_rings(adapter);
3260
3261 #ifdef CONFIG_IXGBE_DCA
3262         /* since we reset the hardware DCA settings were cleared */
3263         ixgbe_setup_dca(adapter);
3264 #endif
3265 }
3266
3267 /**
3268  * ixgbe_poll - NAPI Rx polling callback
3269  * @napi: structure for representing this polling device
3270  * @budget: how many packets driver is allowed to clean
3271  *
3272  * This function is used for legacy and MSI, NAPI mode
3273  **/
3274 static int ixgbe_poll(struct napi_struct *napi, int budget)
3275 {
3276         struct ixgbe_q_vector *q_vector =
3277                                 container_of(napi, struct ixgbe_q_vector, napi);
3278         struct ixgbe_adapter *adapter = q_vector->adapter;
3279         int tx_clean_complete, work_done = 0;
3280
3281 #ifdef CONFIG_IXGBE_DCA
3282         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3283                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3284                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3285         }
3286 #endif
3287
3288         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3289         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3290
3291         if (!tx_clean_complete)
3292                 work_done = budget;
3293
3294         /* If budget not fully consumed, exit the polling mode */
3295         if (work_done < budget) {
3296                 napi_complete(napi);
3297                 if (adapter->rx_itr_setting & 1)
3298                         ixgbe_set_itr(adapter);
3299                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3300                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3301         }
3302         return work_done;
3303 }
3304
3305 /**
3306  * ixgbe_tx_timeout - Respond to a Tx Hang
3307  * @netdev: network interface device structure
3308  **/
3309 static void ixgbe_tx_timeout(struct net_device *netdev)
3310 {
3311         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3312
3313         /* Do the reset outside of interrupt context */
3314         schedule_work(&adapter->reset_task);
3315 }
3316
3317 static void ixgbe_reset_task(struct work_struct *work)
3318 {
3319         struct ixgbe_adapter *adapter;
3320         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3321
3322         /* If we're already down or resetting, just bail */
3323         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3324             test_bit(__IXGBE_RESETTING, &adapter->state))
3325                 return;
3326
3327         adapter->tx_timeout_count++;
3328
3329         ixgbe_reinit_locked(adapter);
3330 }
3331
3332 #ifdef CONFIG_IXGBE_DCB
3333 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3334 {
3335         bool ret = false;
3336         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3337
3338         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3339                 return ret;
3340
3341         f->mask = 0x7 << 3;
3342         adapter->num_rx_queues = f->indices;
3343         adapter->num_tx_queues = f->indices;
3344         ret = true;
3345
3346         return ret;
3347 }
3348 #endif
3349
3350 /**
3351  * ixgbe_set_rss_queues: Allocate queues for RSS
3352  * @adapter: board private structure to initialize
3353  *
3354  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3355  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3356  *
3357  **/
3358 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3359 {
3360         bool ret = false;
3361         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3362
3363         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3364                 f->mask = 0xF;
3365                 adapter->num_rx_queues = f->indices;
3366                 adapter->num_tx_queues = f->indices;
3367                 ret = true;
3368         } else {
3369                 ret = false;
3370         }
3371
3372         return ret;
3373 }
3374
3375 /**
3376  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3377  * @adapter: board private structure to initialize
3378  *
3379  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3380  * to the original CPU that initiated the Tx session.  This runs in addition
3381  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3382  * Rx load across CPUs using RSS.
3383  *
3384  **/
3385 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3386 {
3387         bool ret = false;
3388         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3389
3390         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3391         f_fdir->mask = 0;
3392
3393         /* Flow Director must have RSS enabled */
3394         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3395             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3396              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3397                 adapter->num_tx_queues = f_fdir->indices;
3398                 adapter->num_rx_queues = f_fdir->indices;
3399                 ret = true;
3400         } else {
3401                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3402                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3403         }
3404         return ret;
3405 }
3406
3407 #ifdef IXGBE_FCOE
3408 /**
3409  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3410  * @adapter: board private structure to initialize
3411  *
3412  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3413  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3414  * rx queues out of the max number of rx queues, instead, it is used as the
3415  * index of the first rx queue used by FCoE.
3416  *
3417  **/
3418 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3419 {
3420         bool ret = false;
3421         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3422
3423         f->indices = min((int)num_online_cpus(), f->indices);
3424         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3425                 adapter->num_rx_queues = 1;
3426                 adapter->num_tx_queues = 1;
3427 #ifdef CONFIG_IXGBE_DCB
3428                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3429                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3430                         ixgbe_set_dcb_queues(adapter);
3431                 }
3432 #endif
3433                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3434                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3435                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3436                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3437                                 ixgbe_set_fdir_queues(adapter);
3438                         else
3439                                 ixgbe_set_rss_queues(adapter);
3440                 }
3441                 /* adding FCoE rx rings to the end */
3442                 f->mask = adapter->num_rx_queues;
3443                 adapter->num_rx_queues += f->indices;
3444                 adapter->num_tx_queues += f->indices;
3445
3446                 ret = true;
3447         }
3448
3449         return ret;
3450 }
3451
3452 #endif /* IXGBE_FCOE */
3453 /**
3454  * ixgbe_set_sriov_queues: Allocate queues for IOV use
3455  * @adapter: board private structure to initialize
3456  *
3457  * IOV doesn't actually use anything, so just NAK the
3458  * request for now and let the other queue routines
3459  * figure out what to do.
3460  */
3461 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3462 {
3463         return false;
3464 }
3465
3466 /*
3467  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3468  * @adapter: board private structure to initialize
3469  *
3470  * This is the top level queue allocation routine.  The order here is very
3471  * important, starting with the "most" number of features turned on at once,
3472  * and ending with the smallest set of features.  This way large combinations
3473  * can be allocated if they're turned on, and smaller combinations are the
3474  * fallthrough conditions.
3475  *
3476  **/
3477 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3478 {
3479         /* Start with base case */
3480         adapter->num_rx_queues = 1;
3481         adapter->num_tx_queues = 1;
3482         adapter->num_rx_pools = adapter->num_rx_queues;
3483         adapter->num_rx_queues_per_pool = 1;
3484
3485         if (ixgbe_set_sriov_queues(adapter))
3486                 return;
3487
3488 #ifdef IXGBE_FCOE
3489         if (ixgbe_set_fcoe_queues(adapter))
3490                 goto done;
3491
3492 #endif /* IXGBE_FCOE */
3493 #ifdef CONFIG_IXGBE_DCB
3494         if (ixgbe_set_dcb_queues(adapter))
3495                 goto done;
3496
3497 #endif
3498         if (ixgbe_set_fdir_queues(adapter))
3499                 goto done;
3500
3501         if (ixgbe_set_rss_queues(adapter))
3502                 goto done;
3503
3504         /* fallback to base case */
3505         adapter->num_rx_queues = 1;
3506         adapter->num_tx_queues = 1;
3507
3508 done:
3509         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3510         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3511 }
3512
3513 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3514                                        int vectors)
3515 {
3516         int err, vector_threshold;
3517
3518         /* We'll want at least 3 (vector_threshold):
3519          * 1) TxQ[0] Cleanup
3520          * 2) RxQ[0] Cleanup
3521          * 3) Other (Link Status Change, etc.)
3522          * 4) TCP Timer (optional)
3523          */
3524         vector_threshold = MIN_MSIX_COUNT;
3525
3526         /* The more we get, the more we will assign to Tx/Rx Cleanup
3527          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3528          * Right now, we simply care about how many we'll get; we'll
3529          * set them up later while requesting irq's.
3530          */
3531         while (vectors >= vector_threshold) {
3532                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3533                                       vectors);
3534                 if (!err) /* Success in acquiring all requested vectors. */
3535                         break;
3536                 else if (err < 0)
3537                         vectors = 0; /* Nasty failure, quit now */
3538                 else /* err == number of vectors we should try again with */
3539                         vectors = err;
3540         }
3541
3542         if (vectors < vector_threshold) {
3543                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3544                  * This just means we'll go with either a single MSI
3545                  * vector or fall back to legacy interrupts.
3546                  */
3547                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3548                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3549                 kfree(adapter->msix_entries);
3550                 adapter->msix_entries = NULL;
3551         } else {
3552                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3553                 /*
3554                  * Adjust for only the vectors we'll use, which is minimum
3555                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3556                  * vectors we were allocated.
3557                  */
3558                 adapter->num_msix_vectors = min(vectors,
3559                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3560         }
3561 }
3562
3563 /**
3564  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3565  * @adapter: board private structure to initialize
3566  *
3567  * Cache the descriptor ring offsets for RSS to the assigned rings.
3568  *
3569  **/
3570 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3571 {
3572         int i;
3573         bool ret = false;
3574
3575         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3576                 for (i = 0; i < adapter->num_rx_queues; i++)
3577                         adapter->rx_ring[i].reg_idx = i;
3578                 for (i = 0; i < adapter->num_tx_queues; i++)
3579                         adapter->tx_ring[i].reg_idx = i;
3580                 ret = true;
3581         } else {
3582                 ret = false;
3583         }
3584
3585         return ret;
3586 }
3587
3588 #ifdef CONFIG_IXGBE_DCB
3589 /**
3590  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3591  * @adapter: board private structure to initialize
3592  *
3593  * Cache the descriptor ring offsets for DCB to the assigned rings.
3594  *
3595  **/
3596 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3597 {
3598         int i;
3599         bool ret = false;
3600         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3601
3602         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3603                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3604                         /* the number of queues is assumed to be symmetric */
3605                         for (i = 0; i < dcb_i; i++) {
3606                                 adapter->rx_ring[i].reg_idx = i << 3;
3607                                 adapter->tx_ring[i].reg_idx = i << 2;
3608                         }
3609                         ret = true;
3610                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3611                         if (dcb_i == 8) {
3612                                 /*
3613                                  * Tx TC0 starts at: descriptor queue 0
3614                                  * Tx TC1 starts at: descriptor queue 32
3615                                  * Tx TC2 starts at: descriptor queue 64
3616                                  * Tx TC3 starts at: descriptor queue 80
3617                                  * Tx TC4 starts at: descriptor queue 96
3618                                  * Tx TC5 starts at: descriptor queue 104
3619                                  * Tx TC6 starts at: descriptor queue 112
3620                                  * Tx TC7 starts at: descriptor queue 120
3621                                  *
3622                                  * Rx TC0-TC7 are offset by 16 queues each
3623                                  */
3624                                 for (i = 0; i < 3; i++) {
3625                                         adapter->tx_ring[i].reg_idx = i << 5;
3626                                         adapter->rx_ring[i].reg_idx = i << 4;
3627                                 }
3628                                 for ( ; i < 5; i++) {
3629                                         adapter->tx_ring[i].reg_idx =
3630                                                                  ((i + 2) << 4);
3631                                         adapter->rx_ring[i].reg_idx = i << 4;
3632                                 }
3633                                 for ( ; i < dcb_i; i++) {
3634                                         adapter->tx_ring[i].reg_idx =
3635                                                                  ((i + 8) << 3);
3636                                         adapter->rx_ring[i].reg_idx = i << 4;
3637                                 }
3638
3639                                 ret = true;
3640                         } else if (dcb_i == 4) {
3641                                 /*
3642                                  * Tx TC0 starts at: descriptor queue 0
3643                                  * Tx TC1 starts at: descriptor queue 64
3644                                  * Tx TC2 starts at: descriptor queue 96
3645                                  * Tx TC3 starts at: descriptor queue 112
3646                                  *
3647                                  * Rx TC0-TC3 are offset by 32 queues each
3648                                  */
3649                                 adapter->tx_ring[0].reg_idx = 0;
3650                                 adapter->tx_ring[1].reg_idx = 64;
3651                                 adapter->tx_ring[2].reg_idx = 96;
3652                                 adapter->tx_ring[3].reg_idx = 112;
3653                                 for (i = 0 ; i < dcb_i; i++)
3654                                         adapter->rx_ring[i].reg_idx = i << 5;
3655
3656                                 ret = true;
3657                         } else {
3658                                 ret = false;
3659                         }
3660                 } else {
3661                         ret = false;
3662                 }
3663         } else {
3664                 ret = false;
3665         }
3666
3667         return ret;
3668 }
3669 #endif
3670
3671 /**
3672  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3673  * @adapter: board private structure to initialize
3674  *
3675  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3676  *
3677  **/
3678 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3679 {
3680         int i;
3681         bool ret = false;
3682
3683         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3684             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3685              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3686                 for (i = 0; i < adapter->num_rx_queues; i++)
3687                         adapter->rx_ring[i].reg_idx = i;
3688                 for (i = 0; i < adapter->num_tx_queues; i++)
3689                         adapter->tx_ring[i].reg_idx = i;
3690                 ret = true;
3691         }
3692
3693         return ret;
3694 }
3695
3696 #ifdef IXGBE_FCOE
3697 /**
3698  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3699  * @adapter: board private structure to initialize
3700  *
3701  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3702  *
3703  */
3704 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3705 {
3706         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3707         bool ret = false;
3708         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3709
3710         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3711 #ifdef CONFIG_IXGBE_DCB
3712                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3713                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3714
3715                         ixgbe_cache_ring_dcb(adapter);
3716                         /* find out queues in TC for FCoE */
3717                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3718                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3719                         /*
3720                          * In 82599, the number of Tx queues for each traffic
3721                          * class for both 8-TC and 4-TC modes are:
3722                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3723                          * 8 TCs:  32  32  16  16   8   8   8   8
3724                          * 4 TCs:  64  64  32  32
3725                          * We have max 8 queues for FCoE, where 8 the is
3726                          * FCoE redirection table size. If TC for FCoE is
3727                          * less than or equal to TC3, we have enough queues
3728                          * to add max of 8 queues for FCoE, so we start FCoE
3729                          * tx descriptor from the next one, i.e., reg_idx + 1.
3730                          * If TC for FCoE is above TC3, implying 8 TC mode,
3731                          * and we need 8 for FCoE, we have to take all queues
3732                          * in that traffic class for FCoE.
3733                          */
3734                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3735                                 fcoe_tx_i--;
3736                 }
3737 #endif /* CONFIG_IXGBE_DCB */
3738                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3739                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3740                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3741                                 ixgbe_cache_ring_fdir(adapter);
3742                         else
3743                                 ixgbe_cache_ring_rss(adapter);
3744
3745                         fcoe_rx_i = f->mask;
3746                         fcoe_tx_i = f->mask;
3747                 }
3748                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3749                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3750                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3751                 }
3752                 ret = true;
3753         }
3754         return ret;
3755 }
3756
3757 #endif /* IXGBE_FCOE */
3758 /**
3759  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3760  * @adapter: board private structure to initialize
3761  *
3762  * SR-IOV doesn't use any descriptor rings but changes the default if
3763  * no other mapping is used.
3764  *
3765  */
3766 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3767 {
3768         adapter->rx_ring[0].reg_idx = adapter->num_vfs * 2;
3769         adapter->tx_ring[0].reg_idx = adapter->num_vfs * 2;
3770         if (adapter->num_vfs)
3771                 return true;
3772         else
3773                 return false;
3774 }
3775
3776 /**
3777  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3778  * @adapter: board private structure to initialize
3779  *
3780  * Once we know the feature-set enabled for the device, we'll cache
3781  * the register offset the descriptor ring is assigned to.
3782  *
3783  * Note, the order the various feature calls is important.  It must start with
3784  * the "most" features enabled at the same time, then trickle down to the
3785  * least amount of features turned on at once.
3786  **/
3787 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3788 {
3789         /* start with default case */
3790         adapter->rx_ring[0].reg_idx = 0;
3791         adapter->tx_ring[0].reg_idx = 0;
3792
3793         if (ixgbe_cache_ring_sriov(adapter))
3794                 return;
3795
3796 #ifdef IXGBE_FCOE
3797         if (ixgbe_cache_ring_fcoe(adapter))
3798                 return;
3799
3800 #endif /* IXGBE_FCOE */
3801 #ifdef CONFIG_IXGBE_DCB
3802         if (ixgbe_cache_ring_dcb(adapter))
3803                 return;
3804
3805 #endif
3806         if (ixgbe_cache_ring_fdir(adapter))
3807                 return;
3808
3809         if (ixgbe_cache_ring_rss(adapter))
3810                 return;
3811 }
3812
3813 /**
3814  * ixgbe_alloc_queues - Allocate memory for all rings
3815  * @adapter: board private structure to initialize
3816  *
3817  * We allocate one ring per queue at run-time since we don't know the
3818  * number of queues at compile-time.  The polling_netdev array is
3819  * intended for Multiqueue, but should work fine with a single queue.
3820  **/
3821 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3822 {
3823         int i;
3824
3825         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3826                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3827         if (!adapter->tx_ring)
3828                 goto err_tx_ring_allocation;
3829
3830         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3831                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3832         if (!adapter->rx_ring)
3833                 goto err_rx_ring_allocation;
3834
3835         for (i = 0; i < adapter->num_tx_queues; i++) {
3836                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3837                 adapter->tx_ring[i].queue_index = i;
3838         }
3839
3840         for (i = 0; i < adapter->num_rx_queues; i++) {
3841                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3842                 adapter->rx_ring[i].queue_index = i;
3843         }
3844
3845         ixgbe_cache_ring_register(adapter);
3846
3847         return 0;
3848
3849 err_rx_ring_allocation:
3850         kfree(adapter->tx_ring);
3851 err_tx_ring_allocation:
3852         return -ENOMEM;
3853 }
3854
3855 /**
3856  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3857  * @adapter: board private structure to initialize
3858  *
3859  * Attempt to configure the interrupts using the best available
3860  * capabilities of the hardware and the kernel.
3861  **/
3862 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3863 {
3864         struct ixgbe_hw *hw = &adapter->hw;
3865         int err = 0;
3866         int vector, v_budget;
3867
3868         /*
3869          * It's easy to be greedy for MSI-X vectors, but it really
3870          * doesn't do us much good if we have a lot more vectors
3871          * than CPU's.  So let's be conservative and only ask for
3872          * (roughly) the same number of vectors as there are CPU's.
3873          */
3874         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3875                        (int)num_online_cpus()) + NON_Q_VECTORS;
3876
3877         /*
3878          * At the same time, hardware can only support a maximum of
3879          * hw.mac->max_msix_vectors vectors.  With features
3880          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3881          * descriptor queues supported by our device.  Thus, we cap it off in
3882          * those rare cases where the cpu count also exceeds our vector limit.
3883          */
3884         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3885
3886         /* A failure in MSI-X entry allocation isn't fatal, but it does
3887          * mean we disable MSI-X capabilities of the adapter. */
3888         adapter->msix_entries = kcalloc(v_budget,
3889                                         sizeof(struct msix_entry), GFP_KERNEL);
3890         if (adapter->msix_entries) {
3891                 for (vector = 0; vector < v_budget; vector++)
3892                         adapter->msix_entries[vector].entry = vector;
3893
3894                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3895
3896                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3897                         goto out;
3898         }
3899
3900         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3901         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3902         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3903         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3904         adapter->atr_sample_rate = 0;
3905         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3906                 ixgbe_disable_sriov(adapter);
3907
3908         ixgbe_set_num_queues(adapter);
3909
3910         err = pci_enable_msi(adapter->pdev);
3911         if (!err) {
3912                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3913         } else {
3914                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3915                         "falling back to legacy.  Error: %d\n", err);
3916                 /* reset err */
3917                 err = 0;
3918         }
3919
3920 out:
3921         return err;
3922 }
3923
3924 /**
3925  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3926  * @adapter: board private structure to initialize
3927  *
3928  * We allocate one q_vector per queue interrupt.  If allocation fails we
3929  * return -ENOMEM.
3930  **/
3931 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3932 {
3933         int q_idx, num_q_vectors;
3934         struct ixgbe_q_vector *q_vector;
3935         int napi_vectors;
3936         int (*poll)(struct napi_struct *, int);
3937
3938         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3939                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3940                 napi_vectors = adapter->num_rx_queues;
3941                 poll = &ixgbe_clean_rxtx_many;
3942         } else {
3943                 num_q_vectors = 1;
3944                 napi_vectors = 1;
3945                 poll = &ixgbe_poll;
3946         }
3947
3948         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3949                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3950                 if (!q_vector)
3951                         goto err_out;
3952                 q_vector->adapter = adapter;
3953                 if (q_vector->txr_count && !q_vector->rxr_count)
3954                         q_vector->eitr = adapter->tx_eitr_param;
3955                 else
3956                         q_vector->eitr = adapter->rx_eitr_param;
3957                 q_vector->v_idx = q_idx;
3958                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3959                 adapter->q_vector[q_idx] = q_vector;
3960         }
3961
3962         return 0;
3963
3964 err_out:
3965         while (q_idx) {
3966                 q_idx--;
3967                 q_vector = adapter->q_vector[q_idx];
3968                 netif_napi_del(&q_vector->napi);
3969                 kfree(q_vector);
3970                 adapter->q_vector[q_idx] = NULL;
3971         }
3972         return -ENOMEM;
3973 }
3974
3975 /**
3976  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3977  * @adapter: board private structure to initialize
3978  *
3979  * This function frees the memory allocated to the q_vectors.  In addition if
3980  * NAPI is enabled it will delete any references to the NAPI struct prior
3981  * to freeing the q_vector.
3982  **/
3983 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3984 {
3985         int q_idx, num_q_vectors;
3986
3987         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3988                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3989         else
3990                 num_q_vectors = 1;
3991
3992         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3993                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3994                 adapter->q_vector[q_idx] = NULL;
3995                 netif_napi_del(&q_vector->napi);
3996                 kfree(q_vector);
3997         }
3998 }
3999
4000 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4001 {
4002         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4003                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4004                 pci_disable_msix(adapter->pdev);
4005                 kfree(adapter->msix_entries);
4006                 adapter->msix_entries = NULL;
4007         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4008                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4009                 pci_disable_msi(adapter->pdev);
4010         }
4011         return;
4012 }
4013
4014 /**
4015  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4016  * @adapter: board private structure to initialize
4017  *
4018  * We determine which interrupt scheme to use based on...
4019  * - Kernel support (MSI, MSI-X)
4020  *   - which can be user-defined (via MODULE_PARAM)
4021  * - Hardware queue count (num_*_queues)
4022  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4023  **/
4024 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4025 {
4026         int err;
4027
4028         /* Number of supported queues */
4029         ixgbe_set_num_queues(adapter);
4030
4031         err = ixgbe_set_interrupt_capability(adapter);
4032         if (err) {
4033                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4034                 goto err_set_interrupt;
4035         }
4036
4037         err = ixgbe_alloc_q_vectors(adapter);
4038         if (err) {
4039                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4040                         "vectors\n");
4041                 goto err_alloc_q_vectors;
4042         }
4043
4044         err = ixgbe_alloc_queues(adapter);
4045         if (err) {
4046                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4047                 goto err_alloc_queues;
4048         }
4049
4050         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
4051                 "Tx Queue count = %u\n",
4052                 (adapter->num_rx_queues > 1) ? "Enabled" :
4053                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
4054
4055         set_bit(__IXGBE_DOWN, &adapter->state);
4056
4057         return 0;
4058
4059 err_alloc_queues:
4060         ixgbe_free_q_vectors(adapter);
4061 err_alloc_q_vectors:
4062         ixgbe_reset_interrupt_capability(adapter);
4063 err_set_interrupt:
4064         return err;
4065 }
4066
4067 /**
4068  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4069  * @adapter: board private structure to clear interrupt scheme on
4070  *
4071  * We go through and clear interrupt specific resources and reset the structure
4072  * to pre-load conditions
4073  **/
4074 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4075 {
4076         kfree(adapter->tx_ring);
4077         kfree(adapter->rx_ring);
4078         adapter->tx_ring = NULL;
4079         adapter->rx_ring = NULL;
4080
4081         ixgbe_free_q_vectors(adapter);
4082         ixgbe_reset_interrupt_capability(adapter);
4083 }
4084
4085 /**
4086  * ixgbe_sfp_timer - worker thread to find a missing module
4087  * @data: pointer to our adapter struct
4088  **/
4089 static void ixgbe_sfp_timer(unsigned long data)
4090 {
4091         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4092
4093         /*
4094          * Do the sfp_timer outside of interrupt context due to the
4095          * delays that sfp+ detection requires
4096          */
4097         schedule_work(&adapter->sfp_task);
4098 }
4099
4100 /**
4101  * ixgbe_sfp_task - worker thread to find a missing module
4102  * @work: pointer to work_struct containing our data
4103  **/
4104 static void ixgbe_sfp_task(struct work_struct *work)
4105 {
4106         struct ixgbe_adapter *adapter = container_of(work,
4107                                                      struct ixgbe_adapter,
4108                                                      sfp_task);
4109         struct ixgbe_hw *hw = &adapter->hw;
4110
4111         if ((hw->phy.type == ixgbe_phy_nl) &&
4112             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4113                 s32 ret = hw->phy.ops.identify_sfp(hw);
4114                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4115                         goto reschedule;
4116                 ret = hw->phy.ops.reset(hw);
4117                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4118                         dev_err(&adapter->pdev->dev, "failed to initialize "
4119                                 "because an unsupported SFP+ module type "
4120                                 "was detected.\n"
4121                                 "Reload the driver after installing a "
4122                                 "supported module.\n");
4123                         unregister_netdev(adapter->netdev);
4124                 } else {
4125                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4126                                 hw->phy.sfp_type);
4127                 }
4128                 /* don't need this routine any more */
4129                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4130         }
4131         return;
4132 reschedule:
4133         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4134                 mod_timer(&adapter->sfp_timer,
4135                           round_jiffies(jiffies + (2 * HZ)));
4136 }
4137
4138 /**
4139  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4140  * @adapter: board private structure to initialize
4141  *
4142  * ixgbe_sw_init initializes the Adapter private data structure.
4143  * Fields are initialized based on PCI device information and
4144  * OS network device settings (MTU size).
4145  **/
4146 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4147 {
4148         struct ixgbe_hw *hw = &adapter->hw;
4149         struct pci_dev *pdev = adapter->pdev;
4150         unsigned int rss;
4151 #ifdef CONFIG_IXGBE_DCB
4152         int j;
4153         struct tc_configuration *tc;
4154 #endif
4155
4156         /* PCI config space info */
4157
4158         hw->vendor_id = pdev->vendor;
4159         hw->device_id = pdev->device;
4160         hw->revision_id = pdev->revision;
4161         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4162         hw->subsystem_device_id = pdev->subsystem_device;
4163
4164         /* Set capability flags */
4165         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4166         adapter->ring_feature[RING_F_RSS].indices = rss;
4167         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4168         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4169         if (hw->mac.type == ixgbe_mac_82598EB) {
4170                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4171                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4172                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4173         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4174                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4175                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4176                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4177                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4178                 adapter->ring_feature[RING_F_FDIR].indices =
4179                                                          IXGBE_MAX_FDIR_INDICES;
4180                 adapter->atr_sample_rate = 20;
4181                 adapter->fdir_pballoc = 0;
4182 #ifdef IXGBE_FCOE
4183                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4184                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4185                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4186 #ifdef CONFIG_IXGBE_DCB
4187                 /* Default traffic class to use for FCoE */
4188                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4189 #endif
4190 #endif /* IXGBE_FCOE */
4191         }
4192
4193 #ifdef CONFIG_IXGBE_DCB
4194         /* Configure DCB traffic classes */
4195         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4196                 tc = &adapter->dcb_cfg.tc_config[j];
4197                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4198                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4199                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4200                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4201                 tc->dcb_pfc = pfc_disabled;
4202         }
4203         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4204         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4205         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4206         adapter->dcb_cfg.pfc_mode_enable = false;
4207         adapter->dcb_cfg.round_robin_enable = false;
4208         adapter->dcb_set_bitmap = 0x00;
4209         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4210                            adapter->ring_feature[RING_F_DCB].indices);
4211
4212 #endif
4213
4214         /* default flow control settings */
4215         hw->fc.requested_mode = ixgbe_fc_full;
4216         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4217 #ifdef CONFIG_DCB
4218         adapter->last_lfc_mode = hw->fc.current_mode;
4219 #endif
4220         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4221         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4222         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4223         hw->fc.send_xon = true;
4224         hw->fc.disable_fc_autoneg = false;
4225
4226         /* enable itr by default in dynamic mode */
4227         adapter->rx_itr_setting = 1;
4228         adapter->rx_eitr_param = 20000;
4229         adapter->tx_itr_setting = 1;
4230         adapter->tx_eitr_param = 10000;
4231
4232         /* set defaults for eitr in MegaBytes */
4233         adapter->eitr_low = 10;
4234         adapter->eitr_high = 20;
4235
4236         /* set default ring sizes */
4237         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4238         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4239
4240         /* initialize eeprom parameters */
4241         if (ixgbe_init_eeprom_params_generic(hw)) {
4242                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4243                 return -EIO;
4244         }
4245
4246         /* enable rx csum by default */
4247         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4248
4249         set_bit(__IXGBE_DOWN, &adapter->state);
4250
4251         return 0;
4252 }
4253
4254 /**
4255  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4256  * @adapter: board private structure
4257  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4258  *
4259  * Return 0 on success, negative on failure
4260  **/
4261 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4262                              struct ixgbe_ring *tx_ring)
4263 {
4264         struct pci_dev *pdev = adapter->pdev;
4265         int size;
4266
4267         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4268         tx_ring->tx_buffer_info = vmalloc(size);
4269         if (!tx_ring->tx_buffer_info)
4270                 goto err;
4271         memset(tx_ring->tx_buffer_info, 0, size);
4272
4273         /* round up to nearest 4K */
4274         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4275         tx_ring->size = ALIGN(tx_ring->size, 4096);
4276
4277         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4278                                              &tx_ring->dma);
4279         if (!tx_ring->desc)
4280                 goto err;
4281
4282         tx_ring->next_to_use = 0;
4283         tx_ring->next_to_clean = 0;
4284         tx_ring->work_limit = tx_ring->count;
4285         return 0;
4286
4287 err:
4288         vfree(tx_ring->tx_buffer_info);
4289         tx_ring->tx_buffer_info = NULL;
4290         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4291                             "descriptor ring\n");
4292         return -ENOMEM;
4293 }
4294
4295 /**
4296  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4297  * @adapter: board private structure
4298  *
4299  * If this function returns with an error, then it's possible one or
4300  * more of the rings is populated (while the rest are not).  It is the
4301  * callers duty to clean those orphaned rings.
4302  *
4303  * Return 0 on success, negative on failure
4304  **/
4305 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4306 {
4307         int i, err = 0;
4308
4309         for (i = 0; i < adapter->num_tx_queues; i++) {
4310                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4311                 if (!err)
4312                         continue;
4313                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4314                 break;
4315         }
4316
4317         return err;
4318 }
4319
4320 /**
4321  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4322  * @adapter: board private structure
4323  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4324  *
4325  * Returns 0 on success, negative on failure
4326  **/
4327 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4328                              struct ixgbe_ring *rx_ring)
4329 {
4330         struct pci_dev *pdev = adapter->pdev;
4331         int size;
4332
4333         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4334         rx_ring->rx_buffer_info = vmalloc(size);
4335         if (!rx_ring->rx_buffer_info) {
4336                 DPRINTK(PROBE, ERR,
4337                         "vmalloc allocation failed for the rx desc ring\n");
4338                 goto alloc_failed;
4339         }
4340         memset(rx_ring->rx_buffer_info, 0, size);
4341
4342         /* Round up to nearest 4K */
4343         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4344         rx_ring->size = ALIGN(rx_ring->size, 4096);
4345
4346         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4347
4348         if (!rx_ring->desc) {
4349                 DPRINTK(PROBE, ERR,
4350                         "Memory allocation failed for the rx desc ring\n");
4351                 vfree(rx_ring->rx_buffer_info);
4352                 goto alloc_failed;
4353         }
4354
4355         rx_ring->next_to_clean = 0;
4356         rx_ring->next_to_use = 0;
4357
4358         return 0;
4359
4360 alloc_failed:
4361         return -ENOMEM;
4362 }
4363
4364 /**
4365  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4366  * @adapter: board private structure
4367  *
4368  * If this function returns with an error, then it's possible one or
4369  * more of the rings is populated (while the rest are not).  It is the
4370  * callers duty to clean those orphaned rings.
4371  *
4372  * Return 0 on success, negative on failure
4373  **/
4374
4375 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4376 {
4377         int i, err = 0;
4378
4379         for (i = 0; i < adapter->num_rx_queues; i++) {
4380                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4381                 if (!err)
4382                         continue;
4383                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4384                 break;
4385         }
4386
4387         return err;
4388 }
4389
4390 /**
4391  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4392  * @adapter: board private structure
4393  * @tx_ring: Tx descriptor ring for a specific queue
4394  *
4395  * Free all transmit software resources
4396  **/
4397 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4398                              struct ixgbe_ring *tx_ring)
4399 {
4400         struct pci_dev *pdev = adapter->pdev;
4401
4402         ixgbe_clean_tx_ring(adapter, tx_ring);
4403
4404         vfree(tx_ring->tx_buffer_info);
4405         tx_ring->tx_buffer_info = NULL;
4406
4407         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4408
4409         tx_ring->desc = NULL;
4410 }
4411
4412 /**
4413  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4414  * @adapter: board private structure
4415  *
4416  * Free all transmit software resources
4417  **/
4418 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4419 {
4420         int i;
4421
4422         for (i = 0; i < adapter->num_tx_queues; i++)
4423                 if (adapter->tx_ring[i].desc)
4424                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4425 }
4426
4427 /**
4428  * ixgbe_free_rx_resources - Free Rx Resources
4429  * @adapter: board private structure
4430  * @rx_ring: ring to clean the resources from
4431  *
4432  * Free all receive software resources
4433  **/
4434 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4435                              struct ixgbe_ring *rx_ring)
4436 {
4437         struct pci_dev *pdev = adapter->pdev;
4438
4439         ixgbe_clean_rx_ring(adapter, rx_ring);
4440
4441         vfree(rx_ring->rx_buffer_info);
4442         rx_ring->rx_buffer_info = NULL;
4443
4444         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4445
4446         rx_ring->desc = NULL;
4447 }
4448
4449 /**
4450  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4451  * @adapter: board private structure
4452  *
4453  * Free all receive software resources
4454  **/
4455 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4456 {
4457         int i;
4458
4459         for (i = 0; i < adapter->num_rx_queues; i++)
4460                 if (adapter->rx_ring[i].desc)
4461                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4462 }
4463
4464 /**
4465  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4466  * @netdev: network interface device structure
4467  * @new_mtu: new value for maximum frame size
4468  *
4469  * Returns 0 on success, negative on failure
4470  **/
4471 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4472 {
4473         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4474         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4475
4476         /* MTU < 68 is an error and causes problems on some kernels */
4477         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4478                 return -EINVAL;
4479
4480         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4481                 netdev->mtu, new_mtu);
4482         /* must set new MTU before calling down or up */
4483         netdev->mtu = new_mtu;
4484
4485         if (netif_running(netdev))
4486                 ixgbe_reinit_locked(adapter);
4487
4488         return 0;
4489 }
4490
4491 /**
4492  * ixgbe_open - Called when a network interface is made active
4493  * @netdev: network interface device structure
4494  *
4495  * Returns 0 on success, negative value on failure
4496  *
4497  * The open entry point is called when a network interface is made
4498  * active by the system (IFF_UP).  At this point all resources needed
4499  * for transmit and receive operations are allocated, the interrupt
4500  * handler is registered with the OS, the watchdog timer is started,
4501  * and the stack is notified that the interface is ready.
4502  **/
4503 static int ixgbe_open(struct net_device *netdev)
4504 {
4505         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4506         int err;
4507
4508         /* disallow open during test */
4509         if (test_bit(__IXGBE_TESTING, &adapter->state))
4510                 return -EBUSY;
4511
4512         netif_carrier_off(netdev);
4513
4514         /* allocate transmit descriptors */
4515         err = ixgbe_setup_all_tx_resources(adapter);
4516         if (err)
4517                 goto err_setup_tx;
4518
4519         /* allocate receive descriptors */
4520         err = ixgbe_setup_all_rx_resources(adapter);
4521         if (err)
4522                 goto err_setup_rx;
4523
4524         ixgbe_configure(adapter);
4525
4526         err = ixgbe_request_irq(adapter);
4527         if (err)
4528                 goto err_req_irq;
4529
4530         err = ixgbe_up_complete(adapter);
4531         if (err)
4532                 goto err_up;
4533
4534         netif_tx_start_all_queues(netdev);
4535
4536         return 0;
4537
4538 err_up:
4539         ixgbe_release_hw_control(adapter);
4540         ixgbe_free_irq(adapter);
4541 err_req_irq:
4542 err_setup_rx:
4543         ixgbe_free_all_rx_resources(adapter);
4544 err_setup_tx:
4545         ixgbe_free_all_tx_resources(adapter);
4546         ixgbe_reset(adapter);
4547
4548         return err;
4549 }
4550
4551 /**
4552  * ixgbe_close - Disables a network interface
4553  * @netdev: network interface device structure
4554  *
4555  * Returns 0, this is not allowed to fail
4556  *
4557  * The close entry point is called when an interface is de-activated
4558  * by the OS.  The hardware is still under the drivers control, but
4559  * needs to be disabled.  A global MAC reset is issued to stop the
4560  * hardware, and all transmit and receive resources are freed.
4561  **/
4562 static int ixgbe_close(struct net_device *netdev)
4563 {
4564         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4565
4566         ixgbe_down(adapter);
4567         ixgbe_free_irq(adapter);
4568
4569         ixgbe_free_all_tx_resources(adapter);
4570         ixgbe_free_all_rx_resources(adapter);
4571
4572         ixgbe_release_hw_control(adapter);
4573
4574         return 0;
4575 }
4576
4577 #ifdef CONFIG_PM
4578 static int ixgbe_resume(struct pci_dev *pdev)
4579 {
4580         struct net_device *netdev = pci_get_drvdata(pdev);
4581         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4582         u32 err;
4583
4584         pci_set_power_state(pdev, PCI_D0);
4585         pci_restore_state(pdev);
4586         /*
4587          * pci_restore_state clears dev->state_saved so call
4588          * pci_save_state to restore it.
4589          */
4590         pci_save_state(pdev);
4591
4592         err = pci_enable_device_mem(pdev);
4593         if (err) {
4594                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4595                                 "suspend\n");
4596                 return err;
4597         }
4598         pci_set_master(pdev);
4599
4600         pci_wake_from_d3(pdev, false);
4601
4602         err = ixgbe_init_interrupt_scheme(adapter);
4603         if (err) {
4604                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4605                                 "device\n");
4606                 return err;
4607         }
4608
4609         ixgbe_reset(adapter);
4610
4611         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4612
4613         if (netif_running(netdev)) {
4614                 err = ixgbe_open(adapter->netdev);
4615                 if (err)
4616                         return err;
4617         }
4618
4619         netif_device_attach(netdev);
4620
4621         return 0;
4622 }
4623 #endif /* CONFIG_PM */
4624
4625 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4626 {
4627         struct net_device *netdev = pci_get_drvdata(pdev);
4628         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4629         struct ixgbe_hw *hw = &adapter->hw;
4630         u32 ctrl, fctrl;
4631         u32 wufc = adapter->wol;
4632 #ifdef CONFIG_PM
4633         int retval = 0;
4634 #endif
4635
4636         netif_device_detach(netdev);
4637
4638         if (netif_running(netdev)) {
4639                 ixgbe_down(adapter);
4640                 ixgbe_free_irq(adapter);
4641                 ixgbe_free_all_tx_resources(adapter);
4642                 ixgbe_free_all_rx_resources(adapter);
4643         }
4644         ixgbe_clear_interrupt_scheme(adapter);
4645
4646 #ifdef CONFIG_PM
4647         retval = pci_save_state(pdev);
4648         if (retval)
4649                 return retval;
4650
4651 #endif
4652         if (wufc) {
4653                 ixgbe_set_rx_mode(netdev);
4654
4655                 /* turn on all-multi mode if wake on multicast is enabled */
4656                 if (wufc & IXGBE_WUFC_MC) {
4657                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4658                         fctrl |= IXGBE_FCTRL_MPE;
4659                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4660                 }
4661
4662                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4663                 ctrl |= IXGBE_CTRL_GIO_DIS;
4664                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4665
4666                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4667         } else {
4668                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4669                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4670         }
4671
4672         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4673                 pci_wake_from_d3(pdev, true);
4674         else
4675                 pci_wake_from_d3(pdev, false);
4676
4677         *enable_wake = !!wufc;
4678
4679         ixgbe_release_hw_control(adapter);
4680
4681         pci_disable_device(pdev);
4682
4683         return 0;
4684 }
4685
4686 #ifdef CONFIG_PM
4687 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4688 {
4689         int retval;
4690         bool wake;
4691
4692         retval = __ixgbe_shutdown(pdev, &wake);
4693         if (retval)
4694                 return retval;
4695
4696         if (wake) {
4697                 pci_prepare_to_sleep(pdev);
4698         } else {
4699                 pci_wake_from_d3(pdev, false);
4700                 pci_set_power_state(pdev, PCI_D3hot);
4701         }
4702
4703         return 0;
4704 }
4705 #endif /* CONFIG_PM */
4706
4707 static void ixgbe_shutdown(struct pci_dev *pdev)
4708 {
4709         bool wake;
4710
4711         __ixgbe_shutdown(pdev, &wake);
4712
4713         if (system_state == SYSTEM_POWER_OFF) {
4714                 pci_wake_from_d3(pdev, wake);
4715                 pci_set_power_state(pdev, PCI_D3hot);
4716         }
4717 }
4718
4719 /**
4720  * ixgbe_update_stats - Update the board statistics counters.
4721  * @adapter: board private structure
4722  **/
4723 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4724 {
4725         struct net_device *netdev = adapter->netdev;
4726         struct ixgbe_hw *hw = &adapter->hw;
4727         u64 total_mpc = 0;
4728         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4729         u64 non_eop_descs = 0, restart_queue = 0;
4730
4731         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4732                 u64 rsc_count = 0;
4733                 u64 rsc_flush = 0;
4734                 for (i = 0; i < 16; i++)
4735                         adapter->hw_rx_no_dma_resources +=
4736                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4737                 for (i = 0; i < adapter->num_rx_queues; i++) {
4738                         rsc_count += adapter->rx_ring[i].rsc_count;
4739                         rsc_flush += adapter->rx_ring[i].rsc_flush;
4740                 }
4741                 adapter->rsc_total_count = rsc_count;
4742                 adapter->rsc_total_flush = rsc_flush;
4743         }
4744
4745         /* gather some stats to the adapter struct that are per queue */
4746         for (i = 0; i < adapter->num_tx_queues; i++)
4747                 restart_queue += adapter->tx_ring[i].restart_queue;
4748         adapter->restart_queue = restart_queue;
4749
4750         for (i = 0; i < adapter->num_rx_queues; i++)
4751                 non_eop_descs += adapter->rx_ring[i].non_eop_descs;
4752         adapter->non_eop_descs = non_eop_descs;
4753
4754         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4755         for (i = 0; i < 8; i++) {
4756                 /* for packet buffers not used, the register should read 0 */
4757                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4758                 missed_rx += mpc;
4759                 adapter->stats.mpc[i] += mpc;
4760                 total_mpc += adapter->stats.mpc[i];
4761                 if (hw->mac.type == ixgbe_mac_82598EB)
4762                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4763                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4764                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4765                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4766                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4767                 if (hw->mac.type == ixgbe_mac_82599EB) {
4768                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4769                                                             IXGBE_PXONRXCNT(i));
4770                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4771                                                            IXGBE_PXOFFRXCNT(i));
4772                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4773                 } else {
4774                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4775                                                               IXGBE_PXONRXC(i));
4776                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4777                                                              IXGBE_PXOFFRXC(i));
4778                 }
4779                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4780                                                             IXGBE_PXONTXC(i));
4781                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4782                                                              IXGBE_PXOFFTXC(i));
4783         }
4784         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4785         /* work around hardware counting issue */
4786         adapter->stats.gprc -= missed_rx;
4787
4788         /* 82598 hardware only has a 32 bit counter in the high register */
4789         if (hw->mac.type == ixgbe_mac_82599EB) {
4790                 u64 tmp;
4791                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4792                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4793                 adapter->stats.gorc += (tmp << 32);
4794                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4795                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4796                 adapter->stats.gotc += (tmp << 32);
4797                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4798                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4799                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4800                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4801                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4802                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4803 #ifdef IXGBE_FCOE
4804                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4805                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4806                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4807                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4808                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4809                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4810 #endif /* IXGBE_FCOE */
4811         } else {
4812                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4813                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4814                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4815                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4816                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4817         }
4818         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4819         adapter->stats.bprc += bprc;
4820         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4821         if (hw->mac.type == ixgbe_mac_82598EB)
4822                 adapter->stats.mprc -= bprc;
4823         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4824         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4825         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4826         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4827         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4828         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4829         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4830         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4831         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4832         adapter->stats.lxontxc += lxon;
4833         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4834         adapter->stats.lxofftxc += lxoff;
4835         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4836         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4837         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4838         /*
4839          * 82598 errata - tx of flow control packets is included in tx counters
4840          */
4841         xon_off_tot = lxon + lxoff;
4842         adapter->stats.gptc -= xon_off_tot;
4843         adapter->stats.mptc -= xon_off_tot;
4844         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4845         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4846         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4847         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4848         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4849         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4850         adapter->stats.ptc64 -= xon_off_tot;
4851         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4852         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4853         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4854         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4855         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4856         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4857
4858         /* Fill out the OS statistics structure */
4859         netdev->stats.multicast = adapter->stats.mprc;
4860
4861         /* Rx Errors */
4862         netdev->stats.rx_errors = adapter->stats.crcerrs +
4863                                        adapter->stats.rlec;
4864         netdev->stats.rx_dropped = 0;
4865         netdev->stats.rx_length_errors = adapter->stats.rlec;
4866         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4867         netdev->stats.rx_missed_errors = total_mpc;
4868 }
4869
4870 /**
4871  * ixgbe_watchdog - Timer Call-back
4872  * @data: pointer to adapter cast into an unsigned long
4873  **/
4874 static void ixgbe_watchdog(unsigned long data)
4875 {
4876         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4877         struct ixgbe_hw *hw = &adapter->hw;
4878         u64 eics = 0;
4879         int i;
4880
4881         /*
4882          *  Do the watchdog outside of interrupt context due to the lovely
4883          * delays that some of the newer hardware requires
4884          */
4885
4886         if (test_bit(__IXGBE_DOWN, &adapter->state))
4887                 goto watchdog_short_circuit;
4888
4889         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4890                 /*
4891                  * for legacy and MSI interrupts don't set any bits
4892                  * that are enabled for EIAM, because this operation
4893                  * would set *both* EIMS and EICS for any bit in EIAM
4894                  */
4895                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4896                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4897                 goto watchdog_reschedule;
4898         }
4899
4900         /* get one bit for every active tx/rx interrupt vector */
4901         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4902                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4903                 if (qv->rxr_count || qv->txr_count)
4904                         eics |= ((u64)1 << i);
4905         }
4906
4907         /* Cause software interrupt to ensure rx rings are cleaned */
4908         ixgbe_irq_rearm_queues(adapter, eics);
4909
4910 watchdog_reschedule:
4911         /* Reset the timer */
4912         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4913
4914 watchdog_short_circuit:
4915         schedule_work(&adapter->watchdog_task);
4916 }
4917
4918 /**
4919  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4920  * @work: pointer to work_struct containing our data
4921  **/
4922 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4923 {
4924         struct ixgbe_adapter *adapter = container_of(work,
4925                                                      struct ixgbe_adapter,
4926                                                      multispeed_fiber_task);
4927         struct ixgbe_hw *hw = &adapter->hw;
4928         u32 autoneg;
4929         bool negotiation;
4930
4931         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4932         autoneg = hw->phy.autoneg_advertised;
4933         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4934                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4935         if (hw->mac.ops.setup_link)
4936                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4937         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4938         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4939 }
4940
4941 /**
4942  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4943  * @work: pointer to work_struct containing our data
4944  **/
4945 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4946 {
4947         struct ixgbe_adapter *adapter = container_of(work,
4948                                                      struct ixgbe_adapter,
4949                                                      sfp_config_module_task);
4950         struct ixgbe_hw *hw = &adapter->hw;
4951         u32 err;
4952
4953         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4954
4955         /* Time for electrical oscillations to settle down */
4956         msleep(100);
4957         err = hw->phy.ops.identify_sfp(hw);
4958
4959         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4960                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4961                         "an unsupported SFP+ module type was detected.\n"
4962                         "Reload the driver after installing a supported "
4963                         "module.\n");
4964                 unregister_netdev(adapter->netdev);
4965                 return;
4966         }
4967         hw->mac.ops.setup_sfp(hw);
4968
4969         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4970                 /* This will also work for DA Twinax connections */
4971                 schedule_work(&adapter->multispeed_fiber_task);
4972         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4973 }
4974
4975 /**
4976  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4977  * @work: pointer to work_struct containing our data
4978  **/
4979 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4980 {
4981         struct ixgbe_adapter *adapter = container_of(work,
4982                                                      struct ixgbe_adapter,
4983                                                      fdir_reinit_task);
4984         struct ixgbe_hw *hw = &adapter->hw;
4985         int i;
4986
4987         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4988                 for (i = 0; i < adapter->num_tx_queues; i++)
4989                         set_bit(__IXGBE_FDIR_INIT_DONE,
4990                                 &(adapter->tx_ring[i].reinit_state));
4991         } else {
4992                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4993                         "ignored adding FDIR ATR filters \n");
4994         }
4995         /* Done FDIR Re-initialization, enable transmits */
4996         netif_tx_start_all_queues(adapter->netdev);
4997 }
4998
4999 /**
5000  * ixgbe_watchdog_task - worker thread to bring link up
5001  * @work: pointer to work_struct containing our data
5002  **/
5003 static void ixgbe_watchdog_task(struct work_struct *work)
5004 {
5005         struct ixgbe_adapter *adapter = container_of(work,
5006                                                      struct ixgbe_adapter,
5007                                                      watchdog_task);
5008         struct net_device *netdev = adapter->netdev;
5009         struct ixgbe_hw *hw = &adapter->hw;
5010         u32 link_speed = adapter->link_speed;
5011         bool link_up = adapter->link_up;
5012         int i;
5013         struct ixgbe_ring *tx_ring;
5014         int some_tx_pending = 0;
5015
5016         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
5017
5018         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5019                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5020                 if (link_up) {
5021 #ifdef CONFIG_DCB
5022                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5023                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5024                                         hw->mac.ops.fc_enable(hw, i);
5025                         } else {
5026                                 hw->mac.ops.fc_enable(hw, 0);
5027                         }
5028 #else
5029                         hw->mac.ops.fc_enable(hw, 0);
5030 #endif
5031                 }
5032
5033                 if (link_up ||
5034                     time_after(jiffies, (adapter->link_check_timeout +
5035                                          IXGBE_TRY_LINK_TIMEOUT))) {
5036                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5037                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5038                 }
5039                 adapter->link_up = link_up;
5040                 adapter->link_speed = link_speed;
5041         }
5042
5043         if (link_up) {
5044                 if (!netif_carrier_ok(netdev)) {
5045                         bool flow_rx, flow_tx;
5046
5047                         if (hw->mac.type == ixgbe_mac_82599EB) {
5048                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5049                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5050                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5051                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5052                         } else {
5053                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5054                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5055                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5056                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5057                         }
5058
5059                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5060                                "Flow Control: %s\n",
5061                                netdev->name,
5062                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5063                                 "10 Gbps" :
5064                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5065                                  "1 Gbps" : "unknown speed")),
5066                                ((flow_rx && flow_tx) ? "RX/TX" :
5067                                 (flow_rx ? "RX" :
5068                                 (flow_tx ? "TX" : "None"))));
5069
5070                         netif_carrier_on(netdev);
5071                 } else {
5072                         /* Force detection of hung controller */
5073                         adapter->detect_tx_hung = true;
5074                 }
5075         } else {
5076                 adapter->link_up = false;
5077                 adapter->link_speed = 0;
5078                 if (netif_carrier_ok(netdev)) {
5079                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5080                                netdev->name);
5081                         netif_carrier_off(netdev);
5082                 }
5083         }
5084
5085         if (!netif_carrier_ok(netdev)) {
5086                 for (i = 0; i < adapter->num_tx_queues; i++) {
5087                         tx_ring = &adapter->tx_ring[i];
5088                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5089                                 some_tx_pending = 1;
5090                                 break;
5091                         }
5092                 }
5093
5094                 if (some_tx_pending) {
5095                         /* We've lost link, so the controller stops DMA,
5096                          * but we've got queued Tx work that's never going
5097                          * to get done, so reset controller to flush Tx.
5098                          * (Do the reset outside of interrupt context).
5099                          */
5100                          schedule_work(&adapter->reset_task);
5101                 }
5102         }
5103
5104         ixgbe_update_stats(adapter);
5105         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
5106 }
5107
5108 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5109                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5110                      u32 tx_flags, u8 *hdr_len)
5111 {
5112         struct ixgbe_adv_tx_context_desc *context_desc;
5113         unsigned int i;
5114         int err;
5115         struct ixgbe_tx_buffer *tx_buffer_info;
5116         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5117         u32 mss_l4len_idx, l4len;
5118
5119         if (skb_is_gso(skb)) {
5120                 if (skb_header_cloned(skb)) {
5121                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5122                         if (err)
5123                                 return err;
5124                 }
5125                 l4len = tcp_hdrlen(skb);
5126                 *hdr_len += l4len;
5127
5128                 if (skb->protocol == htons(ETH_P_IP)) {
5129                         struct iphdr *iph = ip_hdr(skb);
5130                         iph->tot_len = 0;
5131                         iph->check = 0;
5132                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5133                                                                  iph->daddr, 0,
5134                                                                  IPPROTO_TCP,
5135                                                                  0);
5136                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
5137                         ipv6_hdr(skb)->payload_len = 0;
5138                         tcp_hdr(skb)->check =
5139                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5140                                              &ipv6_hdr(skb)->daddr,
5141                                              0, IPPROTO_TCP, 0);
5142                 }
5143
5144                 i = tx_ring->next_to_use;
5145
5146                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5147                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5148
5149                 /* VLAN MACLEN IPLEN */
5150                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5151                         vlan_macip_lens |=
5152                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5153                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5154                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5155                 *hdr_len += skb_network_offset(skb);
5156                 vlan_macip_lens |=
5157                     (skb_transport_header(skb) - skb_network_header(skb));
5158                 *hdr_len +=
5159                     (skb_transport_header(skb) - skb_network_header(skb));
5160                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5161                 context_desc->seqnum_seed = 0;
5162
5163                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5164                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5165                                    IXGBE_ADVTXD_DTYP_CTXT);
5166
5167                 if (skb->protocol == htons(ETH_P_IP))
5168                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5169                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5170                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5171
5172                 /* MSS L4LEN IDX */
5173                 mss_l4len_idx =
5174                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5175                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5176                 /* use index 1 for TSO */
5177                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5178                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5179
5180                 tx_buffer_info->time_stamp = jiffies;
5181                 tx_buffer_info->next_to_watch = i;
5182
5183                 i++;
5184                 if (i == tx_ring->count)
5185                         i = 0;
5186                 tx_ring->next_to_use = i;
5187
5188                 return true;
5189         }
5190         return false;
5191 }
5192
5193 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5194                           struct ixgbe_ring *tx_ring,
5195                           struct sk_buff *skb, u32 tx_flags)
5196 {
5197         struct ixgbe_adv_tx_context_desc *context_desc;
5198         unsigned int i;
5199         struct ixgbe_tx_buffer *tx_buffer_info;
5200         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5201
5202         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5203             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5204                 i = tx_ring->next_to_use;
5205                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5206                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5207
5208                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5209                         vlan_macip_lens |=
5210                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5211                 vlan_macip_lens |= (skb_network_offset(skb) <<
5212                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5213                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5214                         vlan_macip_lens |= (skb_transport_header(skb) -
5215                                             skb_network_header(skb));
5216
5217                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5218                 context_desc->seqnum_seed = 0;
5219
5220                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5221                                     IXGBE_ADVTXD_DTYP_CTXT);
5222
5223                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5224                         __be16 protocol;
5225
5226                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5227                                 const struct vlan_ethhdr *vhdr =
5228                                         (const struct vlan_ethhdr *)skb->data;
5229
5230                                 protocol = vhdr->h_vlan_encapsulated_proto;
5231                         } else {
5232                                 protocol = skb->protocol;
5233                         }
5234
5235                         switch (protocol) {
5236                         case cpu_to_be16(ETH_P_IP):
5237                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5238                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5239                                         type_tucmd_mlhl |=
5240                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5241                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5242                                         type_tucmd_mlhl |=
5243                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5244                                 break;
5245                         case cpu_to_be16(ETH_P_IPV6):
5246                                 /* XXX what about other V6 headers?? */
5247                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5248                                         type_tucmd_mlhl |=
5249                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5250                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5251                                         type_tucmd_mlhl |=
5252                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5253                                 break;
5254                         default:
5255                                 if (unlikely(net_ratelimit())) {
5256                                         DPRINTK(PROBE, WARNING,
5257                                          "partial checksum but proto=%x!\n",
5258                                          skb->protocol);
5259                                 }
5260                                 break;
5261                         }
5262                 }
5263
5264                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5265                 /* use index zero for tx checksum offload */
5266                 context_desc->mss_l4len_idx = 0;
5267
5268                 tx_buffer_info->time_stamp = jiffies;
5269                 tx_buffer_info->next_to_watch = i;
5270
5271                 i++;
5272                 if (i == tx_ring->count)
5273                         i = 0;
5274                 tx_ring->next_to_use = i;
5275
5276                 return true;
5277         }
5278
5279         return false;
5280 }
5281
5282 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5283                         struct ixgbe_ring *tx_ring,
5284                         struct sk_buff *skb, u32 tx_flags,
5285                         unsigned int first)
5286 {
5287         struct pci_dev *pdev = adapter->pdev;
5288         struct ixgbe_tx_buffer *tx_buffer_info;
5289         unsigned int len;
5290         unsigned int total = skb->len;
5291         unsigned int offset = 0, size, count = 0, i;
5292         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5293         unsigned int f;
5294
5295         i = tx_ring->next_to_use;
5296
5297         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5298                 /* excluding fcoe_crc_eof for FCoE */
5299                 total -= sizeof(struct fcoe_crc_eof);
5300
5301         len = min(skb_headlen(skb), total);
5302         while (len) {
5303                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5304                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5305
5306                 tx_buffer_info->length = size;
5307                 tx_buffer_info->mapped_as_page = false;
5308                 tx_buffer_info->dma = pci_map_single(pdev,
5309                                                      skb->data + offset,
5310                                                      size, PCI_DMA_TODEVICE);
5311                 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5312                         goto dma_error;
5313                 tx_buffer_info->time_stamp = jiffies;
5314                 tx_buffer_info->next_to_watch = i;
5315
5316                 len -= size;
5317                 total -= size;
5318                 offset += size;
5319                 count++;
5320
5321                 if (len) {
5322                         i++;
5323                         if (i == tx_ring->count)
5324                                 i = 0;
5325                 }
5326         }
5327
5328         for (f = 0; f < nr_frags; f++) {
5329                 struct skb_frag_struct *frag;
5330
5331                 frag = &skb_shinfo(skb)->frags[f];
5332                 len = min((unsigned int)frag->size, total);
5333                 offset = frag->page_offset;
5334
5335                 while (len) {
5336                         i++;
5337                         if (i == tx_ring->count)
5338                                 i = 0;
5339
5340                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5341                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5342
5343                         tx_buffer_info->length = size;
5344                         tx_buffer_info->dma = pci_map_page(adapter->pdev,
5345                                                            frag->page,
5346                                                            offset, size,
5347                                                            PCI_DMA_TODEVICE);
5348                         tx_buffer_info->mapped_as_page = true;
5349                         if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5350                                 goto dma_error;
5351                         tx_buffer_info->time_stamp = jiffies;
5352                         tx_buffer_info->next_to_watch = i;
5353
5354                         len -= size;
5355                         total -= size;
5356                         offset += size;
5357                         count++;
5358                 }
5359                 if (total == 0)
5360                         break;
5361         }
5362
5363         tx_ring->tx_buffer_info[i].skb = skb;
5364         tx_ring->tx_buffer_info[first].next_to_watch = i;
5365
5366         return count;
5367
5368 dma_error:
5369         dev_err(&pdev->dev, "TX DMA map failed\n");
5370
5371         /* clear timestamp and dma mappings for failed tx_buffer_info map */
5372         tx_buffer_info->dma = 0;
5373         tx_buffer_info->time_stamp = 0;
5374         tx_buffer_info->next_to_watch = 0;
5375         if (count)
5376                 count--;
5377
5378         /* clear timestamp and dma mappings for remaining portion of packet */
5379         while (count--) {
5380                 if (i==0)
5381                         i += tx_ring->count;
5382                 i--;
5383                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5384                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5385         }
5386
5387         return count;
5388 }
5389
5390 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5391                            struct ixgbe_ring *tx_ring,
5392                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5393 {
5394         union ixgbe_adv_tx_desc *tx_desc = NULL;
5395         struct ixgbe_tx_buffer *tx_buffer_info;
5396         u32 olinfo_status = 0, cmd_type_len = 0;
5397         unsigned int i;
5398         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5399
5400         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5401
5402         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5403
5404         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5405                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5406
5407         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5408                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5409
5410                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5411                                  IXGBE_ADVTXD_POPTS_SHIFT;
5412
5413                 /* use index 1 context for tso */
5414                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5415                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5416                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5417                                          IXGBE_ADVTXD_POPTS_SHIFT;
5418
5419         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5420                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5421                                  IXGBE_ADVTXD_POPTS_SHIFT;
5422
5423         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5424                 olinfo_status |= IXGBE_ADVTXD_CC;
5425                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5426                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5427                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5428         }
5429
5430         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5431
5432         i = tx_ring->next_to_use;
5433         while (count--) {
5434                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5435                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5436                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5437                 tx_desc->read.cmd_type_len =
5438                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5439                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5440                 i++;
5441                 if (i == tx_ring->count)
5442                         i = 0;
5443         }
5444
5445         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5446
5447         /*
5448          * Force memory writes to complete before letting h/w
5449          * know there are new descriptors to fetch.  (Only
5450          * applicable for weak-ordered memory model archs,
5451          * such as IA-64).
5452          */
5453         wmb();
5454
5455         tx_ring->next_to_use = i;
5456         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5457 }
5458
5459 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5460                       int queue, u32 tx_flags)
5461 {
5462         /* Right now, we support IPv4 only */
5463         struct ixgbe_atr_input atr_input;
5464         struct tcphdr *th;
5465         struct iphdr *iph = ip_hdr(skb);
5466         struct ethhdr *eth = (struct ethhdr *)skb->data;
5467         u16 vlan_id, src_port, dst_port, flex_bytes;
5468         u32 src_ipv4_addr, dst_ipv4_addr;
5469         u8 l4type = 0;
5470
5471         /* check if we're UDP or TCP */
5472         if (iph->protocol == IPPROTO_TCP) {
5473                 th = tcp_hdr(skb);
5474                 src_port = th->source;
5475                 dst_port = th->dest;
5476                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5477                 /* l4type IPv4 type is 0, no need to assign */
5478         } else {
5479                 /* Unsupported L4 header, just bail here */
5480                 return;
5481         }
5482
5483         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5484
5485         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5486                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5487         src_ipv4_addr = iph->saddr;
5488         dst_ipv4_addr = iph->daddr;
5489         flex_bytes = eth->h_proto;
5490
5491         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5492         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5493         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5494         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5495         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5496         /* src and dst are inverted, think how the receiver sees them */
5497         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5498         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5499
5500         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5501         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5502 }
5503
5504 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5505                                  struct ixgbe_ring *tx_ring, int size)
5506 {
5507         netif_stop_subqueue(netdev, tx_ring->queue_index);
5508         /* Herbert's original patch had:
5509          *  smp_mb__after_netif_stop_queue();
5510          * but since that doesn't exist yet, just open code it. */
5511         smp_mb();
5512
5513         /* We need to check again in a case another CPU has just
5514          * made room available. */
5515         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5516                 return -EBUSY;
5517
5518         /* A reprieve! - use start_queue because it doesn't call schedule */
5519         netif_start_subqueue(netdev, tx_ring->queue_index);
5520         ++tx_ring->restart_queue;
5521         return 0;
5522 }
5523
5524 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5525                               struct ixgbe_ring *tx_ring, int size)
5526 {
5527         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5528                 return 0;
5529         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5530 }
5531
5532 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5533 {
5534         struct ixgbe_adapter *adapter = netdev_priv(dev);
5535         int txq = smp_processor_id();
5536
5537         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5538                 return txq;
5539
5540 #ifdef IXGBE_FCOE
5541         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5542             (skb->protocol == htons(ETH_P_FCOE))) {
5543                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5544                 txq += adapter->ring_feature[RING_F_FCOE].mask;
5545                 return txq;
5546         }
5547 #endif
5548         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5549                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5550
5551         return skb_tx_hash(dev, skb);
5552 }
5553
5554 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5555                                     struct net_device *netdev)
5556 {
5557         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5558         struct ixgbe_ring *tx_ring;
5559         struct netdev_queue *txq;
5560         unsigned int first;
5561         unsigned int tx_flags = 0;
5562         u8 hdr_len = 0;
5563         int tso;
5564         int count = 0;
5565         unsigned int f;
5566
5567         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5568                 tx_flags |= vlan_tx_tag_get(skb);
5569                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5570                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5571                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5572                 }
5573                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5574                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5575         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5576                 if (skb->priority != TC_PRIO_CONTROL) {
5577                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5578                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5579                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5580                 } else {
5581                         skb->queue_mapping =
5582                                 adapter->ring_feature[RING_F_DCB].indices-1;
5583                 }
5584         }
5585
5586         tx_ring = &adapter->tx_ring[skb->queue_mapping];
5587
5588         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5589             (skb->protocol == htons(ETH_P_FCOE))) {
5590                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5591 #ifdef IXGBE_FCOE
5592 #ifdef CONFIG_IXGBE_DCB
5593                 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5594                               << IXGBE_TX_FLAGS_VLAN_SHIFT);
5595                 tx_flags |= ((adapter->fcoe.up << 13)
5596                               << IXGBE_TX_FLAGS_VLAN_SHIFT);
5597 #endif
5598 #endif
5599         }
5600         /* four things can cause us to need a context descriptor */
5601         if (skb_is_gso(skb) ||
5602             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5603             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5604             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5605                 count++;
5606
5607         count += TXD_USE_COUNT(skb_headlen(skb));
5608         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5609                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5610
5611         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5612                 adapter->tx_busy++;
5613                 return NETDEV_TX_BUSY;
5614         }
5615
5616         first = tx_ring->next_to_use;
5617         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5618 #ifdef IXGBE_FCOE
5619                 /* setup tx offload for FCoE */
5620                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5621                 if (tso < 0) {
5622                         dev_kfree_skb_any(skb);
5623                         return NETDEV_TX_OK;
5624                 }
5625                 if (tso)
5626                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5627 #endif /* IXGBE_FCOE */
5628         } else {
5629                 if (skb->protocol == htons(ETH_P_IP))
5630                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5631                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5632                 if (tso < 0) {
5633                         dev_kfree_skb_any(skb);
5634                         return NETDEV_TX_OK;
5635                 }
5636
5637                 if (tso)
5638                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5639                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5640                          (skb->ip_summed == CHECKSUM_PARTIAL))
5641                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5642         }
5643
5644         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5645         if (count) {
5646                 /* add the ATR filter if ATR is on */
5647                 if (tx_ring->atr_sample_rate) {
5648                         ++tx_ring->atr_count;
5649                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5650                              test_bit(__IXGBE_FDIR_INIT_DONE,
5651                                       &tx_ring->reinit_state)) {
5652                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5653                                           tx_flags);
5654                                 tx_ring->atr_count = 0;
5655                         }
5656                 }
5657                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5658                 txq->tx_bytes += skb->len;
5659                 txq->tx_packets++;
5660                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5661                                hdr_len);
5662                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5663
5664         } else {
5665                 dev_kfree_skb_any(skb);
5666                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5667                 tx_ring->next_to_use = first;
5668         }
5669
5670         return NETDEV_TX_OK;
5671 }
5672
5673 /**
5674  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5675  * @netdev: network interface device structure
5676  * @p: pointer to an address structure
5677  *
5678  * Returns 0 on success, negative on failure
5679  **/
5680 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5681 {
5682         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5683         struct ixgbe_hw *hw = &adapter->hw;
5684         struct sockaddr *addr = p;
5685
5686         if (!is_valid_ether_addr(addr->sa_data))
5687                 return -EADDRNOTAVAIL;
5688
5689         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5690         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5691
5692         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5693                             IXGBE_RAH_AV);
5694
5695         return 0;
5696 }
5697
5698 static int
5699 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5700 {
5701         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5702         struct ixgbe_hw *hw = &adapter->hw;
5703         u16 value;
5704         int rc;
5705
5706         if (prtad != hw->phy.mdio.prtad)
5707                 return -EINVAL;
5708         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5709         if (!rc)
5710                 rc = value;
5711         return rc;
5712 }
5713
5714 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5715                             u16 addr, u16 value)
5716 {
5717         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5718         struct ixgbe_hw *hw = &adapter->hw;
5719
5720         if (prtad != hw->phy.mdio.prtad)
5721                 return -EINVAL;
5722         return hw->phy.ops.write_reg(hw, addr, devad, value);
5723 }
5724
5725 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5726 {
5727         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5728
5729         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5730 }
5731
5732 /**
5733  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5734  * netdev->dev_addrs
5735  * @netdev: network interface device structure
5736  *
5737  * Returns non-zero on failure
5738  **/
5739 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5740 {
5741         int err = 0;
5742         struct ixgbe_adapter *adapter = netdev_priv(dev);
5743         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5744
5745         if (is_valid_ether_addr(mac->san_addr)) {
5746                 rtnl_lock();
5747                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5748                 rtnl_unlock();
5749         }
5750         return err;
5751 }
5752
5753 /**
5754  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5755  * netdev->dev_addrs
5756  * @netdev: network interface device structure
5757  *
5758  * Returns non-zero on failure
5759  **/
5760 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5761 {
5762         int err = 0;
5763         struct ixgbe_adapter *adapter = netdev_priv(dev);
5764         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5765
5766         if (is_valid_ether_addr(mac->san_addr)) {
5767                 rtnl_lock();
5768                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5769                 rtnl_unlock();
5770         }
5771         return err;
5772 }
5773
5774 #ifdef CONFIG_NET_POLL_CONTROLLER
5775 /*
5776  * Polling 'interrupt' - used by things like netconsole to send skbs
5777  * without having to re-enable interrupts. It's not called while
5778  * the interrupt routine is executing.
5779  */
5780 static void ixgbe_netpoll(struct net_device *netdev)
5781 {
5782         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5783         int i;
5784
5785         /* if interface is down do nothing */
5786         if (test_bit(__IXGBE_DOWN, &adapter->state))
5787                 return;
5788
5789         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5790         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5791                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5792                 for (i = 0; i < num_q_vectors; i++) {
5793                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5794                         ixgbe_msix_clean_many(0, q_vector);
5795                 }
5796         } else {
5797                 ixgbe_intr(adapter->pdev->irq, netdev);
5798         }
5799         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5800 }
5801 #endif
5802
5803 static const struct net_device_ops ixgbe_netdev_ops = {
5804         .ndo_open               = ixgbe_open,
5805         .ndo_stop               = ixgbe_close,
5806         .ndo_start_xmit         = ixgbe_xmit_frame,
5807         .ndo_select_queue       = ixgbe_select_queue,
5808         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5809         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5810         .ndo_validate_addr      = eth_validate_addr,
5811         .ndo_set_mac_address    = ixgbe_set_mac,
5812         .ndo_change_mtu         = ixgbe_change_mtu,
5813         .ndo_tx_timeout         = ixgbe_tx_timeout,
5814         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5815         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5816         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5817         .ndo_do_ioctl           = ixgbe_ioctl,
5818 #ifdef CONFIG_NET_POLL_CONTROLLER
5819         .ndo_poll_controller    = ixgbe_netpoll,
5820 #endif
5821 #ifdef IXGBE_FCOE
5822         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5823         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5824         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5825         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5826         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
5827 #endif /* IXGBE_FCOE */
5828 };
5829
5830 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
5831                            const struct ixgbe_info *ii)
5832 {
5833 #ifdef CONFIG_PCI_IOV
5834         struct ixgbe_hw *hw = &adapter->hw;
5835         int err;
5836
5837         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
5838                 return;
5839
5840         /* The 82599 supports up to 64 VFs per physical function
5841          * but this implementation limits allocation to 63 so that
5842          * basic networking resources are still available to the
5843          * physical function
5844          */
5845         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
5846         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
5847         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
5848         if (err) {
5849                 DPRINTK(PROBE, ERR,
5850                         "Failed to enable PCI sriov: %d\n", err);
5851                 goto err_novfs;
5852         }
5853         /* If call to enable VFs succeeded then allocate memory
5854          * for per VF control structures.